This source file includes following definitions.
- doAppendCycleInstructionFetch
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65 word24 doAppendCycleInstructionFetch (word36 * data, uint nWords) {
66
67 static int evcnt = 0;
68 DCDstruct * i = & cpu.currentInstruction;
69 (void)evcnt;
70 DBGAPP ("doAppendCycleInstructionFetch(Entry) thisCycle=INSTRUCTION_FETCH\n");
71 DBGAPP ("doAppendCycleInstructionFetch(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle));
72 DBGAPP ("doAppendCycleInstructionFetch(Entry) CA %06o\n", cpu.TPR.CA);
73 DBGAPP ("doAppendCycleInstructionFetch(Entry) n=%2u\n", nWords);
74 DBGAPP ("doAppendCycleInstructionFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR);
75 DBGAPP ("doAppendCycleInstructionFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
76
77 if (i->b29) {
78 DBGAPP ("doAppendCycleInstructionFetch(Entry) isb29 PRNO %o\n", GET_PRN (IWB_IRODD));
79 }
80
81 uint this = UC_INSTRUCTION_FETCH;
82
83 word24 finalAddress = 0;
84 word24 pageAddress = 0;
85 word3 RSDWH_R1 = 0;
86 word14 bound = 0;
87 word1 p = 0;
88 bool paged = false;
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111 #ifdef TEST_UCACHE
112 bool cacheHit;
113 cacheHit = false;
114 #endif
115
116
117 if (i->opcode == 0610 && ! i->opcodeX) {
118
119 goto skip_ucache;
120 }
121
122
123 if (cpu.rRALR) {
124
125 goto skip_ucache;
126 }
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132
133 if (i->opcodeX && ((i->opcode & 0770)== 0200|| (i->opcode & 0770) == 0220
134 || (i->opcode & 0770)== 020|| (i->opcode & 0770) == 0300)) {
135
136 goto skip_ucache;
137 }
138
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141
142 #ifdef TEST_UCACHE
143 word24 cachedAddress;
144 word3 cachedR1;
145 word14 cachedBound;
146 word1 cachedP;
147 bool cachedPaged;
148 cacheHit = ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged);
149 goto miss_ucache;
150 #else
151 if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged))
152 goto miss_ucache;
153 #endif
154
155 if (paged) {
156 finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK);
157 } else {
158 finalAddress = pageAddress + cpu.TPR.CA;
159 }
160 cpu.RSDWH_R1 = RSDWH_R1;
161
162
163
164
165 cpu.apu.lastCycle = INSTRUCTION_FETCH;
166 goto HI;
167
168 skip_ucache:;
169
170 #ifdef UCACHE_STATS
171 cpu.uCache.skips[this] ++;
172 #endif
173
174 miss_ucache:;
175
176 bool nomatch = true;
177 if (cpu.tweaks.enable_wam) {
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182
183 nomatch = ((i->opcode == 0232 || i->opcode == 0254 ||
184 i->opcode == 0154 || i->opcode == 0173) &&
185 i->opcodeX ) ||
186 ((i->opcode == 0557 || i->opcode == 0257) &&
187 ! i->opcodeX);
188 }
189
190 processor_cycle_type lastCycle = cpu.apu.lastCycle;
191 cpu.apu.lastCycle = INSTRUCTION_FETCH;
192
193 DBGAPP ("doAppendCycleInstructionFetch(Entry) XSF %o\n", cpu.cu.XSF);
194
195 PNL (L68_ (cpu.apu.state = 0;))
196
197 cpu.RSDWH_R1 = 0;
198
199 cpu.acvFaults = 0;
200
201
202 #define FMSG(x)
203 FMSG (char * acvFaultsMsg = "<unknown>";)
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216 PNL (cpu.APUMemAddr = cpu.TPR.CA;)
217
218 DBGAPP ("doAppendCycleInstructionFetch(A)\n");
219
220
221 if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
222
223 DBGAPP ("doAppendCycleInstructionFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
224
225 DBGAPP ("doAppendCycleInstructionFetch(A):DSBR.U=%o\n", cpu.DSBR.U);
226
227 if (cpu.DSBR.U == 0) {
228 fetch_dsptw (cpu.TPR.TSR);
229
230 if (! cpu.PTW0.DF)
231 doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleInstructionFetch(A): PTW0.F == 0");
232
233 if (! cpu.PTW0.U)
234 modify_dsptw (cpu.TPR.TSR);
235
236 fetch_psdw (cpu.TPR.TSR);
237 } else
238 fetch_nsdw (cpu.TPR.TSR);
239
240 if (cpu.SDW0.DF == 0) {
241 DBGAPP ("doAppendCycleInstructionFetch(A): SDW0.F == 0! " "Initiating directed fault\n");
242
243 doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0");
244 }
245
246 load_sdwam (cpu.TPR.TSR, nomatch);
247 }
248 DBGAPP ("doAppendCycleInstructionFetch(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E);
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251 RSDWH_R1 = cpu.RSDWH_R1 = cpu.SDW->R1;
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263 DBGAPP ("doAppendCycleInstructionFetch(B)\n");
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268 if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) {
269
270 cpu.acvFaults |= ACV0;
271 PNL (L68_ (cpu.apu.state |= apu_FLT;))
272 FMSG (acvFaultsMsg = "acvFaults(B) C(SDW.R1) <= C(SDW.R2) <= " "C(SDW .R3)";)
273 }
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281 if (i->opcode == 0610 && ! i->opcodeX)
282 goto C;
283
284 if (lastCycle == RTCD_OPERAND_FETCH)
285 sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\n", __func__, i->opcode);
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293 goto F;
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301 C:;
302 DBGAPP ("doAppendCycleInstructionFetch(C)\n");
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312 if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) {
313 DBGAPP ("ACV1 c\n");
314 DBGAPP ("acvFaults(C) ACV1 ! ( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2);
315
316 cpu.acvFaults |= ACV1;
317 PNL (L68_ (cpu.apu.state |= apu_FLT;))
318 FMSG (acvFaultsMsg = "acvFaults(C) C(SDW.R1 > C(TPR.TRR) > C(SDW.R2)";)
319 }
320
321 if (! cpu.SDW->E) {
322 DBGAPP ("ACV2 a\n");
323 DBGAPP ("doAppendCycleInstructionFetch(C) ACV2\n");
324
325 cpu.acvFaults |= ACV2;
326 PNL (L68_ (cpu.apu.state |= apu_FLT;))
327 FMSG (acvFaultsMsg = "acvFaults(C) SDW.E";)
328 }
329 if (cpu.TPR.TRR > cpu.PPR.PRR)
330 sim_warn ("rtcd: outbound call cpu.TPR.TRR %d cpu.PPR.PRR %d\n", cpu.TPR.TRR, cpu.PPR.PRR);
331
332 if (cpu.TPR.TRR < cpu.PPR.PRR) {
333 DBGAPP ("ACV11\n");
334 DBGAPP ("doAppendCycleInstructionFetch(C) ACV11\n");
335
336 cpu.acvFaults |= ACV11;
337 PNL (L68_ (cpu.apu.state |= apu_FLT;))
338 FMSG (acvFaultsMsg = "acvFaults(C) TRR>=PRR";)
339 }
340
341 D:;
342 DBGAPP ("doAppendCycleInstructionFetch(D)\n");
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348 if (cpu.rRALR == 0)
349 goto G;
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352 if (! (cpu.PPR.PRR < cpu.rRALR)) {
353 DBGAPP ("ACV13\n");
354 DBGAPP ("acvFaults(D) C(PPR.PRR) %o < RALR %o\n", cpu.PPR.PRR, cpu.rRALR);
355 cpu.acvFaults |= ACV13;
356 PNL (L68_ (cpu.apu.state |= apu_FLT;))
357 FMSG (acvFaultsMsg = "acvFaults(D) C(PPR.PRR) < RALR";)
358 }
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360 goto G;
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368 F:;
369 PNL (L68_ (cpu.apu.state |= apu_PIAU;))
370 DBGAPP ("doAppendCycleInstructionFetch(F): transfer or instruction fetch\n");
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377 if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) {
378 DBGAPP ("ACV1 a/b\n");
379 DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2);
380 cpu.acvFaults |= ACV1;
381 PNL (L68_ (cpu.apu.state |= apu_FLT;))
382 FMSG (acvFaultsMsg = "acvFaults(F) C(TPR.TRR) < C(SDW .R1)";)
383 }
384
385 if (! cpu.SDW->E) {
386 DBGAPP ("ACV2 c \n");
387 DBGAPP ("doAppendCycleInstructionFetch(F) ACV2\n");
388 cpu.acvFaults |= ACV2;
389 PNL (L68_ (cpu.apu.state |= apu_FLT;))
390 FMSG (acvFaultsMsg = "acvFaults(F) SDW .E set OFF";)
391 }
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394 if (cpu.PPR.PRR != cpu.TPR.TRR) {
395 DBGAPP ("ACV12\n");
396 DBGAPP ("doAppendCycleInstructionFetch(F) ACV12\n");
397
398 cpu.acvFaults |= ACV12;
399 PNL (L68_ (cpu.apu.state |= apu_FLT;))
400 FMSG (acvFaultsMsg = "acvFaults(F) C(PPR.PRR) != C(TPR.TRR)";)
401 }
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403 goto D;
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411 G:;
412
413 DBGAPP ("doAppendCycleInstructionFetch(G)\n");
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416 if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
417 DBGAPP ("ACV15\n");
418 DBGAPP ("doAppendCycleInstructionFetch(G) ACV15\n");
419 cpu.acvFaults |= ACV15;
420 PNL (L68_ (cpu.apu.state |= apu_FLT;))
421 FMSG (acvFaultsMsg = "acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND";)
422 DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
423 }
424 bound = cpu.SDW->BOUND;
425 p = cpu.SDW->P;
426
427 if (cpu.acvFaults) {
428 DBGAPP ("doAppendCycleInstructionFetch(G) acvFaults\n");
429 PNL (L68_ (cpu.apu.state |= apu_FLT;))
430
431 doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault");
432 }
433
434
435 if (cpu.SDW->U)
436 goto H;
437
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440
441 DBGAPP ("doAppendCycleInstructionFetch(G) CA %06o\n", cpu.TPR.CA);
442 if (nomatch ||
443 ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) {
444 fetch_ptw (cpu.SDW, cpu.TPR.CA);
445 if (! cpu.PTW0.DF) {
446
447 doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0");
448 }
449 loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch);
450 }
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457
458
459 if (i->opcodeX && ((i->opcode & 0770)== 0200|| (i->opcode & 0770) == 0220
460 || (i->opcode & 0770)== 020|| (i->opcode & 0770) == 0300)) {
461 do_ptw2 (cpu.SDW, cpu.TPR.CA);
462 }
463 goto I;
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471 H:;
472 DBGAPP ("doAppendCycleInstructionFetch(H): FANP\n");
473
474 paged = false;
475
476 PNL (L68_ (cpu.apu.state |= apu_FANP;))
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484
485 set_apu_status (apuStatus_FANP);
486
487 DBGAPP ("doAppendCycleInstructionFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
488
489 pageAddress = (cpu.SDW->ADDR & 077777760);
490 finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
491 finalAddress &= 0xffffff;
492 PNL (cpu.APUMemAddr = finalAddress;)
493
494 DBGAPP ("doAppendCycleInstructionFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
495
496 goto HI;
497
498 I:;
499
500
501
502 DBGAPP ("doAppendCycleInstructionFetch(I): FAP\n");
503
504 paged = true;
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507 set_apu_status (apuStatus_FAP);
508 PNL (L68_ (cpu.apu.state |= apu_FAP;))
509
510 word24 y2 = cpu.TPR.CA % 1024;
511
512 pageAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6);
513
514
515 finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2;
516 finalAddress &= 0xffffff;
517 PNL (cpu.APUMemAddr = finalAddress;)
518
519 #ifdef L68
520 if (cpu.MR_cache.emr && cpu.MR_cache.ihr)
521 add_APU_history (APUH_FAP);
522 #endif
523 DBGAPP ("doAppendCycleInstructionFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
524
525 HI:
526 DBGAPP ("doAppendCycleInstructionFetch(HI)\n");
527
528 #ifdef TEST_UCACHE
529 if (cacheHit) {
530 bool err = false;
531 if (cachedAddress != pageAddress) {
532 sim_printf ("cachedAddress %08o != pageAddress %08o\r\n", cachedAddress, pageAddress);
533 err = true;
534 }
535 if (cachedR1 != RSDWH_R1) {
536 sim_printf ("cachedR1 %01o != RSDWH_R1 %01o\r\n", cachedR1, RSDWH_R1);
537 err = true;
538 }
539 if (cachedBound != bound) {
540 sim_printf ("cachedBound %01o != bound %01o\r\n", cachedBound, bound);
541 err = true;
542 }
543 if (cachedPaged != paged) {
544 sim_printf ("cachedPaged %01o != paged %01o\r\n", cachedPaged, paged);
545 err = true;
546 }
547 if (err) {
548 # ifdef HDBG
549 HDBGPrint ();
550 # endif
551 sim_printf ("ins fetch err %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
552 exit (1);
553 }
554
555 # ifdef HDBG
556 hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
557 # endif
558 } else {
559
560 # ifdef HDBG
561 hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
562 # endif
563 }
564 #endif
565 #ifdef TEST_UCACHE
566 if (cacheHit) {
567 if (cachedPaged != paged) sim_printf ("cachedPaged %01o != paged %01o\r\n", cachedPaged, paged);
568
569 }
570 else
571 {
572
573 }
574 #endif
575
576 ucCacheSave (this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged);
577 evcnt ++;
578
579 cpu.cu.XSF = 1;
580 sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
581
582 core_readN (finalAddress, data, nWords, "INSTRUCTION_FETCH");
583
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590
591
592 DBGAPP ("doAppendCycleInstructionFetch(L)\n");
593
594
595
596 if (i->opcode == 0610 && ! i->opcodeX) {
597
598
599 CPTUR (cptUsePRn + 0);
600 CPTUR (cptUsePRn + 1);
601 CPTUR (cptUsePRn + 2);
602 CPTUR (cptUsePRn + 3);
603 CPTUR (cptUsePRn + 4);
604 CPTUR (cptUsePRn + 5);
605 CPTUR (cptUsePRn + 6);
606 CPTUR (cptUsePRn + 7);
607 cpu.PR[0].RNR =
608 cpu.PR[1].RNR =
609 cpu.PR[2].RNR =
610 cpu.PR[3].RNR =
611 cpu.PR[4].RNR =
612 cpu.PR[5].RNR =
613 cpu.PR[6].RNR =
614 cpu.PR[7].RNR = cpu.TPR.TRR;
615 #ifdef TESTING
616 HDBGRegPRW (0, "app rtcd");
617 HDBGRegPRW (1, "app rtcd");
618 HDBGRegPRW (2, "app rtcd");
619 HDBGRegPRW (3, "app rtcd");
620 HDBGRegPRW (4, "app rtcd");
621 HDBGRegPRW (5, "app rtcd");
622 HDBGRegPRW (6, "app rtcd");
623 HDBGRegPRW (7, "app rtcd");
624 #endif
625 }
626 goto KL;
627
628 KL:
629 DBGAPP ("doAppendCycleInstructionFetch(KL)\n");
630
631
632 cpu.PPR.PSR = cpu.TPR.TSR;
633
634 cpu.PPR.IC = cpu.TPR.CA;
635
636 goto M;
637
638 M:
639 DBGAPP ("doAppendCycleInstructionFetch(M)\n");
640
641
642 if (cpu.TPR.TRR == 0) {
643
644
645 cpu.PPR.P = p;
646 } else {
647
648 cpu.PPR.P = 0;
649 }
650
651 PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
652 PNL (cpu.APUDataBusAddr = finalAddress;)
653
654 PNL (L68_ (cpu.apu.state |= apu_FA;))
655
656 DBGAPP ("doAppendCycleInstructionFetch (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
657 DBGAPP ("doAppendCycleInstructionFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
658
659 return finalAddress;
660 }
661 #undef TEST_UCACHE