TRR 30 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 143 src/dps8/doAppendCycleABSA.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 154 src/dps8/doAppendCycleABSA.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 283 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 28 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 157 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 168 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 190 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 193 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TRR > cpu.SDW->R1) { TRR 194 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1); TRR 203 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 349 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 28 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 152 src/dps8/doAppendCycleAPUDataRead.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 163 src/dps8/doAppendCycleAPUDataRead.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 300 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 28 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 155 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 158 src/dps8/doAppendCycleAPUDataStore.h if (cpu.TPR.TRR > cpu.SDW->R1) { TRR 159 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1); TRR 168 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 303 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 64 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 248 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 259 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 437 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(O) TRR %o RSDWH.R1 %o ITS.RNR %o\n", cpu.TPR.TRR, cpu.RSDWH_R1, its_RNR); TRR 441 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = max3 (its_RNR, cpu.TPR.TRR, cpu.RSDWH_R1); TRR 442 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(O) Set TRR to %o\n", cpu.TPR.TRR); TRR 451 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(P) TRR %o RSDWH.R1 %o PR[n].RNR %o\n", cpu.TPR.TRR, cpu.RSDWH_R1, cpu.PR[n].RNR); TRR 455 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.TPR.TRR, cpu.RSDWH_R1); TRR 456 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(P) Set TRR to %o\n", cpu.TPR.TRR); TRR 468 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 75 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 312 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) { TRR 314 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(C) ACV1 ! ( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TRR 329 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR > cpu.PPR.PRR) TRR 330 src/dps8/doAppendCycleInstructionFetch.h sim_warn ("rtcd: outbound call cpu.TPR.TRR %d cpu.PPR.PRR %d\n", cpu.TPR.TRR, cpu.PPR.PRR); TRR 332 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.PPR.PRR) { TRR 377 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) { TRR 379 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TRR 394 src/dps8/doAppendCycleInstructionFetch.h if (cpu.PPR.PRR != cpu.TPR.TRR) { TRR 614 src/dps8/doAppendCycleInstructionFetch.h cpu.PR[7].RNR = cpu.TPR.TRR; TRR 642 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR == 0) { TRR 657 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 28 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 157 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 168 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 190 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 193 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TRR > cpu.SDW->R1) { TRR 194 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1); TRR 203 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 354 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 70 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 317 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 328 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 386 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(E): E %o G %o PSR %05o TSR %05o CA %06o " "EB %06o R %o%o%o TRR %o PRR %o\n", cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu.SDW->EB, cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.TPR.TRR, cpu.PPR.PRR); TRR 422 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.SDW->R3) { TRR 432 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR < cpu.SDW->R1) { TRR 442 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.PPR.PRR) { TRR 454 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o SDW->R2 %o\n", cpu.TPR.TRR, cpu.SDW->R2); TRR 457 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 459 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TRR = cpu.SDW->R2; TRR 462 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o\n", cpu.TPR.TRR); TRR 482 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) { TRR 484 src/dps8/doAppendCycleOperandRead.h DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TRR 499 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PRR != cpu.TPR.TRR) { TRR 747 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR == 0) { TRR 761 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR == cpu.PPR.PRR) { TRR 767 src/dps8/doAppendCycleOperandRead.h cpu.PR[7].SNR = ((word15) (cpu.DSBR.STACK << 3)) | cpu.TPR.TRR; TRR 768 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(N) STACK %05o TRR %o\n", cpu.DSBR.STACK, cpu.TPR.TRR); TRR 773 src/dps8/doAppendCycleOperandRead.h cpu.PR[7].RNR = cpu.TPR.TRR; TRR 782 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PRR = cpu.TPR.TRR; TRR 798 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 28 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 150 src/dps8/doAppendCycleOperandStore.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 153 src/dps8/doAppendCycleOperandStore.h if (cpu.TPR.TRR > cpu.SDW->R1) { TRR 154 src/dps8/doAppendCycleOperandStore.h DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1); TRR 163 src/dps8/doAppendCycleOperandStore.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 306 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 28 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TRR 89 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("RTCD_OPERAND_FETCH ABSOLUTE mode set TSR %05o TRR %o\n", cpu.TPR.TSR, cpu.TPR.TRR); TRR 181 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.TPR.TRR > cpu.SDW->R2) { TRR 192 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TRR = cpu.PPR.PRR; TRR 352 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1); TRR 376 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.TPR.TRR == 0) { TRR 392 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 225 src/dps8/dps8_addrmods.c cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.RSDWH_R1, cpu.TPR.TRR); TRR 264 src/dps8/dps8_addrmods.c GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR, TRR 265 src/dps8/dps8_addrmods.c max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR)); TRR 267 src/dps8/dps8_addrmods.c cpu.TPR.TRR = max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR); TRR 1211 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.TPR.TSR); TRR 1281 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.TRR); TRR 1433 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R2) TRR 1446 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1480 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1483 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R1) TRR 1486 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.SDW->R1); TRR 1496 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1525 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.SDW->R1 || TRR 1526 src/dps8/dps8_append.c cpu.TPR.TRR > cpu.SDW->R2) TRR 1530 src/dps8/dps8_append.c cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TRR 1546 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.PPR.PRR) TRR 1548 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.PPR.PRR); TRR 1550 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.PPR.PRR) TRR 1601 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.PPR.PRR); TRR 1639 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R3) TRR 1650 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.SDW->R1) TRR 1661 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.PPR.PRR) TRR 1677 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.SDW->R2); TRR 1680 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R2) TRR 1683 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.SDW->R2; TRR 1686 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(E1): CALL6 TPR.TRR %o\n", cpu.TPR.TRR); TRR 1706 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.SDW->R1 || TRR 1707 src/dps8/dps8_append.c cpu.TPR.TRR > cpu.SDW->R2) TRR 1711 src/dps8/dps8_append.c cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TRR 1727 src/dps8/dps8_append.c if (cpu.PPR.PRR != cpu.TPR.TRR) TRR 2034 src/dps8/dps8_append.c cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1); TRR 2097 src/dps8/dps8_append.c cpu.PR[7].RNR = cpu.TPR.TRR; TRR 2125 src/dps8/dps8_append.c if (cpu.TPR.TRR == 0) TRR 2142 src/dps8/dps8_append.c if (cpu.TPR.TRR == cpu.PPR.PRR) TRR 2151 src/dps8/dps8_append.c cpu.PR[7].SNR = ((word15) (cpu.DSBR.STACK << 3)) | cpu.TPR.TRR; TRR 2153 src/dps8/dps8_append.c cpu.DSBR.STACK, cpu.TPR.TRR); TRR 2158 src/dps8/dps8_append.c cpu.PR[7].RNR = cpu.TPR.TRR; TRR 2167 src/dps8/dps8_append.c cpu.PPR.PRR = cpu.TPR.TRR; TRR 2185 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.RSDWH_R1, its_RNR); TRR 2189 src/dps8/dps8_append.c cpu.TPR.TRR = max3 (its_RNR, cpu.TPR.TRR, cpu.RSDWH_R1); TRR 2190 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(O) Set TRR to %o\n", cpu.TPR.TRR); TRR 2200 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.RSDWH_R1, cpu.PR[n].RNR); TRR 2204 src/dps8/dps8_append.c cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.TPR.TRR, cpu.RSDWH_R1); TRR 2205 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(P) Set TRR to %o\n", cpu.TPR.TRR); TRR 2219 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TRR 2407 src/dps8/dps8_cpu.c cpu.TPR.TRR = 0; TRR 2684 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 2699 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 2767 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 3060 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 3187 src/dps8/dps8_cpu.c cpu.TPR.TRR = 0; TRR 4473 src/dps8/dps8_cpu.c putbits36_3 (& w1, 24, cpu.TPR.TRR); TRR 81 src/dps8/dps8_cpu.h word3 TRR; // The current effective ring number TRR 563 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; TRR 569 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; TRR 583 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TRR 595 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 611 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TRR 621 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; TRR 627 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; TRR 646 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; TRR 650 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TRR 665 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 671 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TRR 686 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; TRR 805 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; TRR 809 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; TRR 832 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 846 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; TRR 867 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; TRR 871 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; TRR 894 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 908 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; TRR 1276 src/dps8/dps8_eis.c cpu.TPR.TRR, TRR 1425 src/dps8/dps8_eis.c e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TRR 1630 src/dps8/dps8_eis.c e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TRR 1682 src/dps8/dps8_eis.c e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TRR 1864 src/dps8/dps8_eis.c e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TRR 121 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 196 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 258 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 322 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 384 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 448 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 510 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 585 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 670 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 752 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 830 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 867 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 942 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1038 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1162 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1254 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1316 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1382 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1460 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1533 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1607 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1702 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1831 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 383 src/dps8/dps8_ins.c putbits36_3 (& words[2], 0, cpu.TPR.TRR); TRR 637 src/dps8/dps8_ins.c cpu.TPR.TRR = getbits36_3 (words[2], 0); TRR 1097 src/dps8/dps8_ins.c cpu.TPR.TRR = 0; TRR 1834 src/dps8/dps8_ins.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 1886 src/dps8/dps8_ins.c cpu.TPR.TRR = max (cpu.PAR[n].RNR, cpu.PPR.PRR); TRR 1888 src/dps8/dps8_ins.c cpu.TPR.TRR = max3 (cpu.PAR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TRR 1890 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, "doPtrReg: n=%o offset=%05o TPR.CA=%06o " "TPR.TBR=%o TPR.TSR=%05o TPR.TRR=%o\n", n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR); TRR 1908 src/dps8/dps8_ins.c cpu.TPR.TRR = 0; TRR 1998 src/dps8/dps8_ins.c cpu.TPR.TRR = cpu.PPR.PRR; TRR 2630 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.TPR.TRR; TRR 2808 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.TPR.TRR; TRR 2942 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.TPR.TRR; TRR 3351 src/dps8/dps8_ins.c cpu.rA = cpu.TPR.TRR & MASK3; TRR 6586 src/dps8/dps8_ins.c cpu.PR[n].RNR = max3 (Crr, cpu.SDW->R1, cpu.TPR.TRR); TRR 31 src/dps8/dps8_mp.h word3 TRR; TRR 4152 src/dps8/dps8_sys.c { "cpus[].TPR.TRR", SYM_STRUCT_OFFSET, SYM_UINT8_3, offsetof (struct tpr_s, TRR) },