IC 282 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 348 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 299 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 302 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 467 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 634 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.IC = cpu.TPR.CA; IC 656 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 353 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 726 src/dps8/doAppendCycleOperandRead.h cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; IC 739 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; IC 786 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; IC 797 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 305 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 368 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.IC = cpu.TPR.CA; IC 391 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 87 src/dps8/dps8_addrmods.c return cpu.PPR.IC; IC 2068 src/dps8/dps8_append.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; IC 2117 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; IC 2171 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; IC 2217 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 946 src/dps8/dps8_cpu.c cpu.PPR.IC = 0; IC 1657 src/dps8/dps8_cpu.c { ORDATA (IC, dummy_IC, VASIZE), 0, 0, 0 }, IC 1659 src/dps8/dps8_cpu.c { ORDATA (IC, cpus[0].PPR.IC, VASIZE), 0, 0, 0 }, IC 1793 src/dps8/dps8_cpu.c sim_brk_test ((cpu.PPR.IC & 0777777) | IC 2194 src/dps8/dps8_cpu.c cpus [0].PPR.IC = dummy_IC; IC 2509 src/dps8/dps8_cpu.c get_BAR_address (cpu.PPR.IC); IC 2532 src/dps8/dps8_cpu.c (cpu.PPR.IC & 1) == 0 && IC 2549 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 1) IC 2702 src/dps8/dps8_cpu.c fetchInstruction (cpu.PPR.IC); IC 2721 src/dps8/dps8_cpu.c stall_points[i].offset && stall_points[i].offset == cpu.PPR.IC) IC 2998 src/dps8/dps8_cpu.c (cpu.cu.rd && (cpu.PPR.IC & 1)) || IC 3003 src/dps8/dps8_cpu.c -- cpu.PPR.IC; IC 3024 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3025 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3071 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3073 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3096 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 0 && IC 3100 src/dps8/dps8_cpu.c (cpu.PPR.IC & ~3u) != (cpu.last_write & ~3u)) IC 3102 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3109 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3111 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3126 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3127 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3340 src/dps8/dps8_cpu.c dummy_IC = cpu.PPR.IC; IC 3555 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); IC 3562 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, addr, IC 3596 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3639 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3663 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3679 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3721 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3759 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); IC 3766 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3777 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3796 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); IC 3803 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3814 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3855 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3878 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 4393 src/dps8/dps8_cpu.c putbits36_18 (& w1, 54 - 36, cpu.PPR.IC); IC 100 src/dps8/dps8_cpu.h word18 IC; // The word offset from the origin of the procedure segment IC 1036 src/dps8/dps8_cpu.h #define USE_IRODD (cpu.cu.rd && ((cpu. PPR.IC & 1) != 0)) IC 1654 src/dps8/dps8_cpu.h word18 IC; IC 353 src/dps8/dps8_eis.c return cpu.PPR.IC; IC 450 src/dps8/dps8_eis.c return cpu.PPR.IC; IC 525 src/dps8/dps8_eis.c return cpu.PPR.IC; IC 381 src/dps8/dps8_faults.c sim_printf (" TRO PSR:IC %05o:%06o\r\n", cpu.PPR.PSR, cpu.PPR.IC); IC 386 src/dps8/dps8_faults.c sim_printf (" ACV %012llo PSR:IC %05o:%06o\r\n", subFault.bits, cpu.PPR.PSR, cpu.PPR.IC); IC 418 src/dps8/dps8_faults.c fault_ic = cpu . PPR.IC; IC 690 src/dps8/dps8_faults.c cpu . PPR.IC); IC 834 src/dps8/dps8_faults.c cpu.PPR.IC); IC 138 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) IC 207 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 270 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 333 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 395 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 459 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 521 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 1061 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) IC 1186 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) IC 281 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; IC 287 src/dps8/dps8_ins.c cpu.PPR.IC = cpu.TPR.CA; IC 292 src/dps8/dps8_ins.c __func__, cpu.PPR.PSR, cpu.PPR.IC); IC 293 src/dps8/dps8_ins.c if (cpu.PPR.IC & 1) IC 403 src/dps8/dps8_ins.c putbits36_18 (& words[4], 0, cpu.PPR.IC); IC 549 src/dps8/dps8_ins.c cpu.cu_data.IC = cpu.PPR.IC; IC 660 src/dps8/dps8_ins.c cpu.PPR.IC = getbits36_18 (words[4], 0); IC 1102 src/dps8/dps8_ins.c if (cpu.cu.rd && ((cpu.PPR.IC & 1) != 0)) IC 1138 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) // Even IC 1165 src/dps8/dps8_ins.c char * where = lookup_address (cpu.PPR.PSR, cpu.PPR.IC, & compname, IC 1175 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); IC 1179 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o %s\n", cpu.PPR.IC, where); IC 1188 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); IC 1193 src/dps8/dps8_ins.c cpu.PPR.PSR, cpu.PPR.IC, where); IC 1207 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1224 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1246 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1264 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1316 src/dps8/dps8_ins.c trk (cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IWB_IRODD); IC 1476 src/dps8/dps8_ins.c if (!cpu.cu.xde && cpu.cu.xdo /* odd instr being executed */ && !(cpu.PPR.IC & 1)) IC 1482 src/dps8/dps8_ins.c if (opcode == 0560 && !opcodeX && cpu.cu.xde && !(cpu.PPR.IC & 1)) IC 1672 src/dps8/dps8_ins.c if (n_dbgevents && (dbgevt = (dbgevent_lookup (cpu.PPR.PSR, cpu.PPR.IC))) >= 0) { IC 1763 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD first %d rpt %d rd %d e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], !! (cpu.rX[0] & 01000), !! (cpu.rX[0] & 0400)); IC 1773 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); IC 1844 src/dps8/dps8_ins.c word18 saveIC = cpu.PPR.IC; IC 1846 src/dps8/dps8_ins.c ReadInstructionFetch (cpu.PPR.IC + 1 + n, & cpu.currentEISinstruction.op[n]); IC 1847 src/dps8/dps8_ins.c cpu.PPR.IC = saveIC; IC 2010 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); IC 2231 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPPPR, &cpu_dev, "PRR:%o PSR:%05o P:%o IC:%06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 2902 src/dps8/dps8_ins.c word18 ret = (cpu.PPR.IC + 1) & MASK18; IC 3786 src/dps8/dps8_ins.c SETHI (cpu.CY, (cpu.PPR.IC + 1) & MASK18); IC 3799 src/dps8/dps8_ins.c cpu.CY = ((word36) ((cpu.PPR.IC + 2) & MASK18)) << 18; IC 3870 src/dps8/dps8_ins.c putbits36_18 (& cpu.Ypair[1], 0, cpu.PPR.IC + 2); IC 3880 src/dps8/dps8_ins.c putbits36_18 (& cpu.Ypair[1], 0, cpu.cu_data.IC + 2); IC 6143 src/dps8/dps8_ins.c cpu.PPR.IC = GETHI (cpu.CY); IC 6930 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) IC 7233 src/dps8/dps8_ins.c sim_printf (" ldt %d PSR:IC %05o:%06o\r\n", cpu.rTR, cpu.PPR.PSR, cpu.PPR.IC); IC 7284 src/dps8/dps8_ins.c sim_printf (" RALR set to %o PSR:IC %05o:%06o\r\n", cpu.rRALR, cpu.PPR.PSR, cpu.PPR.IC); IC 8350 src/dps8/dps8_ins.c " no events in queue\n", cpu.PPR.IC); IC 8367 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 0430 && cpu.PPR.IC == 012) IC 8397 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 034 && cpu.PPR.IC == 03535) IC 9429 src/dps8/dps8_ins.c sim_printf (" rcu to %05o:%06o PSR:IC %05o:%06o\r\n", (cpu.Yblock8[0]>>18)&MASK15, (cpu.Yblock8[4]>>18)&MASK18, cpu.PPR.PSR, cpu.PPR.IC); IC 3472 src/dps8/dps8_iom.c __func__, iomChar (iom_unit_idx), cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC); IC 2777 src/dps8/dps8_sys.c word18 icOffset = cpu.PPR.IC; IC 4119 src/dps8/dps8_sys.c { "cpus[].PPR.IC", SYM_STRUCT_OFFSET, SYM_UINT32_18, offsetof (struct ppr_s, IC) }, IC 168 src/dps8/hdbg.c if (filter && hdbgSegNum > 0 && blacklist[cpu.PPR.IC]) \ IC 190 src/dps8/hdbg.c hevents[p].trace.ic = cpu.PPR.IC;