cachedR1 144 src/dps8/doAppendCycleInstructionFetch.h word3 cachedR1; cachedR1 148 src/dps8/doAppendCycleInstructionFetch.h cacheHit = ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); cachedR1 535 src/dps8/doAppendCycleInstructionFetch.h if (cachedR1 != RSDWH_R1) { cachedR1 536 src/dps8/doAppendCycleInstructionFetch.h sim_printf ("cachedR1 %01o != RSDWH_R1 %01o\r\n", cachedR1, RSDWH_R1); cachedR1 133 src/dps8/doAppendCycleOperandRead.h word3 cachedR1; cachedR1 137 src/dps8/doAppendCycleOperandRead.h cacheHit = ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); cachedR1 139 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "test cache check %s %d %u %05o:%06o %05o %o %08o %o %o", cacheHit ? "hit" : "miss", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, cachedBound, cachedP, cachedAddress, cachedR1, cachedPaged); cachedR1 644 src/dps8/doAppendCycleOperandRead.h if (cachedR1 != RSDWH_R1) { cachedR1 645 src/dps8/doAppendCycleOperandRead.h sim_printf ("cachedR1 %01o != RSDWH_R1 %01o\r\n", cachedR1, RSDWH_R1);