cu 53 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) XSF %o\n", cpu.cu.XSF); cu 51 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) XSF %o\n", cpu.cu.XSF); cu 331 src/dps8/doAppendCycleAPUDataRMW.h cpu.cu.XSF = 1; cu 51 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) XSF %o\n", cpu.cu.XSF); cu 287 src/dps8/doAppendCycleAPUDataRead.h cpu.cu.XSF = 1; cu 51 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) XSF %o\n", cpu.cu.XSF); cu 292 src/dps8/doAppendCycleAPUDataStore.h cpu.cu.XSF = 1; cu 136 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) XSF %o\n", cpu.cu.XSF); cu 402 src/dps8/doAppendCycleIndirectWordFetch.h cpu.cu.XSF = 1; cu 193 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) XSF %o\n", cpu.cu.XSF); cu 579 src/dps8/doAppendCycleInstructionFetch.h cpu.cu.XSF = 1; cu 51 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) XSF %o\n", cpu.cu.XSF); cu 330 src/dps8/doAppendCycleOperandRMW.h cpu.cu.XSF = 1; cu 197 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) XSF %o\n", cpu.cu.XSF); cu 684 src/dps8/doAppendCycleOperandRead.h cpu.cu.XSF = 1; cu 51 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) XSF %o\n", cpu.cu.XSF); cu 290 src/dps8/doAppendCycleOperandStore.h cpu.cu.XSF = 1; cu 51 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) XSF %o\n", cpu.cu.XSF); cu 87 src/dps8/doAppendCycleRTCDOperandFetch.h if (get_addr_mode() == ABSOLUTE_mode && ! (cpu.cu.XSF || cpu.currentInstruction.b29)) { cu 285 src/dps8/doAppendCycleRTCDOperandFetch.h if (get_addr_mode () == ABSOLUTE_mode && ! (cpu.cu.XSF || cpu.currentInstruction.b29)) { cu 327 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.cu.XSF = 1; cu 233 src/dps8/dps8_addrmods.c cpu.cu.itp = 1; cu 234 src/dps8/dps8_addrmods.c cpu.cu.TSN_PRNO[0] = n; cu 235 src/dps8/dps8_addrmods.c cpu.cu.TSN_VALID[0] = 1; cu 276 src/dps8/dps8_addrmods.c cpu.cu.its = 1; cu 317 src/dps8/dps8_addrmods.c cpu.cu.XSF = 1; cu 325 src/dps8/dps8_addrmods.c wb = & cpu.cu.IRODD; cu 327 src/dps8/dps8_addrmods.c wb = & cpu.cu.IWB; cu 382 src/dps8/dps8_addrmods.c __func__, cpu.cu.CT_HOLD); cu 414 src/dps8/dps8_addrmods.c if (cpu.cu.CT_HOLD) cu 418 src/dps8/dps8_addrmods.c __func__, cpu.cu.CT_HOLD); cu 421 src/dps8/dps8_addrmods.c GET_TM(cpu.cu.CT_HOLD) == TM_IT && GET_TD (cpu.cu.CT_HOLD) == IT_DIC && cu 422 src/dps8/dps8_addrmods.c cpu.cu.pot == 1 && GET_ADDR (IWB_IRODD) == cpu.TPR.CA) cu 429 src/dps8/dps8_addrmods.c cpu.cu.pot = 1; cu 435 src/dps8/dps8_addrmods.c cpu.cu.its = 0; cu 436 src/dps8/dps8_addrmods.c cpu.cu.itp = 0; cu 437 src/dps8/dps8_addrmods.c cpu.cu.pot = 0; cu 441 src/dps8/dps8_addrmods.c __func__, cpu.rTAG, get_mod_string (buf, cpu.rTAG), Tm, Td, cpu.cu.CT_HOLD); cu 485 src/dps8/dps8_addrmods.c if (cpu.cu.rpt || cpu.cu.rd | cpu.cu.rl) cu 532 src/dps8/dps8_addrmods.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) cu 561 src/dps8/dps8_addrmods.c if (GET_TM(cpu.cu.CT_HOLD) == TM_IR) cu 587 src/dps8/dps8_addrmods.c if (!(cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) cu 620 src/dps8/dps8_addrmods.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) cu 632 src/dps8/dps8_addrmods.c "IR_MOD: CT_HOLD=%o %o\n", cpu.cu.CT_HOLD, Td); cu 650 src/dps8/dps8_addrmods.c cpu.cu.CT_HOLD = cpu.rTAG; cu 671 src/dps8/dps8_addrmods.c "IR_MOD: CT_HOLD=%o\n", cpu.cu.CT_HOLD); cu 687 src/dps8/dps8_addrmods.c Td, cpu.cu.CT_HOLD); cu 726 src/dps8/dps8_addrmods.c word6 Td_hold = GET_TD (cpu.cu.CT_HOLD); cu 948 src/dps8/dps8_addrmods.c cpu.cu.pot = 1; cu 965 src/dps8/dps8_addrmods.c cpu.cu.pot = 0; cu 1367 src/dps8/dps8_addrmods.c cpu.cu.pot = 0; cu 1421 src/dps8/dps8_addrmods.c cpu.cu.CT_HOLD = cpu.rTAG; cu 1479 src/dps8/dps8_addrmods.c cpu.cu.pot = 0; cu 1535 src/dps8/dps8_addrmods.c cpu.cu.CT_HOLD = cpu.rTAG; cu 65 src/dps8/dps8_append.c cu 66 src/dps8/dps8_append.c cu 68 src/dps8/dps8_append.c cu 69 src/dps8/dps8_append.c cu 70 src/dps8/dps8_append.c cu 71 src/dps8/dps8_append.c cu 72 src/dps8/dps8_append.c cu 73 src/dps8/dps8_append.c cu 74 src/dps8/dps8_append.c cu 75 src/dps8/dps8_append.c cu 76 src/dps8/dps8_append.c cu 80 src/dps8/dps8_append.c cu 86 src/dps8/dps8_append.c cu 89 src/dps8/dps8_append.c cu 92 src/dps8/dps8_append.c cu 98 src/dps8/dps8_append.c cu 101 src/dps8/dps8_append.c cu 104 src/dps8/dps8_append.c cu 107 src/dps8/dps8_append.c cu 110 src/dps8/dps8_append.c cu 176 src/dps8/dps8_append.c if (cpu.cu.SD_ON) cu 189 src/dps8/dps8_append.c if (cpu.cu.PT_ON) cu 341 src/dps8/dps8_append.c if ((! cpu.tweaks.enable_wam || ! cpu.cu.SD_ON)) { cu 353 src/dps8/dps8_append.c cpu.cu.SDWAMM = 1; cu 388 src/dps8/dps8_append.c cpu.cu.SDWAMM = 1; cu 411 src/dps8/dps8_append.c cpu.cu.SDWAMM = 0; cu 598 src/dps8/dps8_append.c if (nomatch || (! cpu.tweaks.enable_wam) || (! cpu.cu.SD_ON)) cu 683 src/dps8/dps8_append.c if ((! cpu.tweaks.enable_wam) || (! cpu.cu.PT_ON)) cu 699 src/dps8/dps8_append.c cpu.cu.PTWAMM = 1; cu 739 src/dps8/dps8_append.c cpu.cu.PTWAMM = 1; cu 758 src/dps8/dps8_append.c cpu.cu.PTWAMM = 0; cu 833 src/dps8/dps8_append.c if (nomatch || (! cpu.tweaks.enable_wam) || (! cpu.cu.PT_ON)) cu 1238 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(Entry) XSF %o\n", cpu.cu.XSF); cu 1277 src/dps8/dps8_append.c ! (cpu.cu.XSF || cpu.currentInstruction.b29) /*get_went_appending()*/) cu 1833 src/dps8/dps8_append.c ! (cpu.cu.XSF || cpu.currentInstruction.b29) /*get_went_appending ()*/) cu 1895 src/dps8/dps8_append.c cpu.cu.XSF = 1; cu 121 src/dps8/dps8_append.h word12 FCT = cpu.cu.APUCycleBits & MASK3; cu 122 src/dps8/dps8_append.h cpu.cu.APUCycleBits = (status & 07770) | FCT; cu 964 src/dps8/dps8_cpu.c cpu.cu.SD_ON = cpu.switches.sdwam_enable ? 1 : 0; cu 965 src/dps8/dps8_cpu.c cpu.cu.PT_ON = cpu.switches.ptwam_enable ? 1 : 0; cu 971 src/dps8/dps8_cpu.c cpu.cu.IWB = 0000000616000; //-V536 // Stuff DIS instruction in instruction buffer cu 1836 src/dps8/dps8_cpu.c cpu.cu.IWB = cpu.switches.data_switches; cu 2158 src/dps8/dps8_cpu.c cpu.cu.XSF = false; cu 2167 src/dps8/dps8_cpu.c return cpu.cu.XSF; cu 2396 src/dps8/dps8_cpu.c cpu.cu.FI_ADDR = (word5) (intr_pair_addr / 2); cu 2432 src/dps8/dps8_cpu.c & cpu.cu.IWB, & cpu.cu.IRODD, __func__); cu 2434 src/dps8/dps8_cpu.c HDBGMRead (intr_pair_addr, cpu.cu.IWB, "intr even"); cu 2435 src/dps8/dps8_cpu.c HDBGMRead (intr_pair_addr + 1, cpu.cu.IRODD, "intr odd"); cu 2437 src/dps8/dps8_cpu.c cpu.cu.xde = 1; cu 2438 src/dps8/dps8_cpu.c cpu.cu.xdo = 1; cu 2518 src/dps8/dps8_cpu.c !(is_dis && GET_I (cpu.cu.IWB) == 0); cu 2528 src/dps8/dps8_cpu.c else if (! (cpu.cu.xde | cpu.cu.xdo | cu 2529 src/dps8/dps8_cpu.c cpu.cu.rpt | cpu.cu.rd | cpu.cu.rl)) cu 2681 src/dps8/dps8_cpu.c cpu.cu.XSF = 0; cu 2682 src/dps8/dps8_cpu.c cpu.cu.TSN_VALID [0] = 0; cu 2695 src/dps8/dps8_cpu.c cpu.cu.XSF = 0; cu 2697 src/dps8/dps8_cpu.c cpu.cu.TSN_VALID [0] = 0; cu 2736 src/dps8/dps8_cpu.c if (GET_I (cpu.cu.IWB)) cu 2761 src/dps8/dps8_cpu.c if (cpu.cu.xdo) cu 2764 src/dps8/dps8_cpu.c cpu.cu.XSF = 0; cu 2765 src/dps8/dps8_cpu.c cpu.cu.TSN_VALID [0] = 0; cu 2774 src/dps8/dps8_cpu.c cpu.cu.xde = cpu.cu.xdo = 0; cu 2814 src/dps8/dps8_cpu.c if (TST_I_ABS && cpu.cu.XSF) cu 2996 src/dps8/dps8_cpu.c if ((! cpu.cu.repeat_first) && cu 2997 src/dps8/dps8_cpu.c (cpu.cu.rpt || cu 2998 src/dps8/dps8_cpu.c (cpu.cu.rd && (cpu.PPR.IC & 1)) || cu 2999 src/dps8/dps8_cpu.c cpu.cu.rl)) cu 3002 src/dps8/dps8_cpu.c if (cpu.cu.rd) cu 3011 src/dps8/dps8_cpu.c !cpu.cu.xde && cpu.cu.xdo) cu 3033 src/dps8/dps8_cpu.c !cpu.cu.xde && cpu.cu.xdo) cu 3050 src/dps8/dps8_cpu.c if (cpu.cu.xde && cpu.cu.xdo) cu 3053 src/dps8/dps8_cpu.c cpu.cu.IWB = cpu.cu.IRODD; cu 3054 src/dps8/dps8_cpu.c cpu.cu.xde = 0; cu 3057 src/dps8/dps8_cpu.c cpu.cu.XSF = 0; cu 3058 src/dps8/dps8_cpu.c cpu.cu.TSN_VALID [0] = 0; cu 3064 src/dps8/dps8_cpu.c if (cpu.cu.xde || cpu.cu.xdo) // we are in an XEC/XED cu 3066 src/dps8/dps8_cpu.c cpu.cu.xde = cpu.cu.xdo = 0; cu 3083 src/dps8/dps8_cpu.c cpu.cu.xde = cpu.cu.xdo = 0; cu 3098 src/dps8/dps8_cpu.c !cpu.cu.repeat_first && !cpu.cu.rpt && !cpu.cu.rd && !cpu.cu.rl && cu 3104 src/dps8/dps8_cpu.c cpu.cu.IWB = cpu.cu.IRODD; cu 3157 src/dps8/dps8_cpu.c if ((cpu.cu.APUCycleBits & 060) || cpu.secret_addressing_mode) cu 3170 src/dps8/dps8_cpu.c if (cpu.faultNumber != FAULT_TRB || cpu.cu.xde == 0) cu 3210 src/dps8/dps8_cpu.c core_read2 (addr, & cpu.cu.IWB, & cpu.cu.IRODD, __func__); cu 3212 src/dps8/dps8_cpu.c HDBGMRead (addr, cpu.cu.IWB, "fault even"); cu 3213 src/dps8/dps8_cpu.c HDBGMRead (addr + 1, cpu.cu.IRODD, "fault odd"); cu 3215 src/dps8/dps8_cpu.c cpu.cu.xde = 1; cu 3216 src/dps8/dps8_cpu.c cpu.cu.xdo = 1; cu 4239 src/dps8/dps8_cpu.c putbits36_1 (& w0, 9, cpu.cu.xde); cu 4241 src/dps8/dps8_cpu.c putbits36_1 (& w0, 10, cpu.cu.xdo); cu 4245 src/dps8/dps8_cpu.c putbits36_1 (& w0, 12, cpu.cu.rpt); cu 4254 src/dps8/dps8_cpu.c putbits36_1 (& w0, 17, TSTF (cpu.cu.IR, I_NBAR)?1:0); cu 4460 src/dps8/dps8_cpu.c putbits36_1 (& w0, 25, cpu.cu.SDWAMM); cu 4464 src/dps8/dps8_cpu.c putbits36_1 (& w0, 30, cpu.cu.PTWAMM); cu 1036 src/dps8/dps8_cpu.h #define USE_IRODD (cpu.cu.rd && ((cpu. PPR.IC & 1) != 0)) cu 1037 src/dps8/dps8_cpu.h #define IWB_IRODD (USE_IRODD ? cpu.cu.IRODD : cpu.cu.IWB) cu 1595 src/dps8/dps8_cpu.h ctl_unit_data_t cu; cu 571 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cu 597 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cu 648 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cu 667 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cu 811 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cu 834 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cu 873 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cu 896 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cu 1165 src/dps8/dps8_eis.c e -> MF1 = getbits36_7 (cpu.cu.IWB, 29); cu 1170 src/dps8/dps8_eis.c e -> MF2 = getbits36_7 (cpu.cu.IWB, 11); cu 1175 src/dps8/dps8_eis.c e -> MF3 = getbits36_7 (cpu.cu.IWB, 2); cu 1272 src/dps8/dps8_eis.c cpu.cu.TSN_PRNO[k-1] = n; cu 1273 src/dps8/dps8_eis.c cpu.cu.TSN_VALID[k-1] = 1; cu 1422 src/dps8/dps8_eis.c cpu.cu.TSN_PRNO[k-1] = n; cu 1423 src/dps8/dps8_eis.c cpu.cu.TSN_VALID[k-1] = 1; cu 1627 src/dps8/dps8_eis.c cpu.cu.TSN_PRNO[k-1] = n; cu 1628 src/dps8/dps8_eis.c cpu.cu.TSN_VALID[k-1] = 1; cu 1679 src/dps8/dps8_eis.c cpu.cu.TSN_PRNO[k-1] = n; cu 1680 src/dps8/dps8_eis.c cpu.cu.TSN_VALID[k-1] = 1; cu 1861 src/dps8/dps8_eis.c cpu.cu.TSN_PRNO[k-1] = n; cu 1862 src/dps8/dps8_eis.c cpu.cu.TSN_VALID[k-1] = 1; cu 1959 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cu 1961 src/dps8/dps8_eis.c int32_t address = SIGNEXT15_32 (GET_OFFSET (cpu.cu.IWB)); cu 1965 src/dps8/dps8_eis.c word4 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except cu 1974 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cu 2041 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cu 2043 src/dps8/dps8_eis.c int32_t address = SIGNEXT15_32 (GET_OFFSET (cpu.cu.IWB)); cu 2044 src/dps8/dps8_eis.c word4 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except cu 2051 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cu 2088 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cu 2090 src/dps8/dps8_eis.c int32_t address = SIGNEXT15_32 (GET_OFFSET (cpu.cu.IWB)); cu 2091 src/dps8/dps8_eis.c word6 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except cu 2111 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cu 2119 src/dps8/dps8_eis.c if (sz == 9 || GET_A (cpu.cu.IWB)) cu 2157 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cu 2160 src/dps8/dps8_eis.c word18 address = SIGNEXT15_18 (GET_OFFSET (cpu.cu.IWB)); cu 2163 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); cu 2176 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cu 2216 src/dps8/dps8_eis.c cu 2218 src/dps8/dps8_eis.c cu 2225 src/dps8/dps8_eis.c cu 2245 src/dps8/dps8_eis.c cu 2266 src/dps8/dps8_eis.c cu 2359 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cu 2361 src/dps8/dps8_eis.c int32_t address = SIGNEXT15_32 (GET_OFFSET (cpu.cu.IWB)); cu 2364 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); cu 2374 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cu 2398 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cu 2400 src/dps8/dps8_eis.c word18 address = SIGNEXT15_18 (GET_OFFSET (cpu.cu.IWB)); cu 2401 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); cu 2407 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cu 2434 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cu 2436 src/dps8/dps8_eis.c int32_t address = SIGNEXT15_32 (GET_OFFSET (cpu.cu.IWB)); cu 2439 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); cu 2448 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cu 2472 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cu 2474 src/dps8/dps8_eis.c word18 address = SIGNEXT15_18 (GET_OFFSET (cpu.cu.IWB)); cu 2477 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); cu 2486 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cu 2756 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cu 2757 src/dps8/dps8_eis.c uint address = SIGNEXT15_18 (GET_OFFSET (cpu.cu.IWB)); cu 2758 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); // 4-bit register modification (None except cu 2792 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cu 3028 src/dps8/dps8_eis.c word9 fill = getbits36_9 (cpu.cu.IWB, 0); cu 3548 src/dps8/dps8_eis.c uint mask = (uint) getbits36_9 (cpu.cu.IWB, 0); cu 3720 src/dps8/dps8_eis.c uint mask = (uint) getbits36_9 (cpu.cu.IWB, 0); cu 4382 src/dps8/dps8_eis.c word1 T = getbits36_1 (cpu.cu.IWB, 9); cu 4384 src/dps8/dps8_eis.c word9 fill = getbits36_9 (cpu.cu.IWB, 0); cu 4780 src/dps8/dps8_eis.c word1 T = getbits36_1 (cpu.cu.IWB, 9); cu 4782 src/dps8/dps8_eis.c word9 fill = getbits36_9 (cpu.cu.IWB, 0); cu 7164 src/dps8/dps8_eis.c word1 T = getbits36_1 (cpu.cu.IWB, 9); cu 7166 src/dps8/dps8_eis.c word9 fill = getbits36_9 (cpu.cu.IWB, 0); cu 7645 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character cu 7647 src/dps8/dps8_eis.c word1 T = getbits36_1 (cpu.cu.IWB, 9); cu 7648 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cu 8018 src/dps8/dps8_eis.c bool F = getbits36_1 (cpu.cu.IWB, 0) != 0; // fill bit cu 8019 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // T (enablefault) bit cu 8021 src/dps8/dps8_eis.c uint BOLR = getbits36_4 (cpu.cu.IWB, 5); // T (enablefault) bit cu 8315 src/dps8/dps8_eis.c bool F = getbits36_1 (cpu.cu.IWB, 0) != 0; // fill bit cu 8316 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // T (enablefault) bit cu 8318 src/dps8/dps8_eis.c uint BOLR = getbits36_4 (cpu.cu.IWB, 5); // T (enablefault) bit cu 8503 src/dps8/dps8_eis.c bool F = getbits36_1 (cpu.cu.IWB, 0) != 0; // fill bit cu 8504 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // T (enablefault) bit cu 8506 src/dps8/dps8_eis.c uint BOLR = getbits36_4 (cpu.cu.IWB, 5); // T (enablefault) bit cu 8702 src/dps8/dps8_eis.c bool F = getbits36_1 (cpu.cu.IWB, 0) != 0; // fill bit cu 8703 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // T (enablefault) bit cu 8705 src/dps8/dps8_eis.c uint BOLR = getbits36_4 (cpu.cu.IWB, 5); // T (enablefault) bit cu 8885 src/dps8/dps8_eis.c bool F = getbits36_1 (cpu.cu.IWB, 0) != 0; // fill bit cu 9532 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cu 10140 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cu 10141 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // truncation bit cu 10142 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cu 10491 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cu 10492 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // truncation bit cu 10493 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cu 10834 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cu 10835 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // truncation bit cu 10836 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cu 11144 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cu 11145 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // truncation bit cu 11146 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cu 11473 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cu 11474 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // truncation bit cu 11475 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cu 11743 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cu 11744 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // truncation bit cu 11745 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cu 12796 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cu 12798 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cu 13187 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cu 13189 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cu 442 src/dps8/dps8_faults.c word3 FCT = cpu.cu.APUCycleBits & MASK3; cu 444 src/dps8/dps8_faults.c cpu.cu.APUCycleBits = (word12) ((cpu.cu.APUCycleBits & 07770) | FCT); cu 501 src/dps8/dps8_faults.c cpu . cu . IRO_ISN = 0; cu 502 src/dps8/dps8_faults.c cpu . cu . OEB_IOC = 0; cu 503 src/dps8/dps8_faults.c cpu . cu . EOFF_IAIM = 0; cu 504 src/dps8/dps8_faults.c cpu . cu . ORB_ISP = 0; cu 505 src/dps8/dps8_faults.c cpu . cu . ROFF_IPR = 0; cu 506 src/dps8/dps8_faults.c cpu . cu . OWB_NEA = 0; cu 507 src/dps8/dps8_faults.c cpu . cu . WOFF_OOB = 0; cu 508 src/dps8/dps8_faults.c cpu . cu . NO_GA = 0; cu 509 src/dps8/dps8_faults.c cpu . cu . OCB = 0; cu 510 src/dps8/dps8_faults.c cpu . cu . OCALL = 0; cu 511 src/dps8/dps8_faults.c cpu . cu . BOC = 0; cu 512 src/dps8/dps8_faults.c DPS8M_ (cpu . cu . PTWAM_ER = 0;) cu 513 src/dps8/dps8_faults.c cpu . cu . CRT = 0; cu 514 src/dps8/dps8_faults.c cpu . cu . RALR = 0; cu 515 src/dps8/dps8_faults.c cpu . cu . SDWAM_ER = 0; cu 516 src/dps8/dps8_faults.c cpu . cu . OOSB = 0; cu 517 src/dps8/dps8_faults.c cpu . cu . PARU = 0; cu 518 src/dps8/dps8_faults.c cpu . cu . PARL = 0; cu 519 src/dps8/dps8_faults.c cpu . cu . ONC1 = 0; cu 520 src/dps8/dps8_faults.c cpu . cu . ONC2 = 0; cu 521 src/dps8/dps8_faults.c cpu . cu . IA = 0; cu 522 src/dps8/dps8_faults.c cpu . cu . IACHN = 0; cu 523 src/dps8/dps8_faults.c cpu . cu . CNCHN = (faultNumber == FAULT_CON) ? subFault.fault_con_subtype & MASK3 : 0; cu 526 src/dps8/dps8_faults.c cpu . cu . FIF = cpu . cycle == FETCH_cycle ? 1 : 0; cu 527 src/dps8/dps8_faults.c cpu . cu . FI_ADDR = (word5) faultNumber; cu 533 src/dps8/dps8_faults.c cpu . cu . rfi = 0; cu 567 src/dps8/dps8_faults.c cpu . cu . IRO_ISN = 1; cu 569 src/dps8/dps8_faults.c cpu . cu . OEB_IOC = 1; cu 571 src/dps8/dps8_faults.c cpu . cu . EOFF_IAIM = 1; cu 573 src/dps8/dps8_faults.c cpu . cu . ORB_ISP = 1; cu 575 src/dps8/dps8_faults.c cpu . cu . ROFF_IPR = 1; cu 577 src/dps8/dps8_faults.c cpu . cu . OWB_NEA = 1; cu 579 src/dps8/dps8_faults.c cpu . cu . WOFF_OOB = 1; cu 581 src/dps8/dps8_faults.c cpu . cu . NO_GA = 1; cu 583 src/dps8/dps8_faults.c cpu . cu . OCB = 1; cu 585 src/dps8/dps8_faults.c cpu . cu . OCALL = 1; cu 587 src/dps8/dps8_faults.c cpu . cu . BOC = 1; cu 589 src/dps8/dps8_faults.c cpu . cu . PTWAM_ER = 1; cu 591 src/dps8/dps8_faults.c cpu . cu . CRT = 1; cu 593 src/dps8/dps8_faults.c cpu . cu . RALR = 1; cu 595 src/dps8/dps8_faults.c cpu . cu . SDWAM_ER = 1; cu 597 src/dps8/dps8_faults.c cpu . cu . OOSB = 1; cu 602 src/dps8/dps8_faults.c cpu . cu . WOFF_OOB = 1; cu 606 src/dps8/dps8_faults.c cpu . cu . OWB_NEA = 1; cu 611 src/dps8/dps8_faults.c cpu . cu . OEB_IOC = 1; cu 613 src/dps8/dps8_faults.c cpu . cu . EOFF_IAIM = 1; cu 615 src/dps8/dps8_faults.c cpu . cu . ORB_ISP = 1; cu 617 src/dps8/dps8_faults.c cpu . cu . ROFF_IPR = 1; cu 622 src/dps8/dps8_faults.c cpu . cu . IA = 0; cu 624 src/dps8/dps8_faults.c cpu . cu . IA = 010; cu 677 src/dps8/dps8_faults.c cpu.cu.FI_ADDR = FAULT_TRB; cu 750 src/dps8/dps8_faults.c word3 FCT = cpu.cu.APUCycleBits & MASK3; cu 752 src/dps8/dps8_faults.c cpu.cu.APUCycleBits = (word12) ((cpu.cu.APUCycleBits & 07770) | FCT); cu 760 src/dps8/dps8_faults.c cpu.cu.IRO_ISN = 0; cu 761 src/dps8/dps8_faults.c cpu.cu.OEB_IOC = 0; cu 762 src/dps8/dps8_faults.c cpu.cu.EOFF_IAIM = 0; cu 763 src/dps8/dps8_faults.c cpu.cu.ORB_ISP = 0; cu 764 src/dps8/dps8_faults.c cpu.cu.ROFF_IPR = 0; cu 765 src/dps8/dps8_faults.c cpu.cu.OWB_NEA = 0; cu 766 src/dps8/dps8_faults.c cpu.cu.WOFF_OOB = 0; cu 767 src/dps8/dps8_faults.c cpu.cu.NO_GA = 0; cu 768 src/dps8/dps8_faults.c cpu.cu.OCB = 0; cu 769 src/dps8/dps8_faults.c cpu.cu.OCALL = 0; cu 770 src/dps8/dps8_faults.c cpu.cu.BOC = 0; cu 775 src/dps8/dps8_faults.c cpu.cu.CRT = 0; cu 776 src/dps8/dps8_faults.c cpu.cu.RALR = 0; cu 777 src/dps8/dps8_faults.c cpu.cu.SDWAM_ER = 0; cu 778 src/dps8/dps8_faults.c cpu.cu.OOSB = 0; cu 779 src/dps8/dps8_faults.c cpu.cu.PARU = 0; cu 780 src/dps8/dps8_faults.c cpu.cu.PARL = 0; cu 781 src/dps8/dps8_faults.c cpu.cu.ONC1 = 0; cu 782 src/dps8/dps8_faults.c cpu.cu.ONC2 = 0; cu 783 src/dps8/dps8_faults.c cpu.cu.IA = 0; cu 784 src/dps8/dps8_faults.c cpu.cu.IACHN = 0; cu 785 src/dps8/dps8_faults.c cpu.cu.CNCHN = 0; cu 788 src/dps8/dps8_faults.c cpu.cu.FIF = 0; cu 789 src/dps8/dps8_faults.c cpu.cu.FI_ADDR = (word5) fault_number & MASK5; cu 795 src/dps8/dps8_faults.c cpu.cu.rfi = 0; cu 821 src/dps8/dps8_faults.c cpu.cu.FI_ADDR = FAULT_TRB; cu 584 src/dps8/dps8_hw_consts.h # define CLR_I_ABS CLRF (cpu.cu.IR, I_ABS) cu 585 src/dps8/dps8_hw_consts.h # define CLR_I_MIF CLRF (cpu.cu.IR, I_MIF) cu 586 src/dps8/dps8_hw_consts.h # define CLR_I_TRUNC CLRF (cpu.cu.IR, I_TRUNC) cu 587 src/dps8/dps8_hw_consts.h # define CLR_I_NBAR CLRF (cpu.cu.IR, I_NBAR) cu 588 src/dps8/dps8_hw_consts.h # define CLR_I_TALLY CLRF (cpu.cu.IR, I_TALLY) cu 589 src/dps8/dps8_hw_consts.h # define CLR_I_PMASK CLRF (cpu.cu.IR, I_PMASK) cu 590 src/dps8/dps8_hw_consts.h # define CLR_I_EOFL CLRF (cpu.cu.IR, I_EOFL) cu 591 src/dps8/dps8_hw_consts.h # define CLR_I_EUFL CLRF (cpu.cu.IR, I_EUFL) cu 592 src/dps8/dps8_hw_consts.h # define CLR_I_OFLOW CLRF (cpu.cu.IR, I_OFLOW) cu 593 src/dps8/dps8_hw_consts.h # define CLR_I_CARRY CLRF (cpu.cu.IR, I_CARRY) cu 594 src/dps8/dps8_hw_consts.h # define CLR_I_NEG CLRF (cpu.cu.IR, I_NEG) cu 595 src/dps8/dps8_hw_consts.h # define CLR_I_ZERO CLRF (cpu.cu.IR, I_ZERO) cu 597 src/dps8/dps8_hw_consts.h # define SET_I_ABS SETF (cpu.cu.IR, I_ABS) cu 598 src/dps8/dps8_hw_consts.h # define SET_I_NBAR SETF (cpu.cu.IR, I_NBAR) cu 599 src/dps8/dps8_hw_consts.h # define SET_I_TRUNC SETF (cpu.cu.IR, I_TRUNC) cu 600 src/dps8/dps8_hw_consts.h # define SET_I_TALLY SETF (cpu.cu.IR, I_TALLY) cu 601 src/dps8/dps8_hw_consts.h # define SET_I_EOFL SETF (cpu.cu.IR, I_EOFL) cu 602 src/dps8/dps8_hw_consts.h # define SET_I_EUFL SETF (cpu.cu.IR, I_EUFL) cu 603 src/dps8/dps8_hw_consts.h # define SET_I_OFLOW SETF (cpu.cu.IR, I_OFLOW) cu 604 src/dps8/dps8_hw_consts.h # define SET_I_CARRY SETF (cpu.cu.IR, I_CARRY) cu 605 src/dps8/dps8_hw_consts.h # define SET_I_NEG SETF (cpu.cu.IR, I_NEG) cu 606 src/dps8/dps8_hw_consts.h # define SET_I_ZERO SETF (cpu.cu.IR, I_ZERO) cu 608 src/dps8/dps8_hw_consts.h # define TST_I_ABS TSTF (cpu.cu.IR, I_ABS) cu 609 src/dps8/dps8_hw_consts.h # define TST_I_MIF TSTF (cpu.cu.IR, I_MIF) cu 610 src/dps8/dps8_hw_consts.h # define TST_I_NBAR TSTF (cpu.cu.IR, I_NBAR) cu 611 src/dps8/dps8_hw_consts.h # define TST_I_PMASK TSTF (cpu.cu.IR, I_PMASK) cu 612 src/dps8/dps8_hw_consts.h # define TST_I_TRUNC TSTF (cpu.cu.IR, I_TRUNC) cu 613 src/dps8/dps8_hw_consts.h # define TST_I_TALLY TSTF (cpu.cu.IR, I_TALLY) cu 614 src/dps8/dps8_hw_consts.h # define TST_I_OMASK TSTF (cpu.cu.IR, I_OMASK) cu 615 src/dps8/dps8_hw_consts.h # define TST_I_EUFL TSTF (cpu.cu.IR, I_EUFL ) cu 616 src/dps8/dps8_hw_consts.h # define TST_I_EOFL TSTF (cpu.cu.IR, I_EOFL ) cu 617 src/dps8/dps8_hw_consts.h # define TST_I_OFLOW TSTF (cpu.cu.IR, I_OFLOW) cu 618 src/dps8/dps8_hw_consts.h # define TST_I_CARRY TSTF (cpu.cu.IR, I_CARRY) cu 619 src/dps8/dps8_hw_consts.h # define TST_I_NEG TSTF (cpu.cu.IR, I_NEG) cu 620 src/dps8/dps8_hw_consts.h # define TST_I_ZERO TSTF (cpu.cu.IR, I_ZERO) cu 621 src/dps8/dps8_hw_consts.h # define TST_I_HEX TSTF (cpu.cu.IR, I_HEX) cu 623 src/dps8/dps8_hw_consts.h # define SC_I_HEX(v) SCF (v, cpu.cu.IR, I_HEX) // DPS8M only cu 624 src/dps8/dps8_hw_consts.h # define SC_I_MIF(v) SCF (v, cpu.cu.IR, I_MIF) cu 625 src/dps8/dps8_hw_consts.h # define SC_I_TALLY(v) SCF (v, cpu.cu.IR, I_TALLY) cu 626 src/dps8/dps8_hw_consts.h # define SC_I_NEG(v) SCF (v, cpu.cu.IR, I_NEG) cu 627 src/dps8/dps8_hw_consts.h # define SC_I_ZERO(v) SCF (v, cpu.cu.IR, I_ZERO) cu 628 src/dps8/dps8_hw_consts.h # define SC_I_CARRY(v) SCF (v, cpu.cu.IR, I_CARRY); cu 629 src/dps8/dps8_hw_consts.h # define SC_I_OFLOW(v) SCF (v, cpu.cu.IR, I_OFLOW); cu 630 src/dps8/dps8_hw_consts.h # define SC_I_EOFL(v) SCF (v, cpu.cu.IR, I_EOFL); cu 631 src/dps8/dps8_hw_consts.h # define SC_I_EUFL(v) SCF (v, cpu.cu.IR, I_EUFL); cu 632 src/dps8/dps8_hw_consts.h # define SC_I_OMASK(v) SCF (v, cpu.cu.IR, I_OMASK); cu 633 src/dps8/dps8_hw_consts.h # define SC_I_PERR(v) SCF (v, cpu.cu.IR, I_PERR); cu 634 src/dps8/dps8_hw_consts.h # define SC_I_PMASK(v) SCF (v, cpu.cu.IR, I_PMASK); cu 635 src/dps8/dps8_hw_consts.h # define SC_I_TRUNC(v) SCF (v, cpu.cu.IR, I_TRUNC); cu 60 src/dps8/dps8_iefp.c if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29)) cu 162 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cu 224 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cu 288 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cu 350 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cu 414 src/dps8/dps8_iefp.c if (cpu.cu.XSF) cu 476 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cu 541 src/dps8/dps8_iefp.c if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29) || cyctyp == RTCD_OPERAND_FETCH) // ISOLTS-886 cu 627 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cu 709 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cu 787 src/dps8/dps8_iefp.c if (cpu.cu.XSF) cu 899 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cu 978 src/dps8/dps8_iefp.c if (isAR || cpu.cu.XSF /*get_went_appending ()*/) cu 1102 src/dps8/dps8_iefp.c if (isAR || cpu.cu.XSF /*get_went_appending ()*/) cu 1214 src/dps8/dps8_iefp.c if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29)) cu 1282 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cu 1342 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cu 1410 src/dps8/dps8_iefp.c if (cpu.cu.XSF /*get_went_appending ()*/ || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29)) cu 1497 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cu 1561 src/dps8/dps8_iefp.c if (isAR || cpu.cu.XSF /*get_went_appending ()*/) cu 1645 src/dps8/dps8_iefp.c if (isAR || cpu.cu.XSF /*get_went_appending ()*/) cu 1774 src/dps8/dps8_iefp.c if (isAR || cpu.cu.XSF /*get_went_appending ()*/) cu 101 src/dps8/dps8_ins.c rTAG = GET_TAG (cpu.cu.IWB); cu 182 src/dps8/dps8_ins.c rTAG = GET_TAG (cpu.cu.IWB); cu 261 src/dps8/dps8_ins.c if (! (get_addr_mode () == APPEND_mode || cpu.cu.TSN_VALID [0] || cu 262 src/dps8/dps8_ins.c cpu.cu.XSF || cpu.currentInstruction.b29 /*get_went_appending ()*/)) cu 295 src/dps8/dps8_ins.c cpu.cu.IWB = cpu.CY; cu 296 src/dps8/dps8_ins.c cpu.cu.IRODD = cpu.CY; cu 300 src/dps8/dps8_ins.c cpu.cu.IWB = cpu.Ypair[0]; cu 301 src/dps8/dps8_ins.c cpu.cu.IRODD = cpu.Ypair[1]; cu 329 src/dps8/dps8_ins.c putbits36_1 (& words[0], 19, cpu.cu.XSF); cu 331 src/dps8/dps8_ins.c putbits36_1 (& words[0], 21, cpu.cu.SD_ON); cu 333 src/dps8/dps8_ins.c putbits36_1 (& words[0], 23, cpu.cu.PT_ON); cu 335 src/dps8/dps8_ins.c cu 336 src/dps8/dps8_ins.c cu 337 src/dps8/dps8_ins.c cu 338 src/dps8/dps8_ins.c cu 339 src/dps8/dps8_ins.c cu 340 src/dps8/dps8_ins.c cu 341 src/dps8/dps8_ins.c cu 342 src/dps8/dps8_ins.c cu 343 src/dps8/dps8_ins.c cu 350 src/dps8/dps8_ins.c putbits36_12 (& words[0], 24, cpu.cu.APUCycleBits); cu 355 src/dps8/dps8_ins.c putbits36_1 (& words[1], 0, cpu.cu.IRO_ISN); cu 356 src/dps8/dps8_ins.c putbits36_1 (& words[1], 1, cpu.cu.OEB_IOC); cu 357 src/dps8/dps8_ins.c putbits36_1 (& words[1], 2, cpu.cu.EOFF_IAIM); cu 358 src/dps8/dps8_ins.c putbits36_1 (& words[1], 3, cpu.cu.ORB_ISP); cu 359 src/dps8/dps8_ins.c putbits36_1 (& words[1], 4, cpu.cu.ROFF_IPR); cu 360 src/dps8/dps8_ins.c putbits36_1 (& words[1], 5, cpu.cu.OWB_NEA); cu 361 src/dps8/dps8_ins.c putbits36_1 (& words[1], 6, cpu.cu.WOFF_OOB); cu 362 src/dps8/dps8_ins.c putbits36_1 (& words[1], 7, cpu.cu.NO_GA); cu 363 src/dps8/dps8_ins.c putbits36_1 (& words[1], 8, cpu.cu.OCB); cu 364 src/dps8/dps8_ins.c putbits36_1 (& words[1], 9, cpu.cu.OCALL); cu 365 src/dps8/dps8_ins.c putbits36_1 (& words[1], 10, cpu.cu.BOC); cu 366 src/dps8/dps8_ins.c putbits36_1 (& words[1], 11, cpu.cu.PTWAM_ER); cu 367 src/dps8/dps8_ins.c putbits36_1 (& words[1], 12, cpu.cu.CRT); cu 368 src/dps8/dps8_ins.c putbits36_1 (& words[1], 13, cpu.cu.RALR); cu 369 src/dps8/dps8_ins.c putbits36_1 (& words[1], 14, cpu.cu.SDWAM_ER); cu 370 src/dps8/dps8_ins.c putbits36_1 (& words[1], 15, cpu.cu.OOSB); cu 371 src/dps8/dps8_ins.c putbits36_1 (& words[1], 16, cpu.cu.PARU); cu 372 src/dps8/dps8_ins.c putbits36_1 (& words[1], 17, cpu.cu.PARL); cu 373 src/dps8/dps8_ins.c putbits36_1 (& words[1], 18, cpu.cu.ONC1); cu 374 src/dps8/dps8_ins.c putbits36_1 (& words[1], 19, cpu.cu.ONC2); cu 375 src/dps8/dps8_ins.c putbits36_4 (& words[1], 20, cpu.cu.IA); cu 376 src/dps8/dps8_ins.c putbits36_3 (& words[1], 24, cpu.cu.IACHN); cu 377 src/dps8/dps8_ins.c putbits36_3 (& words[1], 27, cpu.cu.CNCHN); cu 378 src/dps8/dps8_ins.c putbits36_5 (& words[1], 30, cpu.cu.FI_ADDR); cu 389 src/dps8/dps8_ins.c putbits36_6 (& words[2], 30, cpu.cu.delta); cu 393 src/dps8/dps8_ins.c putbits36_3 (& words[3], 18, cpu.cu.TSN_VALID[0] ? cpu.cu.TSN_PRNO[0] : 0); cu 394 src/dps8/dps8_ins.c putbits36_1 (& words[3], 21, cpu.cu.TSN_VALID[0]); cu 395 src/dps8/dps8_ins.c putbits36_3 (& words[3], 22, cpu.cu.TSN_VALID[1] ? cpu.cu.TSN_PRNO[1] : 0); cu 396 src/dps8/dps8_ins.c putbits36_1 (& words[3], 25, cpu.cu.TSN_VALID[1]); cu 397 src/dps8/dps8_ins.c putbits36_3 (& words[3], 26, cpu.cu.TSN_VALID[2] ? cpu.cu.TSN_PRNO[2] : 0); cu 398 src/dps8/dps8_ins.c putbits36_1 (& words[3], 29, cpu.cu.TSN_VALID[2]); cu 407 src/dps8/dps8_ins.c putbits36_18 (& words[4], 18, cpu.cu.IR); cu 445 src/dps8/dps8_ins.c putbits36 (& words[5], 18, 1, cpu.cu.repeat_first); cu 446 src/dps8/dps8_ins.c putbits36 (& words[5], 19, 1, cpu.cu.rpt); cu 447 src/dps8/dps8_ins.c putbits36 (& words[5], 20, 1, cpu.cu.rd); cu 448 src/dps8/dps8_ins.c putbits36 (& words[5], 21, 1, cpu.cu.rl); cu 449 src/dps8/dps8_ins.c putbits36 (& words[5], 22, 1, cpu.cu.pot); cu 451 src/dps8/dps8_ins.c putbits36_1 (& words[5], 24, cpu.cu.xde); cu 452 src/dps8/dps8_ins.c putbits36_1 (& words[5], 25, cpu.cu.xdo); cu 453 src/dps8/dps8_ins.c putbits36_1 (& words[5], 26, cpu.cu.itp); cu 454 src/dps8/dps8_ins.c putbits36_1 (& words[5], 27, cpu.cu.rfi); cu 455 src/dps8/dps8_ins.c putbits36_1 (& words[5], 28, cpu.cu.its); cu 456 src/dps8/dps8_ins.c putbits36_1 (& words[5], 29, cpu.cu.FIF); cu 457 src/dps8/dps8_ins.c putbits36_6 (& words[5], 30, cpu.cu.CT_HOLD); cu 461 src/dps8/dps8_ins.c words[6] = cpu.cu.IWB; cu 465 src/dps8/dps8_ins.c words[7] = cpu.cu.IRODD; cu 561 src/dps8/dps8_ins.c cpu.cu.delta = 0; cu 562 src/dps8/dps8_ins.c cpu.cu.repeat_first = false; cu 563 src/dps8/dps8_ins.c cpu.cu.rpt = false; cu 564 src/dps8/dps8_ins.c cpu.cu.rd = false; cu 565 src/dps8/dps8_ins.c cpu.cu.rl = false; cu 566 src/dps8/dps8_ins.c cpu.cu.pot = false; cu 567 src/dps8/dps8_ins.c cpu.cu.itp = false; cu 568 src/dps8/dps8_ins.c cpu.cu.its = false; cu 569 src/dps8/dps8_ins.c cpu.cu.xde = false; cu 570 src/dps8/dps8_ins.c cpu.cu.xdo = false; cu 583 src/dps8/dps8_ins.c cpu.cu.XSF = getbits36_1 (words[0], 19); cu 584 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s sets XSF to %o\n", __func__, cpu.cu.XSF); cu 603 src/dps8/dps8_ins.c cpu.cu.APUCycleBits = (word12) ((cpu.cu.APUCycleBits & 07770) | (word12) getbits36_3 (words[0], 33)); cu 608 src/dps8/dps8_ins.c cu 609 src/dps8/dps8_ins.c cu 610 src/dps8/dps8_ins.c cu 611 src/dps8/dps8_ins.c cu 612 src/dps8/dps8_ins.c cu 613 src/dps8/dps8_ins.c cu 614 src/dps8/dps8_ins.c cu 615 src/dps8/dps8_ins.c cu 616 src/dps8/dps8_ins.c cu 617 src/dps8/dps8_ins.c cu 618 src/dps8/dps8_ins.c cu 619 src/dps8/dps8_ins.c cu 620 src/dps8/dps8_ins.c cu 621 src/dps8/dps8_ins.c cu 622 src/dps8/dps8_ins.c cu 623 src/dps8/dps8_ins.c cu 624 src/dps8/dps8_ins.c cu 625 src/dps8/dps8_ins.c cu 626 src/dps8/dps8_ins.c cu 627 src/dps8/dps8_ins.c cu 628 src/dps8/dps8_ins.c cu 629 src/dps8/dps8_ins.c cu 630 src/dps8/dps8_ins.c cu 631 src/dps8/dps8_ins.c cu 632 src/dps8/dps8_ins.c cu 643 src/dps8/dps8_ins.c cpu.cu.delta = getbits36_6 (words[2], 30); cu 649 src/dps8/dps8_ins.c cpu.cu.TSN_PRNO[0] = getbits36_3 (words[3], 18); cu 650 src/dps8/dps8_ins.c cpu.cu.TSN_VALID[0] = getbits36_1 (words[3], 21); cu 651 src/dps8/dps8_ins.c cpu.cu.TSN_PRNO[1] = getbits36_3 (words[3], 22); cu 652 src/dps8/dps8_ins.c cpu.cu.TSN_VALID[1] = getbits36_1 (words[3], 25); cu 653 src/dps8/dps8_ins.c cpu.cu.TSN_PRNO[2] = getbits36_3 (words[3], 26); cu 654 src/dps8/dps8_ins.c cpu.cu.TSN_VALID[2] = getbits36_1 (words[3], 29); cu 659 src/dps8/dps8_ins.c cpu.cu.IR = getbits36_18 (words[4], 18); // HWR cu 666 src/dps8/dps8_ins.c cpu.cu.repeat_first = getbits36_1 (words[5], 18); cu 667 src/dps8/dps8_ins.c cpu.cu.rpt = getbits36_1 (words[5], 19); cu 668 src/dps8/dps8_ins.c cpu.cu.rd = getbits36_1 (words[5], 20); cu 669 src/dps8/dps8_ins.c cpu.cu.rl = getbits36_1 (words[5], 21); cu 670 src/dps8/dps8_ins.c cpu.cu.pot = getbits36_1 (words[5], 22); cu 672 src/dps8/dps8_ins.c cpu.cu.xde = getbits36_1 (words[5], 24); cu 673 src/dps8/dps8_ins.c cpu.cu.xdo = getbits36_1 (words[5], 25); cu 674 src/dps8/dps8_ins.c cpu.cu.itp = getbits36_1 (words[5], 26); cu 675 src/dps8/dps8_ins.c cpu.cu.rfi = getbits36_1 (words[5], 27); cu 676 src/dps8/dps8_ins.c cpu.cu.its = getbits36_1 (words[5], 28); cu 677 src/dps8/dps8_ins.c cpu.cu.FIF = getbits36_1 (words[5], 29); cu 678 src/dps8/dps8_ins.c cpu.cu.CT_HOLD = getbits36_6 (words[5], 30); cu 682 src/dps8/dps8_ins.c cpu.cu.IWB = words[6]; cu 686 src/dps8/dps8_ins.c cpu.cu.IRODD = words[7]; cu 1102 src/dps8/dps8_ins.c if (cpu.cu.rd && ((cpu.PPR.IC & 1) != 0)) cu 1104 src/dps8/dps8_ins.c if (cpu.cu.repeat_first) cu 1110 src/dps8/dps8_ins.c else if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) cu 1112 src/dps8/dps8_ins.c if (cpu.cu.repeat_first) cu 1116 src/dps8/dps8_ins.c ReadInstructionFetch (addr, & cpu.cu.IWB); cu 1123 src/dps8/dps8_ins.c cpu.cu.IWB = tmp[0]; cu 1124 src/dps8/dps8_ins.c cpu.cu.IRODD = tmp[1]; cu 1144 src/dps8/dps8_ins.c cpu.cu.IWB = tmp[0]; cu 1145 src/dps8/dps8_ins.c cpu.cu.IRODD = tmp[1]; cu 1149 src/dps8/dps8_ins.c ReadInstructionFetch (addr, & cpu.cu.IWB); cu 1150 src/dps8/dps8_ins.c cpu.cu.IRODD = cpu.cu.IWB; cu 1284 src/dps8/dps8_ins.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) cu 1300 src/dps8/dps8_ins.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) cu 1380 src/dps8/dps8_ins.c const bool restart = cpu.cu.rfi; // instruction is to be restarted cu 1381 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cu 1428 src/dps8/dps8_ins.c cpu.cu.TSN_VALID[0] = 0; cu 1429 src/dps8/dps8_ins.c cpu.cu.TSN_VALID[1] = 0; cu 1430 src/dps8/dps8_ins.c cpu.cu.TSN_VALID[2] = 0; cu 1431 src/dps8/dps8_ins.c cpu.cu.TSN_PRNO[0] = 0; cu 1432 src/dps8/dps8_ins.c cpu.cu.TSN_PRNO[1] = 0; cu 1433 src/dps8/dps8_ins.c cpu.cu.TSN_PRNO[2] = 0; cu 1443 src/dps8/dps8_ins.c cpu.cu.XSF = 0; cu 1445 src/dps8/dps8_ins.c cpu.cu.pot = 0; cu 1446 src/dps8/dps8_ins.c cpu.cu.its = 0; cu 1447 src/dps8/dps8_ins.c cpu.cu.itp = 0; cu 1454 src/dps8/dps8_ins.c cpu.cu.APUCycleBits &= 07770; cu 1466 src/dps8/dps8_ins.c if (opcode == 0717 && !opcodeX && cpu.cu.xde && cpu.cu.xdo /* even instruction being executed */) cu 1472 src/dps8/dps8_ins.c if (cpu.cu.xde && cpu.cu.xdo /* even instr being executed */) cu 1476 src/dps8/dps8_ins.c if (!cpu.cu.xde && cpu.cu.xdo /* odd instr being executed */ && !(cpu.PPR.IC & 1)) cu 1482 src/dps8/dps8_ins.c if (opcode == 0560 && !opcodeX && cpu.cu.xde && !(cpu.PPR.IC & 1)) cu 1492 src/dps8/dps8_ins.c if (unlikely (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) { cu 1499 src/dps8/dps8_ins.c if (cpu.cu.rl) cu 1525 src/dps8/dps8_ins.c if (unlikely (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) { cu 1530 src/dps8/dps8_ins.c if (unlikely (cpu.cu.rl)) { cu 1704 src/dps8/dps8_ins.c if (unlikely (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) { cu 1763 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD first %d rpt %d rd %d e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], !! (cpu.rX[0] & 01000), !! (cpu.rX[0] & 0400)); cu 1768 src/dps8/dps8_ins.c if (cpu.cu.repeat_first) { cu 1777 src/dps8/dps8_ins.c if (cpu.cu.rpt || (cpu.cu.rd && icOdd) || cpu.cu.rl) cu 1778 src/dps8/dps8_ins.c cpu.cu.repeat_first = false; cu 1783 src/dps8/dps8_ins.c if (cpu.cu.rpt || // rpt cu 1784 src/dps8/dps8_ins.c (cpu.cu.rd && icEven) || // rpd & even cu 1785 src/dps8/dps8_ins.c (cpu.cu.rd && icOdd) || // rpd & odd cu 1786 src/dps8/dps8_ins.c cpu.cu.rl) { // rl cu 1904 src/dps8/dps8_ins.c cpu.cu.TSN_VALID [0] = 0; cu 1916 src/dps8/dps8_ins.c cpu.cu.CT_HOLD = 0; // Clear interrupted IR mode flag cu 1938 src/dps8/dps8_ins.c if (cpu.cu.rl) { cu 2019 src/dps8/dps8_ins.c bool rf = cpu.cu.repeat_first; cu 2020 src/dps8/dps8_ins.c if (rf && cpu.cu.rd && icEven) cu 2023 src/dps8/dps8_ins.c if (unlikely ((! rf) && (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl))) { cu 2029 src/dps8/dps8_ins.c if (cpu.cu.rpt || cpu.cu.rd) { cu 2035 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta first %d rf %d rpt %d rd %d " "e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, rf, cpu.cu.rpt, cpu.cu.rd, icOdd, cpu.rX[0], rptA, rptB); cu 2037 src/dps8/dps8_ins.c if (cpu.cu.rpt) { // rpt cu 2039 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IWB, 36 - 3); cu 2040 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; cu 2052 src/dps8/dps8_ins.c if (cpu.cu.rd && icOdd && rptA) { // rpd, even instruction cu 2055 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IWB, 36 - 3); cu 2056 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; cu 2064 src/dps8/dps8_ins.c if (cpu.cu.rd && icOdd && rptB) { // rpdb, odd instruction cu 2067 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IRODD, 36 - 3); cu 2068 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; cu 2092 src/dps8/dps8_ins.c flt = (cpu.cu.rl || cpu.cu.rpt || cpu.cu.rd) && cpu.dlyFlt; // L68 cu 2094 src/dps8/dps8_ins.c flt = cpu.cu.rl && cpu.dlyFlt; cu 2104 src/dps8/dps8_ins.c if (cpu.cu.rpt || (cpu.cu.rd && icOdd) || cpu.cu.rl) { cu 2178 src/dps8/dps8_ins.c cpu.cu.rpt = false; cu 2179 src/dps8/dps8_ins.c cpu.cu.rd = false; cu 2180 src/dps8/dps8_ins.c cpu.cu.rl = false; cu 2186 src/dps8/dps8_ins.c if (cpu.cu.rl) { cu 2190 src/dps8/dps8_ins.c cpu.cu.rpt = false; cu 2191 src/dps8/dps8_ins.c cpu.cu.rd = false; cu 2192 src/dps8/dps8_ins.c cpu.cu.rl = false; cu 2196 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IWB, 36 - 3); cu 2220 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPAQI, &cpu_dev, "A=%012"PRIo64" Q=%012"PRIo64" IR:%s\n", cpu.rA, cpu.rQ, dump_flags (buf, cpu.cu.IR)); cu 2258 src/dps8/dps8_ins.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) cu 2742 src/dps8/dps8_ins.c cmp36 (cpu.rQ, cpu.CY, &cpu.cu.IR); cu 2954 src/dps8/dps8_ins.c cmp36 (cpu.rA, cpu.CY, &cpu.cu.IR); cu 2967 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); cu 3003 src/dps8/dps8_ins.c if (! (cpu.cu.IR & I_NEG) && ! (cpu.cu.IR & I_ZERO)) cu 3251 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); cu 3263 src/dps8/dps8_ins.c if (cpu.cu.IR & (I_NEG | I_ZERO)) cu 3410 src/dps8/dps8_ins.c DPS8M_ (cpu.CY = cpu.cu.IR & 0000000777770LL; ) cu 3412 src/dps8/dps8_ins.c L68_ (cpu.CY = cpu.cu.IR & 0000000777760LL;) cu 3415 src/dps8/dps8_ins.c cpu.CY = cpu.cu.IR & 0000000777600LL; cu 3461 src/dps8/dps8_ins.c cpu.rA = compl36 (cpu.CY, & cpu.cu.IR, & ovf); cu 3472 src/dps8/dps8_ins.c cpu.rQ = compl36 (cpu.CY, & cpu.cu.IR, & ovf); cu 3492 src/dps8/dps8_ins.c cpu.rX[n] = compl18 (GETHI (cpu.CY), & cpu.cu.IR, & ovf); cu 3789 src/dps8/dps8_ins.c DPS8M_ (SETLO (cpu.CY, cpu.cu.IR & 0777770);) cu 3790 src/dps8/dps8_ins.c L68_ (SETLO (cpu.CY, cpu.cu.IR & 0777760);) cu 4249 src/dps8/dps8_ins.c cpu.rA = Add36b (cpu.rA, cpu.CY, 0, I_ZNOC, & cpu.cu.IR, & ovf); cu 4268 src/dps8/dps8_ins.c tmp72, 0, I_ZNOC, & cpu.cu.IR, & ovf); cu 4289 src/dps8/dps8_ins.c tmp72, 0, I_ZNOC, & cpu.cu.IR, & ovf); cu 4314 src/dps8/dps8_ins.c tmp72, 0, I_ZNC, & cpu.cu.IR, & ovf); cu 4335 src/dps8/dps8_ins.c cpu.rA = Add36b (cpu.rA, cpu.CY, 0, I_ZNC, & cpu.cu.IR, & ovf); cu 4354 src/dps8/dps8_ins.c cpu.rQ = Add36b (cpu.rQ, cpu.CY, 0, I_ZNC, & cpu.cu.IR, & ovf); cu 4378 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); cu 4406 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); cu 4427 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); cu 4440 src/dps8/dps8_ins.c cpu.CY = Add36b (cpu.rQ, cpu.CY, 0, I_ZNOC, & cpu.cu.IR, & ovf); cu 4464 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cu 4481 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cu 4500 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cu 4519 src/dps8/dps8_ins.c cpu.rA = Sub36b (cpu.rA, cpu.CY, 1, I_ZNOC, & cpu.cu.IR, & ovf); cu 4538 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, cu 4558 src/dps8/dps8_ins.c cpu.rA = Sub36b (cpu.rA, cpu.CY, 1, I_ZNC, & cpu.cu.IR, & ovf); cu 4582 src/dps8/dps8_ins.c I_ZNC, & cpu.cu.IR, & ovf); cu 4599 src/dps8/dps8_ins.c cpu.rQ = Sub36b (cpu.rQ, cpu.CY, 1, I_ZNC, & cpu.cu.IR, & ovf); cu 4626 src/dps8/dps8_ins.c I_ZNC, & cpu.cu.IR, & ovf); cu 4641 src/dps8/dps8_ins.c cpu.rQ = Sub36b (cpu.rQ, cpu.CY, 1, I_ZNOC, & cpu.cu.IR, & ovf); cu 4669 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cu 4686 src/dps8/dps8_ins.c cpu.CY = Sub36b (cpu.rA, cpu.CY, 1, I_ZNOC, & cpu.cu.IR, & ovf); cu 4700 src/dps8/dps8_ins.c cpu.CY = Sub36b (cpu.rQ, cpu.CY, 1, I_ZNOC, & cpu.cu.IR, & ovf); cu 4725 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cu 4742 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cu 4761 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cu 5172 src/dps8/dps8_ins.c cmp72 (trAQ, tmp72, &cpu.cu.IR); cu 5195 src/dps8/dps8_ins.c cmp18 (cpu.rX[n], GETHI (cpu.CY), &cpu.cu.IR); cu 5211 src/dps8/dps8_ins.c cmp36wl (cpu.rA, cpu.CY, cpu.rQ, &cpu.cu.IR); cu 6184 src/dps8/dps8_ins.c cpu.cu.IR = tempIR; cu 6828 src/dps8/dps8_ins.c cpu.cu.xde = 1; cu 6829 src/dps8/dps8_ins.c cpu.cu.xdo = 0; cu 6833 src/dps8/dps8_ins.c cpu.cu.IWB = cpu.CY; cu 6872 src/dps8/dps8_ins.c cpu.cu.xde = 1; cu 6873 src/dps8/dps8_ins.c cpu.cu.xdo = 1; cu 6877 src/dps8/dps8_ins.c cpu.cu.IWB = cpu.Ypair[0]; cu 6878 src/dps8/dps8_ins.c cpu.cu.IRODD = cpu.Ypair[1]; cu 6932 src/dps8/dps8_ins.c cpu.cu.delta = i->tag; cu 6942 src/dps8/dps8_ins.c cpu.cu.rd = 1; cu 6943 src/dps8/dps8_ins.c cpu.cu.repeat_first = 1; cu 6950 src/dps8/dps8_ins.c cpu.cu.delta = i->tag; cu 6958 src/dps8/dps8_ins.c cpu.cu.rl = 1; cu 6959 src/dps8/dps8_ins.c cpu.cu.repeat_first = 1; cu 6966 src/dps8/dps8_ins.c cpu.cu.delta = i->tag; cu 6974 src/dps8/dps8_ins.c cpu.cu.rpt = 1; cu 6975 src/dps8/dps8_ins.c cpu.cu.repeat_first = 1; cu 7629 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode || cpu.cu.PT_ON) // only clear when enabled cu 7651 src/dps8/dps8_ins.c cpu.cu.PT_ON = 1; cu 7653 src/dps8/dps8_ins.c cpu.cu.PT_ON = 0; cu 7675 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode || cpu.cu.SD_ON) // only clear when enabled cu 7696 src/dps8/dps8_ins.c cpu.cu.SD_ON = 1; cu 7698 src/dps8/dps8_ins.c cpu.cu.SD_ON = 0; cu 8387 src/dps8/dps8_ins.c cu 8439 src/dps8/dps8_ins.c if (GET_I (cpu.cu.IWB) ? bG7PendingNoTRO () : bG7Pending ()) cu 8445 src/dps8/dps8_ins.c cu 9405 src/dps8/dps8_ins.c if (get_addr_mode () == ABSOLUTE_mode && ! (cpu.cu.XSF || cpu.currentInstruction.b29)) // ISOLTS-860 cu 9525 src/dps8/dps8_ins.c if (cpu.cu.FIF) // fault occurred during instruction fetch cu 9533 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cu 9539 src/dps8/dps8_ins.c if (cpu.cu.rfi) cu 9546 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cu 9563 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cu 9567 src/dps8/dps8_ins.c if (cpu.cu.rfi || // S/W asked for the instruction to be started cu 9568 src/dps8/dps8_ins.c cpu.cu.FIF) // fault occurred during instruction fetch cu 9577 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cu 9590 src/dps8/dps8_ins.c cpu.cu.rfi = 1; cu 9621 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cu 9635 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cu 9643 src/dps8/dps8_ins.c cpu.cu.rfi = 1; cu 9660 src/dps8/dps8_ins.c cpu.cu.rfi = 1; cu 601 src/dps8/dps8_math.c m3 = Add72b (m1, m2, 0, I_CARRY, & cpu.cu.IR, & ovf); cu 2124 src/dps8/dps8_math.c word72 m3 = Add72b (m1, m2, 0, I_CARRY, & cpu.cu.IR, & ovf); cu 1881 src/dps8/dps8_sys.c cu 1882 src/dps8/dps8_sys.c cu 1883 src/dps8/dps8_sys.c cu 1884 src/dps8/dps8_sys.c cu 4121 src/dps8/dps8_sys.c { "cpus[].cu", SYM_STRUCT_OFFSET, SYM_PTR, offsetof (cpu_state_t, cu) }, cu 108 src/dps8/hdbg.h # define HDBGRegIR(c) hdbgRegW (hreg_IR, (word36) cpu.cu.IR, c)