uCache 112 src/dps8/doAppendCycleIndirectWordFetch.h cpu.uCache.skips[this] ++; uCache 171 src/dps8/doAppendCycleInstructionFetch.h cpu.uCache.skips[this] ++; uCache 104 src/dps8/doAppendCycleOperandRead.h cpu.uCache.call6Skips ++; uCache 123 src/dps8/doAppendCycleOperandRead.h cpu.uCache.ralrSkips ++; uCache 174 src/dps8/doAppendCycleOperandRead.h cpu.uCache.skips[this] ++; uCache 1533 src/dps8/dps8_cpu.h uCache_t uCache; uCache 26 src/dps8/ucache.c memset (cpu.uCache.caches, 0, sizeof (cpu.uCache.caches)); uCache 34 src/dps8/ucache.c ep = & cpu.uCache.caches[ucNum][segno]; uCache 51 src/dps8/ucache.c cpu.uCache.segnoSkips ++; uCache 56 src/dps8/ucache.c ep = & cpu.uCache.caches[ucNum][segno]; uCache 112 src/dps8/ucache.c cpu.uCache.hits[ucNum] ++; uCache 117 src/dps8/ucache.c cpu.uCache.misses[ucNum] ++; uCache 131 src/dps8/ucache.c # define stats(n) args ( (long long unsigned)cpus[cpuNo].uCache.hits [n], \ uCache 132 src/dps8/ucache.c (long long unsigned)cpus[cpuNo].uCache.misses[n], \ uCache 133 src/dps8/ucache.c (long long unsigned)cpus[cpuNo].uCache.skips [n] ) uCache 152 src/dps8/ucache.c sim_msg ("\r| RALR %15llu |\r\n", (long long unsigned)cpus[cpuNo].uCache.ralrSkips); uCache 153 src/dps8/ucache.c sim_msg ("\r| CALL6 %15llu |\r\n", (long long unsigned)cpus[cpuNo].uCache.call6Skips); uCache 154 src/dps8/ucache.c sim_msg ("\r| Segno %15llu |\r\n", (long long unsigned)cpus[cpuNo].uCache.segnoSkips); uCache 173 src/dps8/ucache.c sim_msg ("\r| RALR %'15llu |\r\n", (long long unsigned)cpus[cpuNo].uCache.ralrSkips); uCache 174 src/dps8/ucache.c sim_msg ("\r| CALL6 %'15llu |\r\n", (long long unsigned)cpus[cpuNo].uCache.call6Skips); uCache 175 src/dps8/ucache.c sim_msg ("\r| Segno %'15llu |\r\n", (long long unsigned)cpus[cpuNo].uCache.segnoSkips);