CA 27 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) CA %06o\n", cpu.TPR.CA); CA 72 src/dps8/doAppendCycleABSA.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 178 src/dps8/doAppendCycleABSA.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 186 src/dps8/doAppendCycleABSA.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 203 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(G) CA %06o\n", cpu.TPR.CA); CA 204 src/dps8/doAppendCycleABSA.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { //TPR.CA)) CA 205 src/dps8/doAppendCycleABSA.h fetch_ptw (cpu.SDW, cpu.TPR.CA); CA 206 src/dps8/doAppendCycleABSA.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 215 src/dps8/doAppendCycleABSA.h do_ptw2 (cpu.SDW, cpu.TPR.CA); CA 238 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 240 src/dps8/doAppendCycleABSA.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 244 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 254 src/dps8/doAppendCycleABSA.h word24 y2 = cpu.TPR.CA % 1024; CA 266 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 277 src/dps8/doAppendCycleABSA.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 283 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 25 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) CA %06o\n", cpu.TPR.CA); CA 76 src/dps8/doAppendCycleAPUDataRMW.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 225 src/dps8/doAppendCycleAPUDataRMW.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 231 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 248 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(G) CA %06o\n", cpu.TPR.CA); CA 249 src/dps8/doAppendCycleAPUDataRMW.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { CA 250 src/dps8/doAppendCycleAPUDataRMW.h fetch_ptw (cpu.SDW, cpu.TPR.CA); CA 255 src/dps8/doAppendCycleAPUDataRMW.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 264 src/dps8/doAppendCycleAPUDataRMW.h do_ptw2 (cpu.SDW, cpu.TPR.CA); CA 289 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 291 src/dps8/doAppendCycleAPUDataRMW.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 295 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 305 src/dps8/doAppendCycleAPUDataRMW.h modify_ptw (cpu.SDW, cpu.TPR.CA); CA 311 src/dps8/doAppendCycleAPUDataRMW.h word24 y2 = cpu.TPR.CA % 1024; CA 323 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 343 src/dps8/doAppendCycleAPUDataRMW.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 349 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 25 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) CA %06o\n", cpu.TPR.CA); CA 77 src/dps8/doAppendCycleAPUDataRead.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 187 src/dps8/doAppendCycleAPUDataRead.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 193 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 210 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(G) CA %06o\n", cpu.TPR.CA); CA 211 src/dps8/doAppendCycleAPUDataRead.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { CA 212 src/dps8/doAppendCycleAPUDataRead.h fetch_ptw (cpu.SDW, cpu.TPR.CA); CA 216 src/dps8/doAppendCycleAPUDataRead.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 225 src/dps8/doAppendCycleAPUDataRead.h do_ptw2 (cpu.SDW, cpu.TPR.CA); CA 249 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 251 src/dps8/doAppendCycleAPUDataRead.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 255 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 269 src/dps8/doAppendCycleAPUDataRead.h word24 y2 = cpu.TPR.CA % 1024; CA 281 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 294 src/dps8/doAppendCycleAPUDataRead.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 300 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 25 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) CA %06o\n", cpu.TPR.CA); CA 75 src/dps8/doAppendCycleAPUDataStore.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 186 src/dps8/doAppendCycleAPUDataStore.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 192 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 209 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(G) CA %06o\n", cpu.TPR.CA); CA 210 src/dps8/doAppendCycleAPUDataStore.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { CA 211 src/dps8/doAppendCycleAPUDataStore.h fetch_ptw (cpu.SDW, cpu.TPR.CA); CA 216 src/dps8/doAppendCycleAPUDataStore.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 226 src/dps8/doAppendCycleAPUDataStore.h do_ptw2 (cpu.SDW, cpu.TPR.CA); CA 250 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 252 src/dps8/doAppendCycleAPUDataStore.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 256 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 266 src/dps8/doAppendCycleAPUDataStore.h modify_ptw (cpu.SDW, cpu.TPR.CA); CA 272 src/dps8/doAppendCycleAPUDataStore.h word24 y2 = cpu.TPR.CA % 1024; CA 284 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 297 src/dps8/doAppendCycleAPUDataStore.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 303 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 61 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) CA %06o\n", cpu.TPR.CA); CA 97 src/dps8/doAppendCycleIndirectWordFetch.h if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) CA 101 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); CA 103 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = pageAddress + cpu.TPR.CA; CA 168 src/dps8/doAppendCycleIndirectWordFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 287 src/dps8/doAppendCycleIndirectWordFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 293 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 312 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(G) CA %06o\n", cpu.TPR.CA); CA 314 src/dps8/doAppendCycleIndirectWordFetch.h ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { CA 315 src/dps8/doAppendCycleIndirectWordFetch.h fetch_ptw (cpu.SDW, cpu.TPR.CA); CA 320 src/dps8/doAppendCycleIndirectWordFetch.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 330 src/dps8/doAppendCycleIndirectWordFetch.h do_ptw2 (cpu.SDW, cpu.TPR.CA); CA 356 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 359 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 363 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 379 src/dps8/doAppendCycleIndirectWordFetch.h word24 y2 = cpu.TPR.CA % 1024; CA 392 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 399 src/dps8/doAppendCycleIndirectWordFetch.h ucCacheSave (this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); CA 419 src/dps8/doAppendCycleIndirectWordFetch.h if ((GET_TM (tag) == TM_IR || GET_TM (tag) == TM_RI) && (cpu.TPR.CA & 1) == 0) { CA 462 src/dps8/doAppendCycleIndirectWordFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 468 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 72 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) CA %06o\n", cpu.TPR.CA); CA 148 src/dps8/doAppendCycleInstructionFetch.h cacheHit = ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); CA 151 src/dps8/doAppendCycleInstructionFetch.h if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) CA 156 src/dps8/doAppendCycleInstructionFetch.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); CA 158 src/dps8/doAppendCycleInstructionFetch.h finalAddress = pageAddress + cpu.TPR.CA; CA 216 src/dps8/doAppendCycleInstructionFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 416 src/dps8/doAppendCycleInstructionFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 422 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 441 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(G) CA %06o\n", cpu.TPR.CA); CA 443 src/dps8/doAppendCycleInstructionFetch.h ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { CA 444 src/dps8/doAppendCycleInstructionFetch.h fetch_ptw (cpu.SDW, cpu.TPR.CA); CA 449 src/dps8/doAppendCycleInstructionFetch.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 461 src/dps8/doAppendCycleInstructionFetch.h do_ptw2 (cpu.SDW, cpu.TPR.CA); CA 487 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 490 src/dps8/doAppendCycleInstructionFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 494 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 510 src/dps8/doAppendCycleInstructionFetch.h word24 y2 = cpu.TPR.CA % 1024; CA 523 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 551 src/dps8/doAppendCycleInstructionFetch.h sim_printf ("ins fetch err %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 556 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 561 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 576 src/dps8/doAppendCycleInstructionFetch.h ucCacheSave (this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); CA 634 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.IC = cpu.TPR.CA; CA 651 src/dps8/doAppendCycleInstructionFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 657 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 25 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) CA %06o\n", cpu.TPR.CA); CA 77 src/dps8/doAppendCycleOperandRMW.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 225 src/dps8/doAppendCycleOperandRMW.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 231 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 248 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(G) CA %06o\n", cpu.TPR.CA); CA 249 src/dps8/doAppendCycleOperandRMW.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { CA 250 src/dps8/doAppendCycleOperandRMW.h fetch_ptw (cpu.SDW, cpu.TPR.CA); CA 255 src/dps8/doAppendCycleOperandRMW.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 265 src/dps8/doAppendCycleOperandRMW.h do_ptw2 (cpu.SDW, cpu.TPR.CA); CA 288 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 290 src/dps8/doAppendCycleOperandRMW.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 294 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 304 src/dps8/doAppendCycleOperandRMW.h modify_ptw (cpu.SDW, cpu.TPR.CA); CA 310 src/dps8/doAppendCycleOperandRMW.h word24 y2 = cpu.TPR.CA % 1024; CA 322 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 348 src/dps8/doAppendCycleOperandRMW.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 354 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 67 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) CA %06o\n", cpu.TPR.CA); CA 137 src/dps8/doAppendCycleOperandRead.h cacheHit = ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); CA 139 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "test cache check %s %d %u %05o:%06o %05o %o %08o %o %o", cacheHit ? "hit" : "miss", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, cachedBound, cachedP, cachedAddress, cachedR1, cachedPaged); CA 143 src/dps8/doAppendCycleOperandRead.h if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) { CA 145 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 152 src/dps8/doAppendCycleOperandRead.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); CA 154 src/dps8/doAppendCycleOperandRead.h finalAddress = pageAddress + cpu.TPR.CA; CA 161 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 171 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "skip %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 229 src/dps8/doAppendCycleOperandRead.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 386 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(E): E %o G %o PSR %05o TSR %05o CA %06o " "EB %06o R %o%o%o TRR %o PRR %o\n", cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu.SDW->EB, cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.TPR.TRR, cpu.PPR.PRR); CA 409 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.CA >= (word18) cpu.SDW->EB) { CA 521 src/dps8/doAppendCycleOperandRead.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 527 src/dps8/doAppendCycleOperandRead.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 546 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(G) CA %06o\n", cpu.TPR.CA); CA 548 src/dps8/doAppendCycleOperandRead.h ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { CA 549 src/dps8/doAppendCycleOperandRead.h fetch_ptw (cpu.SDW, cpu.TPR.CA); CA 554 src/dps8/doAppendCycleOperandRead.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 564 src/dps8/doAppendCycleOperandRead.h do_ptw2 (cpu.SDW, cpu.TPR.CA); CA 591 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 594 src/dps8/doAppendCycleOperandRead.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 598 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 617 src/dps8/doAppendCycleOperandRead.h word24 y2 = cpu.TPR.CA % 1024; CA 630 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 660 src/dps8/doAppendCycleOperandRead.h sim_printf ("oprnd read err %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 665 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 670 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 675 src/dps8/doAppendCycleOperandRead.h ucCacheSave (this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); CA 678 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "cache %d %u %05o:%06o %05o %o %08o %o %o", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); CA 739 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; CA 786 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; CA 792 src/dps8/doAppendCycleOperandRead.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 798 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 25 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) CA %06o\n", cpu.TPR.CA); CA 76 src/dps8/doAppendCycleOperandStore.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 185 src/dps8/doAppendCycleOperandStore.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 191 src/dps8/doAppendCycleOperandStore.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 208 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(G) CA %06o\n", cpu.TPR.CA); CA 209 src/dps8/doAppendCycleOperandStore.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { CA 210 src/dps8/doAppendCycleOperandStore.h fetch_ptw (cpu.SDW, cpu.TPR.CA); CA 215 src/dps8/doAppendCycleOperandStore.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 225 src/dps8/doAppendCycleOperandStore.h do_ptw2 (cpu.SDW, cpu.TPR.CA); CA 248 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 250 src/dps8/doAppendCycleOperandStore.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 254 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 264 src/dps8/doAppendCycleOperandStore.h modify_ptw (cpu.SDW, cpu.TPR.CA); CA 270 src/dps8/doAppendCycleOperandStore.h word24 y2 = cpu.TPR.CA % 1024; CA 282 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 300 src/dps8/doAppendCycleOperandStore.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 306 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 25 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) CA %06o\n", cpu.TPR.CA); CA 107 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 220 src/dps8/doAppendCycleRTCDOperandFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 226 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 243 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(G) CA %06o\n", cpu.TPR.CA); CA 244 src/dps8/doAppendCycleRTCDOperandFetch.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { CA 245 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_ptw (cpu.SDW, cpu.TPR.CA); CA 250 src/dps8/doAppendCycleRTCDOperandFetch.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 260 src/dps8/doAppendCycleRTCDOperandFetch.h do_ptw2 (cpu.SDW, cpu.TPR.CA); CA 283 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 286 src/dps8/doAppendCycleRTCDOperandFetch.h finalAddress = cpu.TPR.CA; CA 288 src/dps8/doAppendCycleRTCDOperandFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 293 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 307 src/dps8/doAppendCycleRTCDOperandFetch.h word24 y2 = cpu.TPR.CA % 1024; CA 319 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 356 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.CA = GET_ITS_WORDNO (data); CA 368 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.IC = cpu.TPR.CA; CA 386 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 392 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 227 src/dps8/dps8_addrmods.c cpu.TPR.CA = cpu.PAR[n].WORDNO + GET_ITP_WORDNO (cpu.itxPair); CA 228 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; CA 229 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; CA 269 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ITS_WORDNO (cpu.itxPair); CA 270 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; CA 272 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; CA 364 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ADDR (IWB_IRODD); CA 373 src/dps8/dps8_addrmods.c cpu.TPR.CA = (cpu.PAR[n].WORDNO + SIGNEXT15_18 (offset)) CA 379 src/dps8/dps8_addrmods.c __func__, op_desc_str (buf), cpu.TPR.CA); CA 422 src/dps8/dps8_addrmods.c cpu.cu.pot == 1 && GET_ADDR (IWB_IRODD) == cpu.TPR.CA) CA 424 src/dps8/dps8_addrmods.c cpu.TPR.CA--; CA 494 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO; CA 495 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; CA 499 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr; CA 504 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; CA 505 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits CA 508 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 530 src/dps8/dps8_addrmods.c "RI_MOD: Cr=%06o CA(Before)=%06o\n", Cr, cpu.TPR.CA); CA 541 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO; CA 545 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr; CA 547 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; CA 551 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; CA 552 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits CA 555 src/dps8/dps8_addrmods.c "RI_MOD: CA(After)=%06o\n", cpu.TPR.CA); CA 569 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 575 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, cpu.rTAG); CA 603 src/dps8/dps8_addrmods.c cpu.TPR.CA = GETHI (cpu.itxPair[0]); CA 604 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; CA 616 src/dps8/dps8_addrmods.c cpu.itxPair[0], cpu.TPR.CA, cpu.rTAG); CA 643 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 645 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 665 src/dps8/dps8_addrmods.c cpu.TPR.CA = GETHI (cpu.itxPair[0]); CA 666 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; CA 678 src/dps8/dps8_addrmods.c cpu.itxPair[0], cpu.TPR.CA, Tm, Td, CA 691 src/dps8/dps8_addrmods.c updateIWB(cpu.TPR.CA, cpu.rTAG); CA 696 src/dps8/dps8_addrmods.c cpu.TPR.CA = saveCA; CA 701 src/dps8/dps8_addrmods.c cpu.TPR.CA = saveCA; CA 728 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, cpu.rTAG); CA 742 src/dps8/dps8_addrmods.c Td, Cr, cpu.TPR.CA); CA 744 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; CA 745 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits CA 748 src/dps8/dps8_addrmods.c "IR_MOD(TM_RI): TPR.CA=%06o\n", cpu.TPR.CA); CA 752 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 755 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, (TM_RI|TD_N)); CA 761 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, cpu.rTAG); // XXX guessing here... CA 840 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 847 src/dps8/dps8_addrmods.c word18 indaddr = cpu.TPR.CA; CA 881 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 929 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 952 src/dps8/dps8_addrmods.c Read (cpu.TPR.CA, & cpu.ou.character_data, (i->info->flags & RMW) == \ CA 955 src/dps8/dps8_addrmods.c ReadOperandRead (cpu.TPR.CA, & cpu.ou.character_data); CA 1027 src/dps8/dps8_addrmods.c indword, cpu.TPR.CA); CA 1032 src/dps8/dps8_addrmods.c cpu.TPR.CA = cpu.ou.character_address; CA 1040 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1049 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ADDR (cpu.itxPair[0]); CA 1050 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, (TM_R|TD_N)); CA 1068 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1074 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1076 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpu.TPR.CA, & indword); CA 1090 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1091 src/dps8/dps8_addrmods.c word18 computedAddress = cpu.TPR.CA; CA 1120 src/dps8/dps8_addrmods.c cpu.TPR.CA = computedAddress; CA 1121 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, (TM_R|TD_N)); CA 1141 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1143 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpu.TPR.CA, & indword); CA 1147 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1162 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1188 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1189 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, (TM_R|TD_N)); CA 1206 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1212 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1214 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpu.TPR.CA, & indword); CA 1229 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1237 src/dps8/dps8_addrmods.c indword = (word36) (((word36) cpu.TPR.CA << 18) | CA 1255 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1256 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, (TM_R|TD_N)); CA 1271 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1275 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1282 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpu.TPR.CA, & indword); CA 1293 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1294 src/dps8/dps8_addrmods.c word18 computedAddress = cpu.TPR.CA; CA 1327 src/dps8/dps8_addrmods.c cpu.TPR.CA = computedAddress; CA 1328 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, (TM_R|TD_N)); CA 1357 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1363 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1365 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpu.TPR.CA, & indword); CA 1416 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1440 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, cpu.rTAG); CA 1469 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1475 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1477 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpu.TPR.CA, & indword); CA 1530 src/dps8/dps8_addrmods.c cpu.TPR.CA = YiSafe; CA 1551 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, cpu.rTAG); CA 681 src/dps8/dps8_append.c static ptw_s * fetch_ptw_from_ptwam (word15 segno, word18 CA) CA 693 src/dps8/dps8_append.c if (cpu.PTWAM[_n].FE && ((CA >> 6) & 07760) == cpu.PTWAM[_n].PAGENO && CA 727 src/dps8/dps8_append.c uint setno = (CA >> 10) & 017; CA 734 src/dps8/dps8_append.c if (p->FE && ((CA >> 6) & 07760) == p->PAGENO && p->POINTER == segno) CA 1205 src/dps8/dps8_append.c cpu.TPR.CA); CA 1299 src/dps8/dps8_append.c PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 1599 src/dps8/dps8_append.c cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, CA 1625 src/dps8/dps8_append.c if (cpu.TPR.CA >= (word18) cpu.SDW->EB) CA 1750 src/dps8/dps8_append.c if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) CA 1759 src/dps8/dps8_append.c cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 1778 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(G) CA %06o\n", cpu.TPR.CA); CA 1780 src/dps8/dps8_append.c ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) //TPR.CA)) CA 1782 src/dps8/dps8_append.c fetch_ptw (cpu.SDW, cpu.TPR.CA); CA 1792 src/dps8/dps8_append.c loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 1803 src/dps8/dps8_append.c do_ptw2 (cpu.SDW, cpu.TPR.CA); CA 1829 src/dps8/dps8_append.c cpu.SDW->ADDR, cpu.TPR.CA); CA 1835 src/dps8/dps8_append.c finalAddress = cpu.TPR.CA; CA 1839 src/dps8/dps8_append.c finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 1845 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 1864 src/dps8/dps8_append.c modify_ptw (cpu.SDW, cpu.TPR.CA); CA 1871 src/dps8/dps8_append.c word24 y2 = cpu.TPR.CA % 1024; CA 1883 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 1961 src/dps8/dps8_append.c (cpu.TPR.CA & 1) == 0) CA 2038 src/dps8/dps8_append.c cpu.TPR.CA = GET_ITS_WORDNO (data); CA 2117 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; CA 2171 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; CA 2211 src/dps8/dps8_append.c PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 2219 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 4259 src/dps8/dps8_cpu.c putbits36_18 (& w1, 0, cpu.TPR.CA); CA 85 src/dps8/dps8_cpu.h word18 CA; // The current computed address relative to the origin of the CA 56 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 119 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 129 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read BAR"); CA 146 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read"); CA 159 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 194 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 201 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead BAR"); CA 211 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead"); CA 221 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 256 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 263 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead BAR"); CA 274 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead"); CA 285 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 320 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 327 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW BAR"); CA 337 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW"); CA 347 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 382 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 389 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW BAR"); CA 399 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW"); CA 411 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 446 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 453 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch BAR"); CA 463 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch"); CA 473 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 508 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 515 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch BAR"); CA 525 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch"); CA 537 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 583 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 593 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn"); CA 594 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd"); CA 611 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn"); CA 612 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd"); CA 623 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 668 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 678 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead BR evn"); CA 679 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead BR odd"); CA 694 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead evn"); CA 695 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead odd"); CA 705 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 750 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 760 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW BR evn"); CA 761 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW BR odd"); CA 772 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW evn"); CA 773 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW odd"); CA 783 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 828 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 838 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch BR evn"); CA 839 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch BR odd"); CA 850 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch evn"); CA 851 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch odd"); CA 860 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 865 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 875 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn"); CA 876 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd"); CA 887 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn"); CA 888 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd"); CA 895 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 940 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 950 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch BR evn"); CA 951 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch BR odd"); CA 962 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch evn"); CA 963 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch odd"); CA 974 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1036 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 1052 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result[i], "Read8 BAR"); CA 1074 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "Read8"); CA 1098 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1160 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 1176 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage B"); CA 1199 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage"); CA 1210 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1252 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 1259 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write BR"); CA 1267 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write"); CA 1278 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1314 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 1321 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore BR"); CA 1329 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore"); CA 1338 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1380 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 1387 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore BR"); CA 1395 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore"); CA 1407 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1458 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 1468 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 BR evn"); CA 1469 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 BR odd"); CA 1482 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 evn"); CA 1483 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 odd"); CA 1494 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1531 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 1538 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore BR evn"); CA 1539 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore BR odd"); CA 1547 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore evn"); CA 1548 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore odd"); CA 1559 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1605 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 1616 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1 BR"); CA 1630 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1"); CA 1641 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1700 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 1716 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8 BR"); CA 1736 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8"); CA 1770 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1829 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 1846 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage BR"); CA 1865 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage"); CA 1876 src/dps8/dps8_iefp.c if (cpu.TPR.CA & 1) // is odd? CA 1878 src/dps8/dps8_iefp.c ReadIndirectWordFetch (cpu.TPR.CA, cpu.itxPair); CA 1883 src/dps8/dps8_iefp.c Read2IndirectWordFetch (cpu.TPR.CA, cpu.itxPair); CA 156 src/dps8/dps8_ins.c cpu.TPR.CA = cpu.ou.character_address; CA 160 src/dps8/dps8_ins.c write_operand (cpu.TPR.CA, OPERAND_STORE); CA 176 src/dps8/dps8_ins.c "%s a %d address %08o\n", __func__, i->b29, cpu.TPR.CA); CA 193 src/dps8/dps8_ins.c SETHI (cpu.CY, cpu.TPR.CA); CA 206 src/dps8/dps8_ins.c SETLO (cpu.CY, cpu.TPR.CA); CA 239 src/dps8/dps8_ins.c cpu.TPR.CA = cpu.ou.character_address; CA 245 src/dps8/dps8_ins.c readOperandRMW (cpu.TPR.CA); CA 247 src/dps8/dps8_ins.c readOperandRead (cpu.TPR.CA); CA 249 src/dps8/dps8_ins.c readOperandRead (cpu.TPR.CA); CA 257 src/dps8/dps8_ins.c if (cpu.TPR.CA & 1) CA 258 src/dps8/dps8_ins.c ReadOperandRead (cpu.TPR.CA, &cpu.CY); CA 260 src/dps8/dps8_ins.c Read2OperandRead (cpu.TPR.CA, cpu.Ypair); CA 287 src/dps8/dps8_ins.c cpu.PPR.IC = cpu.TPR.CA; CA 444 src/dps8/dps8_ins.c putbits36 (& words[5], 0, 18, cpu.TPR.CA); CA 1764 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD CA %06o\n", cpu.TPR.CA); CA 1796 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + offset) & AMASK; CA 1797 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; CA 1890 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, "doPtrReg: n=%o offset=%05o TPR.CA=%06o " "TPR.TBR=%o TPR.TSR=%05o TPR.TRR=%o\n", n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR); CA 1929 src/dps8/dps8_ins.c cpu.iefpFinalAddress = cpu.TPR.CA; CA 1976 src/dps8/dps8_ins.c cpu.last_write = cpu.TPR.CA; CA 2040 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; CA 2041 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; CA 2056 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; CA 2057 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; CA 2068 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; CA 2069 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; CA 2632 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = cpu.TPR.CA; CA 2876 src/dps8/dps8_ins.c cpu.rX[n] = cpu.TPR.CA; CA 2881 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); CA 2882 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); CA 3073 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 3099 src/dps8/dps8_ins.c Read2RTCDOperandFetch (cpu.TPR.CA, cpu.Ypair); CA 3358 src/dps8/dps8_ins.c cpu.rQ |= (word36) (cpu.TPR.CA & MASK18) << 18; CA 3374 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 3427 src/dps8/dps8_ins.c SETHI (cpu.rA, cpu.TPR.CA); CA 3431 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); CA 3432 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); CA 3438 src/dps8/dps8_ins.c SETHI (cpu.rQ, cpu.TPR.CA); CA 3443 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); CA 3444 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); CA 3936 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 3965 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 3987 src/dps8/dps8_ins.c word18 tmp18 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4015 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4055 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4093 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4125 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4161 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4189 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4213 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 6141 src/dps8/dps8_ins.c ReadOperandRead (cpu.TPR.CA, & cpu.CY); CA 6325 src/dps8/dps8_ins.c cpu.TPR.CA = get_BAR_address (cpu.TPR.CA); CA 6380 src/dps8/dps8_ins.c cpu.PR[0].SNR = cpu.TPR.CA & MASK15; CA 6389 src/dps8/dps8_ins.c cpu.PR[1].SNR = cpu.TPR.CA & MASK15; CA 6398 src/dps8/dps8_ins.c cpu.PR[2].SNR = cpu.TPR.CA & MASK15; CA 6407 src/dps8/dps8_ins.c cpu.PR[3].SNR = cpu.TPR.CA & MASK15; CA 6416 src/dps8/dps8_ins.c cpu.PR[4].SNR = cpu.TPR.CA & MASK15; CA 6425 src/dps8/dps8_ins.c cpu.PR[5].SNR = cpu.TPR.CA & MASK15; CA 6434 src/dps8/dps8_ins.c cpu.PR[6].SNR = cpu.TPR.CA & MASK15; CA 6443 src/dps8/dps8_ins.c cpu.PR[7].SNR = cpu.TPR.CA & MASK15; CA 6456 src/dps8/dps8_ins.c cpu.PR[0].WORDNO = cpu.TPR.CA; CA 6468 src/dps8/dps8_ins.c cpu.PR[1].WORDNO = cpu.TPR.CA; CA 6480 src/dps8/dps8_ins.c cpu.PR[2].WORDNO = cpu.TPR.CA; CA 6492 src/dps8/dps8_ins.c cpu.PR[3].WORDNO = cpu.TPR.CA; CA 6504 src/dps8/dps8_ins.c cpu.PR[4].WORDNO = cpu.TPR.CA; CA 6516 src/dps8/dps8_ins.c cpu.PR[5].WORDNO = cpu.TPR.CA; CA 6528 src/dps8/dps8_ins.c cpu.PR[6].WORDNO = cpu.TPR.CA; CA 6540 src/dps8/dps8_ins.c cpu.PR[7].WORDNO = cpu.TPR.CA; CA 6758 src/dps8/dps8_ins.c cpu_port_num = (cpu.TPR.CA >> 15) & 07; CA 6760 src/dps8/dps8_ins.c cpu_port_num = (cpu.TPR.CA >> 15) & 03; CA 7484 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) CA 7522 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) CA 7542 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) CA 7580 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 5) & 03;) CA 7648 src/dps8/dps8_ins.c DPS8M_ (if (cpu.TPR.CA != 0000002 && (cpu.TPR.CA & 3) != 0) CA 7649 src/dps8/dps8_ins.c sim_warn ("CAMP ignores enable/disable %06o\n", cpu.TPR.CA);) CA 7650 src/dps8/dps8_ins.c if ((cpu.TPR.CA & 3) == 02) CA 7652 src/dps8/dps8_ins.c else if ((cpu.TPR.CA & 3) == 01) CA 7693 src/dps8/dps8_ins.c DPS8M_ (if (cpu.TPR.CA != 0000006 && (cpu.TPR.CA & 3) != 0) CA 7694 src/dps8/dps8_ins.c sim_warn ("CAMS ignores enable/disable %06o\n", cpu.TPR.CA);) CA 7695 src/dps8/dps8_ins.c if ((cpu.TPR.CA & 3) == 02) CA 7697 src/dps8/dps8_ins.c else if ((cpu.TPR.CA & 3) == 01) CA 7717 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) CA 7718 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) CA 7776 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 10) & 03;) CA 7777 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 10) & 07;) CA 7826 src/dps8/dps8_ins.c cpu.rA = PROM[cpu.TPR.CA & 1023]; CA 7830 src/dps8/dps8_ins.c uint select = cpu.TPR.CA & 0x7; CA 8229 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) CA 8230 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) CA 8257 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) CA 8258 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) CA 8288 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 10) & 03;) CA 8289 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 10) & 07;) CA 9401 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, & cpu_dev, "absa CA:%08o\n", cpu.TPR.CA); CA 9407 src/dps8/dps8_ins.c * result = ((word36) (cpu.TPR.CA & MASK18)) << 12; // 24:12 format CA 34 src/dps8/dps8_mp.h word18 CA; CA 4155 src/dps8/dps8_sys.c { "cpus[].TPR.CA", SYM_STRUCT_OFFSET, SYM_UINT32_18, offsetof (struct tpr_s, CA) },