TSR 30 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TSR 77 src/dps8/doAppendCycleABSA.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { TSR 79 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TSR 84 src/dps8/doAppendCycleABSA.h fetch_dsptw (cpu.TPR.TSR); TSR 90 src/dps8/doAppendCycleABSA.h modify_dsptw (cpu.TPR.TSR); TSR 92 src/dps8/doAppendCycleABSA.h fetch_psdw (cpu.TPR.TSR); TSR 94 src/dps8/doAppendCycleABSA.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. TSR 97 src/dps8/doAppendCycleABSA.h load_sdwam (cpu.TPR.TSR, nomatch); TSR 157 src/dps8/doAppendCycleABSA.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TSR 244 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 266 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 283 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TSR 28 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TSR 81 src/dps8/doAppendCycleAPUDataRMW.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { TSR 83 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TSR 88 src/dps8/doAppendCycleAPUDataRMW.h fetch_dsptw (cpu.TPR.TSR); TSR 94 src/dps8/doAppendCycleAPUDataRMW.h modify_dsptw (cpu.TPR.TSR); TSR 96 src/dps8/doAppendCycleAPUDataRMW.h fetch_psdw (cpu.TPR.TSR); TSR 98 src/dps8/doAppendCycleAPUDataRMW.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. TSR 106 src/dps8/doAppendCycleAPUDataRMW.h load_sdwam (cpu.TPR.TSR, nomatch); TSR 171 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TSR 189 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TSR == cpu.PPR.PSR) TSR 295 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 323 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 349 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TSR 28 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TSR 82 src/dps8/doAppendCycleAPUDataRead.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { TSR 84 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TSR 89 src/dps8/doAppendCycleAPUDataRead.h fetch_dsptw (cpu.TPR.TSR); TSR 95 src/dps8/doAppendCycleAPUDataRead.h modify_dsptw (cpu.TPR.TSR); TSR 97 src/dps8/doAppendCycleAPUDataRead.h fetch_psdw (cpu.TPR.TSR); TSR 99 src/dps8/doAppendCycleAPUDataRead.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. TSR 107 src/dps8/doAppendCycleAPUDataRead.h load_sdwam (cpu.TPR.TSR, nomatch); TSR 166 src/dps8/doAppendCycleAPUDataRead.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TSR 255 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 281 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 300 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TSR 28 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TSR 80 src/dps8/doAppendCycleAPUDataStore.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { TSR 82 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TSR 87 src/dps8/doAppendCycleAPUDataStore.h fetch_dsptw (cpu.TPR.TSR); TSR 93 src/dps8/doAppendCycleAPUDataStore.h modify_dsptw (cpu.TPR.TSR); TSR 95 src/dps8/doAppendCycleAPUDataStore.h fetch_psdw (cpu.TPR.TSR); TSR 97 src/dps8/doAppendCycleAPUDataStore.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. TSR 105 src/dps8/doAppendCycleAPUDataStore.h load_sdwam (cpu.TPR.TSR, nomatch); TSR 154 src/dps8/doAppendCycleAPUDataStore.h if (cpu.TPR.TSR == cpu.PPR.PSR) TSR 256 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 284 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 303 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TSR 64 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TSR 97 src/dps8/doAppendCycleIndirectWordFetch.h if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) TSR 173 src/dps8/doAppendCycleIndirectWordFetch.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { TSR 175 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TSR 179 src/dps8/doAppendCycleIndirectWordFetch.h fetch_dsptw (cpu.TPR.TSR); TSR 185 src/dps8/doAppendCycleIndirectWordFetch.h modify_dsptw (cpu.TPR.TSR); TSR 187 src/dps8/doAppendCycleIndirectWordFetch.h fetch_psdw (cpu.TPR.TSR); TSR 189 src/dps8/doAppendCycleIndirectWordFetch.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. TSR 197 src/dps8/doAppendCycleIndirectWordFetch.h load_sdwam (cpu.TPR.TSR, nomatch); TSR 262 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TSR 363 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 392 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 399 src/dps8/doAppendCycleIndirectWordFetch.h ucCacheSave (this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); TSR 468 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TSR 75 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TSR 148 src/dps8/doAppendCycleInstructionFetch.h cacheHit = ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); TSR 151 src/dps8/doAppendCycleInstructionFetch.h if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) TSR 221 src/dps8/doAppendCycleInstructionFetch.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { TSR 223 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TSR 228 src/dps8/doAppendCycleInstructionFetch.h fetch_dsptw (cpu.TPR.TSR); TSR 234 src/dps8/doAppendCycleInstructionFetch.h modify_dsptw (cpu.TPR.TSR); TSR 236 src/dps8/doAppendCycleInstructionFetch.h fetch_psdw (cpu.TPR.TSR); TSR 238 src/dps8/doAppendCycleInstructionFetch.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. TSR 246 src/dps8/doAppendCycleInstructionFetch.h load_sdwam (cpu.TPR.TSR, nomatch); TSR 494 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 523 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 551 src/dps8/doAppendCycleInstructionFetch.h sim_printf ("ins fetch err %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TSR 556 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TSR 561 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TSR 576 src/dps8/doAppendCycleInstructionFetch.h ucCacheSave (this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); TSR 632 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.PSR = cpu.TPR.TSR; TSR 657 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TSR 28 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TSR 82 src/dps8/doAppendCycleOperandRMW.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { TSR 84 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TSR 88 src/dps8/doAppendCycleOperandRMW.h fetch_dsptw (cpu.TPR.TSR); TSR 94 src/dps8/doAppendCycleOperandRMW.h modify_dsptw (cpu.TPR.TSR); TSR 96 src/dps8/doAppendCycleOperandRMW.h fetch_psdw (cpu.TPR.TSR); TSR 98 src/dps8/doAppendCycleOperandRMW.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. TSR 106 src/dps8/doAppendCycleOperandRMW.h load_sdwam (cpu.TPR.TSR, nomatch); TSR 171 src/dps8/doAppendCycleOperandRMW.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TSR 189 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TSR == cpu.PPR.PSR) TSR 294 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 322 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 354 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TSR 70 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TSR 137 src/dps8/doAppendCycleOperandRead.h cacheHit = ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); TSR 139 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "test cache check %s %d %u %05o:%06o %05o %o %08o %o %o", cacheHit ? "hit" : "miss", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, cachedBound, cachedP, cachedAddress, cachedR1, cachedPaged); TSR 143 src/dps8/doAppendCycleOperandRead.h if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) { TSR 145 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TSR 161 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TSR 171 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "skip %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TSR 234 src/dps8/doAppendCycleOperandRead.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { TSR 236 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TSR 240 src/dps8/doAppendCycleOperandRead.h fetch_dsptw (cpu.TPR.TSR); TSR 246 src/dps8/doAppendCycleOperandRead.h modify_dsptw (cpu.TPR.TSR); TSR 248 src/dps8/doAppendCycleOperandRead.h fetch_psdw (cpu.TPR.TSR); TSR 250 src/dps8/doAppendCycleOperandRead.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. TSR 258 src/dps8/doAppendCycleOperandRead.h load_sdwam (cpu.TPR.TSR, nomatch); TSR 331 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TSR 386 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(E): E %o G %o PSR %05o TSR %05o CA %06o " "EB %06o R %o%o%o TRR %o PRR %o\n", cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu.SDW->EB, cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.TPR.TRR, cpu.PPR.PRR); TSR 403 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS) TSR 598 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 630 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 660 src/dps8/doAppendCycleOperandRead.h sim_printf ("oprnd read err %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TSR 665 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TSR 670 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TSR 675 src/dps8/doAppendCycleOperandRead.h ucCacheSave (this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); TSR 678 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "cache %d %u %05o:%06o %05o %o %08o %o %o", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); TSR 737 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PSR = cpu.TPR.TSR; TSR 784 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PSR = cpu.TPR.TSR; TSR 798 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TSR 28 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TSR 81 src/dps8/doAppendCycleOperandStore.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { TSR 83 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TSR 88 src/dps8/doAppendCycleOperandStore.h fetch_dsptw (cpu.TPR.TSR); TSR 94 src/dps8/doAppendCycleOperandStore.h modify_dsptw (cpu.TPR.TSR); TSR 96 src/dps8/doAppendCycleOperandStore.h fetch_psdw (cpu.TPR.TSR); TSR 98 src/dps8/doAppendCycleOperandStore.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. TSR 106 src/dps8/doAppendCycleOperandStore.h load_sdwam (cpu.TPR.TSR, nomatch); TSR 149 src/dps8/doAppendCycleOperandStore.h if (cpu.TPR.TSR == cpu.PPR.PSR) TSR 254 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 282 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 306 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TSR 28 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TSR 88 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TSR = 0; TSR 89 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("RTCD_OPERAND_FETCH ABSOLUTE mode set TSR %05o TRR %o\n", cpu.TPR.TSR, cpu.TPR.TRR); TSR 112 src/dps8/doAppendCycleRTCDOperandFetch.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { TSR 114 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TSR 118 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_dsptw (cpu.TPR.TSR); TSR 124 src/dps8/doAppendCycleRTCDOperandFetch.h modify_dsptw (cpu.TPR.TSR); TSR 126 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_psdw (cpu.TPR.TSR); TSR 128 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. TSR 136 src/dps8/doAppendCycleRTCDOperandFetch.h load_sdwam (cpu.TPR.TSR, nomatch); TSR 195 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TSR 293 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 319 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 347 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TSR = GET_ITS_SEGNO (data); TSR 366 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PSR = cpu.TPR.TSR; TSR 392 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TSR 224 src/dps8/dps8_addrmods.c cpu.TPR.TSR = cpu.PR[n].SNR; TSR 260 src/dps8/dps8_addrmods.c cpu.TPR.TSR = GET_ITS_SEGNO (cpu.itxPair); TSR 1211 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.TPR.TSR); TSR 1279 src/dps8/dps8_append.c cpu.TPR.TSR = 0; TSR 1281 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.TRR); TSR 1304 src/dps8/dps8_append.c if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) TSR 1308 src/dps8/dps8_append.c cpu.TPR.TSR); TSR 1315 src/dps8/dps8_append.c fetch_dsptw (cpu.TPR.TSR); TSR 1322 src/dps8/dps8_append.c modify_dsptw (cpu.TPR.TSR); TSR 1324 src/dps8/dps8_append.c fetch_psdw (cpu.TPR.TSR); TSR 1327 src/dps8/dps8_append.c fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. TSR 1340 src/dps8/dps8_append.c load_sdwam (cpu.TPR.TSR, nomatch); TSR 1449 src/dps8/dps8_append.c if (cpu.PPR.PSR != cpu.TPR.TSR) TSR 1479 src/dps8/dps8_append.c if (cpu.TPR.TSR == cpu.PPR.PSR) TSR 1599 src/dps8/dps8_append.c cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, TSR 1619 src/dps8/dps8_append.c if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS) TSR 1845 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 1883 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TSR 2029 src/dps8/dps8_append.c cpu.TPR.TSR = GET_ITS_SEGNO (data); TSR 2115 src/dps8/dps8_append.c cpu.PPR.PSR = cpu.TPR.TSR; TSR 2169 src/dps8/dps8_append.c cpu.PPR.PSR = cpu.TPR.TSR; TSR 2219 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TSR 2683 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 2698 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 2766 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 3059 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 4455 src/dps8/dps8_cpu.c putbits36_15 (& w0, 0, cpu.TPR.TSR); TSR 82 src/dps8/dps8_cpu.h word15 TSR; // The current effective segment number TSR 570 src/dps8/dps8_eis.c cpu.TPR.TSR = p -> SNR; TSR 583 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TSR 596 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 607 src/dps8/dps8_eis.c __func__, p -> cachedParagraph [i], cpu.TPR.TSR, p -> cachedAddr + i); TSR 611 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TSR 647 src/dps8/dps8_eis.c cpu.TPR.TSR = p -> SNR; TSR 650 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TSR 666 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 671 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TSR 678 src/dps8/dps8_eis.c __func__, p -> cachedParagraph [i], cpu.TPR.TSR, paragraphAddress + i); TSR 810 src/dps8/dps8_eis.c cpu.TPR.TSR = p -> SNR; TSR 820 src/dps8/dps8_eis.c __func__, data [i], cpu.TPR.TSR, addressN + i); TSR 833 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 843 src/dps8/dps8_eis.c __func__, data [i], cpu.TPR.TSR, addressN + i); TSR 872 src/dps8/dps8_eis.c cpu.TPR.TSR = p -> SNR; TSR 882 src/dps8/dps8_eis.c __func__, data [i], cpu.TPR.TSR, addressN + i); TSR 895 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 905 src/dps8/dps8_eis.c __func__, data [i], cpu.TPR.TSR, addressN + i); TSR 120 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 128 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read BAR"); TSR 129 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read BAR"); TSR 145 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read"); TSR 146 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read"); TSR 195 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 200 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRead BAR"); TSR 201 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead BAR"); TSR 210 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRead"); TSR 211 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead"); TSR 257 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 262 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "readOperandRead BAR"); TSR 263 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead BAR"); TSR 273 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "readOperandRead"); TSR 274 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead"); TSR 321 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 326 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadOperandRMW BAR"); TSR 327 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW BAR"); TSR 336 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadOperandRMW"); TSR 337 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW"); TSR 383 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 388 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRMW BAR"); TSR 389 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW BAR"); TSR 398 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRMW"); TSR 399 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW"); TSR 447 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 452 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadInstructionFetch BAR"); TSR 453 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch BAR"); TSR 462 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadInstructionFetch"); TSR 463 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch"); TSR 509 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 514 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch BAR"); TSR 515 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch BAR"); TSR 524 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch"); TSR 525 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch"); TSR 584 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 592 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR"); TSR 593 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn"); TSR 594 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd"); TSR 610 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2"); TSR 611 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn"); TSR 612 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd"); TSR 669 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 677 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRead BR"); TSR 678 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead BR evn"); TSR 679 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead BR odd"); TSR 693 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRead"); TSR 694 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead evn"); TSR 695 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead odd"); TSR 751 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 759 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRMW BR"); TSR 760 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW BR evn"); TSR 761 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW BR odd"); TSR 771 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRMW"); TSR 772 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW evn"); TSR 773 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW odd"); TSR 829 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 837 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2InstructionFetch BR"); TSR 838 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch BR evn"); TSR 839 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch BR odd"); TSR 849 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2InstructionFetch"); TSR 850 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch evn"); TSR 851 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch odd"); TSR 866 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 874 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR"); TSR 875 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn"); TSR 876 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd"); TSR 886 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2"); TSR 887 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn"); TSR 888 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd"); TSR 941 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 949 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch BR"); TSR 950 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch BR evn"); TSR 951 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch BR odd"); TSR 961 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch"); TSR 962 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch evn"); TSR 963 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch odd"); TSR 1037 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 1050 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read8 BAR"); TSR 1052 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result[i], "Read8 BAR"); TSR 1072 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read8"); TSR 1074 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "Read8"); TSR 1161 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 1174 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadPage B"); TSR 1176 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage B"); TSR 1197 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadPage"); TSR 1199 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage"); TSR 1253 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 1258 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write BR"); TSR 1259 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write BR"); TSR 1266 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write"); TSR 1267 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write"); TSR 1315 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 1320 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteAPUDataStore BR"); TSR 1321 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore BR"); TSR 1328 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteAPUDataStore"); TSR 1329 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore"); TSR 1381 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 1386 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteOperandStore BR"); TSR 1387 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore BR"); TSR 1394 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteOperandStore"); TSR 1395 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore"); TSR 1459 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 1467 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2 BR"); TSR 1468 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 BR evn"); TSR 1469 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 BR odd"); TSR 1481 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2"); TSR 1482 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 evn"); TSR 1483 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 odd"); TSR 1532 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 1537 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2OperandStore BR"); TSR 1538 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore BR evn"); TSR 1539 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore BR odd"); TSR 1546 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2OperandStore"); TSR 1547 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore evn"); TSR 1548 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore odd"); TSR 1606 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 1615 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write1 BR"); TSR 1616 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1 BR"); TSR 1629 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write1"); TSR 1630 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1"); TSR 1701 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 1714 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write8 BR"); TSR 1716 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8 BR"); TSR 1734 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write8"); TSR 1736 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8"); TSR 1830 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 1844 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WritePage BR"); TSR 1846 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage BR"); TSR 1863 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WritePage"); TSR 1865 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage"); TSR 384 src/dps8/dps8_ins.c putbits36_15 (& words[2], 3, cpu.TPR.TSR); TSR 638 src/dps8/dps8_ins.c cpu.TPR.TSR = getbits36_15 (words[2], 3); TSR 1835 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 1884 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PAR[n].SNR; TSR 1890 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, "doPtrReg: n=%o offset=%05o TPR.CA=%06o " "TPR.TBR=%o TPR.TSR=%05o TPR.TRR=%o\n", n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR); TSR 1907 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 1999 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; TSR 2631 src/dps8/dps8_ins.c cpu.PR[n].SNR = cpu.TPR.TSR; TSR 2943 src/dps8/dps8_ins.c cpu.PR[n].SNR = cpu.TPR.TSR; TSR 3352 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.TPR.TSR & MASK15) << 18; TSR 32 src/dps8/dps8_mp.h word15 TSR; TSR 4153 src/dps8/dps8_sys.c { "cpus[].TPR.TSR", SYM_STRUCT_OFFSET, SYM_UINT16_15, offsetof (struct tpr_s, TSR) },