cpu_dev 332 src/dps8/doAppendCycleAPUDataRMW.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 288 src/dps8/doAppendCycleAPUDataRead.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 293 src/dps8/doAppendCycleAPUDataStore.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 403 src/dps8/doAppendCycleIndirectWordFetch.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 580 src/dps8/doAppendCycleInstructionFetch.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 331 src/dps8/doAppendCycleOperandRMW.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 685 src/dps8/doAppendCycleOperandRead.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 291 src/dps8/doAppendCycleOperandStore.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 328 src/dps8/doAppendCycleRTCDOperandFetch.h sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 80 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 106 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 198 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 242 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 262 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 286 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 318 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, "do_ITS_ITP sets XSF to 1\n"); cpu_dev 328 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 337 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 377 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 380 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 416 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 439 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 473 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, "R_MOD: Cr=%06o\n", Cr); cpu_dev 477 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 507 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, "R_MOD: TPR.CA=%06o\n", cpu_dev 516 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, "RI_MOD: Td=%o\n", Td); cpu_dev 529 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 554 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 613 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 631 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 641 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 670 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 675 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 685 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 740 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 747 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 750 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 799 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 838 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 853 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 865 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 961 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 997 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1024 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1038 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1045 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1066 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1082 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1085 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1115 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1145 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1152 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1155 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1183 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1204 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1220 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1223 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1241 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1273 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1288 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1312 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1355 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1373 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1395 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1418 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1467 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1485 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1506 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1532 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 56 src/dps8/dps8_append.c # define DBGAPP(...) sim_debug (DBG_APPENDING, & cpu_dev, __VA_ARGS__) cpu_dev 1896 src/dps8/dps8_append.c sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 717 src/dps8/dps8_cpu.c sim_msg ("Number of CPUs in system is %d\n", cpu_dev.numunits); cpu_dev 729 src/dps8/dps8_cpu.c cpu_dev.numunits = (uint32) n; cpu_dev 906 src/dps8/dps8_cpu.c sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to %s\n", cpu_dev 1599 src/dps8/dps8_cpu.c sim_debug (DBG_INFO, & cpu_dev, "CPU reset: Running\n"); cpu_dev 1672 src/dps8/dps8_cpu.c DEVICE cpu_dev = cpu_dev 1893 src/dps8/dps8_cpu.c cpu_dev 1926 src/dps8/dps8_cpu.c cpu_dev 2159 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, "set_temporary_absolute_mode bit 29 sets XSF to 0\n"); cpu_dev 2199 src/dps8/dps8_cpu.c set_cpu_idx (cpu_dev.numunits - 1); cpu_dev 2204 src/dps8/dps8_cpu.c for (c = 0; c < cpu_dev.numunits; c ++) cpu_dev 2210 src/dps8/dps8_cpu.c if (c == cpu_dev.numunits) cpu_dev 2215 src/dps8/dps8_cpu.c set_cpu_idx ((current + 1) % cpu_dev.numunits); cpu_dev 2373 src/dps8/dps8_cpu.c sim_debug (DBG_CYCLE, & cpu_dev, "Cycle is %s\n", cpu_dev 2409 src/dps8/dps8_cpu.c sim_debug (DBG_INTR, & cpu_dev, "intr_pair_addr %u flag %d\n", cpu_dev 2412 src/dps8/dps8_cpu.c if_sim_debug (DBG_INTR, & cpu_dev) cpu_dev 2593 src/dps8/dps8_cpu.c sim_debug (DBG_CYCLE, & cpu_dev, cpu_dev 2696 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, "fetchCycle bit 29 sets XSF to 0\n"); cpu_dev 2799 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 2807 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 3552 src/dps8/dps8_cpu.c sim_debug (DBG_WARN, & cpu_dev, cpu_dev 3580 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3647 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3729 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3747 src/dps8/dps8_cpu.c sim_debug (DBG_MSG, & cpu_dev, cpu_dev 3756 src/dps8/dps8_cpu.c sim_debug (DBG_WARN, & cpu_dev, cpu_dev 3784 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3793 src/dps8/dps8_cpu.c sim_debug (DBG_WARN, & cpu_dev, cpu_dev 3820 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3835 src/dps8/dps8_cpu.c sim_debug (DBG_MSG, & cpu_dev, cpu_dev 3869 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, "core_write2 %08o %012llo (%s)\n", addr - 1, cpu_dev 3895 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, "core_write2 %08o %012"PRIo64" (%s)\n", addr, odd, ctx); cpu_dev 4032 src/dps8/dps8_cpu.c sim_debug (DBG_DEBUG, & cpu_dev, "APU: Setting absolute mode.\n"); cpu_dev 4041 src/dps8/dps8_cpu.c sim_debug (DBG_DEBUG, & cpu_dev, "APU: Keeping append mode.\n"); cpu_dev 4043 src/dps8/dps8_cpu.c sim_debug (DBG_DEBUG, & cpu_dev, "APU: Setting append mode.\n"); cpu_dev 4049 src/dps8/dps8_cpu.c sim_debug (DBG_ERR, & cpu_dev, cpu_dev 472 src/dps8/dps8_cpu.h extern DEVICE cpu_dev; cpu_dev 420 src/dps8/dps8_decimal.c cpu_dev 422 src/dps8/dps8_decimal.c cpu_dev 450 src/dps8/dps8_decimal.c cpu_dev 465 src/dps8/dps8_decimal.c cpu_dev 468 src/dps8/dps8_decimal.c cpu_dev 476 src/dps8/dps8_decimal.c cpu_dev 482 src/dps8/dps8_decimal.c cpu_dev 501 src/dps8/dps8_decimal.c cpu_dev 530 src/dps8/dps8_decimal.c cpu_dev 547 src/dps8/dps8_decimal.c cpu_dev 569 src/dps8/dps8_decimal.c cpu_dev 582 src/dps8/dps8_decimal.c cpu_dev 600 src/dps8/dps8_decimal.c cpu_dev 604 src/dps8/dps8_decimal.c cpu_dev 611 src/dps8/dps8_decimal.c cpu_dev 620 src/dps8/dps8_decimal.c cpu_dev 645 src/dps8/dps8_decimal.c cpu_dev 669 src/dps8/dps8_decimal.c cpu_dev 687 src/dps8/dps8_decimal.c cpu_dev 695 src/dps8/dps8_decimal.c cpu_dev 32 src/dps8/dps8_decimal.h if_sim_debug (DBG_TRACEEXT, & cpu_dev) \ cpu_dev 42 src/dps8/dps8_decimal.h if_sim_debug (DBG_TRACEEXT, & cpu_dev) \ cpu_dev 562 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteCache addr %06o\n", p->cachedAddr); cpu_dev 572 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 577 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 583 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 600 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 605 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 611 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 626 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadCache addr %06o\n", address); cpu_dev 650 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 653 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 656 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 671 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 673 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 676 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 694 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteIdx addr %06o n %u\n", cpu.du.Dk_PTR_W[eisaddr_idx], n); cpu_dev 697 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteIdx addr %06o n %u\n", p->address, n); cpu_dev 733 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadIdx addr %06o n %u\n", cpu.du.Dk_PTR_W[eisaddr_idx], n); cpu_dev 737 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadIdx %ld addr %06o n %u\n", eisaddr_idx, p->address, n); cpu_dev 763 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISRead addr %06o\n", cpu.du.Dk_PTR_W[eisaddr_idx]); cpu_dev 765 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISRead addr %06o\n", p->address); cpu_dev 776 src/dps8/dps8_eis.c cpu_dev 778 src/dps8/dps8_eis.c cpu_dev 798 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s addr %06o\n", __func__, addressN); cpu_dev 814 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 818 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 822 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 838 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 841 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 860 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s addr %06o\n", __func__, addressN); cpu_dev 876 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 880 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 884 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 900 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 903 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 965 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISGet469 : k: %u TAk %u coffset %u c %o \n", k, cpu.du.TAk[k - 1], residue, c); cpu_dev 967 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISGet469 : k: %u TAk %u coffset %u c %o \n", k, e -> TA [k - 1], residue, c); cpu_dev 1280 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "AR n %u k %u\n", n, k - 1); cpu_dev 1285 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "No ARb %u\n", k - 1); cpu_dev 1312 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "No ARa %u\n", k - 1); cpu_dev 1428 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "AR n %u k %u\n", n, k - 1); cpu_dev 1435 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "initial CN%u %u\n", k, CN); cpu_dev 1470 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "N%u %o\n", k, e->N[k-1]); cpu_dev 1514 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA4\n", cpu_dev 1538 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA6\n", cpu_dev 1552 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 1564 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA9\n", cpu_dev 1719 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(): N%u %0o\n", k, e->N[k-1]); cpu_dev 1817 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(): address:%06o cPos:%d bPos:%d N%u %u\n", cpu.du.Dk_PTR_W[k-1], a->cPos, a->bPos, k, e->N[k-1]); cpu_dev 1819 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(): address:%06o cPos:%d bPos:%d N%u %u\n", a->address, a->cPos, a->bPos, k, e->N[k-1]); cpu_dev 1857 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d AR%d\n", k, n); cpu_dev 1877 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d RL reg %u val %"PRIo64"\n", k, reg, (word36)e->N[k-1]); cpu_dev 1884 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d opdesc %012"PRIo64"\n", k, opDesc); cpu_dev 1885 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "N%u %u\n", k, e->N[k-1]); cpu_dev 2108 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r); cpu_dev 2113 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn)); cpu_dev 2116 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd augend 0%o\n", augend); cpu_dev 2122 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd force augend 0%o\n", augend); cpu_dev 2141 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum); cpu_dev 2250 src/dps8/dps8_eis.c cpu_dev 2281 src/dps8/dps8_eis.c cpu_dev 2332 src/dps8/dps8_eis.c cpu_dev 2370 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2376 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "awd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn)); cpu_dev 2382 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "awd augend 0%o\n", augend); cpu_dev 2387 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "awd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum); cpu_dev 2445 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r); cpu_dev 2450 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn)); cpu_dev 2456 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd minued 0%o\n", minued); cpu_dev 2461 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd minued 0%o subtractend 0%o difference 0%o\n", minued, subtractend, difference); cpu_dev 2482 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd r 0%o\n", r); cpu_dev 2484 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r); cpu_dev 2768 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d r 0%"PRIo64"\n", sz, rcnt); cpu_dev 2784 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r); cpu_dev 2861 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum); cpu_dev 3040 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpc tally %d c1 %03o c2 %03o\n", cpu.du.CHTALLY, c1, c2); cpu_dev 3917 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 3920 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 3984 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4011 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4112 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4115 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4179 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4207 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4436 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, TA1, TA2, e -> N1, e -> N2, e -> CN1, e -> CN2); cpu_dev 4438 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, e -> TA1, e -> TA2, e -> N1, e -> N2, e -> CN1, e -> CN2); cpu_dev 4473 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #3\n"); cpu_dev 4513 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #4\n"); cpu_dev 4553 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #1\n"); cpu_dev 4583 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #2\n"); cpu_dev 4848 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MRL special case #1\n"); cpu_dev 4879 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MRL special case #2\n"); cpu_dev 5042 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "src: %d: %o\n", n, c); cpu_dev 5164 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 5166 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "inBuffer:"); cpu_dev 5168 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, " %02o", * q); cpu_dev 5169 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "\n"); cpu_dev 5842 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "LTE IT[%d]<=%d\n", e -> mopIF - 1, next); cpu_dev 5893 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC IF %d, srcTally %d, dstTally %d\n", e->mopIF, e->srcTally, e->dstTally); cpu_dev 5896 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC n %d, srcTally %d, dstTally %d\n", n, e->srcTally, e->dstTally); cpu_dev 5908 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC c %d (0%o)\n", c, c); cpu_dev 5911 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC ES off\n"); cpu_dev 5913 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC is zero\n"); cpu_dev 5920 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC is not zero\n"); cpu_dev 5934 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC ES on\n"); cpu_dev 6004 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLS n %d c %o\n", n, c); cpu_dev 6010 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is off, c is zero; edit insertion table entry 1 is moved to the receiving field in place of the character.\n"); cpu_dev 6021 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is off, c is non-zero, SN is off; edit insertion table entry 3 is moved to the receiving field; the character is also moved to the receiving field, and ES is set ON.\n"); cpu_dev 6042 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is off, c is non-zero, SN is OFF; edit insertion table entry 4 is moved to the receiving field; the character is also moved to the receiving field, and ES is set ON.\n"); cpu_dev 6056 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is ON, the character is moved to the receiving field.\n"); cpu_dev 6098 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MORS mopIF %d src %d dst %d\n", e->mopIF, e->srcTally, e->dstTally); cpu_dev 6140 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC mopIF %d\n", e->mopIF); cpu_dev 6144 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC n %d srcTally %d dstTally %d\n", n, e->srcTally, e->dstTally); cpu_dev 6152 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC write to output buffer %o\n", *e->in); cpu_dev 6161 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC done\n"); cpu_dev 6492 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MOP %s(%o) %o\n", m -> mopName, mop, e->mopIF); cpu_dev 6496 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "getMop(e->m == NULL || e->m->f == NULL): mop:%d IF:%d\n", mop, e->mopIF); cpu_dev 6544 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "mopExecutor srcTally %d dstTally %d mopTally %d\n", e->srcTally, e->dstTally, e->mopTally); cpu_dev 6548 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "mopExecutor EISgetMop forced break\n"); cpu_dev 6573 src/dps8/dps8_eis.c cpu_dev 6579 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6599 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "mop faults %o src %d dst %d mop %d\n", e->_faults, e->srcTally, e->dstTally, e->mopTally); cpu_dev 6616 src/dps8/dps8_eis.c cpu_dev 6632 src/dps8/dps8_eis.c cpu_dev 6653 src/dps8/dps8_eis.c sim_debug(DBG_TRACEEXT, & cpu_dev, "mve\n"); cpu_dev 6950 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6954 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7179 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7657 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 7660 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 7663 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 7702 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "n1 %d sc1 %d\n", n1, sc1); cpu_dev 7733 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "n2 %d\n", n2); cpu_dev 7755 src/dps8/dps8_eis.c if_sim_debug (DBG_CAC, & cpu_dev) cpu_dev 7766 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "mvn res: '%s'\n", res); cpu_dev 7888 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "is neg %o\n", decNumberIsNegative(op1)); cpu_dev 7889 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "is zero %o\n", decNumberIsZero(op1)); cpu_dev 7890 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "R %o\n", R); cpu_dev 7891 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "Trunc %o\n", Trunc); cpu_dev 7892 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "TRUNC %o\n", TST_I_TRUNC); cpu_dev 7893 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "OMASK %o\n", TST_I_OMASK); cpu_dev 7894 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "tstOVFfault %o\n", tstOVFfault ()); cpu_dev 7895 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "T %o\n", T); cpu_dev 7896 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "EOvr %o\n", EOvr); cpu_dev 7897 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "Ovr %o\n", Ovr); cpu_dev 8030 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8299 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8303 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8516 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8686 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8690 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8890 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb N1 %d N2 %d\n", e -> N1, e -> N2); cpu_dev 8917 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(min(e->N1, e->N2)) i %d b1 %d b2 %d\n", i, b1, b2); cpu_dev 8937 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(e->N1 < e->N2) i %d b1fill %d b2 %d\n", i, b1, b2); cpu_dev 8957 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(e->N1 > e->N2) i %d b1 %d b2fill %d\n", i, b1, b2); cpu_dev 9554 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 9720 src/dps8/dps8_eis.c cpu_dev 9745 src/dps8/dps8_eis.c cpu_dev 9756 src/dps8/dps8_eis.c cpu_dev 9778 src/dps8/dps8_eis.c cpu_dev 9799 src/dps8/dps8_eis.c cpu_dev 9820 src/dps8/dps8_eis.c cpu_dev 9840 src/dps8/dps8_eis.c cpu_dev 9847 src/dps8/dps8_eis.c cpu_dev 12376 src/dps8/dps8_eis.c cpu_dev 12378 src/dps8/dps8_eis.c cpu_dev 12407 src/dps8/dps8_eis.c cpu_dev 12422 src/dps8/dps8_eis.c cpu_dev 12425 src/dps8/dps8_eis.c cpu_dev 12435 src/dps8/dps8_eis.c cpu_dev 12441 src/dps8/dps8_eis.c cpu_dev 12460 src/dps8/dps8_eis.c cpu_dev 12550 src/dps8/dps8_eis.c cpu_dev 12567 src/dps8/dps8_eis.c cpu_dev 12589 src/dps8/dps8_eis.c cpu_dev 12602 src/dps8/dps8_eis.c cpu_dev 12616 src/dps8/dps8_eis.c cpu_dev 12620 src/dps8/dps8_eis.c cpu_dev 12627 src/dps8/dps8_eis.c cpu_dev 12636 src/dps8/dps8_eis.c cpu_dev 12679 src/dps8/dps8_eis.c cpu_dev 12716 src/dps8/dps8_eis.c cpu_dev 12734 src/dps8/dps8_eis.c cpu_dev 12742 src/dps8/dps8_eis.c cpu_dev 12924 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: clz1 %d clz2 %d\n",clz1,clz2); cpu_dev 12930 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d S1 %d S2 %d N1 %d N2 %d clz1 %d clz2 %d E1 %d E2 %d SF2 %d NQ %d\n",e->S1,e->S2,e->N1,e->N2,clz1,clz2,op1->exponent,op2->exponent,e->SF2,NQ); cpu_dev 12951 src/dps8/dps8_eis.c ) { sim_debug (DBG_TRACEEXT, & cpu_dev, "oops! dv2d anomalous results"); } // divide by zero has already been checked before cpu_dev 13004 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: exp1 %d exp2 %d digits op1 %d op2 %d op1a %d op2a %d\n",op1->exponent,op2->exponent,op1->digits,op2->digits,_1a.digits,_2a.digits); cpu_dev 13015 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: addzero n2 %d %s exp %d\n",n2,res,op3->exponent); cpu_dev 13352 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: clz1 %d clz2 %d\n",clz1,clz2); cpu_dev 13358 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d S1 %d S2 %d N1 %d N2 %d clz1 %d clz2 %d E1 %d E2 %d SF3 %d NQ %d\n",e->S1,e->S2,e->N1,e->N2,clz1,clz2,op1->exponent,op2->exponent,e->SF3,NQ); cpu_dev 13379 src/dps8/dps8_eis.c ) { sim_debug (DBG_TRACEEXT, & cpu_dev, "oops! dv3d anomalous results"); } // divide by zero has already been checked before cpu_dev 13432 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: exp1 %d exp2 %d digits op1 %d op2 %d op1a %d op2a %d\n",op1->exponent,op2->exponent,op1->digits,op2->digits,_1a.digits,_2a.digits); cpu_dev 13443 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: addzero n3 %d %s exp %d\n",n3,res,op3->exponent); cpu_dev 395 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 409 src/dps8/dps8_faults.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 546 src/dps8/dps8_faults.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MIF %o\n", TST_I_MIF); cpu_dev 548 src/dps8/dps8_faults.c cpu_dev 674 src/dps8/dps8_faults.c sim_debug (DBG_CYCLE, & cpu_dev, "Changing fault number to Trouble fault\n"); cpu_dev 717 src/dps8/dps8_faults.c sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to FAULT_cycle\n"); cpu_dev 725 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 729 src/dps8/dps8_faults.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 804 src/dps8/dps8_faults.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MIF %o\n", TST_I_MIF); cpu_dev 848 src/dps8/dps8_faults.c sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to FAULT_cycle\n"); cpu_dev 897 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, "setG7fault CPU %d fault %d (%o) sub %"PRId64" %"PRIo64"\n", cpu_dev 909 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, "set_FFV_fault CPU f_fault_no %u\n", cpu_dev 82 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 103 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 123 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 140 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 172 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read: bar address=%08o readData=%012"PRIo64"\n", address, *result); cpu_dev 182 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read: abs address=%08o readData=%012"PRIo64"\n", address, *result); cpu_dev 198 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu_dev 208 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu_dev 234 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read: bar address=%08o readData=%012"PRIo64"\n", address, *result); cpu_dev 244 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read: abs address=%08o readData=%012"PRIo64"\n", address, *result); cpu_dev 260 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu_dev 271 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu_dev 298 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read: bar address=%08o readData=%012"PRIo64"\n", address, *result); cpu_dev 308 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read: abs address=%08o readData=%012"PRIo64"\n", address, *result); cpu_dev 324 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu_dev 334 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu_dev 360 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read: bar address=%08o readData=%012"PRIo64"\n", address, *result); cpu_dev 370 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read: abs address=%08o readData=%012"PRIo64"\n", address, *result); cpu_dev 386 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu_dev 396 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu_dev 424 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read: bar address=%08o readData=%012"PRIo64"\n", address, *result); cpu_dev 434 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read: abs address=%08o readData=%012"PRIo64"\n", address, *result); cpu_dev 450 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu_dev 460 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu_dev 486 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read: bar address=%08o readData=%012"PRIo64"\n", address, *result); cpu_dev 496 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read: abs address=%08o readData=%012"PRIo64"\n", address, *result); cpu_dev 512 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu_dev 522 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu_dev 553 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 555 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2 (Actual) Read: bar address=%08o" " readData=%012"PRIo64"\n", address + i, result [i]); cpu_dev 567 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 569 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2 (Actual) Read: abs address=%08o" " readData=%012"PRIo64"\n", address + i, result [i]); cpu_dev 587 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 589 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 599 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 601 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 603 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 606 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2 (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 638 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 640 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read: bar address=%08o" " readData=%012"PRIo64"\n", address + i, result [i]); cpu_dev 652 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 654 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read: abs address=%08o" " readData=%012"PRIo64"\n", address + i, result [i]); cpu_dev 672 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 674 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 684 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 686 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 688 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 690 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 720 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 722 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read: bar address=%08o" " readData=%012"PRIo64"\n", address + i, result [i]); cpu_dev 734 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 736 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read: abs address=%08o" " readData=%012"PRIo64"\n", address + i, result [i]); cpu_dev 754 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 756 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 766 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 768 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 798 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 800 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read: bar address=%08o" " readData=%012"PRIo64"\n", address + i, result [i]); cpu_dev 812 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 814 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read: abs address=%08o" " readData=%012"PRIo64"\n", address + i, result [i]); cpu_dev 832 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 834 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 844 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 846 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 869 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 871 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 881 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 883 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 910 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 912 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read: bar address=%08o" " readData=%012"PRIo64"\n", address + i, result [i]); cpu_dev 924 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) { cpu_dev 926 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read: abs address=%08o" " readData=%012"PRIo64"\n", address + i, result [i]); cpu_dev 944 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 946 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 956 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) { cpu_dev 958 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu_dev 994 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 997 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1014 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1017 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1041 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1044 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1063 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1066 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1118 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1121 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1138 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1141 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1165 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1168 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1188 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1191 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1227 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Write(Actual) Write: bar address=%08o writeData=%012"PRIo64"\n", address, data); cpu_dev 1240 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Write(Actual) Write: abs address=%08o writeData=%012"PRIo64"\n", address, data); cpu_dev 1256 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data); cpu_dev 1264 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data); cpu_dev 1292 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write: bar address=%08o writeData=%012"PRIo64"\n", address, data); cpu_dev 1302 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write: abs address=%08o writeData=%012"PRIo64"\n", address, data); cpu_dev 1318 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data); cpu_dev 1326 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data); cpu_dev 1355 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write: bar address=%08o writeData=%012"PRIo64"\n", address, data); cpu_dev 1368 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write: abs address=%08o writeData=%012"PRIo64"\n", address, data); cpu_dev 1384 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data); cpu_dev 1392 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data); cpu_dev 1429 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1440 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1462 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1476 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1512 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Write2OperandStore (Actual) Write: bar address=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n", address, data [0], data [1]); cpu_dev 1518 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Write2OperandStore (Actual) Write: abs address=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n", address, data [0], data [1]); cpu_dev 1535 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write2OperandStore (Actual) Write: bar iefpFinalAddress=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n", address, data [0], data [1]); cpu_dev 1544 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write2OperandStore (Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n", address, data [0], data [1]); cpu_dev 1573 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1588 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1610 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1624 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1658 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1661 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1678 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1681 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1705 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1708 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1725 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1728 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1787 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1790 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1807 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 1810 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 1834 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1837 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 1854 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1857 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 93 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 148 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 172 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, &cpu_dev, cpu_dev 175 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, &cpu_dev, cpu_dev 194 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 207 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 233 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 291 src/dps8/dps8_ins.c sim_debug (DBG_TRACE, & cpu_dev, "%s %05o:%06o\n", cpu_dev 307 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "CU: P %d IR %#o PSR %0#o IC %0#o TSR %0#o\n", cpu_dev 310 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "CU: xsf %d rf %d rpt %d rd %d rl %d pot %d xde %d xdo %d itp %d rfi %d its %d fif %d hold %0#o\n", cpu_dev 315 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "CU: iwb %012"PRIo64" irodd %012"PRIo64"\n", cpu_dev 468 src/dps8/dps8_ins.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 584 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s sets XSF to %o\n", __func__, cpu.cu.XSF); cpu_dev 1160 src/dps8/dps8_ins.c if_sim_debug (flag, &cpu_dev) cpu_dev 1174 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o|%06o %s\n", cpu_dev 1179 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o %s\n", cpu.PPR.IC, where); cpu_dev 1186 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%05o:%06o|%06o %s\n", cpu_dev 1192 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%05o:%06o %s\n", cpu_dev 1202 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1220 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1240 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1259 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1763 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD first %d rpt %d rd %d e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], !! (cpu.rX[0] & 01000), !! (cpu.rX[0] & 0400)); cpu_dev 1764 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD CA %06o\n", cpu.TPR.CA); cpu_dev 1790 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; offset is %06o\n", offset); cpu_dev 1794 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d was %06o\n", Xn, cpu.rX[Xn]); cpu_dev 1801 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu_dev 1817 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, "initialize EIS descriptors\n"); cpu_dev 1875 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, "doPtrReg: PR[%o] SNR=%05o RNR=%o WORDNO=%06o " "BITNO=%02o\n", n, cpu.PAR[n].SNR, cpu.PAR[n].RNR, cpu.PAR[n].WORDNO, GET_PR_BITNO (n)); cpu_dev 1890 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, "doPtrReg: n=%o offset=%05o TPR.CA=%06o " "TPR.TBR=%o TPR.TSR=%05o TPR.TRR=%o\n", n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR); cpu_dev 2035 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta first %d rf %d rpt %d rd %d " "e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, rf, cpu.cu.rpt, cpu.cu.rd, icOdd, cpu.rX[0], rptA, rptB); cpu_dev 2045 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu_dev 2061 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu_dev 2073 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu_dev 2125 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "tally %d\n", x); cpu_dev 2127 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "tally runout\n"); cpu_dev 2131 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "not tally runout\n"); cpu_dev 2139 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is zero terminate\n"); cpu_dev 2144 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not zero terminate\n"); cpu_dev 2149 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is neg terminate\n"); cpu_dev 2154 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not neg terminate\n"); cpu_dev 2159 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is carry terminate\n"); cpu_dev 2164 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not carry terminate\n"); cpu_dev 2169 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is overflow terminate\n"); cpu_dev 2182 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "not terminate\n"); cpu_dev 2218 src/dps8/dps8_ins.c if_sim_debug (DBG_REGDUMP, & cpu_dev) { cpu_dev 2220 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPAQI, &cpu_dev, "A=%012"PRIo64" Q=%012"PRIo64" IR:%s\n", cpu.rA, cpu.rQ, dump_flags (buf, cpu.cu.IR)); cpu_dev 2222 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPFLT, &cpu_dev, "E=%03o A=%012"PRIo64" Q=%012"PRIo64" %.10Lg\n", cpu.rE, cpu.rA, cpu.rQ, EAQToIEEElongdouble ()); cpu_dev 2224 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPFLT, &cpu_dev, "E=%03o A=%012"PRIo64" Q=%012"PRIo64" %.10g\n", cpu.rE, cpu.rA, cpu.rQ, EAQToIEEEdouble ()); cpu_dev 2226 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPIDX, &cpu_dev, "X[0]=%06o X[1]=%06o X[2]=%06o X[3]=%06o\n", cpu.rX[0], cpu.rX[1], cpu.rX[2], cpu.rX[3]); cpu_dev 2227 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPIDX, &cpu_dev, "X[4]=%06o X[5]=%06o X[6]=%06o X[7]=%06o\n", cpu.rX[4], cpu.rX[5], cpu.rX[6], cpu.rX[7]); cpu_dev 2229 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPPR, &cpu_dev, "PR%d/%s: SNR=%05o RNR=%o WORDNO=%06o BITNO:%02o ARCHAR:%o ARBITNO:%02o\n", n, PRalias[n], cpu.PR[n].SNR, cpu.PR[n].RNR, cpu.PR[n].WORDNO, GET_PR_BITNO (n), GET_AR_CHAR (n), GET_AR_BITNO (n)); cpu_dev 2231 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPPPR, &cpu_dev, "PRR:%o PSR:%05o P:%o IC:%06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu_dev 2232 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPDSBR, &cpu_dev, "ADDR:%08o BND:%05o U:%o STACK:%04o\n", cpu.DSBR.ADDR, cpu.DSBR.BND, cpu.DSBR.U, cpu.DSBR.STACK); cpu_dev 2854 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 4910 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "\n"); cpu_dev 4911 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 4914 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 4925 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, ">>> quot 1 %"PRId64"\n", quotient); cpu_dev 4926 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, ">>> rem 1 %"PRId64"\n", remainder); cpu_dev 4942 src/dps8/dps8_ins.c cpu_dev 4944 src/dps8/dps8_ins.c cpu_dev 4952 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 4954 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 4959 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 4967 src/dps8/dps8_ins.c sim_debug (DBG_ERR, & cpu_dev, cpu_dev 4979 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "rA (rem) %012"PRIo64"\n", cpu.rA); cpu_dev 4980 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "rQ (quot) %012"PRIo64"\n", cpu.rQ); cpu_dev 5641 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6123 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6778 src/dps8/dps8_ins.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 6797 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6805 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7229 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ldt TR %d (%o)\n", cpu_dev 7279 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RALR set to %o\n", cpu.rRALR); cpu_dev 8370 src/dps8/dps8_ins.c sim_debug (DBG_MSG, & cpu_dev, "BCE DIS causes CPU halt\n"); cpu_dev 8390 src/dps8/dps8_ins.c cpu_dev 8400 src/dps8/dps8_ins.c sim_debug (DBG_MSG, & cpu_dev, "sys_trouble$die DIS causes CPU halt\n"); cpu_dev 8405 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "entered DIS_cycle\n"); cpu_dev 8432 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS sees an interrupt\n"); cpu_dev 8449 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS sees a TRO\n"); cpu_dev 8455 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS refetches\n"); cpu_dev 9401 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, & cpu_dev, "absa CA:%08o\n", cpu.TPR.CA); cpu_dev 9432 src/dps8/dps8_ins.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 9456 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU interrupt return\n"); cpu_dev 9534 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU FIF REFETCH return\n"); cpu_dev 9542 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU rfi refetch return\n"); cpu_dev 9562 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU MME2 restart return\n"); cpu_dev 9578 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU rfi/FIF REFETCH return\n"); cpu_dev 9589 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU MME2 restart return\n"); cpu_dev 9620 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU sync fault return\n"); cpu_dev 9634 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU MMEx sync fault return\n"); cpu_dev 9644 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU LUF RESTART return\n"); cpu_dev 9661 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU ACV RESTART return\n"); cpu_dev 1214 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "fmp A %012"PRIo64" Q %012"PRIo64" E %03o\n", cpu.rA, cpu.rQ, cpu.rE); cpu_dev 2308 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dufm e1 %d %03o m1 %012"PRIo64" %012"PRIo64"\n", e1, e1, (word36) (m1 >> 36) & MASK36, (word36) m1 & MASK36); cpu_dev 2323 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dufm e2 %d %03o m2 %012"PRIo64" %012"PRIo64"\n", e2, e2, (word36) (m2 >> 36) & MASK36, (word36) m2 & MASK36); cpu_dev 1339 src/dps8/dps8_scu.c for (uint cpun = 0; cpun < cpu_dev.numunits; cpun ++) cpu_dev 31 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || ((1 << current_running_cpu_idx) & dbgCPUMask)) && \ cpu_dev 32 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || (((dptr)->dctrl & (DBG_INTR | DBG_FAULT))) || (! sim_deb_segno_on) || sim_deb_segno[cpu.PPR.PSR & (DEBUG_SEGNO_LIMIT - 1)]) && \ cpu_dev 33 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || sim_deb_ringno == NO_SUCH_RINGNO || sim_deb_ringno == cpu . PPR. PRR) && \ cpu_dev 34 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || (! sim_deb_bar) || (! TST_I_NBAR)) && \ cpu_dev 38 src/dps8/dps8_simh.h ((dptr != & cpu_dev) | (((dbits) & DBG_TRACE) ? (sim_deb_skip_cnt ++ >= sim_deb_skip_limit) : (sim_deb_skip_cnt >= sim_deb_skip_limit))) \ cpu_dev 1825 src/dps8/dps8_sys.c cpu_dev.numunits = 1; cpu_dev 2615 src/dps8/dps8_sys.c sim_debug (dflag, & cpu_dev, "%s", line); cpu_dev 2736 src/dps8/dps8_sys.c sim_debug (dflag, & cpu_dev, "%s", line); cpu_dev 2755 src/dps8/dps8_sys.c sim_debug (dflag, & cpu_dev, "%s", line); cpu_dev 4854 src/dps8/dps8_sys.c if (uptr == &cpu_dev.units[0]) cpu_dev 5058 src/dps8/dps8_sys.c & cpu_dev, // dev[0] is special to the scp interface; it is the 'default device' cpu_dev 178 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Add36b op1 %012"PRIo64" op2 %012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", op1, op2, carryin, flagsToSet, * flags); cpu_dev 249 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Add36b res %012"PRIo64" flags %06o ovf %o\n", res, * flags, * ovf); cpu_dev 615 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1 %012"PRIo64"%012"PRIo64" op2 %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", cpu_dev 618 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1 %012"PRIo64"%012"PRIo64" op2 %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", cpu_dev 659 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1e %012"PRIo64"%012"PRIo64" op2e %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", cpu_dev 662 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1e %012"PRIo64"%012"PRIo64" op2e %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", cpu_dev 673 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) (rshift_128 (res, 36).l & MASK36), (word36) (res.l & MASK36), * flags, * ovf); cpu_dev 675 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) ((res >> 36) & MASK36), (word36) (res & MASK36), * flags, * ovf); cpu_dev 753 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) (rshift_128 (res, 36).l & MASK36), (word36) (res.l & MASK36), * flags, * ovf); cpu_dev 755 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) ((res >> 36) & MASK36), (word36) (res & MASK36), * flags, * ovf); cpu_dev 1091 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1 %016"PRIx64"%016"PRIx64"\n", op1.h, op1.l); cpu_dev 1092 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2 %016"PRIx64"%016"PRIx64"\n", op2.h, op2.l); cpu_dev 1095 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\n", op1s.h, op1s.l); cpu_dev 1096 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2s %016"PRIx64"%016"PRIx64"\n", op2s.h, op2s.l); cpu_dev 1098 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1 %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op1>>64), (uint64_t) op1); cpu_dev 1099 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2 %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op2>>64), (uint64_t) op2); cpu_dev 1102 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op1s>>64), (uint64_t) op1s); cpu_dev 1103 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2s %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op2s>>64), (uint64_t) op2s);