root/src/dps8/ucache.c

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DEFINITIONS

This source file includes following definitions.
  1. ucInvalidate
  2. ucCacheSave
  3. ucCacheCheck
  4. ucacheStats
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 70f11728-171b-11ee-ac22-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2022 Charles Anthony
   9  * Copyright (c) 2022-2023 The DPS8M Development Team
  10  *
  11  * All rights reserved.
  12  *
  13  * This software is made available under the terms of the ICU
  14  * License, version 1.8.1 or later.  For more details, see the
  15  * LICENSE.md file at the top-level directory of this distribution.
  16  *
  17  * ---------------------------------------------------------------------------
  18  */
  19 
  20 #include <string.h>
  21 
  22 #include "dps8.h"
  23 #include "dps8_cpu.h"
  24 
  25 void ucInvalidate (void) {
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  26   memset (cpu.uCache.caches, 0, sizeof (cpu.uCache.caches));
  27 }
  28 
  29 void ucCacheSave (uint ucNum, word15 segno, word18 offset, word14 bound, word1 p, word24 address, word3 r1, bool paged) {
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  30   if (segno >= UC_CACHE_SZ) {
  31     return;
  32   }
  33   ucache_t * ep;
  34   ep          = & cpu.uCache.caches[ucNum][segno];
  35   ep->valid   = true;
  36   ep->segno   = segno;
  37   ep->offset  = offset;
  38   ep->bound   = bound;
  39   ep->address = address;
  40   ep->r1      = r1;
  41   ep->p       = p;
  42   ep->paged   = paged;
  43 #ifdef HDBG
  44   hdbgNote ("ucache", "save %u %05o:%06o %05o %o %08o %o %o", ucNum, segno, offset, bound, p, address, r1, paged);
  45 #endif
  46 }
  47 
  48 bool ucCacheCheck (uint ucNum, word15 segno, word18 offset, word14 * bound, word1 * p, word24 * address, word3 * r1, bool * paged) {
     /* [previous][next][first][last][top][bottom][index][help] */
  49   if (segno >= UC_CACHE_SZ) {
  50 #ifdef UCACHE_STATS
  51     cpu.uCache.segnoSkips ++;
  52 #endif
  53     return false;
  54   }
  55   ucache_t * ep;
  56   ep = & cpu.uCache.caches[ucNum][segno];
  57   // Is cache entry valid?
  58   if (! ep->valid) {
  59 #ifdef HDBG
  60     hdbgNote ("ucache", "check not valid");
  61 #endif
  62     goto miss;
  63   }
  64 
  65 
  66 
  67 
  68 
  69 
  70 
  71 
  72 
  73   // Same page?
  74   if (ep->paged && ((ep->offset & PG18MASK) != (offset & PG18MASK))) {
  75 #ifdef HDBG
  76     hdbgNote ("ucache", "pgno %o != %o\r\n", (ep->offset & PG18MASK), (offset & PG18MASK));
  77 #endif
  78     goto miss;
  79   }
  80   // In bounds?
  81   if (((offset >> 4) & 037777) > ep->bound) {
  82     //sim_printf ("bound %o != %o\r\n", ((offset >> 4) & 037777), ep->bound);
  83 #ifdef HDBG
  84     hdbgNote ("ucache", "bound %o != %o\r\n", ((offset >> 4) & 037777), ep->bound);
  85 #endif
  86     goto miss;
  87   }
  88 #ifdef HDBG
  89   hdbgNote ("ucache", "hit %u %05o:%06o %05o %o %08o %o %o", ucNum, segno, offset, ep->bound, ep->p, ep->address, ep->r1, ep->paged);
  90 #endif
  91   * bound = ep->bound;
  92 
  93 
  94 
  95 
  96 
  97 
  98 
  99 
 100 
 101 
 102 
 103 
 104 
 105 
 106   * address = ep->address;
 107 
 108   * r1      = ep->r1;
 109   * p       = ep->p;
 110   * paged   = ep->paged;
 111 #ifdef UCACHE_STATS
 112   cpu.uCache.hits[ucNum] ++;
 113 #endif
 114   return true;
 115 miss:;
 116 #ifdef UCACHE_STATS
 117   cpu.uCache.misses[ucNum] ++;
 118 #endif
 119   return false;
 120 }
 121 
 122 #ifdef UCACHE_STATS
 123 void ucacheStats (int cpuNo) {
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 124 
 125   (void)fflush(stdout);
 126   (void)fflush(stderr);
 127   sim_msg ("\r\n|   CPU %c Micro-cache Statistics  |", 'A' + cpuNo);
 128   sim_msg ("\r\n+---------------------------------+\r\n");
 129 # define pct(a, b) ((b) ? (a) * 100.0 / ((a) + (b)) : 0)
 130 # define args(a, b, c) a, b, c, pct (a, (b + c))
 131 # define stats(n) args ( (long long unsigned)cpus[cpuNo].uCache.hits  [n], \
 132                          (long long unsigned)cpus[cpuNo].uCache.misses[n], \
 133                          (long long unsigned)cpus[cpuNo].uCache.skips [n] )
 134   (void)fflush(stdout);
 135   (void)fflush(stderr);
 136 # ifdef WIN_STDIO
 137   sim_msg ("\r|  Instruction Fetch:             |\r\n|    Hits        %15llu  |\r\n|    Misses      %15llu  |\r\n|    Skipped     %15llu  |\r\n|    Effectiveness   %10.2f%%  |\r\n", stats (UC_INSTRUCTION_FETCH));
 138   (void)fflush(stdout);
 139   (void)fflush(stderr);
 140   sim_msg ("\r+---------------------------------+\r\n");
 141   sim_msg ("\r|  Operand Read:                  |\r\n|    Hits        %15llu  |\r\n|    Misses      %15llu  |\r\n|    Skipped     %15llu  |\r\n|    Effectiveness   %10.2f%%  |\r\n", stats (UC_OPERAND_READ));
 142   (void)fflush(stdout);
 143   (void)fflush(stderr);
 144 #  ifdef IDWF_CACHE
 145   sim_msg ("\r+---------------------------------+\r\n");
 146   sim_msg ("\r|  Indirect Word Fetch:           |\r\n|    Hits        %15llu  |\r\n|    Misses      %15llu  |\r\n|    Skipped     %15llu  |\r\n|    Effectiveness   %10.2f%%  |\r\n", stats (UC_INDIRECT_WORD_FETCH));
 147   (void)fflush(stdout);
 148   (void)fflush(stderr);
 149 #  endif
 150   sim_msg ("\r+---------------------------------+\r\n");
 151   sim_msg ("\r|  Cache Bypasses:                |\r\n");
 152   sim_msg ("\r|    RALR        %15llu  |\r\n", (long long unsigned)cpus[cpuNo].uCache.ralrSkips);
 153   sim_msg ("\r|    CALL6       %15llu  |\r\n", (long long unsigned)cpus[cpuNo].uCache.call6Skips);
 154   sim_msg ("\r|    Segno       %15llu  |\r\n", (long long unsigned)cpus[cpuNo].uCache.segnoSkips);
 155   (void)fflush(stdout);
 156   (void)fflush(stderr);
 157 # else
 158   sim_msg ("\r|  Instruction Fetch:             |\r\n|    Hits        %'15llu  |\r\n|    Misses      %'15llu  |\r\n|    Skipped     %'15llu  |\r\n|    Effectiveness   %'10.2f%%  |\r\n", stats (UC_INSTRUCTION_FETCH));
 159   (void)fflush(stdout);
 160   (void)fflush(stderr);
 161   sim_msg ("\r+---------------------------------+\r\n");
 162   sim_msg ("\r|  Operand Read:                  |\r\n|    Hits        %'15llu  |\r\n|    Misses      %'15llu  |\r\n|    Skipped     %'15llu  |\r\n|    Effectiveness   %'10.2f%%  |\r\n", stats (UC_OPERAND_READ));
 163   (void)fflush(stdout);
 164   (void)fflush(stderr);
 165 #  ifdef IDWF_CACHE
 166   sim_msg ("\r+---------------------------------+\r\n");
 167   sim_msg ("\r|  Indirect Word Fetch:           |\r\n|    Hits        %'15llu  |\r\n|    Misses      %'15llu  |\r\n|    Skipped     %'15llu  |\r\n|    Effectiveness   %'10.2f%%  |\r\n", stats (UC_INDIRECT_WORD_FETCH));
 168   (void)fflush(stdout);
 169   (void)fflush(stderr);
 170 #  endif
 171   sim_msg ("\r+---------------------------------+\r\n");
 172   sim_msg ("\r|  Cache Bypasses:                |\r\n");
 173   sim_msg ("\r|    RALR        %'15llu  |\r\n", (long long unsigned)cpus[cpuNo].uCache.ralrSkips);
 174   sim_msg ("\r|    CALL6       %'15llu  |\r\n", (long long unsigned)cpus[cpuNo].uCache.call6Skips);
 175   sim_msg ("\r|    Segno       %'15llu  |\r\n", (long long unsigned)cpus[cpuNo].uCache.segnoSkips);
 176   (void)fflush(stdout);
 177   (void)fflush(stderr);
 178 # endif
 179   sim_msg ("\r+---------------------------------+\r\n");
 180   (void)fflush(stdout);
 181   (void)fflush(stderr);
 182 # undef pct
 183 # undef args
 184 # undef stats
 185 }
 186 #endif
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