TPR                27 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA(Entry) CA %06o\n", cpu.TPR.CA);
TPR                30 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TPR                72 src/dps8/doAppendCycleABSA.h   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
TPR                77 src/dps8/doAppendCycleABSA.h   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
TPR                79 src/dps8/doAppendCycleABSA.h     DBGAPP ("doAppendCycleABSA(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TPR                84 src/dps8/doAppendCycleABSA.h       fetch_dsptw (cpu.TPR.TSR);
TPR                90 src/dps8/doAppendCycleABSA.h         modify_dsptw (cpu.TPR.TSR);
TPR                92 src/dps8/doAppendCycleABSA.h       fetch_psdw (cpu.TPR.TSR);
TPR                94 src/dps8/doAppendCycleABSA.h       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TPR                97 src/dps8/doAppendCycleABSA.h     load_sdwam (cpu.TPR.TSR, nomatch);
TPR               143 src/dps8/doAppendCycleABSA.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TPR               154 src/dps8/doAppendCycleABSA.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               157 src/dps8/doAppendCycleABSA.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TPR               178 src/dps8/doAppendCycleABSA.h   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
TPR               186 src/dps8/doAppendCycleABSA.h             cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
TPR               203 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA(G) CA %06o\n", cpu.TPR.CA);
TPR               204 src/dps8/doAppendCycleABSA.h   if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { //TPR.CA))
TPR               205 src/dps8/doAppendCycleABSA.h     fetch_ptw (cpu.SDW, cpu.TPR.CA);
TPR               206 src/dps8/doAppendCycleABSA.h     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
TPR               215 src/dps8/doAppendCycleABSA.h     do_ptw2 (cpu.SDW, cpu.TPR.CA);
TPR               238 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
TPR               240 src/dps8/doAppendCycleABSA.h   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
TPR               244 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               254 src/dps8/doAppendCycleABSA.h   word24 y2 = cpu.TPR.CA % 1024;
TPR               266 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               277 src/dps8/doAppendCycleABSA.h   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
TPR               283 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TPR                25 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW(Entry) CA %06o\n", cpu.TPR.CA);
TPR                28 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TPR                76 src/dps8/doAppendCycleAPUDataRMW.h   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
TPR                81 src/dps8/doAppendCycleAPUDataRMW.h   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
TPR                83 src/dps8/doAppendCycleAPUDataRMW.h     DBGAPP ("doAppendCycleAPUDataRMW(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TPR                88 src/dps8/doAppendCycleAPUDataRMW.h       fetch_dsptw (cpu.TPR.TSR);
TPR                94 src/dps8/doAppendCycleAPUDataRMW.h         modify_dsptw (cpu.TPR.TSR);
TPR                96 src/dps8/doAppendCycleAPUDataRMW.h       fetch_psdw (cpu.TPR.TSR);
TPR                98 src/dps8/doAppendCycleAPUDataRMW.h       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TPR               106 src/dps8/doAppendCycleAPUDataRMW.h     load_sdwam (cpu.TPR.TSR, nomatch);
TPR               157 src/dps8/doAppendCycleAPUDataRMW.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TPR               168 src/dps8/doAppendCycleAPUDataRMW.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               171 src/dps8/doAppendCycleAPUDataRMW.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TPR               189 src/dps8/doAppendCycleAPUDataRMW.h   if (cpu.TPR.TSR == cpu.PPR.PSR)
TPR               190 src/dps8/doAppendCycleAPUDataRMW.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               193 src/dps8/doAppendCycleAPUDataRMW.h   if (cpu.TPR.TRR > cpu.SDW->R1) {
TPR               194 src/dps8/doAppendCycleAPUDataRMW.h     DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1);
TPR               203 src/dps8/doAppendCycleAPUDataRMW.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               225 src/dps8/doAppendCycleAPUDataRMW.h   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
TPR               231 src/dps8/doAppendCycleAPUDataRMW.h     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
TPR               248 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW(G) CA %06o\n", cpu.TPR.CA);
TPR               249 src/dps8/doAppendCycleAPUDataRMW.h   if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) {
TPR               250 src/dps8/doAppendCycleAPUDataRMW.h     fetch_ptw (cpu.SDW, cpu.TPR.CA);
TPR               255 src/dps8/doAppendCycleAPUDataRMW.h     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
TPR               264 src/dps8/doAppendCycleAPUDataRMW.h     do_ptw2 (cpu.SDW, cpu.TPR.CA);
TPR               289 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
TPR               291 src/dps8/doAppendCycleAPUDataRMW.h   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
TPR               295 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               305 src/dps8/doAppendCycleAPUDataRMW.h      modify_ptw (cpu.SDW, cpu.TPR.CA);
TPR               311 src/dps8/doAppendCycleAPUDataRMW.h   word24 y2 = cpu.TPR.CA % 1024;
TPR               323 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               343 src/dps8/doAppendCycleAPUDataRMW.h   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
TPR               349 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TPR                25 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead(Entry) CA %06o\n", cpu.TPR.CA);
TPR                28 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TPR                77 src/dps8/doAppendCycleAPUDataRead.h   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
TPR                82 src/dps8/doAppendCycleAPUDataRead.h   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
TPR                84 src/dps8/doAppendCycleAPUDataRead.h     DBGAPP ("doAppendCycleAPUDataRead(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TPR                89 src/dps8/doAppendCycleAPUDataRead.h       fetch_dsptw (cpu.TPR.TSR);
TPR                95 src/dps8/doAppendCycleAPUDataRead.h         modify_dsptw (cpu.TPR.TSR);
TPR                97 src/dps8/doAppendCycleAPUDataRead.h       fetch_psdw (cpu.TPR.TSR);
TPR                99 src/dps8/doAppendCycleAPUDataRead.h       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TPR               107 src/dps8/doAppendCycleAPUDataRead.h     load_sdwam (cpu.TPR.TSR, nomatch);
TPR               152 src/dps8/doAppendCycleAPUDataRead.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TPR               163 src/dps8/doAppendCycleAPUDataRead.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               166 src/dps8/doAppendCycleAPUDataRead.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TPR               187 src/dps8/doAppendCycleAPUDataRead.h   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
TPR               193 src/dps8/doAppendCycleAPUDataRead.h     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
TPR               210 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead(G) CA %06o\n", cpu.TPR.CA);
TPR               211 src/dps8/doAppendCycleAPUDataRead.h   if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) {
TPR               212 src/dps8/doAppendCycleAPUDataRead.h     fetch_ptw (cpu.SDW, cpu.TPR.CA);
TPR               216 src/dps8/doAppendCycleAPUDataRead.h     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
TPR               225 src/dps8/doAppendCycleAPUDataRead.h     do_ptw2 (cpu.SDW, cpu.TPR.CA);
TPR               249 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
TPR               251 src/dps8/doAppendCycleAPUDataRead.h   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
TPR               255 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               269 src/dps8/doAppendCycleAPUDataRead.h   word24 y2 = cpu.TPR.CA % 1024;
TPR               281 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               294 src/dps8/doAppendCycleAPUDataRead.h   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
TPR               300 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TPR                25 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore(Entry) CA %06o\n", cpu.TPR.CA);
TPR                28 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TPR                75 src/dps8/doAppendCycleAPUDataStore.h   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
TPR                80 src/dps8/doAppendCycleAPUDataStore.h   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
TPR                82 src/dps8/doAppendCycleAPUDataStore.h     DBGAPP ("doAppendCycleAPUDataStore(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TPR                87 src/dps8/doAppendCycleAPUDataStore.h       fetch_dsptw (cpu.TPR.TSR);
TPR                93 src/dps8/doAppendCycleAPUDataStore.h           modify_dsptw (cpu.TPR.TSR);
TPR                95 src/dps8/doAppendCycleAPUDataStore.h       fetch_psdw (cpu.TPR.TSR);
TPR                97 src/dps8/doAppendCycleAPUDataStore.h       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TPR               105 src/dps8/doAppendCycleAPUDataStore.h     load_sdwam (cpu.TPR.TSR, nomatch);
TPR               154 src/dps8/doAppendCycleAPUDataStore.h   if (cpu.TPR.TSR == cpu.PPR.PSR)
TPR               155 src/dps8/doAppendCycleAPUDataStore.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               158 src/dps8/doAppendCycleAPUDataStore.h   if (cpu.TPR.TRR > cpu.SDW->R1) {
TPR               159 src/dps8/doAppendCycleAPUDataStore.h     DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1);
TPR               168 src/dps8/doAppendCycleAPUDataStore.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               186 src/dps8/doAppendCycleAPUDataStore.h   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
TPR               192 src/dps8/doAppendCycleAPUDataStore.h     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
TPR               209 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore(G) CA %06o\n", cpu.TPR.CA);
TPR               210 src/dps8/doAppendCycleAPUDataStore.h   if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) {
TPR               211 src/dps8/doAppendCycleAPUDataStore.h     fetch_ptw (cpu.SDW, cpu.TPR.CA);
TPR               216 src/dps8/doAppendCycleAPUDataStore.h     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
TPR               226 src/dps8/doAppendCycleAPUDataStore.h     do_ptw2 (cpu.SDW, cpu.TPR.CA);
TPR               250 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
TPR               252 src/dps8/doAppendCycleAPUDataStore.h   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
TPR               256 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               266 src/dps8/doAppendCycleAPUDataStore.h      modify_ptw (cpu.SDW, cpu.TPR.CA);
TPR               272 src/dps8/doAppendCycleAPUDataStore.h   word24 y2 = cpu.TPR.CA % 1024;
TPR               284 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               297 src/dps8/doAppendCycleAPUDataStore.h   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
TPR               303 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TPR                61 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(Entry) CA %06o\n", cpu.TPR.CA);
TPR                64 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TPR                97 src/dps8/doAppendCycleIndirectWordFetch.h   if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged))
TPR               101 src/dps8/doAppendCycleIndirectWordFetch.h     finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK);
TPR               103 src/dps8/doAppendCycleIndirectWordFetch.h     finalAddress = pageAddress + cpu.TPR.CA;
TPR               168 src/dps8/doAppendCycleIndirectWordFetch.h   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
TPR               173 src/dps8/doAppendCycleIndirectWordFetch.h   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
TPR               175 src/dps8/doAppendCycleIndirectWordFetch.h     DBGAPP ("doAppendCycleIndirectWordFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TPR               179 src/dps8/doAppendCycleIndirectWordFetch.h       fetch_dsptw (cpu.TPR.TSR);
TPR               185 src/dps8/doAppendCycleIndirectWordFetch.h           modify_dsptw (cpu.TPR.TSR);
TPR               187 src/dps8/doAppendCycleIndirectWordFetch.h       fetch_psdw (cpu.TPR.TSR);
TPR               189 src/dps8/doAppendCycleIndirectWordFetch.h       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TPR               197 src/dps8/doAppendCycleIndirectWordFetch.h     load_sdwam (cpu.TPR.TSR, nomatch);
TPR               248 src/dps8/doAppendCycleIndirectWordFetch.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TPR               259 src/dps8/doAppendCycleIndirectWordFetch.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               262 src/dps8/doAppendCycleIndirectWordFetch.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TPR               287 src/dps8/doAppendCycleIndirectWordFetch.h   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
TPR               293 src/dps8/doAppendCycleIndirectWordFetch.h     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
TPR               312 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(G) CA %06o\n", cpu.TPR.CA);
TPR               314 src/dps8/doAppendCycleIndirectWordFetch.h       ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) {
TPR               315 src/dps8/doAppendCycleIndirectWordFetch.h     fetch_ptw (cpu.SDW, cpu.TPR.CA);
TPR               320 src/dps8/doAppendCycleIndirectWordFetch.h     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
TPR               330 src/dps8/doAppendCycleIndirectWordFetch.h     do_ptw2 (cpu.SDW, cpu.TPR.CA);
TPR               356 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
TPR               359 src/dps8/doAppendCycleIndirectWordFetch.h   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
TPR               363 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               379 src/dps8/doAppendCycleIndirectWordFetch.h   word24 y2 = cpu.TPR.CA % 1024;
TPR               392 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               399 src/dps8/doAppendCycleIndirectWordFetch.h   ucCacheSave (this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged);
TPR               419 src/dps8/doAppendCycleIndirectWordFetch.h   if ((GET_TM (tag) == TM_IR || GET_TM (tag) == TM_RI) && (cpu.TPR.CA & 1) == 0) {
TPR               437 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(O) TRR %o RSDWH.R1 %o ITS.RNR %o\n", cpu.TPR.TRR, cpu.RSDWH_R1, its_RNR);
TPR               441 src/dps8/doAppendCycleIndirectWordFetch.h   cpu.TPR.TRR = max3 (its_RNR, cpu.TPR.TRR, cpu.RSDWH_R1);
TPR               442 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(O) Set TRR to %o\n", cpu.TPR.TRR);
TPR               451 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(P) TRR %o RSDWH.R1 %o PR[n].RNR %o\n", cpu.TPR.TRR, cpu.RSDWH_R1, cpu.PR[n].RNR);
TPR               455 src/dps8/doAppendCycleIndirectWordFetch.h   cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.TPR.TRR, cpu.RSDWH_R1);
TPR               456 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(P) Set TRR to %o\n", cpu.TPR.TRR);
TPR               462 src/dps8/doAppendCycleIndirectWordFetch.h   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
TPR               468 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TPR                72 src/dps8/doAppendCycleInstructionFetch.h   DBGAPP ("doAppendCycleInstructionFetch(Entry) CA %06o\n", cpu.TPR.CA);
TPR                75 src/dps8/doAppendCycleInstructionFetch.h   DBGAPP ("doAppendCycleInstructionFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TPR               148 src/dps8/doAppendCycleInstructionFetch.h   cacheHit = ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged);
TPR               151 src/dps8/doAppendCycleInstructionFetch.h   if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged))
TPR               156 src/dps8/doAppendCycleInstructionFetch.h     finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK);
TPR               158 src/dps8/doAppendCycleInstructionFetch.h     finalAddress = pageAddress + cpu.TPR.CA;
TPR               216 src/dps8/doAppendCycleInstructionFetch.h   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
TPR               221 src/dps8/doAppendCycleInstructionFetch.h   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
TPR               223 src/dps8/doAppendCycleInstructionFetch.h     DBGAPP ("doAppendCycleInstructionFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TPR               228 src/dps8/doAppendCycleInstructionFetch.h       fetch_dsptw (cpu.TPR.TSR);
TPR               234 src/dps8/doAppendCycleInstructionFetch.h         modify_dsptw (cpu.TPR.TSR);
TPR               236 src/dps8/doAppendCycleInstructionFetch.h       fetch_psdw (cpu.TPR.TSR);
TPR               238 src/dps8/doAppendCycleInstructionFetch.h       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TPR               246 src/dps8/doAppendCycleInstructionFetch.h     load_sdwam (cpu.TPR.TSR, nomatch);
TPR               312 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) {
TPR               314 src/dps8/doAppendCycleInstructionFetch.h     DBGAPP ("acvFaults(C) ACV1 ! ( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2);
TPR               329 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.TPR.TRR > cpu.PPR.PRR)
TPR               330 src/dps8/doAppendCycleInstructionFetch.h     sim_warn ("rtcd: outbound call cpu.TPR.TRR %d cpu.PPR.PRR %d\n", cpu.TPR.TRR, cpu.PPR.PRR);
TPR               332 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.TPR.TRR < cpu.PPR.PRR) {
TPR               377 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) {
TPR               379 src/dps8/doAppendCycleInstructionFetch.h     DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2);
TPR               394 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.PPR.PRR != cpu.TPR.TRR) {
TPR               416 src/dps8/doAppendCycleInstructionFetch.h   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
TPR               422 src/dps8/doAppendCycleInstructionFetch.h     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
TPR               441 src/dps8/doAppendCycleInstructionFetch.h   DBGAPP ("doAppendCycleInstructionFetch(G) CA %06o\n", cpu.TPR.CA);
TPR               443 src/dps8/doAppendCycleInstructionFetch.h       ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) {
TPR               444 src/dps8/doAppendCycleInstructionFetch.h     fetch_ptw (cpu.SDW, cpu.TPR.CA);
TPR               449 src/dps8/doAppendCycleInstructionFetch.h     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
TPR               461 src/dps8/doAppendCycleInstructionFetch.h       do_ptw2 (cpu.SDW, cpu.TPR.CA);
TPR               487 src/dps8/doAppendCycleInstructionFetch.h   DBGAPP ("doAppendCycleInstructionFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
TPR               490 src/dps8/doAppendCycleInstructionFetch.h   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
TPR               494 src/dps8/doAppendCycleInstructionFetch.h   DBGAPP ("doAppendCycleInstructionFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               510 src/dps8/doAppendCycleInstructionFetch.h   word24 y2 = cpu.TPR.CA % 1024;
TPR               523 src/dps8/doAppendCycleInstructionFetch.h   DBGAPP ("doAppendCycleInstructionFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               551 src/dps8/doAppendCycleInstructionFetch.h       sim_printf ("ins fetch err  %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TPR               556 src/dps8/doAppendCycleInstructionFetch.h     hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TPR               561 src/dps8/doAppendCycleInstructionFetch.h     hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TPR               576 src/dps8/doAppendCycleInstructionFetch.h   ucCacheSave (this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged);
TPR               614 src/dps8/doAppendCycleInstructionFetch.h     cpu.PR[7].RNR = cpu.TPR.TRR;
TPR               632 src/dps8/doAppendCycleInstructionFetch.h   cpu.PPR.PSR = cpu.TPR.TSR;
TPR               634 src/dps8/doAppendCycleInstructionFetch.h   cpu.PPR.IC = cpu.TPR.CA;
TPR               642 src/dps8/doAppendCycleInstructionFetch.h   if (cpu.TPR.TRR == 0) {
TPR               651 src/dps8/doAppendCycleInstructionFetch.h   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
TPR               657 src/dps8/doAppendCycleInstructionFetch.h   DBGAPP ("doAppendCycleInstructionFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TPR                25 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW(Entry) CA %06o\n", cpu.TPR.CA);
TPR                28 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TPR                77 src/dps8/doAppendCycleOperandRMW.h   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
TPR                82 src/dps8/doAppendCycleOperandRMW.h   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
TPR                84 src/dps8/doAppendCycleOperandRMW.h     DBGAPP ("doAppendCycleOperandRMW(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TPR                88 src/dps8/doAppendCycleOperandRMW.h       fetch_dsptw (cpu.TPR.TSR);
TPR                94 src/dps8/doAppendCycleOperandRMW.h         modify_dsptw (cpu.TPR.TSR);
TPR                96 src/dps8/doAppendCycleOperandRMW.h       fetch_psdw (cpu.TPR.TSR);
TPR                98 src/dps8/doAppendCycleOperandRMW.h       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TPR               106 src/dps8/doAppendCycleOperandRMW.h     load_sdwam (cpu.TPR.TSR, nomatch);
TPR               157 src/dps8/doAppendCycleOperandRMW.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TPR               168 src/dps8/doAppendCycleOperandRMW.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               171 src/dps8/doAppendCycleOperandRMW.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TPR               189 src/dps8/doAppendCycleOperandRMW.h   if (cpu.TPR.TSR == cpu.PPR.PSR)
TPR               190 src/dps8/doAppendCycleOperandRMW.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               193 src/dps8/doAppendCycleOperandRMW.h   if (cpu.TPR.TRR > cpu.SDW->R1) {
TPR               194 src/dps8/doAppendCycleOperandRMW.h     DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1);
TPR               203 src/dps8/doAppendCycleOperandRMW.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               225 src/dps8/doAppendCycleOperandRMW.h   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
TPR               231 src/dps8/doAppendCycleOperandRMW.h     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
TPR               248 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW(G) CA %06o\n", cpu.TPR.CA);
TPR               249 src/dps8/doAppendCycleOperandRMW.h   if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA))  {
TPR               250 src/dps8/doAppendCycleOperandRMW.h     fetch_ptw (cpu.SDW, cpu.TPR.CA);
TPR               255 src/dps8/doAppendCycleOperandRMW.h     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
TPR               265 src/dps8/doAppendCycleOperandRMW.h     do_ptw2 (cpu.SDW, cpu.TPR.CA);
TPR               288 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
TPR               290 src/dps8/doAppendCycleOperandRMW.h   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
TPR               294 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               304 src/dps8/doAppendCycleOperandRMW.h     modify_ptw (cpu.SDW, cpu.TPR.CA);
TPR               310 src/dps8/doAppendCycleOperandRMW.h   word24 y2 = cpu.TPR.CA % 1024;
TPR               322 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               348 src/dps8/doAppendCycleOperandRMW.h   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
TPR               354 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TPR                67 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead(Entry) CA %06o\n", cpu.TPR.CA);
TPR                70 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TPR               137 src/dps8/doAppendCycleOperandRead.h   cacheHit = ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged);
TPR               139 src/dps8/doAppendCycleOperandRead.h   hdbgNote ("doAppendCycleOperandRead.h", "test cache check %s %d %u %05o:%06o %05o %o %08o %o %o", cacheHit ? "hit" : "miss", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, cachedBound, cachedP, cachedAddress, cachedR1, cachedPaged);
TPR               143 src/dps8/doAppendCycleOperandRead.h   if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) {
TPR               145 src/dps8/doAppendCycleOperandRead.h     hdbgNote ("doAppendCycleOperandRead.h", "miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TPR               152 src/dps8/doAppendCycleOperandRead.h     finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK);
TPR               154 src/dps8/doAppendCycleOperandRead.h     finalAddress = pageAddress + cpu.TPR.CA;
TPR               161 src/dps8/doAppendCycleOperandRead.h   hdbgNote ("doAppendCycleOperandRead.h", "hit  %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TPR               171 src/dps8/doAppendCycleOperandRead.h   hdbgNote ("doAppendCycleOperandRead.h", "skip %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TPR               229 src/dps8/doAppendCycleOperandRead.h   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
TPR               234 src/dps8/doAppendCycleOperandRead.h   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
TPR               236 src/dps8/doAppendCycleOperandRead.h     DBGAPP ("doAppendCycleOperandRead(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TPR               240 src/dps8/doAppendCycleOperandRead.h       fetch_dsptw (cpu.TPR.TSR);
TPR               246 src/dps8/doAppendCycleOperandRead.h         modify_dsptw (cpu.TPR.TSR);
TPR               248 src/dps8/doAppendCycleOperandRead.h       fetch_psdw (cpu.TPR.TSR);
TPR               250 src/dps8/doAppendCycleOperandRead.h       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TPR               258 src/dps8/doAppendCycleOperandRead.h     load_sdwam (cpu.TPR.TSR, nomatch);
TPR               317 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TPR               328 src/dps8/doAppendCycleOperandRead.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               331 src/dps8/doAppendCycleOperandRead.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TPR               386 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead(E): E %o G %o PSR %05o TSR %05o CA %06o " "EB %06o R %o%o%o TRR %o PRR %o\n", cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu.SDW->EB, cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.TPR.TRR, cpu.PPR.PRR);
TPR               403 src/dps8/doAppendCycleOperandRead.h   if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS)
TPR               409 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.CA >= (word18) cpu.SDW->EB) {
TPR               422 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR > cpu.SDW->R3) {
TPR               432 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR < cpu.SDW->R1) {
TPR               442 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR > cpu.PPR.PRR) {
TPR               454 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o SDW->R2 %o\n", cpu.TPR.TRR, cpu.SDW->R2);
TPR               457 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TPR               459 src/dps8/doAppendCycleOperandRead.h     cpu.TPR.TRR = cpu.SDW->R2;
TPR               462 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o\n", cpu.TPR.TRR);
TPR               482 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) {
TPR               484 src/dps8/doAppendCycleOperandRead.h     DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2);
TPR               499 src/dps8/doAppendCycleOperandRead.h   if (cpu.PPR.PRR != cpu.TPR.TRR) {
TPR               521 src/dps8/doAppendCycleOperandRead.h   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
TPR               527 src/dps8/doAppendCycleOperandRead.h     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
TPR               546 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead(G) CA %06o\n", cpu.TPR.CA);
TPR               548 src/dps8/doAppendCycleOperandRead.h       ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) {
TPR               549 src/dps8/doAppendCycleOperandRead.h     fetch_ptw (cpu.SDW, cpu.TPR.CA);
TPR               554 src/dps8/doAppendCycleOperandRead.h     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
TPR               564 src/dps8/doAppendCycleOperandRead.h     do_ptw2 (cpu.SDW, cpu.TPR.CA);
TPR               591 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
TPR               594 src/dps8/doAppendCycleOperandRead.h   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
TPR               598 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               617 src/dps8/doAppendCycleOperandRead.h   word24 y2 = cpu.TPR.CA % 1024;
TPR               630 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               660 src/dps8/doAppendCycleOperandRead.h       sim_printf ("oprnd read err  %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TPR               665 src/dps8/doAppendCycleOperandRead.h     hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TPR               670 src/dps8/doAppendCycleOperandRead.h     hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TPR               675 src/dps8/doAppendCycleOperandRead.h   ucCacheSave (this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged);
TPR               678 src/dps8/doAppendCycleOperandRead.h   hdbgNote ("doAppendCycleOperandRead.h", "cache %d %u %05o:%06o %05o %o %08o %o %o", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged);
TPR               737 src/dps8/doAppendCycleOperandRead.h   cpu.PPR.PSR = cpu.TPR.TSR;
TPR               739 src/dps8/doAppendCycleOperandRead.h   cpu.PPR.IC = cpu.TPR.CA;
TPR               747 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR == 0) {
TPR               761 src/dps8/doAppendCycleOperandRead.h   if (cpu.TPR.TRR == cpu.PPR.PRR) {
TPR               767 src/dps8/doAppendCycleOperandRead.h     cpu.PR[7].SNR = ((word15) (cpu.DSBR.STACK << 3)) | cpu.TPR.TRR;
TPR               768 src/dps8/doAppendCycleOperandRead.h     DBGAPP ("doAppendCycleOperandRead(N) STACK %05o TRR %o\n", cpu.DSBR.STACK, cpu.TPR.TRR);
TPR               773 src/dps8/doAppendCycleOperandRead.h   cpu.PR[7].RNR = cpu.TPR.TRR;
TPR               782 src/dps8/doAppendCycleOperandRead.h   cpu.PPR.PRR = cpu.TPR.TRR;
TPR               784 src/dps8/doAppendCycleOperandRead.h   cpu.PPR.PSR = cpu.TPR.TSR;
TPR               786 src/dps8/doAppendCycleOperandRead.h   cpu.PPR.IC = cpu.TPR.CA;
TPR               792 src/dps8/doAppendCycleOperandRead.h   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
TPR               798 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TPR                25 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore(Entry) CA %06o\n", cpu.TPR.CA);
TPR                28 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TPR                76 src/dps8/doAppendCycleOperandStore.h   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
TPR                81 src/dps8/doAppendCycleOperandStore.h   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
TPR                83 src/dps8/doAppendCycleOperandStore.h     DBGAPP ("doAppendCycleOperandStore(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TPR                88 src/dps8/doAppendCycleOperandStore.h       fetch_dsptw (cpu.TPR.TSR);
TPR                94 src/dps8/doAppendCycleOperandStore.h         modify_dsptw (cpu.TPR.TSR);
TPR                96 src/dps8/doAppendCycleOperandStore.h       fetch_psdw (cpu.TPR.TSR);
TPR                98 src/dps8/doAppendCycleOperandStore.h       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TPR               106 src/dps8/doAppendCycleOperandStore.h     load_sdwam (cpu.TPR.TSR, nomatch);
TPR               149 src/dps8/doAppendCycleOperandStore.h   if (cpu.TPR.TSR == cpu.PPR.PSR)
TPR               150 src/dps8/doAppendCycleOperandStore.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               153 src/dps8/doAppendCycleOperandStore.h   if (cpu.TPR.TRR > cpu.SDW->R1) {
TPR               154 src/dps8/doAppendCycleOperandStore.h     DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1);
TPR               163 src/dps8/doAppendCycleOperandStore.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               185 src/dps8/doAppendCycleOperandStore.h   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
TPR               191 src/dps8/doAppendCycleOperandStore.h     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
TPR               208 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore(G) CA %06o\n", cpu.TPR.CA);
TPR               209 src/dps8/doAppendCycleOperandStore.h   if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) {
TPR               210 src/dps8/doAppendCycleOperandStore.h     fetch_ptw (cpu.SDW, cpu.TPR.CA);
TPR               215 src/dps8/doAppendCycleOperandStore.h     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
TPR               225 src/dps8/doAppendCycleOperandStore.h     do_ptw2 (cpu.SDW, cpu.TPR.CA);
TPR               248 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
TPR               250 src/dps8/doAppendCycleOperandStore.h   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
TPR               254 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               264 src/dps8/doAppendCycleOperandStore.h    modify_ptw (cpu.SDW, cpu.TPR.CA);
TPR               270 src/dps8/doAppendCycleOperandStore.h   word24 y2 = cpu.TPR.CA % 1024;
TPR               282 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               300 src/dps8/doAppendCycleOperandStore.h   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
TPR               306 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TPR                25 src/dps8/doAppendCycleRTCDOperandFetch.h   DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) CA %06o\n", cpu.TPR.CA);
TPR                28 src/dps8/doAppendCycleRTCDOperandFetch.h   DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TPR                88 src/dps8/doAppendCycleRTCDOperandFetch.h     cpu.TPR.TSR = 0;
TPR                89 src/dps8/doAppendCycleRTCDOperandFetch.h     DBGAPP ("RTCD_OPERAND_FETCH ABSOLUTE mode set TSR %05o TRR %o\n", cpu.TPR.TSR, cpu.TPR.TRR);
TPR               107 src/dps8/doAppendCycleRTCDOperandFetch.h   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
TPR               112 src/dps8/doAppendCycleRTCDOperandFetch.h   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
TPR               114 src/dps8/doAppendCycleRTCDOperandFetch.h     DBGAPP ("doAppendCycleRTCDOperandFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TPR               118 src/dps8/doAppendCycleRTCDOperandFetch.h       fetch_dsptw (cpu.TPR.TSR);
TPR               124 src/dps8/doAppendCycleRTCDOperandFetch.h         modify_dsptw (cpu.TPR.TSR);
TPR               126 src/dps8/doAppendCycleRTCDOperandFetch.h       fetch_psdw (cpu.TPR.TSR);
TPR               128 src/dps8/doAppendCycleRTCDOperandFetch.h       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TPR               136 src/dps8/doAppendCycleRTCDOperandFetch.h     load_sdwam (cpu.TPR.TSR, nomatch);
TPR               181 src/dps8/doAppendCycleRTCDOperandFetch.h   if (cpu.TPR.TRR > cpu.SDW->R2) {
TPR               192 src/dps8/doAppendCycleRTCDOperandFetch.h     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               195 src/dps8/doAppendCycleRTCDOperandFetch.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TPR               220 src/dps8/doAppendCycleRTCDOperandFetch.h   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
TPR               226 src/dps8/doAppendCycleRTCDOperandFetch.h     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
TPR               243 src/dps8/doAppendCycleRTCDOperandFetch.h   DBGAPP ("doAppendCycleRTCDOperandFetch(G) CA %06o\n", cpu.TPR.CA);
TPR               244 src/dps8/doAppendCycleRTCDOperandFetch.h   if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) {
TPR               245 src/dps8/doAppendCycleRTCDOperandFetch.h     fetch_ptw (cpu.SDW, cpu.TPR.CA);
TPR               250 src/dps8/doAppendCycleRTCDOperandFetch.h     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
TPR               260 src/dps8/doAppendCycleRTCDOperandFetch.h     do_ptw2 (cpu.SDW, cpu.TPR.CA);
TPR               283 src/dps8/doAppendCycleRTCDOperandFetch.h   DBGAPP ("doAppendCycleRTCDOperandFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
TPR               286 src/dps8/doAppendCycleRTCDOperandFetch.h     finalAddress = cpu.TPR.CA;
TPR               288 src/dps8/doAppendCycleRTCDOperandFetch.h     finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
TPR               293 src/dps8/doAppendCycleRTCDOperandFetch.h   DBGAPP ("doAppendCycleRTCDOperandFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               307 src/dps8/doAppendCycleRTCDOperandFetch.h   word24 y2 = cpu.TPR.CA % 1024;
TPR               319 src/dps8/doAppendCycleRTCDOperandFetch.h   DBGAPP ("doAppendCycleRTCDOperandFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR               347 src/dps8/doAppendCycleRTCDOperandFetch.h   cpu.TPR.TSR = GET_ITS_SEGNO (data);
TPR               352 src/dps8/doAppendCycleRTCDOperandFetch.h   cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1);
TPR               356 src/dps8/doAppendCycleRTCDOperandFetch.h   cpu.TPR.CA = GET_ITS_WORDNO (data);
TPR               366 src/dps8/doAppendCycleRTCDOperandFetch.h   cpu.PPR.PSR = cpu.TPR.TSR;
TPR               368 src/dps8/doAppendCycleRTCDOperandFetch.h   cpu.PPR.IC = cpu.TPR.CA;
TPR               376 src/dps8/doAppendCycleRTCDOperandFetch.h   if (cpu.TPR.TRR == 0) {
TPR               386 src/dps8/doAppendCycleRTCDOperandFetch.h   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
TPR               392 src/dps8/doAppendCycleRTCDOperandFetch.h   DBGAPP ("doAppendCycleRTCDOperandFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TPR               224 src/dps8/dps8_addrmods.c     cpu.TPR.TSR  = cpu.PR[n].SNR;
TPR               225 src/dps8/dps8_addrmods.c     cpu.TPR.TRR  = max3 (cpu.PR[n].RNR, cpu.RSDWH_R1, cpu.TPR.TRR);
TPR               226 src/dps8/dps8_addrmods.c     cpu.TPR.TBR  = GET_ITP_BITNO (cpu.itxPair);
TPR               227 src/dps8/dps8_addrmods.c     cpu.TPR.CA   = cpu.PAR[n].WORDNO + GET_ITP_WORDNO (cpu.itxPair);
TPR               228 src/dps8/dps8_addrmods.c     cpu.TPR.CA  &= AMASK;
TPR               229 src/dps8/dps8_addrmods.c     cpu.rY       = cpu.TPR.CA;
TPR               260 src/dps8/dps8_addrmods.c     cpu.TPR.TSR = GET_ITS_SEGNO (cpu.itxPair);
TPR               264 src/dps8/dps8_addrmods.c                GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR,
TPR               265 src/dps8/dps8_addrmods.c                max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR));
TPR               267 src/dps8/dps8_addrmods.c     cpu.TPR.TRR  = max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR);
TPR               268 src/dps8/dps8_addrmods.c     cpu.TPR.TBR  = GET_ITS_BITNO (cpu.itxPair);
TPR               269 src/dps8/dps8_addrmods.c     cpu.TPR.CA   = GET_ITS_WORDNO (cpu.itxPair);
TPR               270 src/dps8/dps8_addrmods.c     cpu.TPR.CA  &= AMASK;
TPR               272 src/dps8/dps8_addrmods.c     cpu.rY = cpu.TPR.CA;
TPR               364 src/dps8/dps8_addrmods.c         cpu.TPR.CA = GET_ADDR (IWB_IRODD);
TPR               373 src/dps8/dps8_addrmods.c         cpu.TPR.CA = (cpu.PAR[n].WORDNO + SIGNEXT15_18 (offset))
TPR               379 src/dps8/dps8_addrmods.c                 __func__, op_desc_str (buf), cpu.TPR.CA);
TPR               422 src/dps8/dps8_addrmods.c                 cpu.cu.pot == 1 && GET_ADDR (IWB_IRODD) == cpu.TPR.CA)
TPR               424 src/dps8/dps8_addrmods.c            cpu.TPR.CA--;
TPR               494 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO;
TPR               495 src/dps8/dps8_addrmods.c                 cpu.TPR.CA &= AMASK;
TPR               499 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = Cr;
TPR               504 src/dps8/dps8_addrmods.c             cpu.TPR.CA += Cr;
TPR               505 src/dps8/dps8_addrmods.c             cpu.TPR.CA &= MASK18;   // keep to 18-bits
TPR               508 src/dps8/dps8_addrmods.c                    cpu.TPR.CA);
TPR               530 src/dps8/dps8_addrmods.c                        "RI_MOD: Cr=%06o CA(Before)=%06o\n", Cr, cpu.TPR.CA);
TPR               541 src/dps8/dps8_addrmods.c                     cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO;
TPR               545 src/dps8/dps8_addrmods.c                     cpu.TPR.CA = Cr;
TPR               547 src/dps8/dps8_addrmods.c                 cpu.TPR.CA &= AMASK;
TPR               551 src/dps8/dps8_addrmods.c                 cpu.TPR.CA += Cr;
TPR               552 src/dps8/dps8_addrmods.c                 cpu.TPR.CA &= MASK18;   // keep to 18-bits
TPR               555 src/dps8/dps8_addrmods.c                        "RI_MOD: CA(After)=%06o\n", cpu.TPR.CA);
TPR               569 src/dps8/dps8_addrmods.c         word18 saveCA = cpu.TPR.CA;
TPR               575 src/dps8/dps8_addrmods.c             updateIWB (cpu.TPR.CA, cpu.rTAG);
TPR               603 src/dps8/dps8_addrmods.c             cpu.TPR.CA = GETHI (cpu.itxPair[0]);
TPR               604 src/dps8/dps8_addrmods.c             cpu.rY = cpu.TPR.CA;
TPR               616 src/dps8/dps8_addrmods.c                    cpu.itxPair[0], cpu.TPR.CA, cpu.rTAG);
TPR               643 src/dps8/dps8_addrmods.c                    cpu.TPR.CA);
TPR               645 src/dps8/dps8_addrmods.c         word18 saveCA = cpu.TPR.CA;
TPR               665 src/dps8/dps8_addrmods.c             cpu.TPR.CA = GETHI (cpu.itxPair[0]);
TPR               666 src/dps8/dps8_addrmods.c             cpu.rY = cpu.TPR.CA;
TPR               678 src/dps8/dps8_addrmods.c                    cpu.itxPair[0], cpu.TPR.CA, Tm, Td,
TPR               691 src/dps8/dps8_addrmods.c                     updateIWB(cpu.TPR.CA, cpu.rTAG);
TPR               696 src/dps8/dps8_addrmods.c                           cpu.TPR.CA = saveCA;
TPR               701 src/dps8/dps8_addrmods.c                           cpu.TPR.CA = saveCA;
TPR               728 src/dps8/dps8_addrmods.c                 updateIWB (cpu.TPR.CA, cpu.rTAG);
TPR               742 src/dps8/dps8_addrmods.c                            Td, Cr, cpu.TPR.CA);
TPR               744 src/dps8/dps8_addrmods.c                 cpu.TPR.CA += Cr;
TPR               745 src/dps8/dps8_addrmods.c                 cpu.TPR.CA &= MASK18;   // keep to 18-bits
TPR               748 src/dps8/dps8_addrmods.c                                "IR_MOD(TM_RI): TPR.CA=%06o\n", cpu.TPR.CA);
TPR               752 src/dps8/dps8_addrmods.c                            cpu.TPR.CA);
TPR               755 src/dps8/dps8_addrmods.c                 updateIWB (cpu.TPR.CA, (TM_RI|TD_N));
TPR               761 src/dps8/dps8_addrmods.c                 updateIWB (cpu.TPR.CA, cpu.rTAG); // XXX guessing here...
TPR               840 src/dps8/dps8_addrmods.c                            cpu.TPR.CA);
TPR               847 src/dps8/dps8_addrmods.c                 word18 indaddr = cpu.TPR.CA;
TPR               881 src/dps8/dps8_addrmods.c                 cpu.TPR.CA                    = Yi;
TPR               929 src/dps8/dps8_addrmods.c                     cpu.TPR.CA                    = Yi;
TPR               952 src/dps8/dps8_addrmods.c                 Read (cpu.TPR.CA, & cpu.ou.character_data, (i->info->flags & RMW) == \
TPR               955 src/dps8/dps8_addrmods.c                 ReadOperandRead (cpu.TPR.CA, & cpu.ou.character_data);
TPR              1027 src/dps8/dps8_addrmods.c                                indword, cpu.TPR.CA);
TPR              1032 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = cpu.ou.character_address;
TPR              1040 src/dps8/dps8_addrmods.c                            cpu.TPR.CA);
TPR              1049 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = GET_ADDR (cpu.itxPair[0]);
TPR              1050 src/dps8/dps8_addrmods.c                 updateIWB (cpu.TPR.CA, (TM_R|TD_N));
TPR              1068 src/dps8/dps8_addrmods.c                            cpu.TPR.CA);
TPR              1074 src/dps8/dps8_addrmods.c                 word18 saveCA = cpu.TPR.CA;
TPR              1076 src/dps8/dps8_addrmods.c                 ReadAPUDataRMW (cpu.TPR.CA, & indword);
TPR              1090 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = Yi;
TPR              1091 src/dps8/dps8_addrmods.c                 word18 computedAddress = cpu.TPR.CA;
TPR              1120 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = computedAddress;
TPR              1121 src/dps8/dps8_addrmods.c                 updateIWB (cpu.TPR.CA, (TM_R|TD_N));
TPR              1141 src/dps8/dps8_addrmods.c                 word18 saveCA = cpu.TPR.CA;
TPR              1143 src/dps8/dps8_addrmods.c                 ReadAPUDataRMW (cpu.TPR.CA, & indword);
TPR              1147 src/dps8/dps8_addrmods.c                            cpu.TPR.CA);
TPR              1162 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = Yi;
TPR              1188 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = Yi;
TPR              1189 src/dps8/dps8_addrmods.c                 updateIWB (cpu.TPR.CA, (TM_R|TD_N));
TPR              1206 src/dps8/dps8_addrmods.c                            cpu.TPR.CA);
TPR              1212 src/dps8/dps8_addrmods.c                 word18 saveCA = cpu.TPR.CA;
TPR              1214 src/dps8/dps8_addrmods.c                 ReadAPUDataRMW (cpu.TPR.CA, & indword);
TPR              1229 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = Yi;
TPR              1237 src/dps8/dps8_addrmods.c                 indword = (word36) (((word36) cpu.TPR.CA << 18) |
TPR              1255 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = Yi;
TPR              1256 src/dps8/dps8_addrmods.c                 updateIWB (cpu.TPR.CA, (TM_R|TD_N));
TPR              1271 src/dps8/dps8_addrmods.c                 word18 saveCA = cpu.TPR.CA;
TPR              1275 src/dps8/dps8_addrmods.c                            cpu.TPR.CA);
TPR              1282 src/dps8/dps8_addrmods.c                 ReadAPUDataRMW (cpu.TPR.CA, & indword);
TPR              1293 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = Yi;
TPR              1294 src/dps8/dps8_addrmods.c                 word18 computedAddress = cpu.TPR.CA;
TPR              1327 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = computedAddress;
TPR              1328 src/dps8/dps8_addrmods.c                 updateIWB (cpu.TPR.CA, (TM_R|TD_N));
TPR              1357 src/dps8/dps8_addrmods.c                            cpu.TPR.CA);
TPR              1363 src/dps8/dps8_addrmods.c                 word18 saveCA = cpu.TPR.CA;
TPR              1365 src/dps8/dps8_addrmods.c                 ReadAPUDataRMW (cpu.TPR.CA, & indword);
TPR              1416 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = Yi;
TPR              1440 src/dps8/dps8_addrmods.c                   updateIWB (cpu.TPR.CA, cpu.rTAG);
TPR              1469 src/dps8/dps8_addrmods.c                            cpu.TPR.CA);
TPR              1475 src/dps8/dps8_addrmods.c                 word18 saveCA = cpu.TPR.CA;
TPR              1477 src/dps8/dps8_addrmods.c                 ReadAPUDataRMW (cpu.TPR.CA, & indword);
TPR              1530 src/dps8/dps8_addrmods.c                 cpu.TPR.CA = YiSafe;
TPR              1551 src/dps8/dps8_addrmods.c                 updateIWB (cpu.TPR.CA, cpu.rTAG);
TPR              1205 src/dps8/dps8_append.c             cpu.TPR.CA);
TPR              1211 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.TPR.TSR);
TPR              1279 src/dps8/dps8_append.c         cpu.TPR.TSR = 0;
TPR              1281 src/dps8/dps8_append.c                 cpu.TPR.TSR, cpu.TPR.TRR);
TPR              1299 src/dps8/dps8_append.c     PNL (cpu.APUMemAddr = cpu.TPR.CA;)
TPR              1304 src/dps8/dps8_append.c     if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR))
TPR              1308 src/dps8/dps8_append.c                  cpu.TPR.TSR);
TPR              1315 src/dps8/dps8_append.c             fetch_dsptw (cpu.TPR.TSR);
TPR              1322 src/dps8/dps8_append.c               modify_dsptw (cpu.TPR.TSR);
TPR              1324 src/dps8/dps8_append.c             fetch_psdw (cpu.TPR.TSR);
TPR              1327 src/dps8/dps8_append.c           fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TPR              1340 src/dps8/dps8_append.c         load_sdwam (cpu.TPR.TSR, nomatch);
TPR              1433 src/dps8/dps8_append.c         if (cpu.TPR.TRR > cpu.SDW->R2)
TPR              1446 src/dps8/dps8_append.c             cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1449 src/dps8/dps8_append.c             if (cpu.PPR.PSR != cpu.TPR.TSR)
TPR              1479 src/dps8/dps8_append.c         if (cpu.TPR.TSR == cpu.PPR.PSR)
TPR              1480 src/dps8/dps8_append.c             cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1483 src/dps8/dps8_append.c         if (cpu.TPR.TRR > cpu.SDW->R1)
TPR              1486 src/dps8/dps8_append.c                     cpu.TPR.TRR, cpu.SDW->R1);
TPR              1496 src/dps8/dps8_append.c             cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1525 src/dps8/dps8_append.c     if (cpu.TPR.TRR < cpu.SDW->R1 ||
TPR              1526 src/dps8/dps8_append.c         cpu.TPR.TRR > cpu.SDW->R2)
TPR              1530 src/dps8/dps8_append.c                 cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2);
TPR              1546 src/dps8/dps8_append.c     if (cpu.TPR.TRR > cpu.PPR.PRR)
TPR              1548 src/dps8/dps8_append.c                 cpu.TPR.TRR, cpu.PPR.PRR);
TPR              1550 src/dps8/dps8_append.c     if (cpu.TPR.TRR < cpu.PPR.PRR)
TPR              1599 src/dps8/dps8_append.c             cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA,
TPR              1601 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.PPR.PRR);
TPR              1619 src/dps8/dps8_append.c     if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS)
TPR              1625 src/dps8/dps8_append.c     if (cpu.TPR.CA >= (word18) cpu.SDW->EB)
TPR              1639 src/dps8/dps8_append.c     if (cpu.TPR.TRR > cpu.SDW->R3)
TPR              1650 src/dps8/dps8_append.c     if (cpu.TPR.TRR < cpu.SDW->R1)
TPR              1661 src/dps8/dps8_append.c     if (cpu.TPR.TRR > cpu.PPR.PRR)
TPR              1677 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.SDW->R2);
TPR              1680 src/dps8/dps8_append.c     if (cpu.TPR.TRR > cpu.SDW->R2)
TPR              1683 src/dps8/dps8_append.c         cpu.TPR.TRR = cpu.SDW->R2;
TPR              1686 src/dps8/dps8_append.c     DBGAPP ("do_append_cycle(E1): CALL6 TPR.TRR %o\n", cpu.TPR.TRR);
TPR              1706 src/dps8/dps8_append.c     if (cpu.TPR.TRR < cpu.SDW->R1 ||
TPR              1707 src/dps8/dps8_append.c         cpu.TPR.TRR > cpu.SDW->R2)
TPR              1711 src/dps8/dps8_append.c                 cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2);
TPR              1727 src/dps8/dps8_append.c     if (cpu.PPR.PRR != cpu.TPR.TRR)
TPR              1750 src/dps8/dps8_append.c     if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND)
TPR              1759 src/dps8/dps8_append.c                 cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
TPR              1778 src/dps8/dps8_append.c     DBGAPP ("do_append_cycle(G) CA %06o\n", cpu.TPR.CA);
TPR              1780 src/dps8/dps8_append.c         ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA))  //TPR.CA))
TPR              1782 src/dps8/dps8_append.c         fetch_ptw (cpu.SDW, cpu.TPR.CA);
TPR              1792 src/dps8/dps8_append.c         loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
TPR              1803 src/dps8/dps8_append.c         do_ptw2 (cpu.SDW, cpu.TPR.CA);
TPR              1829 src/dps8/dps8_append.c             cpu.SDW->ADDR, cpu.TPR.CA);
TPR              1835 src/dps8/dps8_append.c         finalAddress = cpu.TPR.CA;
TPR              1839 src/dps8/dps8_append.c         finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
TPR              1845 src/dps8/dps8_append.c             cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR              1864 src/dps8/dps8_append.c        modify_ptw (cpu.SDW, cpu.TPR.CA);
TPR              1871 src/dps8/dps8_append.c     word24 y2 = cpu.TPR.CA % 1024;
TPR              1883 src/dps8/dps8_append.c             cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TPR              1961 src/dps8/dps8_append.c         (cpu.TPR.CA & 1) == 0)
TPR              2029 src/dps8/dps8_append.c     cpu.TPR.TSR = GET_ITS_SEGNO (data);
TPR              2034 src/dps8/dps8_append.c     cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1);
TPR              2038 src/dps8/dps8_append.c     cpu.TPR.CA = GET_ITS_WORDNO (data);
TPR              2097 src/dps8/dps8_append.c         cpu.PR[7].RNR = cpu.TPR.TRR;
TPR              2115 src/dps8/dps8_append.c     cpu.PPR.PSR   = cpu.TPR.TSR;
TPR              2117 src/dps8/dps8_append.c     cpu.PPR.IC    = cpu.TPR.CA;
TPR              2125 src/dps8/dps8_append.c     if (cpu.TPR.TRR == 0)
TPR              2142 src/dps8/dps8_append.c     if (cpu.TPR.TRR == cpu.PPR.PRR)
TPR              2151 src/dps8/dps8_append.c         cpu.PR[7].SNR = ((word15) (cpu.DSBR.STACK << 3)) | cpu.TPR.TRR;
TPR              2153 src/dps8/dps8_append.c                 cpu.DSBR.STACK, cpu.TPR.TRR);
TPR              2158 src/dps8/dps8_append.c     cpu.PR[7].RNR = cpu.TPR.TRR;
TPR              2167 src/dps8/dps8_append.c     cpu.PPR.PRR   = cpu.TPR.TRR;
TPR              2169 src/dps8/dps8_append.c     cpu.PPR.PSR   = cpu.TPR.TSR;
TPR              2171 src/dps8/dps8_append.c     cpu.PPR.IC    = cpu.TPR.CA;
TPR              2185 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.RSDWH_R1, its_RNR);
TPR              2189 src/dps8/dps8_append.c     cpu.TPR.TRR = max3 (its_RNR, cpu.TPR.TRR, cpu.RSDWH_R1);
TPR              2190 src/dps8/dps8_append.c     DBGAPP ("do_append_cycle(O) Set TRR to %o\n", cpu.TPR.TRR);
TPR              2200 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.RSDWH_R1, cpu.PR[n].RNR);
TPR              2204 src/dps8/dps8_append.c     cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.TPR.TRR, cpu.RSDWH_R1);
TPR              2205 src/dps8/dps8_append.c     DBGAPP ("do_append_cycle(P) Set TRR to %o\n", cpu.TPR.TRR);
TPR              2211 src/dps8/dps8_append.c     PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
TPR              2219 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TPR              2407 src/dps8/dps8_cpu.c                 cpu.TPR.TRR = 0;
TPR              2683 src/dps8/dps8_cpu.c                 cpu.TPR.TSR          = cpu.PPR.PSR;
TPR              2684 src/dps8/dps8_cpu.c                 cpu.TPR.TRR          = cpu.PPR.PRR;
TPR              2698 src/dps8/dps8_cpu.c                 cpu.TPR.TSR              = cpu.PPR.PSR;
TPR              2699 src/dps8/dps8_cpu.c                 cpu.TPR.TRR              = cpu.PPR.PRR;
TPR              2766 src/dps8/dps8_cpu.c                   cpu.TPR.TSR          = cpu.PPR.PSR;
TPR              2767 src/dps8/dps8_cpu.c                   cpu.TPR.TRR          = cpu.PPR.PRR;
TPR              3059 src/dps8/dps8_cpu.c                   cpu.TPR.TSR          = cpu.PPR.PSR;
TPR              3060 src/dps8/dps8_cpu.c                   cpu.TPR.TRR          = cpu.PPR.PRR;
TPR              3187 src/dps8/dps8_cpu.c               cpu.TPR.TRR = 0;
TPR              4259 src/dps8/dps8_cpu.c     putbits36_18 (& w1, 0, cpu.TPR.CA);
TPR              4455 src/dps8/dps8_cpu.c     putbits36_15 (& w0,      0,  cpu.TPR.TSR);
TPR              4473 src/dps8/dps8_cpu.c     putbits36_3 (& w1,       24, cpu.TPR.TRR);
TPR              1658 src/dps8/dps8_cpu.h     struct tpr_s TPR;     // Temporary Pointer Register
TPR               563 src/dps8/dps8_eis.c     word3 saveTRR = cpu.TPR.TRR;
TPR               569 src/dps8/dps8_eis.c             cpu.TPR.TRR = p -> RNR;
TPR               570 src/dps8/dps8_eis.c             cpu.TPR.TSR = p -> SNR;
TPR               583 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
TPR               595 src/dps8/dps8_eis.c             cpu.TPR.TRR = cpu.PPR.PRR;
TPR               596 src/dps8/dps8_eis.c             cpu.TPR.TSR = cpu.PPR.PSR;
TPR               607 src/dps8/dps8_eis.c                              __func__, p -> cachedParagraph [i], cpu.TPR.TSR, p -> cachedAddr + i);
TPR               611 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
TPR               621 src/dps8/dps8_eis.c     cpu.TPR.TRR = saveTRR;
TPR               627 src/dps8/dps8_eis.c     word3 saveTRR = cpu.TPR.TRR;
TPR               646 src/dps8/dps8_eis.c         cpu.TPR.TRR = p -> RNR;
TPR               647 src/dps8/dps8_eis.c         cpu.TPR.TSR = p -> SNR;
TPR               650 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
TPR               665 src/dps8/dps8_eis.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               666 src/dps8/dps8_eis.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               671 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
TPR               678 src/dps8/dps8_eis.c                          __func__, p -> cachedParagraph [i], cpu.TPR.TSR, paragraphAddress + i);
TPR               686 src/dps8/dps8_eis.c     cpu.TPR.TRR = saveTRR;
TPR               805 src/dps8/dps8_eis.c     word3 saveTRR = cpu.TPR.TRR;
TPR               809 src/dps8/dps8_eis.c         cpu.TPR.TRR = p -> RNR;
TPR               810 src/dps8/dps8_eis.c         cpu.TPR.TSR = p -> SNR;
TPR               820 src/dps8/dps8_eis.c                            __func__, data [i], cpu.TPR.TSR, addressN + i);
TPR               832 src/dps8/dps8_eis.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               833 src/dps8/dps8_eis.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               843 src/dps8/dps8_eis.c                          __func__, data [i], cpu.TPR.TSR, addressN + i);
TPR               846 src/dps8/dps8_eis.c     cpu.TPR.TRR = saveTRR;
TPR               867 src/dps8/dps8_eis.c     word3 saveTRR = cpu.TPR.TRR;
TPR               871 src/dps8/dps8_eis.c         cpu.TPR.TRR = p -> RNR;
TPR               872 src/dps8/dps8_eis.c         cpu.TPR.TSR = p -> SNR;
TPR               882 src/dps8/dps8_eis.c                            __func__, data [i], cpu.TPR.TSR, addressN + i);
TPR               894 src/dps8/dps8_eis.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               895 src/dps8/dps8_eis.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               905 src/dps8/dps8_eis.c                          __func__, data [i], cpu.TPR.TSR, addressN + i);
TPR               908 src/dps8/dps8_eis.c     cpu.TPR.TRR = saveTRR;
TPR              1276 src/dps8/dps8_eis.c                                             cpu.TPR.TRR,
TPR              1425 src/dps8/dps8_eis.c         e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR);
TPR              1630 src/dps8/dps8_eis.c         e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR);
TPR              1682 src/dps8/dps8_eis.c         e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR);
TPR              1864 src/dps8/dps8_eis.c         e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR);
TPR                56 src/dps8/dps8_iefp.c     cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR               119 src/dps8/dps8_iefp.c                 cpu.TPR.CA = get_BAR_address (address);
TPR               120 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TPR               121 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TPR               128 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read BAR");
TPR               129 src/dps8/dps8_iefp.c                 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read BAR");
TPR               145 src/dps8/dps8_iefp.c                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read");
TPR               146 src/dps8/dps8_iefp.c                     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read");
TPR               159 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR               194 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR               195 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               196 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               200 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRead BAR");
TPR               201 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead BAR");
TPR               210 src/dps8/dps8_iefp.c           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRead");
TPR               211 src/dps8/dps8_iefp.c           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead");
TPR               221 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR               256 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR               257 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               258 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               262 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "readOperandRead BAR");
TPR               263 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead BAR");
TPR               273 src/dps8/dps8_iefp.c           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "readOperandRead");
TPR               274 src/dps8/dps8_iefp.c           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead");
TPR               285 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR               320 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR               321 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               322 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               326 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadOperandRMW BAR");
TPR               327 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW BAR");
TPR               336 src/dps8/dps8_iefp.c           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadOperandRMW");
TPR               337 src/dps8/dps8_iefp.c           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW");
TPR               347 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR               382 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR               383 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               384 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               388 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRMW BAR");
TPR               389 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW BAR");
TPR               398 src/dps8/dps8_iefp.c           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRMW");
TPR               399 src/dps8/dps8_iefp.c           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW");
TPR               411 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR               446 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR               447 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               448 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               452 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadInstructionFetch BAR");
TPR               453 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch BAR");
TPR               462 src/dps8/dps8_iefp.c           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadInstructionFetch");
TPR               463 src/dps8/dps8_iefp.c           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch");
TPR               473 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR               508 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR               509 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               510 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               514 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch BAR");
TPR               515 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch BAR");
TPR               524 src/dps8/dps8_iefp.c             HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch");
TPR               525 src/dps8/dps8_iefp.c             HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch");
TPR               537 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR               583 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR               584 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               585 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               592 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR");
TPR               593 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn");
TPR               594 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd");
TPR               610 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2");
TPR               611 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn");
TPR               612 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd");
TPR               623 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR               668 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR               669 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               670 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               677 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRead BR");
TPR               678 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead BR evn");
TPR               679 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead BR odd");
TPR               693 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRead");
TPR               694 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead evn");
TPR               695 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead odd");
TPR               705 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR               750 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR               751 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               752 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               759 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRMW BR");
TPR               760 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW BR evn");
TPR               761 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW BR odd");
TPR               771 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRMW");
TPR               772 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW evn");
TPR               773 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW odd");
TPR               783 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR               828 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR               829 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               830 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               837 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2InstructionFetch BR");
TPR               838 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch BR evn");
TPR               839 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch BR odd");
TPR               849 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2InstructionFetch");
TPR               850 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch evn");
TPR               851 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch odd");
TPR               860 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR               865 src/dps8/dps8_iefp.c     cpu.TPR.CA = get_BAR_address (address);
TPR               866 src/dps8/dps8_iefp.c     cpu.TPR.TSR = cpu.PPR.PSR;
TPR               867 src/dps8/dps8_iefp.c     cpu.TPR.TRR = cpu.PPR.PRR;
TPR               874 src/dps8/dps8_iefp.c     HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR");
TPR               875 src/dps8/dps8_iefp.c     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn");
TPR               876 src/dps8/dps8_iefp.c     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd");
TPR               886 src/dps8/dps8_iefp.c     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2");
TPR               887 src/dps8/dps8_iefp.c     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn");
TPR               888 src/dps8/dps8_iefp.c     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd");
TPR               895 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR               940 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR               941 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR               942 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR               949 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch BR");
TPR               950 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch BR evn");
TPR               951 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch BR odd");
TPR               961 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch");
TPR               962 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch evn");
TPR               963 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch odd");
TPR               974 src/dps8/dps8_iefp.c     cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR              1036 src/dps8/dps8_iefp.c                 cpu.TPR.CA = get_BAR_address (address);
TPR              1037 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TPR              1038 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1050 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read8 BAR");
TPR              1052 src/dps8/dps8_iefp.c                   HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result[i], "Read8 BAR");
TPR              1072 src/dps8/dps8_iefp.c                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read8");
TPR              1074 src/dps8/dps8_iefp.c                       HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "Read8");
TPR              1098 src/dps8/dps8_iefp.c     cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR              1160 src/dps8/dps8_iefp.c                 cpu.TPR.CA = get_BAR_address (address);
TPR              1161 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TPR              1162 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1174 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadPage B");
TPR              1176 src/dps8/dps8_iefp.c                   HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage B");
TPR              1197 src/dps8/dps8_iefp.c                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadPage");
TPR              1199 src/dps8/dps8_iefp.c                       HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage");
TPR              1210 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR              1252 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR              1253 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR              1254 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1258 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write BR");
TPR              1259 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write BR");
TPR              1266 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write");
TPR              1267 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write");
TPR              1278 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR              1314 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR              1315 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR              1316 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1320 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteAPUDataStore BR");
TPR              1321 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore BR");
TPR              1328 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteAPUDataStore");
TPR              1329 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore");
TPR              1338 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR              1380 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR              1381 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR              1382 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1386 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteOperandStore BR");
TPR              1387 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore BR");
TPR              1394 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteOperandStore");
TPR              1395 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore");
TPR              1407 src/dps8/dps8_iefp.c     cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR              1458 src/dps8/dps8_iefp.c                 cpu.TPR.CA = get_BAR_address (address);
TPR              1459 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TPR              1460 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1467 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2 BR");
TPR              1468 src/dps8/dps8_iefp.c                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 BR evn");
TPR              1469 src/dps8/dps8_iefp.c                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 BR odd");
TPR              1481 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2");
TPR              1482 src/dps8/dps8_iefp.c                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 evn");
TPR              1483 src/dps8/dps8_iefp.c                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 odd");
TPR              1494 src/dps8/dps8_iefp.c   cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR              1531 src/dps8/dps8_iefp.c         cpu.TPR.CA = get_BAR_address (address);
TPR              1532 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TPR              1533 src/dps8/dps8_iefp.c         cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1537 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2OperandStore BR");
TPR              1538 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore BR evn");
TPR              1539 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore BR odd");
TPR              1546 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2OperandStore");
TPR              1547 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore evn");
TPR              1548 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore odd");
TPR              1559 src/dps8/dps8_iefp.c     cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR              1605 src/dps8/dps8_iefp.c                 cpu.TPR.CA = get_BAR_address (address);
TPR              1606 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TPR              1607 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1615 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write1 BR");
TPR              1616 src/dps8/dps8_iefp.c                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1 BR");
TPR              1629 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write1");
TPR              1630 src/dps8/dps8_iefp.c                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1");
TPR              1641 src/dps8/dps8_iefp.c     cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR              1700 src/dps8/dps8_iefp.c                 cpu.TPR.CA = get_BAR_address (address);
TPR              1701 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TPR              1702 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1714 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write8 BR");
TPR              1716 src/dps8/dps8_iefp.c                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8 BR");
TPR              1734 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write8");
TPR              1736 src/dps8/dps8_iefp.c                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8");
TPR              1770 src/dps8/dps8_iefp.c     cpu.TPR.CA = cpu.iefpFinalAddress = address;
TPR              1829 src/dps8/dps8_iefp.c                 cpu.TPR.CA = get_BAR_address (address);
TPR              1830 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TPR              1831 src/dps8/dps8_iefp.c                 cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1844 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WritePage BR");
TPR              1846 src/dps8/dps8_iefp.c                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage BR");
TPR              1863 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WritePage");
TPR              1865 src/dps8/dps8_iefp.c                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage");
TPR              1876 src/dps8/dps8_iefp.c     if (cpu.TPR.CA & 1) // is odd?
TPR              1878 src/dps8/dps8_iefp.c         ReadIndirectWordFetch (cpu.TPR.CA, cpu.itxPair);
TPR              1883 src/dps8/dps8_iefp.c         Read2IndirectWordFetch (cpu.TPR.CA, cpu.itxPair);
TPR               156 src/dps8/dps8_ins.c         cpu.TPR.CA = cpu.ou.character_address;
TPR               160 src/dps8/dps8_ins.c     write_operand (cpu.TPR.CA, OPERAND_STORE);
TPR               176 src/dps8/dps8_ins.c               "%s a %d address %08o\n", __func__, i->b29, cpu.TPR.CA);
TPR               193 src/dps8/dps8_ins.c         SETHI (cpu.CY, cpu.TPR.CA);
TPR               206 src/dps8/dps8_ins.c         SETLO (cpu.CY, cpu.TPR.CA);
TPR               239 src/dps8/dps8_ins.c         cpu.TPR.CA = cpu.ou.character_address;
TPR               245 src/dps8/dps8_ins.c       readOperandRMW (cpu.TPR.CA);
TPR               247 src/dps8/dps8_ins.c       readOperandRead (cpu.TPR.CA);
TPR               249 src/dps8/dps8_ins.c     readOperandRead (cpu.TPR.CA);
TPR               257 src/dps8/dps8_ins.c     if (cpu.TPR.CA & 1)
TPR               258 src/dps8/dps8_ins.c       ReadOperandRead (cpu.TPR.CA, &cpu.CY);
TPR               260 src/dps8/dps8_ins.c       Read2OperandRead (cpu.TPR.CA, cpu.Ypair);
TPR               287 src/dps8/dps8_ins.c         cpu.PPR.IC = cpu.TPR.CA;
TPR               383 src/dps8/dps8_ins.c     putbits36_3 (& words[2],  0, cpu.TPR.TRR);
TPR               384 src/dps8/dps8_ins.c     putbits36_15 (& words[2], 3, cpu.TPR.TSR);
TPR               399 src/dps8/dps8_ins.c     putbits36_6 (& words[3], 30, cpu.TPR.TBR);
TPR               444 src/dps8/dps8_ins.c     putbits36 (& words[5],  0, 18, cpu.TPR.CA);
TPR               637 src/dps8/dps8_ins.c     cpu.TPR.TRR         = getbits36_3  (words[2], 0);
TPR               638 src/dps8/dps8_ins.c     cpu.TPR.TSR         = getbits36_15 (words[2], 3);
TPR               655 src/dps8/dps8_ins.c     cpu.TPR.TBR         = getbits36_6  (words[3], 30);
TPR              1097 src/dps8/dps8_ins.c         cpu.TPR.TRR  = 0;
TPR              1764 src/dps8/dps8_ins.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD CA %06o\n", cpu.TPR.CA);
TPR              1796 src/dps8/dps8_ins.c         cpu.TPR.CA = (cpu.rX[Xn] + offset) & AMASK;
TPR              1797 src/dps8/dps8_ins.c         cpu.rX[Xn] = cpu.TPR.CA;
TPR              1834 src/dps8/dps8_ins.c             cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1835 src/dps8/dps8_ins.c             cpu.TPR.TSR = cpu.PPR.PSR;
TPR              1882 src/dps8/dps8_ins.c       cpu.TPR.TBR = GET_PR_BITNO (n);
TPR              1884 src/dps8/dps8_ins.c       cpu.TPR.TSR = cpu.PAR[n].SNR;
TPR              1886 src/dps8/dps8_ins.c         cpu.TPR.TRR = max (cpu.PAR[n].RNR, cpu.PPR.PRR);
TPR              1888 src/dps8/dps8_ins.c         cpu.TPR.TRR = max3 (cpu.PAR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR);
TPR              1890 src/dps8/dps8_ins.c       sim_debug (DBG_APPENDING, &cpu_dev, "doPtrReg: n=%o offset=%05o TPR.CA=%06o " "TPR.TBR=%o TPR.TSR=%05o TPR.TRR=%o\n", n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR);
TPR              1905 src/dps8/dps8_ins.c         cpu.TPR.TBR = 0;
TPR              1907 src/dps8/dps8_ins.c           cpu.TPR.TSR  = cpu.PPR.PSR;
TPR              1908 src/dps8/dps8_ins.c           cpu.TPR.TRR  = 0;
TPR              1929 src/dps8/dps8_ins.c       cpu.iefpFinalAddress = cpu.TPR.CA;
TPR              1976 src/dps8/dps8_ins.c     cpu.last_write = cpu.TPR.CA;
TPR              1998 src/dps8/dps8_ins.c     cpu.TPR.TRR = cpu.PPR.PRR;
TPR              1999 src/dps8/dps8_ins.c     cpu.TPR.TSR = cpu.PPR.PSR;
TPR              2000 src/dps8/dps8_ins.c     cpu.TPR.TBR = 0;
TPR              2040 src/dps8/dps8_ins.c         cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK;
TPR              2041 src/dps8/dps8_ins.c         cpu.rX[Xn] = cpu.TPR.CA;
TPR              2056 src/dps8/dps8_ins.c         cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK;
TPR              2057 src/dps8/dps8_ins.c         cpu.rX[Xn] = cpu.TPR.CA;
TPR              2068 src/dps8/dps8_ins.c         cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK;
TPR              2069 src/dps8/dps8_ins.c         cpu.rX[Xn] = cpu.TPR.CA;
TPR              2630 src/dps8/dps8_ins.c             cpu.PR[n].RNR    = cpu.TPR.TRR;
TPR              2631 src/dps8/dps8_ins.c             cpu.PR[n].SNR    = cpu.TPR.TSR;
TPR              2632 src/dps8/dps8_ins.c             cpu.PR[n].WORDNO = cpu.TPR.CA;
TPR              2633 src/dps8/dps8_ins.c             SET_PR_BITNO (n, cpu.TPR.TBR);
TPR              2808 src/dps8/dps8_ins.c               cpu.PR[n].RNR = cpu.TPR.TRR;
TPR              2876 src/dps8/dps8_ins.c             cpu.rX[n] = cpu.TPR.CA;
TPR              2881 src/dps8/dps8_ins.c             SC_I_ZERO (cpu.TPR.CA == 0);
TPR              2882 src/dps8/dps8_ins.c             SC_I_NEG (cpu.TPR.CA & SIGN18);
TPR              2942 src/dps8/dps8_ins.c             cpu.PR[n].RNR    = cpu.TPR.TRR;
TPR              2943 src/dps8/dps8_ins.c             cpu.PR[n].SNR    = cpu.TPR.TSR;
TPR              3073 src/dps8/dps8_ins.c             word36 tmp36 = cpu.TPR.CA & 0177;   // CY bits 11-17
TPR              3099 src/dps8/dps8_ins.c           Read2RTCDOperandFetch (cpu.TPR.CA, cpu.Ypair);
TPR              3351 src/dps8/dps8_ins.c           cpu.rA  = cpu.TPR.TRR & MASK3;
TPR              3352 src/dps8/dps8_ins.c           cpu.rA |= (word36) (cpu.TPR.TSR & MASK15) << 18;
TPR              3357 src/dps8/dps8_ins.c           cpu.rQ  = cpu.TPR.TBR & MASK6;
TPR              3358 src/dps8/dps8_ins.c           cpu.rQ |= (word36) (cpu.TPR.CA & MASK18) << 18;
TPR              3374 src/dps8/dps8_ins.c             word36 tmp36   = cpu.TPR.CA & 0177;   // CY bits 11-17
TPR              3427 src/dps8/dps8_ins.c           SETHI (cpu.rA, cpu.TPR.CA);
TPR              3431 src/dps8/dps8_ins.c           SC_I_ZERO (cpu.TPR.CA == 0);
TPR              3432 src/dps8/dps8_ins.c           SC_I_NEG (cpu.TPR.CA & SIGN18);
TPR              3438 src/dps8/dps8_ins.c           SETHI (cpu.rQ, cpu.TPR.CA);
TPR              3443 src/dps8/dps8_ins.c           SC_I_ZERO (cpu.TPR.CA == 0);
TPR              3444 src/dps8/dps8_ins.c           SC_I_NEG (cpu.TPR.CA & SIGN18);
TPR              3936 src/dps8/dps8_ins.c               word36 tmp36 = cpu.TPR.CA & 0177;   // CY bits 11-17
TPR              3965 src/dps8/dps8_ins.c             word36 tmp36 = cpu.TPR.CA & 0177;   // CY bits 11-17
TPR              3987 src/dps8/dps8_ins.c             word18 tmp18 = cpu.TPR.CA & 0177;   // CY bits 11-17
TPR              4015 src/dps8/dps8_ins.c             word36 tmp36 = cpu.TPR.CA & 0177;      // CY bits 11-17
TPR              4055 src/dps8/dps8_ins.c             word36 tmp36   = cpu.TPR.CA & 0177;   // CY bits 11-17
TPR              4093 src/dps8/dps8_ins.c             word36 tmp36 = cpu.TPR.CA & 0177;   // CY bits 11-17
TPR              4125 src/dps8/dps8_ins.c             word36 tmp36  = cpu.TPR.CA & 0177;   // CY bits 11-17
TPR              4161 src/dps8/dps8_ins.c             word36 tmp36 = cpu.TPR.CA & 0177;   // CY bits 11-17
TPR              4189 src/dps8/dps8_ins.c             word36 tmp36 = cpu.TPR.CA & 0177;   // CY bits 11-17
TPR              4213 src/dps8/dps8_ins.c             word36 tmp36 = cpu.TPR.CA & 0177;   // CY bits 11-17
TPR              6141 src/dps8/dps8_ins.c             ReadOperandRead (cpu.TPR.CA, & cpu.CY);
TPR              6325 src/dps8/dps8_ins.c               cpu.TPR.CA = get_BAR_address (cpu.TPR.CA);
TPR              6380 src/dps8/dps8_ins.c           cpu.PR[0].SNR = cpu.TPR.CA & MASK15;
TPR              6389 src/dps8/dps8_ins.c           cpu.PR[1].SNR = cpu.TPR.CA & MASK15;
TPR              6398 src/dps8/dps8_ins.c           cpu.PR[2].SNR = cpu.TPR.CA & MASK15;
TPR              6407 src/dps8/dps8_ins.c           cpu.PR[3].SNR = cpu.TPR.CA & MASK15;
TPR              6416 src/dps8/dps8_ins.c           cpu.PR[4].SNR = cpu.TPR.CA & MASK15;
TPR              6425 src/dps8/dps8_ins.c           cpu.PR[5].SNR = cpu.TPR.CA & MASK15;
TPR              6434 src/dps8/dps8_ins.c           cpu.PR[6].SNR = cpu.TPR.CA & MASK15;
TPR              6443 src/dps8/dps8_ins.c           cpu.PR[7].SNR = cpu.TPR.CA & MASK15;
TPR              6456 src/dps8/dps8_ins.c           cpu.PR[0].WORDNO = cpu.TPR.CA;
TPR              6457 src/dps8/dps8_ins.c           SET_PR_BITNO (0, cpu.TPR.TBR);
TPR              6468 src/dps8/dps8_ins.c           cpu.PR[1].WORDNO = cpu.TPR.CA;
TPR              6469 src/dps8/dps8_ins.c           SET_PR_BITNO (1, cpu.TPR.TBR);
TPR              6480 src/dps8/dps8_ins.c           cpu.PR[2].WORDNO = cpu.TPR.CA;
TPR              6481 src/dps8/dps8_ins.c           SET_PR_BITNO (2, cpu.TPR.TBR);
TPR              6492 src/dps8/dps8_ins.c           cpu.PR[3].WORDNO = cpu.TPR.CA;
TPR              6493 src/dps8/dps8_ins.c           SET_PR_BITNO (3, cpu.TPR.TBR);
TPR              6504 src/dps8/dps8_ins.c           cpu.PR[4].WORDNO = cpu.TPR.CA;
TPR              6505 src/dps8/dps8_ins.c           SET_PR_BITNO (4, cpu.TPR.TBR);
TPR              6516 src/dps8/dps8_ins.c           cpu.PR[5].WORDNO = cpu.TPR.CA;
TPR              6517 src/dps8/dps8_ins.c           SET_PR_BITNO (5, cpu.TPR.TBR);
TPR              6528 src/dps8/dps8_ins.c           cpu.PR[6].WORDNO = cpu.TPR.CA;
TPR              6529 src/dps8/dps8_ins.c           SET_PR_BITNO (6, cpu.TPR.TBR);
TPR              6540 src/dps8/dps8_ins.c           cpu.PR[7].WORDNO = cpu.TPR.CA;
TPR              6541 src/dps8/dps8_ins.c           SET_PR_BITNO (7, cpu.TPR.TBR);
TPR              6586 src/dps8/dps8_ins.c                 cpu.PR[n].RNR = max3 (Crr, cpu.SDW->R1, cpu.TPR.TRR);
TPR              6758 src/dps8/dps8_ins.c               cpu_port_num = (cpu.TPR.CA >> 15) & 07;
TPR              6760 src/dps8/dps8_ins.c               cpu_port_num = (cpu.TPR.CA >> 15) & 03;
TPR              7484 src/dps8/dps8_ins.c             DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;)
TPR              7522 src/dps8/dps8_ins.c             DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;)
TPR              7542 src/dps8/dps8_ins.c             DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;)
TPR              7580 src/dps8/dps8_ins.c             DPS8M_ (level = (cpu.TPR.CA >> 5) & 03;)
TPR              7648 src/dps8/dps8_ins.c                 DPS8M_ (if (cpu.TPR.CA != 0000002 && (cpu.TPR.CA & 3) != 0)
TPR              7649 src/dps8/dps8_ins.c                   sim_warn ("CAMP ignores enable/disable %06o\n", cpu.TPR.CA);)
TPR              7650 src/dps8/dps8_ins.c                 if ((cpu.TPR.CA & 3) == 02)
TPR              7652 src/dps8/dps8_ins.c                 else if ((cpu.TPR.CA & 3) == 01)
TPR              7693 src/dps8/dps8_ins.c                 DPS8M_ (if (cpu.TPR.CA != 0000006 && (cpu.TPR.CA & 3) != 0)
TPR              7694 src/dps8/dps8_ins.c                   sim_warn ("CAMS ignores enable/disable %06o\n", cpu.TPR.CA);)
TPR              7695 src/dps8/dps8_ins.c                 if ((cpu.TPR.CA & 3) == 02)
TPR              7697 src/dps8/dps8_ins.c                 else if ((cpu.TPR.CA & 3) == 01)
TPR              7717 src/dps8/dps8_ins.c             DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;)
TPR              7718 src/dps8/dps8_ins.c             L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;)
TPR              7776 src/dps8/dps8_ins.c             DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 10) & 03;)
TPR              7777 src/dps8/dps8_ins.c             L68_ (cpu_port_num = (cpu.TPR.CA >> 10) & 07;)
TPR              7826 src/dps8/dps8_ins.c                   cpu.rA = PROM[cpu.TPR.CA & 1023];
TPR              7830 src/dps8/dps8_ins.c             uint select = cpu.TPR.CA & 0x7;
TPR              8229 src/dps8/dps8_ins.c             DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;)
TPR              8230 src/dps8/dps8_ins.c             L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;)
TPR              8257 src/dps8/dps8_ins.c             DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;)
TPR              8258 src/dps8/dps8_ins.c             L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;)
TPR              8288 src/dps8/dps8_ins.c             DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 10) & 03;)
TPR              8289 src/dps8/dps8_ins.c             L68_ (cpu_port_num = (cpu.TPR.CA >> 10) & 07;)
TPR              9401 src/dps8/dps8_ins.c     sim_debug (DBG_APPENDING, & cpu_dev, "absa CA:%08o\n", cpu.TPR.CA);
TPR              9407 src/dps8/dps8_ins.c         * result = ((word36) (cpu.TPR.CA & MASK18)) << 12; // 24:12 format
TPR              4151 src/dps8/dps8_sys.c     { "cpus[].TPR",             SYM_STRUCT_OFFSET, SYM_PTR,       offsetof (cpu_state_t,           TPR)         },