This source file includes following definitions.
- get_Cr
- op_desc_str
- do_ITP
- do_ITS
- do_ITS_ITP
- updateIWB
- do_caf
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19 #include <stdio.h>
20 #include "dps8.h"
21 #include "dps8_sys.h"
22 #include "dps8_iom.h"
23 #include "dps8_cable.h"
24 #include "dps8_cpu.h"
25 #include "dps8_scu.h"
26 #include "dps8_faults.h"
27 #include "dps8_addrmods.h"
28 #include "dps8_append.h"
29 #include "dps8_ins.h"
30 #include "dps8_iefp.h"
31 #include "dps8_opcodetable.h"
32 #include "dps8_utils.h"
33 #if defined(THREADZ) || defined(LOCKLESS)
34 # include "threadz.h"
35 #endif
36
37 #define DBG_CTR cpu.cycleCnt
38
39
40
41
42
43
44
45 static word18 get_Cr (cpu_state_t * cpup, word4 Tdes)
46 {
47 cpu.ou.directOperandFlag = false;
48
49 if (Tdes == TD_N)
50 return 0;
51
52 if (Tdes & 010)
53 return cpu.rX [X (Tdes)];
54
55 switch (Tdes)
56 {
57 case TD_N:
58 return 0;
59
60 case TD_AU:
61 #if defined(TESTING)
62 HDBGRegAR ("au");
63 #endif
64 return GETHI (cpu.rA);
65
66 case TD_QU:
67 #if defined(TESTING)
68 HDBGRegAR ("qu");
69 #endif
70 return GETHI (cpu.rQ);
71
72 case TD_DU:
73 cpu.ou.directOperand = 0;
74 SETHI (cpu.ou.directOperand, cpu.rY);
75 cpu.ou.directOperandFlag = true;
76
77 sim_debug (DBG_ADDRMOD, & cpu_dev,
78 "%s(TD_DU): rY=%06o directOperand=%012"PRIo64"\n",
79 __func__, cpu.rY, cpu.ou.directOperand);
80
81 return 0;
82
83 case TD_IC:
84 return cpu.PPR.IC;
85
86 case TD_AL:
87 #if defined(TESTING)
88 HDBGRegAR ("al");
89 #endif
90 return GETLO (cpu.rA);
91
92 case TD_QL:
93 #if defined(TESTING)
94 HDBGRegAR ("ql");
95 #endif
96 return GETLO (cpu.rQ);
97
98 case TD_DL:
99 cpu.ou.directOperand = 0;
100 SETLO (cpu.ou.directOperand, cpu.rY);
101 cpu.ou.directOperandFlag = true;
102
103 sim_debug (DBG_ADDRMOD, & cpu_dev,
104 "%s(TD_DL): rY=%06o directOperand=%012"PRIo64"\n",
105 __func__, cpu.rY, cpu.ou.directOperand);
106
107 return 0;
108 }
109 return 0;
110 }
111
112 static char * op_desc_str (cpu_state_t * cpup, char * temp)
113 {
114 DCDstruct * i = & cpu.currentInstruction;
115
116 strcpy (temp, "");
117
118 if (READOP (i))
119 {
120 switch (operand_size (cpup))
121 {
122 case 1:
123 strcat (temp, "readCY");
124 break;
125
126 case 2:
127 strcat (temp, "readCYpair2");
128 break;
129
130 case 8:
131 strcat (temp, "readCYblock8");
132 break;
133
134 case 16:
135 strcat (temp, "readCYblock16");
136 break;
137
138 case 32:
139 strcat (temp, "readCYblock32");
140 break;
141 }
142 }
143
144 if (WRITEOP (i))
145 {
146 if (strlen (temp))
147 strcat (temp, "/");
148
149 switch (operand_size (cpup))
150 {
151 case 1:
152 strcat (temp, "writeCY");
153 break;
154
155 case 2:
156 strcat (temp, "writeCYpair2");
157 break;
158
159 case 8:
160 strcat (temp, "writeCYblock8");
161 break;
162
163 case 16:
164 strcat (temp, "writeCYblock16");
165 break;
166
167 case 32:
168 strcat (temp, "writeCYblock32");
169 break;
170 }
171 }
172
173 if (TRANSOP (i))
174 {
175 if (strlen (temp))
176 strcat (temp, "/");
177
178 strcat (temp, "prepareCA (TRA)");
179 }
180
181 if (! READOP (i) && ! WRITEOP (i) && ! TRANSOP (i) &&
182 i -> info -> flags & PREPARE_CA)
183 {
184 if (strlen (temp))
185 strcat (temp, "/");
186
187 strcat (temp, "prepareCA");
188 }
189
190 return temp;
191 }
192
193 static void do_ITP (cpu_state_t * cpup)
194 {
195 sim_debug (DBG_APPENDING, & cpu_dev,
196 "ITP Pair: PRNUM=%o BITNO=%o WORDNO=%o MOD=%o\n",
197 GET_ITP_PRNUM (cpu.itxPair), GET_ITP_WORDNO (cpu.itxPair),
198 GET_ITP_BITNO (cpu.itxPair), GET_ITP_MOD (cpu.itxPair));
199
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215
216 word3 n = GET_ITP_PRNUM (cpu.itxPair);
217 CPTUR (cptUsePRn + n);
218 #if defined(TESTING)
219 HDBGRegPRR (n, "ITP");
220 #endif
221 cpu.TPR.TSR = cpu.PR[n].SNR;
222 cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.RSDWH_R1, cpu.TPR.TRR);
223 cpu.TPR.TBR = GET_ITP_BITNO (cpu.itxPair);
224 cpu.TPR.CA = cpu.PAR[n].WORDNO + GET_ITP_WORDNO (cpu.itxPair);
225 cpu.TPR.CA &= AMASK;
226 cpu.rY = cpu.TPR.CA;
227
228 cpu.rTAG = GET_ITP_MOD (cpu.itxPair);
229
230 cpu.cu.itp = 1;
231 cpu.cu.TSN_PRNO[0] = n;
232 cpu.cu.TSN_VALID[0] = 1;
233
234 return;
235 }
236
237 static void do_ITS (cpu_state_t * cpup)
238 {
239 sim_debug (DBG_APPENDING, & cpu_dev,
240 "ITS Pair: SEGNO=%o RN=%o WORDNO=%o BITNO=%o MOD=%o\n",
241 GET_ITS_SEGNO (cpu.itxPair), GET_ITS_RN (cpu.itxPair),
242 GET_ITS_WORDNO (cpu.itxPair), GET_ITS_BITNO (cpu.itxPair),
243 GET_ITS_MOD (cpu.itxPair));
244
245
246
247
248
249
250
251
252
253
254
255
256
257 cpu.TPR.TSR = GET_ITS_SEGNO (cpu.itxPair);
258
259 sim_debug (DBG_APPENDING, & cpu_dev,
260 "ITS Pair Ring: RN %o RSDWH_R1 %o TRR %o max %o\n",
261 GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR,
262 max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR));
263
264 cpu.TPR.TRR = max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR);
265 cpu.TPR.TBR = GET_ITS_BITNO (cpu.itxPair);
266 cpu.TPR.CA = GET_ITS_WORDNO (cpu.itxPair);
267 cpu.TPR.CA &= AMASK;
268
269 cpu.rY = cpu.TPR.CA;
270
271 cpu.rTAG = GET_ITS_MOD (cpu.itxPair);
272
273 cpu.cu.its = 1;
274
275 return;
276 }
277
278
279 static void do_ITS_ITP (cpu_state_t * cpup)
280 {
281 word6 ind_tag = GET_TAG (cpu.itxPair [0]);
282
283 sim_debug (DBG_APPENDING, & cpu_dev,
284 "do_ITS/ITP: %012"PRIo64" %012"PRIo64"\n",
285 cpu.itxPair[0], cpu.itxPair[1]);
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306
307
308 if (ISITS (ind_tag))
309 do_ITS (cpup);
310 else
311 do_ITP (cpup);
312
313
314 cpu.cu.XSF = 1;
315 sim_debug (DBG_APPENDING, & cpu_dev, "do_ITS_ITP sets XSF to 1\n");
316 }
317
318 void updateIWB (cpu_state_t * cpup, word18 addr, word6 tag)
319 {
320 word36 * wb;
321 if (USE_IRODD)
322 wb = & cpu.cu.IRODD;
323 else
324 wb = & cpu.cu.IWB;
325 sim_debug (DBG_ADDRMOD, & cpu_dev,
326 "updateIWB: IWB was %012"PRIo64" %06o %s\n",
327 * wb, GET_ADDR (* wb),
328 extMods [GET_TAG (* wb)].mod);
329
330 putbits36_18 (wb, 0, addr);
331 putbits36_6 (wb, 30, tag);
332 putbits36_1 (wb, 29, 0);
333
334 sim_debug (DBG_ADDRMOD, & cpu_dev,
335 "updateIWB: IWB now %012"PRIo64" %06o %s\n",
336 * wb, GET_ADDR (* wb),
337 extMods [GET_TAG (* wb)].mod);
338
339 decode_instruction (cpup, IWB_IRODD, & cpu.currentInstruction);
340 }
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357 void do_caf (cpu_state_t * cpup)
358 {
359 if (cpu.currentInstruction.b29 == 0)
360 {
361 cpu.TPR.CA = GET_ADDR (IWB_IRODD);
362 }
363 else
364 {
365 word3 n = GET_PRN(IWB_IRODD);
366 #if defined(TESTING)
367 HDBGRegPRR (n, "b29");
368 #endif
369 word15 offset = GET_OFFSET(IWB_IRODD);
370 cpu.TPR.CA = (cpu.PAR[n].WORDNO + SIGNEXT15_18 (offset))
371 & MASK18;
372 }
373 char buf [256];
374 sim_debug (DBG_ADDRMOD, & cpu_dev,
375 "%s(Entry): operType:%s TPR.CA=%06o\n",
376 __func__, op_desc_str (cpup, buf), cpu.TPR.CA);
377 sim_debug (DBG_ADDRMOD, & cpu_dev,
378 "%s(Entry): CT_HOLD %o\n",
379 __func__, cpu.cu.CT_HOLD);
380
381 DCDstruct * i = & cpu.currentInstruction;
382
383 word6 Tm = 0;
384 word6 Td = 0;
385
386
387
388 cpu.ou.directOperandFlag = false;
389
390 if (i -> info -> flags & NO_TAG)
391 cpu.rTAG = 0;
392 else
393 cpu.rTAG = GET_TAG (IWB_IRODD);
394
395 int lockupCnt = 0;
396 #define lockupLimit 4096
397
398 startCA:;
399
400 if (++ lockupCnt > lockupLimit)
401 {
402 doFault (FAULT_LUF, fst_zero, "Lockup in addrmod");
403 }
404
405 Td = GET_TD (cpu.rTAG);
406 Tm = GET_TM (cpu.rTAG);
407
408
409
410
411 if (cpu.cu.CT_HOLD)
412 {
413 sim_debug (DBG_ADDRMOD, & cpu_dev,
414 "%s(startCA): restart; CT_HOLD %02o\n",
415 __func__, cpu.cu.CT_HOLD);
416
417 if (cpu.tweaks.isolts_mode &&
418 GET_TM(cpu.cu.CT_HOLD) == TM_IT && GET_TD (cpu.cu.CT_HOLD) == IT_DIC &&
419 cpu.cu.pot == 1 && GET_ADDR (IWB_IRODD) == cpu.TPR.CA)
420 {
421 cpu.TPR.CA--;
422 sim_warn ("%s: correct CA\n", __func__);
423 }
424 if (Tm == TM_IT && (Td == IT_IDC || Td == IT_DIC))
425 {
426 cpu.cu.pot = 1;
427 }
428 }
429 else
430 {
431
432 cpu.cu.its = 0;
433 cpu.cu.itp = 0;
434 cpu.cu.pot = 0;
435 }
436 sim_debug (DBG_ADDRMOD, & cpu_dev,
437 "%s(startCA): TAG=%02o(%s) Tm=%o Td=%o CT_HOLD %02o\n",
438 __func__, cpu.rTAG, get_mod_string (buf, cpu.rTAG), Tm, Td, cpu.cu.CT_HOLD);
439
440 switch (Tm)
441 {
442 case TM_R:
443 goto R_MOD;
444 case TM_RI:
445 goto RI_MOD;
446 case TM_IT:
447 goto IT_MOD;
448 case TM_IR:
449 goto IR_MOD;
450 default:
451 break;
452 }
453
454 sim_printf ("%s(startCA): unknown Tm??? %o\n",
455 __func__, GET_TM (cpu.rTAG));
456 sim_warn ("(startCA): unknown Tmi; can't happen!\n");
457 return;
458
459
460 R_MOD:;
461 {
462 if (Td == TD_N)
463 {
464
465 return;
466 }
467
468 word18 Cr = get_Cr (cpup, Td);
469
470 sim_debug (DBG_ADDRMOD, & cpu_dev, "R_MOD: Cr=%06o\n", Cr);
471
472 if (cpu.ou.directOperandFlag)
473 {
474 sim_debug (DBG_ADDRMOD, & cpu_dev,
475 "R_MOD: directOperand = %012"PRIo64"\n",
476 cpu.ou.directOperand);
477 return;
478 }
479
480
481
482 if (cpu.cu.rpt || cpu.cu.rd | cpu.cu.rl)
483 {
484 if (cpu.currentInstruction.b29)
485 {
486 word3 PRn = GET_PRN(IWB_IRODD);
487 #if defined(TESTING)
488 HDBGRegPRR (PRn, "rpx b29");
489 #endif
490 CPTUR (cptUsePRn + PRn);
491 cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO;
492 cpu.TPR.CA &= AMASK;
493 }
494 else
495 {
496 cpu.TPR.CA = Cr;
497 }
498 }
499 else
500 {
501 cpu.TPR.CA += Cr;
502 cpu.TPR.CA &= MASK18;
503 }
504 sim_debug (DBG_ADDRMOD, & cpu_dev, "R_MOD: TPR.CA=%06o\n",
505 cpu.TPR.CA);
506
507 return;
508 }
509
510
511 RI_MOD:;
512 {
513 sim_debug (DBG_ADDRMOD, & cpu_dev, "RI_MOD: Td=%o\n", Td);
514
515 if (Td == TD_DU || Td == TD_DL)
516 doFault (FAULT_IPR, fst_ill_mod,
517 "RI_MOD: Td == TD_DU || Td == TD_DL");
518
519 if (Td != TD_N)
520 {
521 word18 Cr = get_Cr (cpup, Td);
522
523
524
525
526 sim_debug (DBG_ADDRMOD, & cpu_dev,
527 "RI_MOD: Cr=%06o CA(Before)=%06o\n", Cr, cpu.TPR.CA);
528
529 if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)
530 {
531 if (cpu.currentInstruction.b29)
532 {
533 word3 PRn = GET_PRN(IWB_IRODD);
534 #if defined(TESTING)
535 HDBGRegPRR (PRn, "rpx b29");
536 #endif
537 CPTUR (cptUsePRn + PRn);
538 cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO;
539 }
540 else
541 {
542 cpu.TPR.CA = Cr;
543 }
544 cpu.TPR.CA &= AMASK;
545 }
546 else
547 {
548 cpu.TPR.CA += Cr;
549 cpu.TPR.CA &= MASK18;
550 }
551 sim_debug (DBG_ADDRMOD, & cpu_dev,
552 "RI_MOD: CA(After)=%06o\n", cpu.TPR.CA);
553 }
554
555
556
557
558 if (GET_TM(cpu.cu.CT_HOLD) == TM_IR)
559 {
560 goto IR_MOD_2;
561 }
562
563
564
565
566 word18 saveCA = cpu.TPR.CA;
567 ReadIndirect (cpup);
568
569 if ((saveCA & 1) == 0 && (ISITP (cpu.itxPair[0]) || ISITS (cpu.itxPair[0])))
570 {
571 do_ITS_ITP (cpup);
572 updateIWB (cpup, cpu.TPR.CA, cpu.rTAG);
573 }
574 else
575 {
576 cpu.rTAG = GET_TAG (cpu.itxPair[0]);
577 if (ISITP (cpu.itxPair[0]) || ISITS (cpu.itxPair[0]))
578 {
579 sim_warn ("%s: itp/its at odd address\n", __func__);
580 #if defined(TESTING)
581 traceInstruction (0);
582 #endif
583 }
584 if (!(cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl))
585 {
586 updateIWB (cpup, GET_ADDR (cpu.itxPair[0]), cpu.rTAG);
587 }
588
589 if (GET_TM (cpu.rTAG) == TM_IT)
590 {
591 if (GET_TD (cpu.rTAG) == IT_F2)
592 {
593 doFault (FAULT_F2, fst_zero, "RI_MOD: IT_F2 (0)");
594 }
595 if (GET_TD (cpu.rTAG) == IT_F3)
596 {
597 doFault (FAULT_F3, fst_zero, "RI_MOD: IT_F3");
598 }
599 }
600 cpu.TPR.CA = GETHI (cpu.itxPair[0]);
601 cpu.rY = cpu.TPR.CA;
602 }
603
604
605
606
607
608
609
610 sim_debug (DBG_ADDRMOD, & cpu_dev,
611 "RI_MOD: cpu.itxPair[0]=%012"PRIo64
612 " TPR.CA=%06o rTAG=%02o\n",
613 cpu.itxPair[0], cpu.TPR.CA, cpu.rTAG);
614
615
616
617 if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)
618 return;
619
620 goto startCA;
621 }
622
623
624 IR_MOD:;
625 {
626 IR_MOD_1:;
627
628 sim_debug (DBG_ADDRMOD, & cpu_dev,
629 "IR_MOD: CT_HOLD=%o %o\n", cpu.cu.CT_HOLD, Td);
630
631 IR_MOD_2:;
632
633 if (++ lockupCnt > lockupLimit)
634 {
635 doFault (FAULT_LUF, fst_zero, "Lockup in addrmod IR mode");
636 }
637
638 sim_debug (DBG_ADDRMOD, & cpu_dev,
639 "IR_MOD: fetching indirect word from %06o\n",
640 cpu.TPR.CA);
641
642 word18 saveCA = cpu.TPR.CA;
643 ReadIndirect (cpup);
644
645
646 if (GET_TM(cpu.rTAG) == TM_IR)
647 cpu.cu.CT_HOLD = cpu.rTAG;
648
649 if ((saveCA & 1) == 0 && (ISITP (cpu.itxPair[0]) || ISITS (cpu.itxPair[0])))
650 {
651 do_ITS_ITP (cpup);
652 }
653 else
654 {
655 if (ISITP (cpu.itxPair[0]) || ISITS (cpu.itxPair[0]))
656 {
657 sim_warn ("%s: itp/its at odd address\n", __func__);
658 #if defined(TESTING)
659 traceInstruction (0);
660 #endif
661 }
662 cpu.TPR.CA = GETHI (cpu.itxPair[0]);
663 cpu.rY = cpu.TPR.CA;
664 cpu.rTAG = GET_TAG (cpu.itxPair[0]);
665 }
666
667 sim_debug (DBG_ADDRMOD, & cpu_dev,
668 "IR_MOD: CT_HOLD=%o\n", cpu.cu.CT_HOLD);
669 Td = GET_TD (cpu.rTAG);
670 Tm = GET_TM (cpu.rTAG);
671
672 sim_debug (DBG_ADDRMOD, & cpu_dev,
673 "IR_MOD1: cpu.itxPair[0]=%012"PRIo64
674 " TPR.CA=%06o Tm=%o Td=%02o (%s)\n",
675 cpu.itxPair[0], cpu.TPR.CA, Tm, Td,
676 get_mod_string (buf, GET_TAG (cpu.itxPair[0])));
677
678 switch (Tm)
679 {
680 case TM_IT:
681 {
682 sim_debug (DBG_ADDRMOD, & cpu_dev,
683 "IR_MOD(TM_IT): Td=%02o => %02o\n",
684 Td, cpu.cu.CT_HOLD);
685
686 if (Td == IT_F2 || Td == IT_F3)
687 {
688 updateIWB(cpup, cpu.TPR.CA, cpu.rTAG);
689
690 switch (Td)
691 {
692 case IT_F2:
693 cpu.TPR.CA = saveCA;
694 doFault (FAULT_F2, fst_zero, "TM_IT: IT_F2 (1)");
695
696
697 case IT_F3:
698 cpu.TPR.CA = saveCA;
699 doFault (FAULT_F3, fst_zero, "TM_IT: IT_F3");
700 }
701 }
702
703 #if !defined(__SUNPRO_C) && !defined(__SUNPRO_CC) && !defined(__SUNPRO_CC_COMPAT)
704
705
706 # if defined(__GNUC__) && __GNUC__ > 6
707 __attribute__ ((fallthrough));
708 # endif
709
710 # if defined(__clang__)
711 (void)0;
712 # endif
713 #endif
714 }
715
716
717 case TM_R:
718 {
719 word6 Td_hold = GET_TD (cpu.cu.CT_HOLD);
720 cpu.rTAG = (TM_R | Td_hold);
721 updateIWB (cpup, cpu.TPR.CA, cpu.rTAG);
722 goto startCA;
723 }
724
725 case TM_RI:
726 {
727 if (Td == TD_DU || Td == TD_DL)
728 doFault (FAULT_IPR, fst_ill_mod,
729 "RI_MOD: Td == TD_DU || Td == TD_DL");
730
731 word18 Cr = get_Cr (cpup, Td);
732
733 sim_debug (DBG_ADDRMOD, & cpu_dev,
734 "IR_MOD(TM_RI): Td=%o Cr=%06o TPR.CA(Before)=%06o\n",
735 Td, Cr, cpu.TPR.CA);
736
737 cpu.TPR.CA += Cr;
738 cpu.TPR.CA &= MASK18;
739
740 sim_debug (DBG_ADDRMOD, & cpu_dev,
741 "IR_MOD(TM_RI): TPR.CA=%06o\n", cpu.TPR.CA);
742
743 sim_debug (DBG_ADDRMOD, & cpu_dev,
744 "IR_MOD(TM_RI): TPR.CA(After)=%06o\n",
745 cpu.TPR.CA);
746
747
748 updateIWB (cpup, cpu.TPR.CA, (TM_RI|TD_N));
749 goto IR_MOD_2;
750 }
751
752 case TM_IR:
753 {
754 updateIWB (cpup, cpu.TPR.CA, cpu.rTAG);
755 goto IR_MOD_1;
756 }
757 }
758
759 sim_printf ("%s(IR_MOD): unknown Tm??? %o\n",
760 __func__, GET_TM (cpu.rTAG));
761 return;
762 }
763
764 IT_MOD:;
765 {
766
767
768
769
770
771
772
773
774
775
776 word6 idwtag, delta;
777 word24 Yi = (word24) -1;
778
779 switch (Td)
780 {
781
782 case SPEC_ITP:
783
784 case SPEC_ITS:
785 {
786 doFault(FAULT_IPR, fst_ill_mod, "ITx in IT_MOD)");
787 }
788
789
790 case 2:
791 {
792 sim_debug (DBG_ADDRMOD, & cpu_dev,
793 "IT_MOD(): illegal procedure, illegal modifier, "
794 "fault Td=%o\n", Td);
795 doFault (FAULT_IPR, fst_ill_mod,
796 "IT_MOD(): illegal procedure, illegal modifier, "
797 "fault");
798 }
799
800
801 case IT_F1:
802 {
803 doFault(FAULT_F1, fst_zero, "IT_MOD: IT_F1");
804 }
805
806
807 case IT_F2:
808 {
809 doFault(FAULT_F2, fst_zero, "IT_MOD: IT_F2 (2)");
810 }
811
812
813 case IT_F3:
814 {
815 doFault(FAULT_F3, fst_zero, "IT_MOD: IT_F3");
816 }
817
818
819 case IT_CI:
820
821 case IT_SC:
822
823 case IT_SCR:
824 {
825
826
827
828
829
830
831 sim_debug (DBG_ADDRMOD, & cpu_dev,
832 "IT_MOD CI/SC/SCR reading indirect word from %06o\n",
833 cpu.TPR.CA);
834
835
836
837
838
839 word36 indword;
840 word18 indaddr = cpu.TPR.CA;
841 ReadAPUDataRead (cpup, indaddr, & indword);
842 #if defined(LOCKLESS)
843 word24 phys_address = cpu.iefpFinalAddress;
844 #endif
845
846 sim_debug (DBG_ADDRMOD, & cpu_dev,
847 "IT_MOD CI/SC/SCR indword=%012"PRIo64"\n", indword);
848
849
850
851
852
853 Yi = GET_ADDR (indword);
854 word6 sz = GET_TB (GET_TAG (indword));
855 word3 os = GET_CF (GET_TAG (indword));
856 word12 tally = GET_TALLY (indword);
857
858 sim_debug (DBG_ADDRMOD, & cpu_dev,
859 "IT_MOD CI/SC/SCR size=%o offset=%o Yi=%06o\n",
860 sz, os, Yi);
861
862 if (sz == TB6 && os > 5)
863
864 doFault (FAULT_IPR, fst_ill_mod,
865 "co size == TB6 && offset > 5");
866
867 if (sz == TB9 && os > 3)
868
869 doFault (FAULT_IPR, fst_ill_mod,
870 "co size == TB9 && offset > 3");
871
872
873
874 cpu.TPR.CA = Yi;
875 cpu.ou.character_address = Yi;
876 cpu.ou.characterOperandSize = sz;
877 cpu.ou.characterOperandOffset = os;
878
879
880
881 if (Td == IT_SCR)
882 {
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902 if (os == 0)
903 {
904 if (sz == TB6)
905 os = 5;
906 else
907 os = 3;
908 Yi -= 1;
909 Yi &= MASK18;
910 }
911 else
912 {
913 os -= 1;
914 }
915
916 CPT (cpt2L, 5);
917 tally ++;
918 tally &= 07777;
919
920
921
922 cpu.TPR.CA = Yi;
923 cpu.ou.character_address = Yi;
924 cpu.ou.characterOperandSize = sz;
925 cpu.ou.characterOperandOffset = os;
926 }
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941 cpu.cu.pot = 1;
942
943 #if defined(LOCKLESSXXX)
944
945 Read (cpu.TPR.CA, & cpu.ou.character_data, (i->info->flags & RMW) == \
946 STORE_OPERAND ? OPERAND_RMW : OPERAND_READ);
947 #else
948 ReadOperandRead (cpup, cpu.TPR.CA, & cpu.ou.character_data);
949 #endif
950 #if defined(LOCKLESS)
951 cpu.char_word_address = cpu.iefpFinalAddress;
952 #endif
953
954 sim_debug (DBG_ADDRMOD, & cpu_dev,
955 "IT_MOD CI/SC/SCR data=%012"PRIo64"\n",
956 cpu.ou.character_data);
957
958 cpu.cu.pot = 0;
959
960 if (Td == IT_SC)
961 {
962
963
964
965
966
967
968
969
970
971
972
973
974 os ++;
975
976 if (((sz == TB6) && (os > 5)) ||
977 ((sz == TB9) && (os > 3)))
978 {
979 os = 0;
980 Yi += 1;
981 Yi &= MASK18;
982 }
983 CPT (cpt2L, 6);
984 tally --;
985 tally &= 07777;
986 }
987
988 if (Td == IT_SC || Td == IT_SCR)
989 {
990 sim_debug (DBG_ADDRMOD, & cpu_dev,
991 "update IT tally now %o\n", tally);
992
993
994
995
996
997
998 #if defined(LOCKLESS)
999 word36 indword_new;
1000 core_read_lock(cpup, phys_address, &indword_new, __func__);
1001 if (indword_new != indword)
1002 sim_warn("indword changed from %llo to %llo\n",
1003 (long long unsigned int)indword,
1004 (long long unsigned int)indword_new);
1005 #endif
1006 putbits36_18 (& indword, 0, Yi);
1007 putbits36_12 (& indword, 18, tally);
1008 putbits36_3 (& indword, 33, os);
1009 #if defined(LOCKLESS)
1010 core_write_unlock(cpup, phys_address, indword, __func__);
1011 #else
1012 WriteAPUDataStore (cpup, indaddr, indword);
1013 #endif
1014
1015 SC_I_TALLY (tally == 0);
1016
1017 sim_debug (DBG_ADDRMOD, & cpu_dev,
1018 "update IT wrote tally word %012"PRIo64
1019 " to %06o\n",
1020 indword, cpu.TPR.CA);
1021 }
1022
1023
1024
1025 cpu.TPR.CA = cpu.ou.character_address;
1026 return;
1027 }
1028
1029 case IT_I:
1030 {
1031 sim_debug (DBG_ADDRMOD, & cpu_dev,
1032 "IT_MOD(IT_I): reading indirect word from %06o\n",
1033 cpu.TPR.CA);
1034
1035
1036 ReadIndirect (cpup);
1037
1038 sim_debug (DBG_ADDRMOD, & cpu_dev,
1039 "IT_MOD(IT_I): indword=%012"PRIo64"\n",
1040 cpu.itxPair[0]);
1041
1042 cpu.TPR.CA = GET_ADDR (cpu.itxPair[0]);
1043 updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N));
1044 return;
1045 }
1046
1047 case IT_AD:
1048 {
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059 sim_debug (DBG_ADDRMOD, & cpu_dev,
1060 "IT_MOD(IT_AD): reading indirect word from %06o\n",
1061 cpu.TPR.CA);
1062
1063 #if defined(THREADZ)
1064 lock_rmw ();
1065 #endif
1066
1067 word18 saveCA = cpu.TPR.CA;
1068 word36 indword;
1069 ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword);
1070
1071 cpu.AM_tally = GET_TALLY (indword);
1072 delta = GET_DELTA (indword);
1073 Yi = GETHI (indword);
1074
1075 sim_debug (DBG_ADDRMOD, & cpu_dev,
1076 "IT_MOD(IT_AD): indword=%012"PRIo64"\n",
1077 indword);
1078 sim_debug (DBG_ADDRMOD, & cpu_dev,
1079 "IT_MOD(IT_AD): address:%06o tally:%04o "
1080 "delta:%03o\n",
1081 Yi, cpu.AM_tally, delta);
1082
1083 cpu.TPR.CA = Yi;
1084 word18 computedAddress = cpu.TPR.CA;
1085
1086 Yi += delta;
1087 Yi &= MASK18;
1088
1089 cpu.AM_tally -= 1;
1090 cpu.AM_tally &= 07777;
1091
1092
1093
1094 SC_I_TALLY (cpu.AM_tally == 0);
1095 indword = (word36) (((word36) Yi << 18) |
1096 (((word36) cpu.AM_tally & 07777) << 6) |
1097 delta);
1098 #if defined(LOCKLESS)
1099 core_write_unlock(cpup, cpu.iefpFinalAddress, indword, __func__);
1100 #else
1101 WriteAPUDataStore (cpup, saveCA, indword);
1102 #endif
1103
1104 #if defined(THREADZ)
1105 unlock_rmw ();
1106 #endif
1107
1108 sim_debug (DBG_ADDRMOD, & cpu_dev,
1109 "IT_MOD(IT_AD): wrote tally word %012"PRIo64
1110 " to %06o\n",
1111 indword, saveCA);
1112
1113 cpu.TPR.CA = computedAddress;
1114 updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N));
1115 return;
1116 }
1117
1118 case IT_SD:
1119 {
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130 #if defined(THREADZ)
1131 lock_rmw ();
1132 #endif
1133
1134 word18 saveCA = cpu.TPR.CA;
1135 word36 indword;
1136 ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword);
1137
1138 sim_debug (DBG_ADDRMOD, & cpu_dev,
1139 "IT_MOD(IT_SD): reading indirect word from %06o\n",
1140 cpu.TPR.CA);
1141 cpu.AM_tally = GET_TALLY (indword);
1142 delta = GET_DELTA (indword);
1143 Yi = GETHI (indword);
1144
1145 sim_debug (DBG_ADDRMOD, & cpu_dev,
1146 "IT_MOD(IT_SD): indword=%012"PRIo64"\n",
1147 indword);
1148 sim_debug (DBG_ADDRMOD, & cpu_dev,
1149 "IT_MOD(IT_SD): address:%06o tally:%04o "
1150 "delta:%03o\n",
1151 Yi, cpu.AM_tally, delta);
1152
1153 Yi -= delta;
1154 Yi &= MASK18;
1155 cpu.TPR.CA = Yi;
1156
1157 cpu.AM_tally += 1;
1158 cpu.AM_tally &= 07777;
1159 if (cpu.AM_tally == 0)
1160 SET_I_TALLY;
1161
1162
1163 indword = (word36) (((word36) Yi << 18) |
1164 (((word36) cpu.AM_tally & 07777) << 6) |
1165 delta);
1166 #if defined(LOCKLESS)
1167 core_write_unlock(cpup, cpu.iefpFinalAddress, indword, __func__);
1168 #else
1169 WriteAPUDataStore (cpup, saveCA, indword);
1170 #endif
1171
1172 #if defined(THREADZ)
1173 unlock_rmw ();
1174 #endif
1175
1176 sim_debug (DBG_ADDRMOD, & cpu_dev,
1177 "IT_MOD(IT_SD): wrote tally word %012"PRIo64
1178 " to %06o\n",
1179 indword, saveCA);
1180
1181 cpu.TPR.CA = Yi;
1182 updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N));
1183 return;
1184 }
1185
1186 case IT_DI:
1187 {
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197 sim_debug (DBG_ADDRMOD, & cpu_dev,
1198 "IT_MOD(IT_DI): reading indirect word from %06o\n",
1199 cpu.TPR.CA);
1200
1201 #if defined(THREADZ)
1202 lock_rmw ();
1203 #endif
1204
1205 word18 saveCA = cpu.TPR.CA;
1206 word36 indword;
1207 ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword);
1208
1209 Yi = GETHI (indword);
1210 cpu.AM_tally = GET_TALLY (indword);
1211 word6 junk = GET_TAG (indword);
1212
1213 sim_debug (DBG_ADDRMOD, & cpu_dev,
1214 "IT_MOD(IT_DI): indword=%012"PRIo64"\n",
1215 indword);
1216 sim_debug (DBG_ADDRMOD, & cpu_dev,
1217 "IT_MOD(IT_DI): address:%06o tally:%04o\n",
1218 Yi, cpu.AM_tally);
1219
1220 Yi -= 1;
1221 Yi &= MASK18;
1222 cpu.TPR.CA = Yi;
1223
1224 cpu.AM_tally += 1;
1225 cpu.AM_tally &= 07777;
1226 SC_I_TALLY (cpu.AM_tally == 0);
1227
1228
1229
1230 indword = (word36) (((word36) cpu.TPR.CA << 18) |
1231 ((word36) cpu.AM_tally << 6) |
1232 junk);
1233
1234 sim_debug (DBG_ADDRMOD, & cpu_dev,
1235 "IT_MOD(IT_DI): writing indword=%012"PRIo64" to "
1236 "addr %06o\n",
1237 indword, saveCA);
1238
1239 #if defined(LOCKLESS)
1240 core_write_unlock(cpup, cpu.iefpFinalAddress, indword, __func__);
1241 #else
1242 WriteAPUDataStore (cpup, saveCA, indword);
1243 #endif
1244
1245 #if defined(THREADZ)
1246 unlock_rmw ();
1247 #endif
1248 cpu.TPR.CA = Yi;
1249 updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N));
1250 return;
1251 }
1252
1253 case IT_ID:
1254 {
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264 word18 saveCA = cpu.TPR.CA;
1265
1266 sim_debug (DBG_ADDRMOD, & cpu_dev,
1267 "IT_MOD(IT_ID): fetching indirect word from %06o\n",
1268 cpu.TPR.CA);
1269
1270 #if defined(THREADZ)
1271 lock_rmw ();
1272 #endif
1273
1274 word36 indword;
1275 ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword);
1276
1277 Yi = GETHI (indword);
1278 cpu.AM_tally = GET_TALLY (indword);
1279
1280 word6 junk = GET_TAG (indword);
1281 sim_debug (DBG_ADDRMOD, & cpu_dev,
1282 "IT_MOD(IT_ID): indword=%012"PRIo64
1283 " Yi=%06o tally=%04o\n",
1284 indword, Yi, cpu.AM_tally);
1285
1286 cpu.TPR.CA = Yi;
1287 word18 computedAddress = cpu.TPR.CA;
1288
1289 Yi += 1;
1290 Yi &= MASK18;
1291
1292 cpu.AM_tally -= 1;
1293 cpu.AM_tally &= 07777;
1294
1295
1296
1297
1298 SC_I_TALLY (cpu.AM_tally == 0);
1299
1300
1301 indword = (word36) (((word36) Yi << 18) |
1302 ((word36) cpu.AM_tally << 6) |
1303 junk);
1304
1305 sim_debug (DBG_ADDRMOD, & cpu_dev,
1306 "IT_MOD(IT_ID): writing indword=%012"PRIo64" to "
1307 "addr %06o\n",
1308 indword, saveCA);
1309
1310 #if defined(LOCKLESS)
1311 core_write_unlock(cpup, cpu.iefpFinalAddress, indword, __func__);
1312 #else
1313 WriteAPUDataStore (cpup, saveCA, indword);
1314 #endif
1315
1316 #if defined(THREADZ)
1317 unlock_rmw ();
1318 #endif
1319
1320 cpu.TPR.CA = computedAddress;
1321 updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N));
1322 return;
1323 }
1324
1325
1326 case IT_DIC:
1327 {
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348 sim_debug (DBG_ADDRMOD, & cpu_dev,
1349 "IT_MOD(IT_DIC): fetching indirect word from %06o\n",
1350 cpu.TPR.CA);
1351
1352 #if defined(THREADZ)
1353 lock_rmw ();
1354 #endif
1355
1356 word18 saveCA = cpu.TPR.CA;
1357 word36 indword;
1358 ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword);
1359
1360 cpu.cu.pot = 0;
1361
1362 Yi = GETHI (indword);
1363 cpu.AM_tally = GET_TALLY (indword);
1364 idwtag = GET_TAG (indword);
1365
1366 sim_debug (DBG_ADDRMOD, & cpu_dev,
1367 "IT_MOD(IT_DIC): indword=%012"PRIo64" Yi=%06o "
1368 "tally=%04o idwtag=%02o\n",
1369 indword, Yi, cpu.AM_tally, idwtag);
1370
1371 word24 YiSafe2 = Yi;
1372
1373 Yi -= 1;
1374 Yi &= MASK18;
1375
1376 cpu.AM_tally += 1;
1377 cpu.AM_tally &= 07777;
1378
1379
1380
1381
1382
1383
1384
1385 indword = (word36) (((word36) Yi << 18) |
1386 ((word36) cpu.AM_tally << 6) | idwtag);
1387
1388 sim_debug (DBG_ADDRMOD, & cpu_dev,
1389 "IT_MOD(IT_DIC): writing indword=%012"PRIo64" to "
1390 "addr %06o\n", indword, saveCA);
1391
1392 #if defined(LOCKLESS)
1393 core_write_unlock(cpup, cpu.iefpFinalAddress, indword, __func__);
1394 #else
1395 WriteAPUDataStore (cpup, saveCA, indword);
1396 #endif
1397
1398 #if defined(THREADZ)
1399 unlock_rmw ();
1400 #endif
1401
1402
1403
1404
1405
1406
1407
1408
1409 cpu.TPR.CA = Yi;
1410
1411 sim_debug (DBG_ADDRMOD, & cpu_dev,
1412 "IT_MOD(IT_DIC): new CT_HOLD %02o new TAG %02o\n",
1413 cpu.rTAG, idwtag);
1414 cpu.cu.CT_HOLD = cpu.rTAG;
1415 cpu.rTAG = idwtag;
1416
1417 Tm = GET_TM (cpu.rTAG);
1418 if (Tm == TM_RI || Tm == TM_R)
1419 {
1420 if (GET_TD (cpu.rTAG) != 0)
1421 {
1422 doFault (FAULT_IPR, fst_ill_mod,
1423 "DIC Incorrect address modifier");
1424 }
1425 }
1426
1427
1428
1429 SC_I_TALLY (cpu.AM_tally == 0);
1430 if (cpu.tweaks.isolts_mode)
1431 updateIWB (cpup, YiSafe2, cpu.rTAG);
1432 else
1433 updateIWB (cpup, cpu.TPR.CA, cpu.rTAG);
1434 goto startCA;
1435 }
1436
1437
1438 case IT_IDC:
1439 {
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460 sim_debug (DBG_ADDRMOD, & cpu_dev,
1461 "IT_MOD(IT_IDC): fetching indirect word from %06o\n",
1462 cpu.TPR.CA);
1463
1464 #if defined(THREADZ)
1465 lock_rmw ();
1466 #endif
1467
1468 word18 saveCA = cpu.TPR.CA;
1469 word36 indword;
1470 ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword);
1471
1472 cpu.cu.pot = 0;
1473
1474 Yi = GETHI (indword);
1475 cpu.AM_tally = GET_TALLY (indword);
1476 idwtag = GET_TAG (indword);
1477
1478 sim_debug (DBG_ADDRMOD, & cpu_dev,
1479 "IT_MOD(IT_IDC): indword=%012"PRIo64" Yi=%06o "
1480 "tally=%04o idwtag=%02o\n",
1481 indword, Yi, cpu.AM_tally, idwtag);
1482
1483 word24 YiSafe = Yi;
1484
1485 Yi += 1;
1486 Yi &= MASK18;
1487
1488 cpu.AM_tally -= 1;
1489 cpu.AM_tally &= 07777;
1490
1491
1492
1493
1494
1495 indword = (word36) (((word36) Yi << 18) |
1496 ((word36) cpu.AM_tally << 6) |
1497 idwtag);
1498
1499 sim_debug (DBG_ADDRMOD, & cpu_dev,
1500 "IT_MOD(IT_IDC): writing indword=%012"PRIo64""
1501 " to addr %06o\n",
1502 indword, saveCA);
1503
1504 #if defined(LOCKLESS)
1505 core_write_unlock(cpup, cpu.iefpFinalAddress, indword, __func__);
1506 #else
1507 WriteAPUDataStore (cpup, saveCA, indword);
1508 #endif
1509
1510 #if defined(THREADZ)
1511 unlock_rmw ();
1512 #endif
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523 cpu.TPR.CA = YiSafe;
1524
1525 sim_debug (DBG_ADDRMOD, & cpu_dev,
1526 "IT_MOD(IT_IDC): new CT_HOLD %02o new TAG %02o\n",
1527 cpu.rTAG, idwtag);
1528 cpu.cu.CT_HOLD = cpu.rTAG;
1529 cpu.rTAG = idwtag;
1530
1531 Tm = GET_TM (cpu.rTAG);
1532 if (Tm == TM_RI || Tm == TM_R)
1533 {
1534 if (GET_TD (cpu.rTAG) != 0)
1535 {
1536 doFault (FAULT_IPR, fst_ill_mod,
1537 "IDC Incorrect address modifier");
1538 }
1539 }
1540
1541
1542
1543 SC_I_TALLY (cpu.AM_tally == 0);
1544 updateIWB (cpup, cpu.TPR.CA, cpu.rTAG);
1545
1546 goto startCA;
1547 }
1548 }
1549 sim_printf ("IT_MOD/Td how did we get here?\n");
1550 return;
1551 }
1552 }