IC 280 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 347 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 298 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 300 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 469 src/dps8/doAppendCycleIndirectWordFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 635 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.IC = cpu.TPR.CA; IC 658 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 351 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 742 src/dps8/doAppendCycleOperandRead.h cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; IC 755 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; IC 802 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; IC 813 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 303 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 366 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.IC = cpu.TPR.CA; IC 390 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 84 src/dps8/dps8_addrmods.c return cpu.PPR.IC; IC 2063 src/dps8/dps8_append.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; IC 2112 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; IC 2166 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; IC 2212 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 941 src/dps8/dps8_cpu.c cpu.PPR.IC = 0; IC 1635 src/dps8/dps8_cpu.c { ORDATA (IC, dummy_IC, VASIZE), 0, 0, 0 }, IC 1637 src/dps8/dps8_cpu.c { ORDATA (IC, cpus[0].PPR.IC, VASIZE), 0, 0, 0 }, IC 1771 src/dps8/dps8_cpu.c sim_brk_test ((cpu.PPR.IC & 0777777) | IC 2152 src/dps8/dps8_cpu.c cpus [0].PPR.IC = dummy_IC; IC 2470 src/dps8/dps8_cpu.c get_BAR_address (cpup, cpu.PPR.IC); IC 2493 src/dps8/dps8_cpu.c (cpu.PPR.IC & 1) == 0 && IC 2510 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 1) IC 2663 src/dps8/dps8_cpu.c fetchInstruction (cpup, cpu.PPR.IC); IC 2682 src/dps8/dps8_cpu.c stall_points[i].offset && stall_points[i].offset == cpu.PPR.IC) IC 2958 src/dps8/dps8_cpu.c (cpu.cu.rd && (cpu.PPR.IC & 1)) || IC 2963 src/dps8/dps8_cpu.c -- cpu.PPR.IC; IC 2984 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 2985 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3031 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3033 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3056 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 0 && IC 3060 src/dps8/dps8_cpu.c (cpu.PPR.IC & ~3u) != (cpu.last_write & ~3u)) IC 3062 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3069 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3071 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3086 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3087 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3300 src/dps8/dps8_cpu.c dummy_IC = cpu.PPR.IC; IC 3516 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); IC 3523 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, addr, IC 3557 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3600 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3624 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3640 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3682 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3720 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); IC 3727 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3738 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3757 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); IC 3764 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3775 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3816 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3839 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 4353 src/dps8/dps8_cpu.c putbits36_18 (& w1, 54 - 36, cpu.PPR.IC); IC 97 src/dps8/dps8_cpu.h word18 IC; // The word offset from the origin of the procedure segment IC 1029 src/dps8/dps8_cpu.h #define USE_IRODD (cpu.cu.rd && ((cpu. PPR.IC & 1) != 0)) IC 1651 src/dps8/dps8_cpu.h word18 IC; IC 347 src/dps8/dps8_eis.c return cpu.PPR.IC; IC 444 src/dps8/dps8_eis.c return cpu.PPR.IC; IC 519 src/dps8/dps8_eis.c return cpu.PPR.IC; IC 380 src/dps8/dps8_faults.c sim_printf (" TRO PSR:IC %05o:%06o\r\n", cpu.PPR.PSR, cpu.PPR.IC); IC 385 src/dps8/dps8_faults.c sim_printf (" ACV %012llo PSR:IC %05o:%06o\r\n", subFault.bits, cpu.PPR.PSR, cpu.PPR.IC); IC 417 src/dps8/dps8_faults.c fault_ic = cpu . PPR.IC; IC 689 src/dps8/dps8_faults.c cpu.PPR.IC); IC 835 src/dps8/dps8_faults.c cpu.PPR.IC); IC 135 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) IC 210 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 281 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 352 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 422 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 494 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 564 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 1154 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) IC 1279 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) IC 312 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; IC 318 src/dps8/dps8_ins.c cpu.PPR.IC = cpu.TPR.CA; IC 323 src/dps8/dps8_ins.c __func__, cpu.PPR.PSR, cpu.PPR.IC); IC 324 src/dps8/dps8_ins.c if (cpu.PPR.IC & 1) IC 437 src/dps8/dps8_ins.c putbits36_18 (& words[4], 0, cpu.PPR.IC); IC 606 src/dps8/dps8_ins.c cpu.cu_data.IC = cpu.PPR.IC; IC 716 src/dps8/dps8_ins.c cpu.PPR.IC = getbits36_18 (words[4], 0); IC 1158 src/dps8/dps8_ins.c if (cpu.cu.rd && ((cpu.PPR.IC & 1) != 0)) IC 1194 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) // Even IC 1222 src/dps8/dps8_ins.c char * where = lookup_address (cpu.PPR.PSR, cpu.PPR.IC, & compname, IC 1232 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); IC 1236 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o %s\n", cpu.PPR.IC, where); IC 1245 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); IC 1250 src/dps8/dps8_ins.c cpu.PPR.PSR, cpu.PPR.IC, where); IC 1264 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1281 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1303 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1321 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1373 src/dps8/dps8_ins.c trk (cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IWB_IRODD); IC 1536 src/dps8/dps8_ins.c if (!cpu.cu.xde && cpu.cu.xdo /* odd instr being executed */ && !(cpu.PPR.IC & 1)) IC 1543 src/dps8/dps8_ins.c if (opcode == 0560 && !opcodeX && cpu.cu.xde && !(cpu.PPR.IC & 1)) IC 1744 src/dps8/dps8_ins.c if (n_dbgevents && (dbgevt = (dbgevent_lookup (cpu.PPR.PSR, cpu.PPR.IC))) >= 0) { IC 1837 src/dps8/dps8_ins.c cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], IC 1849 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); IC 1920 src/dps8/dps8_ins.c word18 saveIC = cpu.PPR.IC; IC 1922 src/dps8/dps8_ins.c ReadInstructionFetch (cpup, cpu.PPR.IC + 1 + n, & cpu.currentEISinstruction.op[n]); IC 1923 src/dps8/dps8_ins.c cpu.PPR.IC = saveIC; IC 2090 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); IC 2321 src/dps8/dps8_ins.c cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 2992 src/dps8/dps8_ins.c word18 ret = (cpu.PPR.IC + 1) & MASK18; IC 3932 src/dps8/dps8_ins.c SETHI (cpu.CY, (cpu.PPR.IC + 1) & MASK18); IC 3945 src/dps8/dps8_ins.c cpu.CY = ((word36) ((cpu.PPR.IC + 2) & MASK18)) << 18; IC 4016 src/dps8/dps8_ins.c putbits36_18 (& cpu.Ypair[1], 0, cpu.PPR.IC + 2); IC 4026 src/dps8/dps8_ins.c putbits36_18 (& cpu.Ypair[1], 0, cpu.cu_data.IC + 2); IC 6478 src/dps8/dps8_ins.c cpu.PPR.IC = GETHI (cpu.CY); IC 7265 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) IC 7568 src/dps8/dps8_ins.c sim_printf (" ldt %d PSR:IC %05o:%06o\r\n", cpu.rTR, cpu.PPR.PSR, cpu.PPR.IC); IC 7619 src/dps8/dps8_ins.c sim_printf (" RALR set to %o PSR:IC %05o:%06o\r\n", cpu.rRALR, cpu.PPR.PSR, cpu.PPR.IC); IC 8685 src/dps8/dps8_ins.c " no events in queue\n", cpu.PPR.IC); IC 8702 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 0430 && cpu.PPR.IC == 012) IC 8732 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 034 && cpu.PPR.IC == 03535) IC 9765 src/dps8/dps8_ins.c (cpu.Yblock8[0]>>18)&MASK15, (cpu.Yblock8[4]>>18)&MASK18, cpu.PPR.PSR, cpu.PPR.IC); IC 3513 src/dps8/dps8_iom.c __func__, iomChar (iom_unit_idx), cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC); IC 2726 src/dps8/dps8_sys.c word18 icOffset = cpu.PPR.IC; IC 4057 src/dps8/dps8_sys.c { "cpus[].PPR.IC", SYM_STRUCT_OFFSET, SYM_UINT32_18, offsetof (struct ppr_s, IC) }, IC 171 src/dps8/hdbg.c if (filter && hdbgSegNum > 0 && blacklist[cpu.PPR.IC]) \ IC 194 src/dps8/hdbg.c hevents[p].trace.ic = cpu.PPR.IC; IC 663 src/dps8/panelScraper.c SETL (bank_e, 0+3, cpu.PPR.IC, 18); IC 923 src/dps8/panelScraper.c SETL (bank_g, 0, cpu.PPR.IC, 18); IC 957 src/dps8/panelScraper.c SETL (bank_j, 3, cpu.PPR.IC, 18);