rd 482 src/dps8/dps8_addrmods.c if (cpu.cu.rpt || cpu.cu.rd | cpu.cu.rl) rd 529 src/dps8/dps8_addrmods.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) rd 584 src/dps8/dps8_addrmods.c if (!(cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) rd 617 src/dps8/dps8_addrmods.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) rd 2492 src/dps8/dps8_cpu.c cpu.cu.rpt | cpu.cu.rd | cpu.cu.rl)) rd 2960 src/dps8/dps8_cpu.c (cpu.cu.rd && (cpu.PPR.IC & 1)) || rd 2964 src/dps8/dps8_cpu.c if (cpu.cu.rd) rd 3060 src/dps8/dps8_cpu.c !cpu.cu.repeat_first && !cpu.cu.rpt && !cpu.cu.rd && !cpu.cu.rl && rd 1004 src/dps8/dps8_cpu.h word1 rd; // 20 RD Execute an Repeat Double (rpd) instruction rd 1029 src/dps8/dps8_cpu.h #define USE_IRODD (cpu.cu.rd && ((cpu. PPR.IC & 1) != 0)) rd 482 src/dps8/dps8_ins.c putbits36 (& words[5], 20, 1, cpu.cu.rd); rd 620 src/dps8/dps8_ins.c cpu.cu.rd = false; rd 724 src/dps8/dps8_ins.c cpu.cu.rd = getbits36_1 (words[5], 20); rd 1158 src/dps8/dps8_ins.c if (cpu.cu.rd && ((cpu.PPR.IC & 1) != 0)) rd 1166 src/dps8/dps8_ins.c else if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) rd 1341 src/dps8/dps8_ins.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) rd 1357 src/dps8/dps8_ins.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) rd 1554 src/dps8/dps8_ins.c if (unlikely (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) { rd 1588 src/dps8/dps8_ins.c if (unlikely (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) { rd 1776 src/dps8/dps8_ins.c if (unlikely (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) { rd 1837 src/dps8/dps8_ins.c cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], rd 1853 src/dps8/dps8_ins.c if (cpu.cu.rpt || (cpu.cu.rd && icOdd) || cpu.cu.rl) rd 1860 src/dps8/dps8_ins.c (cpu.cu.rd && icEven) || // rpd & even rd 1861 src/dps8/dps8_ins.c (cpu.cu.rd && icOdd) || // rpd & odd rd 2100 src/dps8/dps8_ins.c if (rf && cpu.cu.rd && icEven) rd 2103 src/dps8/dps8_ins.c if (unlikely ((! rf) && (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl))) { rd 2109 src/dps8/dps8_ins.c if (cpu.cu.rpt || cpu.cu.rd) { rd 2117 src/dps8/dps8_ins.c cpu.cu.repeat_first, rf, cpu.cu.rpt, cpu.cu.rd, icOdd, cpu.rX[0], rptA, rptB); rd 2134 src/dps8/dps8_ins.c if (cpu.cu.rd && icOdd && rptA) { // rpd, even instruction rd 2146 src/dps8/dps8_ins.c if (cpu.cu.rd && icOdd && rptB) { // rpdb, odd instruction rd 2174 src/dps8/dps8_ins.c flt = (cpu.cu.rl || cpu.cu.rpt || cpu.cu.rd) && cpu.dlyFlt; // L68 rd 2186 src/dps8/dps8_ins.c if (cpu.cu.rpt || (cpu.cu.rd && icOdd) || cpu.cu.rl) { rd 2261 src/dps8/dps8_ins.c cpu.cu.rd = false; rd 2273 src/dps8/dps8_ins.c cpu.cu.rd = false; rd 2349 src/dps8/dps8_ins.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) rd 7277 src/dps8/dps8_ins.c cpu.cu.rd = 1; rd 465 src/dps8/panelScraper.c SETL1 (bank_a, 20+3, cpu.cu.rd); rd 973 src/dps8/panelScraper.c SETL (bank_j, 37, cpu.cu.rd, 1); rd 1055 src/simh/sim_sock.c int sim_check_conn (SOCKET sock, int rd) rd 1073 src/simh/sim_sock.c if (rd) rd 110 src/simh/sim_sock.h int sim_check_conn (SOCKET sock, int rd);