This source file includes following definitions.
- Read
- ReadAPUDataRead
- ReadOperandRead
- ReadOperandRMW
- ReadAPUDataRMW
- ReadInstructionFetch
- ReadIndirectWordFetch
- Read2
- Read2OperandRead
- Read2OperandRMW
- Read2InstructionFetch
- Read2RTCDOperandFetch
- Read2IndirectWordFetch
- Read8
- Read16
- ReadPage
- Write
- WriteAPUDataStore
- WriteOperandStore
- Write2
- Write2OperandStore
- Write1
- Write8
- Write16
- Write32
- WritePage
- ReadIndirect
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34 #include "dps8.h"
35 #include "dps8_sys.h"
36 #include "dps8_iom.h"
37 #include "dps8_cable.h"
38 #include "dps8_cpu.h"
39 #include "dps8_faults.h"
40 #include "dps8_scu.h"
41 #include "dps8_append.h"
42 #include "dps8_iefp.h"
43 #include "dps8_addrmods.h"
44 #include "dps8_utils.h"
45
46 #define DBG_CTR cpu.cycleCnt
47
48
49
50 #if defined(OLDAPP)
51 void Read (cpu_state_t * cpup, word18 address, word36 * result, processor_cycle_type cyctyp)
52 {
53 cpu.TPR.CA = cpu.iefpFinalAddress = address;
54 bool isBAR = get_bar_mode (cpup);
55
56
57 if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29))
58 {
59 goto B29;
60 }
61
62 switch (get_addr_mode (cpup))
63 {
64 case ABSOLUTE_mode:
65 {
66 if (isBAR)
67 {
68 set_apu_status (cpup, apuStatus_FABS);
69 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
70 fauxDoAppendCycle (cpup, cyctyp);
71 # if defined(LOCKLESS)
72 if (cyctyp == OPERAND_RMW || cyctyp == APU_DATA_RMW)
73 core_read_lock (cpup, cpu.iefpFinalAddress, result, __func__);
74 else
75 core_read (cpup, cpu.iefpFinalAddress, result, __func__);
76 # else
77 core_read (cpup, cpu.iefpFinalAddress, result, __func__);
78 # endif
79 sim_debug (DBG_FINAL, & cpu_dev,
80 "Read (Actual) Read: bar address=%08o "
81 "readData=%012"PRIo64"\n", address, *result);
82 # if defined(TESTING)
83 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read ABS BAR");
84 HDBGMRead (cpu.iefpFinalAddress, * result, "Read ABS BAR");
85 # endif
86 return;
87 }
88 else
89 {
90 set_apu_status (cpup, apuStatus_FABS);
91 fauxDoAppendCycle (cpup, cyctyp);
92 # if defined(LOCKLESS)
93 if (cyctyp == OPERAND_RMW || cyctyp == APU_DATA_RMW)
94 core_read_lock (cpup, address, result, __func__);
95 else
96 core_read (cpup, address, result, __func__);
97 # else
98 core_read (cpup, address, result, __func__);
99 # endif
100 sim_debug (DBG_FINAL, & cpu_dev,
101 "Read (Actual) Read: abs address=%08o "
102 "readData=%012"PRIo64"\n", address, *result);
103 # if defined(TESTING)
104 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read ABS");
105 HDBGMRead (address, * result, "Read ABS");
106 # endif
107 return;
108 }
109 }
110
111 case APPEND_mode:
112 {
113 B29:;
114 if (isBAR)
115 {
116 cpu.TPR.CA = get_BAR_address (address);
117 cpu.TPR.TSR = cpu.PPR.PSR;
118 cpu.TPR.TRR = cpu.PPR.PRR;
119 cpu.iefpFinalAddress = do_append_cycle (cpup, cyctyp, result, 1);
120 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
121 "Read (Actual) Read: bar iefpFinalAddress=%08o "
122 "readData=%012"PRIo64"\n",
123 cpu.iefpFinalAddress, * result);
124 # if defined(TESTING)
125 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read BAR");
126 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read BAR");
127 # endif
128
129 return;
130 }
131 else
132 {
133 cpu.iefpFinalAddress = do_append_cycle (cpup, cyctyp, result, 1);
134
135 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
136 {
137 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
138 "Read (Actual) Read: iefpFinalAddress=%08o "
139 "readData=%012"PRIo64"\n",
140 cpu.iefpFinalAddress, * result);
141 # if defined(TESTING)
142 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read");
143 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read");
144 # endif
145 }
146 }
147 return;
148 }
149 }
150 return ;
151 }
152 #endif
153
154 #if !defined(OLDAPP)
155 void ReadAPUDataRead (cpu_state_t * cpup, word18 address, word36 * result) {
156 cpu.TPR.CA = cpu.iefpFinalAddress = address;
157 bool isBAR = get_bar_mode (cpup);
158
159 if (cpu.cu.XSF || cpu.currentInstruction.b29)
160 goto B29;
161
162 switch (get_addr_mode (cpup)) {
163 case ABSOLUTE_mode: {
164 if (isBAR) {
165 set_apu_status (cpup, apuStatus_FABS);
166 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
167 fauxDoAppendCycle (cpup, APU_DATA_READ);
168 core_read (cpup, cpu.iefpFinalAddress, result, __func__);
169 sim_debug (DBG_FINAL, & cpu_dev,
170 "ReadAPUDataRead (Actual) Read: bar address=%08o readData=%012"PRIo64"\n",
171 address, *result);
172 # if defined(TESTING)
173 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadAPUDataRead ABS BAR");
174 HDBGMRead (cpu.iefpFinalAddress, * result, "ReadAPUDataRead ABS BAR");
175 # endif
176 return;
177 } else {
178 set_apu_status (cpup, apuStatus_FABS);
179 fauxDoAppendCycle (cpup, APU_DATA_READ);
180 core_read (cpup, address, result, __func__);
181 sim_debug (DBG_FINAL, & cpu_dev,
182 "ReadAPUDataRead (Actual) Read: abs address=%08o readData=%012"PRIo64"\n",
183 address, *result);
184 # if defined(TESTING)
185 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadAPUDataRead ABS");
186 HDBGMRead (address, * result, "ReadAPUDataRead ABS");
187 # endif
188 return;
189 }
190 }
191
192 case APPEND_mode: {
193 B29:;
194 if (isBAR) {
195 cpu.TPR.CA = get_BAR_address (cpup, address);
196 cpu.TPR.TSR = cpu.PPR.PSR;
197 cpu.TPR.TRR = cpu.PPR.PRR;
198 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (cpup, result, 1);
199 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
200 "ReadAPUDataRead (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n",
201 cpu.iefpFinalAddress, * result);
202 # if defined(TESTING)
203 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRead BAR");
204 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead BAR");
205 # endif
206 return;
207 } else {
208 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (cpup, result, 1);
209
210 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
211 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
212 "ReadAPUDataRead (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n",
213 cpu.iefpFinalAddress, * result);
214 # if defined(TESTING)
215 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRead");
216 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead");
217 # endif
218 }
219 return;
220 }
221 }
222 }
223 }
224
225 void ReadOperandRead (cpu_state_t * cpup, word18 address, word36 * result) {
226 cpu.TPR.CA = cpu.iefpFinalAddress = address;
227 bool isBAR = get_bar_mode (cpup);
228
229 if (cpu.cu.XSF || cpu.currentInstruction.b29)
230 goto B29;
231
232 switch (get_addr_mode (cpup)) {
233 case ABSOLUTE_mode: {
234 if (isBAR) {
235 set_apu_status (cpup, apuStatus_FABS);
236 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
237 fauxDoAppendCycle (cpup, OPERAND_READ);
238 core_read (cpup, cpu.iefpFinalAddress, result, __func__);
239 sim_debug (DBG_FINAL, & cpu_dev,
240 "readOperandRead (Actual) Read: bar address=%08o readData=%012"PRIo64"\n",
241 address, *result);
242 # if defined(TESTING)
243 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "readOperandRead ABS BAR");
244 HDBGMRead (cpu.iefpFinalAddress, * result, "readOperandRead ABS BAR");
245 # endif
246 return;
247 } else {
248 set_apu_status (cpup, apuStatus_FABS);
249 fauxDoAppendCycle (cpup, OPERAND_READ);
250 core_read (cpup, address, result, __func__);
251 sim_debug (DBG_FINAL, & cpu_dev,
252 "readOperandRead (Actual) Read: abs address=%08o readData=%012"PRIo64"\n",
253 address, *result);
254 # if defined(TESTING)
255 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "readOperandRead ABS");
256 HDBGMRead (address, * result, "readOperandRead ABS");
257 # endif
258 return;
259 }
260 }
261
262 case APPEND_mode: {
263 B29:;
264 if (isBAR) {
265 cpu.TPR.CA = get_BAR_address (cpup, address);
266 cpu.TPR.TSR = cpu.PPR.PSR;
267 cpu.TPR.TRR = cpu.PPR.PRR;
268 cpu.iefpFinalAddress = doAppendCycleOperandRead (cpup, result, 1);
269 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
270 "readOperandRead (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n",
271 cpu.iefpFinalAddress, * result);
272 # if defined(TESTING)
273 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "readOperandRead BAR");
274 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead BAR");
275 # endif
276
277 return;
278 } else {
279 cpu.iefpFinalAddress = doAppendCycleOperandRead (cpup, result, 1);
280
281 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
282 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
283 "readOperandRead (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n",
284 cpu.iefpFinalAddress, * result);
285 # if defined(TESTING)
286 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "readOperandRead");
287 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead");
288 # endif
289 }
290 return;
291 }
292 }
293 }
294 }
295
296 # if defined(LOCKLESS)
297 void ReadOperandRMW (cpu_state_t * cpup, word18 address, word36 * result) {
298 cpu.TPR.CA = cpu.iefpFinalAddress = address;
299 bool isBAR = get_bar_mode (cpup);
300
301 if (cpu.cu.XSF || cpu.currentInstruction.b29)
302 goto B29;
303
304 switch (get_addr_mode (cpup)) {
305 case ABSOLUTE_mode: {
306 if (isBAR) {
307 set_apu_status (cpup, apuStatus_FABS);
308 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
309 fauxDoAppendCycle (cpup, OPERAND_RMW);
310 core_read_lock (cpup, cpu.iefpFinalAddress, result, __func__);
311 sim_debug (DBG_FINAL, & cpu_dev,
312 "ReadOperandRMW (Actual) Read: bar address=%08o readData=%012"PRIo64"\n",
313 address, *result);
314 # if defined(TESTING)
315 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadOperandRMW ABS BAR");
316 HDBGMRead (cpu.iefpFinalAddress, * result, "ReadOperandRMW ABS BAR");
317 # endif
318 return;
319 } else {
320 set_apu_status (cpup, apuStatus_FABS);
321 fauxDoAppendCycle (cpup, OPERAND_RMW);
322 core_read_lock (cpup, address, result, __func__);
323 sim_debug (DBG_FINAL, & cpu_dev,
324 "ReadOperandRMW (Actual) Read: abs address=%08o readData=%012"PRIo64"\n",
325 address, *result);
326 # if defined(TESTING)
327 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadOperandRMW ABS");
328 HDBGMRead (address, * result, "ReadOperandRMW ABS");
329 # endif
330 return;
331 }
332 }
333
334 case APPEND_mode: {
335 B29:;
336 if (isBAR) {
337 cpu.TPR.CA = get_BAR_address (cpup, address);
338 cpu.TPR.TSR = cpu.PPR.PSR;
339 cpu.TPR.TRR = cpu.PPR.PRR;
340 cpu.iefpFinalAddress = doAppendCycleOperandRMW (cpup, result, 1);
341 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
342 "ReadOperandRMW (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n",
343 cpu.iefpFinalAddress, * result);
344 # if defined(TESTING)
345 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadOperandRMW BAR");
346 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW BAR");
347 # endif
348 return;
349 } else {
350 cpu.iefpFinalAddress = doAppendCycleOperandRMW (cpup, result, 1);
351
352 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
353 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
354 "ReadOperandRMW (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n",
355 cpu.iefpFinalAddress, * result);
356 # if defined(TESTING)
357 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadOperandRMW");
358 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW");
359 # endif
360 }
361 return;
362 }
363 }
364 }
365 }
366
367 void ReadAPUDataRMW (cpu_state_t * cpup, word18 address, word36 * result) {
368 cpu.TPR.CA = cpu.iefpFinalAddress = address;
369 bool isBAR = get_bar_mode (cpup);
370
371 if (cpu.cu.XSF || cpu.currentInstruction.b29)
372 goto B29;
373
374 switch (get_addr_mode (cpup)) {
375 case ABSOLUTE_mode: {
376 if (isBAR) {
377 set_apu_status (cpup, apuStatus_FABS);
378 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
379 fauxDoAppendCycle (cpup, APU_DATA_RMW);
380 core_read_lock (cpup, cpu.iefpFinalAddress, result, __func__);
381 sim_debug (DBG_FINAL, & cpu_dev,
382 "ReadAPUDataRMW (Actual) Read: bar address=%08o readData=%012"PRIo64"\n",
383 address, *result);
384 # if defined(TESTING)
385 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadAPUDataRMW ABS BAR");
386 HDBGMRead (cpu.iefpFinalAddress, * result, "ReadAPUDataRMW ABS BAR");
387 # endif
388 return;
389 } else {
390 set_apu_status (cpup, apuStatus_FABS);
391 fauxDoAppendCycle (cpup, APU_DATA_RMW);
392 core_read_lock (cpup, address, result, __func__);
393 sim_debug (DBG_FINAL, & cpu_dev,
394 "ReadAPUDataRMW (Actual) Read: abs address=%08o readData=%012"PRIo64"\n",
395 address, *result);
396 # if defined(TESTING)
397 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadAPUDataRMW ABS");
398 HDBGMRead (address, * result, "ReadAPUDataRMW ABS");
399 # endif
400 return;
401 }
402 }
403
404 case APPEND_mode: {
405 B29:;
406 if (isBAR) {
407 cpu.TPR.CA = get_BAR_address (cpup, address);
408 cpu.TPR.TSR = cpu.PPR.PSR;
409 cpu.TPR.TRR = cpu.PPR.PRR;
410 cpu.iefpFinalAddress = doAppendCycleAPUDataRMW (cpup, result, 1);
411 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
412 "ReadAPUDataRMW (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n",
413 cpu.iefpFinalAddress, * result);
414 # if defined(TESTING)
415 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRMW BAR");
416 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW BAR");
417 # endif
418 return;
419 } else {
420 cpu.iefpFinalAddress = doAppendCycleAPUDataRMW (cpup, result, 1);
421
422 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
423 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
424 "ReadAPUDataRMW (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n",
425 cpu.iefpFinalAddress, * result);
426 # if defined(TESTING)
427 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRMW");
428 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW");
429 # endif
430 }
431 return;
432 }
433 }
434 }
435 return ;
436 }
437 # endif
438
439 void ReadInstructionFetch (cpu_state_t * cpup, word18 address, word36 * result) {
440 cpu.TPR.CA = cpu.iefpFinalAddress = address;
441 bool isBAR = get_bar_mode (cpup);
442
443 if (cpu.cu.XSF)
444 goto B29;
445
446 switch (get_addr_mode (cpup)) {
447 case ABSOLUTE_mode: {
448 if (isBAR) {
449 set_apu_status (cpup, apuStatus_FABS);
450 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
451 fauxDoAppendCycle (cpup, INSTRUCTION_FETCH);
452 core_read (cpup, cpu.iefpFinalAddress, result, __func__);
453 sim_debug (DBG_FINAL, & cpu_dev,
454 "ReadInstructionFetch (Actual) Read: bar address=%08o readData=%012"PRIo64"\n",
455 address, *result);
456 # if defined(TESTING)
457 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadInstructionFetch ABS BAR");
458 HDBGMRead (cpu.iefpFinalAddress, * result, "ReadInstructionFetch ABS BAR");
459 # endif
460 return;
461 } else {
462 set_apu_status (cpup, apuStatus_FABS);
463 fauxDoAppendCycle (cpup, INSTRUCTION_FETCH);
464 core_read (cpup, address, result, __func__);
465 sim_debug (DBG_FINAL, & cpu_dev,
466 "ReadInstructionFetch (Actual) Read: abs address=%08o readData=%012"PRIo64"\n",
467 address, *result);
468 # if defined(TESTING)
469 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadInstructionFetch ABS");
470 HDBGMRead (address, * result, "ReadInstructionFetch ABS");
471 # endif
472 return;
473 }
474 }
475
476 case APPEND_mode: {
477 B29:;
478 if (isBAR) {
479 cpu.TPR.CA = get_BAR_address (cpup, address);
480 cpu.TPR.TSR = cpu.PPR.PSR;
481 cpu.TPR.TRR = cpu.PPR.PRR;
482 cpu.iefpFinalAddress = doAppendCycleInstructionFetch (cpup, result, 1);
483 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
484 "ReadInstructionFetch (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n",
485 cpu.iefpFinalAddress, * result);
486 # if defined(TESTING)
487 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadInstructionFetch BAR");
488 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch BAR");
489 # endif
490 return;
491 } else {
492 cpu.iefpFinalAddress = doAppendCycleInstructionFetch (cpup, result, 1);
493
494 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
495 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
496 "ReadInstructionFetch (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n",
497 cpu.iefpFinalAddress, * result);
498 # if defined(TESTING)
499 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadInstructionFetch");
500 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch");
501 # endif
502 }
503 return;
504 }
505 }
506 }
507 }
508
509 void ReadIndirectWordFetch (cpu_state_t * cpup, word18 address, word36 * result) {
510 cpu.TPR.CA = cpu.iefpFinalAddress = address;
511 bool isBAR = get_bar_mode (cpup);
512
513 if (cpu.cu.XSF || cpu.currentInstruction.b29)
514 goto B29;
515
516 switch (get_addr_mode (cpup)) {
517 case ABSOLUTE_mode: {
518 if (isBAR) {
519 set_apu_status (cpup, apuStatus_FABS);
520 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
521 fauxDoAppendCycle (cpup, INDIRECT_WORD_FETCH);
522 core_read (cpup, cpu.iefpFinalAddress, result, __func__);
523 sim_debug (DBG_FINAL, & cpu_dev,
524 "ReadIndirectWordFetch (Actual) Read: bar address=%08o readData=%012"PRIo64"\n",
525 address, *result);
526 # if defined(TESTING)
527 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadIndirectWordFetch ABS BAR");
528 HDBGMRead (cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch ABS BAR");
529 # endif
530 return;
531 } else {
532 set_apu_status (cpup, apuStatus_FABS);
533 fauxDoAppendCycle (cpup, INDIRECT_WORD_FETCH);
534 core_read (cpup, address, result, __func__);
535 sim_debug (DBG_FINAL, & cpu_dev,
536 "ReadIndirectWordFetch (Actual) Read: abs address=%08o readData=%012"PRIo64"\n",
537 address, *result);
538 # if defined(TESTING)
539 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadIndirectWordFetch ABS");
540 HDBGMRead (address, * result, "ReadIndirectWordFetch ABS");
541 # endif
542 return;
543 }
544 }
545
546 case APPEND_mode: {
547 B29:;
548 if (isBAR) {
549 cpu.TPR.CA = get_BAR_address (cpup, address);
550 cpu.TPR.TSR = cpu.PPR.PSR;
551 cpu.TPR.TRR = cpu.PPR.PRR;
552 cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (cpup, result, 1);
553 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
554 "ReadIndirectWordFetch (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n",
555 cpu.iefpFinalAddress, * result);
556 # if defined(TESTING)
557 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch BAR");
558 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch BAR");
559 # endif
560 return;
561 } else {
562 cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (cpup, result, 1);
563
564 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
565 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
566 "ReadIndirectWordFetch (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n",
567 cpu.iefpFinalAddress, * result);
568 # if defined(TESTING)
569 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch");
570 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch");
571 # endif
572 }
573 return;
574 }
575 }
576 }
577 }
578 #endif
579
580 #if defined(OLDAPP)
581 void Read2 (cpu_state_t * cpup, word18 address, word36 * result, processor_cycle_type cyctyp) {
582 cpu.TPR.CA = cpu.iefpFinalAddress = address;
583
584 bool isBAR = get_bar_mode (cpup);
585
586 if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29) || cyctyp == RTCD_OPERAND_FETCH)
587
588 goto B29;
589
590 switch (get_addr_mode (cpup)) {
591 case ABSOLUTE_mode: {
592 if (isBAR) {
593 set_apu_status (cpup, apuStatus_FABS);
594 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
595
596 fauxDoAppendCycle (cpup, cyctyp);
597 core_read2 (cpup, cpu.iefpFinalAddress, result + 0, result + 1, __func__);
598 if_sim_debug (DBG_FINAL, & cpu_dev) {
599 for (uint i = 0; i < 2; i ++)
600 sim_debug (DBG_FINAL, & cpu_dev,
601 "Read2 (Actual) Read: bar address=%08o" " readData=%012"PRIo64"\n",
602 address + i, result [i]);
603 }
604 # if defined(TESTING)
605 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2 ABBR");
606 HDBGMRead (cpu.iefpFinalAddress, * result, "Read2 ABBR evn");
607 HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2 ABBR odd");
608 # endif
609 return;
610 } else {
611 set_apu_status (cpup, apuStatus_FABS);
612 fauxDoAppendCycle (cpup, cyctyp);
613 core_read2 (cpup, address, result + 0, result + 1, __func__);
614 if_sim_debug (DBG_FINAL, & cpu_dev) {
615 for (uint i = 0; i < 2; i ++)
616 sim_debug (DBG_FINAL, & cpu_dev,
617 "Read2 (Actual) Read: abs address=%08o" " readData=%012"PRIo64"\n",
618 address + i, result [i]);
619 }
620 # if defined(TESTING)
621 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2 AB");
622 HDBGMRead (cpu.iefpFinalAddress, * result, "Read2 AB evn");
623 HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2 AB odd");
624 # endif
625 return;
626 }
627 }
628
629 case APPEND_mode: {
630 B29:;
631 if (isBAR) {
632 cpu.TPR.CA = get_BAR_address (cpup, address);
633 cpu.TPR.TSR = cpu.PPR.PSR;
634 cpu.TPR.TRR = cpu.PPR.PRR;
635 cpu.iefpFinalAddress = do_append_cycle (cpup, cyctyp, result, 2);
636 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
637 for (uint i = 0; i < 2; i ++)
638 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
639 "Read2 (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n",
640 cpu.iefpFinalAddress + i, result [i]);
641 }
642 # if defined(TESTING)
643 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR");
644 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn");
645 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd");
646 # endif
647 return;
648 } else {
649 cpu.iefpFinalAddress = do_append_cycle (cpup, cyctyp, result, 2);
650 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
651 for (uint i = 0; i < 2; i ++)
652 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
653 "Read2 (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n",
654 cpu.iefpFinalAddress + i, result [i]);
655 }
656 if_sim_debug (DBG_FINAL, & cpu_dev) {
657 if (cyctyp == OPERAND_READ) {
658 for (uint i = 0; i < 2; i ++)
659 sim_debug (DBG_FINAL, & cpu_dev,
660 "Read2 (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n",
661 cpu.iefpFinalAddress + i, result [i]);
662 }
663 }
664 # if defined(TESTING)
665 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2");
666 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn");
667 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd");
668 # endif
669 }
670 return;
671 }
672 }
673 }
674 #endif
675
676 #if !defined(OLDAPP)
677 void Read2OperandRead (cpu_state_t * cpup, word18 address, word36 * result) {
678 cpu.TPR.CA = cpu.iefpFinalAddress = address;
679
680 bool isBAR = get_bar_mode (cpup);
681
682 if (cpu.cu.XSF || cpu.currentInstruction.b29)
683 goto B29;
684
685 switch (get_addr_mode (cpup)) {
686 case ABSOLUTE_mode: {
687 if (isBAR) {
688 set_apu_status (cpup, apuStatus_FABS);
689 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
690
691 fauxDoAppendCycle (cpup, OPERAND_READ);
692 core_read2 (cpup, cpu.iefpFinalAddress, result + 0, result + 1, __func__);
693 if_sim_debug (DBG_FINAL, & cpu_dev) {
694 for (uint i = 0; i < 2; i ++)
695 sim_debug (DBG_FINAL, & cpu_dev,
696 "Read2OperandRead (Actual) Read: bar address=%08o" " readData=%012"PRIo64"\n",
697 address + i, result [i]);
698 }
699 # if defined(TESTING)
700 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2OperandRead ABBR");
701 HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRead ABBR evn");
702 HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRead ABBR odd");
703 # endif
704 return;
705 } else {
706 set_apu_status (cpup, apuStatus_FABS);
707 fauxDoAppendCycle (cpup, OPERAND_READ);
708 core_read2 (cpup, address, result + 0, result + 1, __func__);
709 if_sim_debug (DBG_FINAL, & cpu_dev) {
710 for (uint i = 0; i < 2; i ++)
711 sim_debug (DBG_FINAL, & cpu_dev,
712 "Read2OperandRead (Actual) Read: abs address=%08o" " readData=%012"PRIo64"\n",
713 address + i, result [i]);
714 }
715 # if defined(TESTING)
716 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2OperandRead AB");
717 HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRead AB evn");
718 HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRead AB odd");
719 # endif
720 return;
721 }
722 }
723
724 case APPEND_mode: {
725 B29:;
726 if (isBAR) {
727 cpu.TPR.CA = get_BAR_address (cpup, address);
728 cpu.TPR.TSR = cpu.PPR.PSR;
729 cpu.TPR.TRR = cpu.PPR.PRR;
730 cpu.iefpFinalAddress = doAppendCycleOperandRead (cpup, result, 2);
731 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
732 for (uint i = 0; i < 2; i ++)
733 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
734 "Read2OperandRead (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n",
735 cpu.iefpFinalAddress + i, result [i]);
736 }
737 # if defined(TESTING)
738 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRead BR");
739 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead BR evn");
740 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead BR odd");
741 # endif
742 return;
743 } else {
744 cpu.iefpFinalAddress = doAppendCycleOperandRead (cpup, result, 2);
745 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
746 for (uint i = 0; i < 2; i ++)
747 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
748 "Read2OperandRead (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n",
749 cpu.iefpFinalAddress + i, result [i]);
750 }
751 if_sim_debug (DBG_FINAL, & cpu_dev) {
752 for (uint i = 0; i < 2; i ++)
753 sim_debug (DBG_FINAL, & cpu_dev,
754 "Read2OperandRead (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n",
755 cpu.iefpFinalAddress + i, result [i]);
756 }
757 # if defined(TESTING)
758 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRead");
759 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead evn");
760 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead odd");
761 # endif
762 return;
763 }
764 }
765 }
766 }
767
768 # if defined(LOCKLESS)
769 void Read2OperandRMW (cpu_state_t * cpup, word18 address, word36 * result) {
770 cpu.TPR.CA = cpu.iefpFinalAddress = address;
771
772 bool isBAR = get_bar_mode (cpup);
773
774 if (cpu.cu.XSF || cpu.currentInstruction.b29)
775 goto B29;
776
777 switch (get_addr_mode (cpup)) {
778 case ABSOLUTE_mode: {
779 if (isBAR) {
780 set_apu_status (cpup, apuStatus_FABS);
781 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
782
783 fauxDoAppendCycle (cpup, OPERAND_RMW);
784 core_read2 (cpup, cpu.iefpFinalAddress, result + 0, result + 1, __func__);
785 if_sim_debug (DBG_FINAL, & cpu_dev) {
786 for (uint i = 0; i < 2; i ++)
787 sim_debug (DBG_FINAL, & cpu_dev,
788 "Read2OperandRMW (Actual) Read: bar address=%08o" " readData=%012"PRIo64"\n",
789 address + i, result [i]);
790 }
791 # if defined(TESTING)
792 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2OperandRMW ABBR");
793 HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRMW ABBR evn");
794 HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRMW ABBR odd");
795 # endif
796 return;
797 } else {
798 set_apu_status (cpup, apuStatus_FABS);
799 fauxDoAppendCycle (cpup, OPERAND_RMW);
800 core_read2 (cpup, address, result + 0, result + 1, __func__);
801 if_sim_debug (DBG_FINAL, & cpu_dev) {
802 for (uint i = 0; i < 2; i ++)
803 sim_debug (DBG_FINAL, & cpu_dev,
804 "Read2OperandRMW (Actual) Read: abs address=%08o" " readData=%012"PRIo64"\n",
805 address + i, result [i]);
806 }
807 # if defined(TESTING)
808 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2OperandRMW AB");
809 HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRMW AB evn");
810 HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRMW AB odd");
811 # endif
812 return;
813 }
814 }
815
816 case APPEND_mode: {
817 B29:;
818 if (isBAR) {
819 cpu.TPR.CA = get_BAR_address (cpup, address);
820 cpu.TPR.TSR = cpu.PPR.PSR;
821 cpu.TPR.TRR = cpu.PPR.PRR;
822 cpu.iefpFinalAddress = doAppendCycleOperandRMW (cpup, result, 2);
823 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
824 for (uint i = 0; i < 2; i ++)
825 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
826 "Read2OperandRMW (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n",
827 cpu.iefpFinalAddress + i, result [i]);
828 }
829 # if defined(TESTING)
830 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRMW BR");
831 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW BR evn");
832 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW BR odd");
833 # endif
834 return;
835 } else {
836 cpu.iefpFinalAddress = doAppendCycleOperandRMW (cpup, result, 2);
837 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
838 for (uint i = 0; i < 2; i ++)
839 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
840 "Read2OperandRMW (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n",
841 cpu.iefpFinalAddress + i, result [i]);
842 }
843 # if defined(TESTING)
844 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRMW");
845 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW evn");
846 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW odd");
847 # endif
848 return;
849 }
850 }
851 }
852 }
853 # endif
854
855 void Read2InstructionFetch (cpu_state_t * cpup, word18 address, word36 * result) {
856 cpu.TPR.CA = cpu.iefpFinalAddress = address;
857
858 bool isBAR = get_bar_mode (cpup);
859
860 if (cpu.cu.XSF)
861 goto B29;
862
863 switch (get_addr_mode (cpup)) {
864 case ABSOLUTE_mode: {
865 if (isBAR) {
866 set_apu_status (cpup, apuStatus_FABS);
867 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
868
869 fauxDoAppendCycle (cpup, INSTRUCTION_FETCH);
870 core_read2 (cpup, cpu.iefpFinalAddress, result + 0, result + 1, __func__);
871 if_sim_debug (DBG_FINAL, & cpu_dev) {
872 for (uint i = 0; i < 2; i ++)
873 sim_debug (DBG_FINAL, & cpu_dev,
874 "Read2InstructionFetch (Actual) Read: bar address=%08o" " readData=%012"PRIo64"\n",
875 address + i, result [i]);
876 }
877 # if defined(TESTING)
878 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2InstructionFetch ABBR");
879 HDBGMRead (cpu.iefpFinalAddress, * result, "Read2InstructionFetch ABBR evn");
880 HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2InstructionFetch ABBR odd");
881 # endif
882 return;
883 } else {
884 set_apu_status (cpup, apuStatus_FABS);
885 fauxDoAppendCycle (cpup, INSTRUCTION_FETCH);
886 core_read2 (cpup, address, result + 0, result + 1, __func__);
887 if_sim_debug (DBG_FINAL, & cpu_dev) {
888 for (uint i = 0; i < 2; i ++)
889 sim_debug (DBG_FINAL, & cpu_dev,
890 "Read2InstructionFetch (Actual) Read: abs address=%08o" " readData=%012"PRIo64"\n",
891 address + i, result [i]);
892 }
893 # if defined(TESTING)
894 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2InstructionFetch AB");
895 HDBGMRead (cpu.iefpFinalAddress, * result, "Read2InstructionFetch AB evn");
896 HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2InstructionFetch AB odd");
897 # endif
898 return;
899 }
900 }
901
902 case APPEND_mode: {
903 B29:;
904 if (isBAR) {
905 cpu.TPR.CA = get_BAR_address (cpup, address);
906 cpu.TPR.TSR = cpu.PPR.PSR;
907 cpu.TPR.TRR = cpu.PPR.PRR;
908 cpu.iefpFinalAddress = doAppendCycleInstructionFetch (cpup, result, 2);
909 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
910 for (uint i = 0; i < 2; i ++)
911 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
912 "Read2InstructionFetch (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n",
913 cpu.iefpFinalAddress + i, result [i]);
914 }
915 # if defined(TESTING)
916 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2InstructionFetch BR");
917 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch BR evn");
918 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch BR odd");
919 # endif
920 return;
921 } else {
922 cpu.iefpFinalAddress = doAppendCycleInstructionFetch (cpup, result, 2);
923 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
924 for (uint i = 0; i < 2; i ++)
925 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
926 "Read2InstructionFetch (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n",
927 cpu.iefpFinalAddress + i, result [i]);
928 }
929 # if defined(TESTING)
930 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2InstructionFetch");
931 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch evn");
932 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch odd");
933 # endif
934 return;
935 }
936 }
937 }
938 }
939
940 void Read2RTCDOperandFetch (cpu_state_t * cpup, word18 address, word36 * result) {
941 cpu.TPR.CA = cpu.iefpFinalAddress = address;
942
943 bool isBAR = get_bar_mode (cpup);
944
945 if (isBAR) {
946 cpu.TPR.CA = get_BAR_address (cpup, address);
947 cpu.TPR.TSR = cpu.PPR.PSR;
948 cpu.TPR.TRR = cpu.PPR.PRR;
949 cpu.iefpFinalAddress = doAppendCycleRTCDOperandFetch (cpup, result, 2);
950 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
951 for (uint i = 0; i < 2; i ++)
952 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
953 "Read2 (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n",
954 cpu.iefpFinalAddress + i, result [i]);
955 }
956 # if defined(TESTING)
957 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR");
958 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn");
959 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd");
960 # endif
961 return;
962 } else {
963 cpu.iefpFinalAddress = doAppendCycleRTCDOperandFetch (cpup, result, 2);
964 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
965 for (uint i = 0; i < 2; i ++)
966 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
967 "Read2 (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n",
968 cpu.iefpFinalAddress + i, result [i]);
969 }
970 # if defined(TESTING)
971 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2");
972 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn");
973 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd");
974 # endif
975 return;
976 }
977 }
978
979 void Read2IndirectWordFetch (cpu_state_t * cpup, word18 address, word36 * result) {
980 cpu.TPR.CA = cpu.iefpFinalAddress = address;
981
982 bool isBAR = get_bar_mode (cpup);
983
984 if (cpu.cu.XSF || cpu.currentInstruction.b29)
985 goto B29;
986
987 switch (get_addr_mode (cpup)) {
988 case ABSOLUTE_mode: {
989 if (isBAR) {
990 set_apu_status (cpup, apuStatus_FABS);
991 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
992
993 fauxDoAppendCycle (cpup, INDIRECT_WORD_FETCH);
994 core_read2 (cpup, cpu.iefpFinalAddress, result + 0, result + 1, __func__);
995 if_sim_debug (DBG_FINAL, & cpu_dev) {
996 for (uint i = 0; i < 2; i ++)
997 sim_debug (DBG_FINAL, & cpu_dev,
998 "Read2IndirectWordFetch (Actual) Read: bar address=%08o" " readData=%012"PRIo64"\n",
999 address + i, result [i]);
1000 }
1001 # if defined(TESTING)
1002 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2IndirectWordFetch ABBR");
1003 HDBGMRead (cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch ABBR evn");
1004 HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2IndirectWordFetch ABBR odd");
1005 # endif
1006 return;
1007 } else {
1008 set_apu_status (cpup, apuStatus_FABS);
1009 fauxDoAppendCycle (cpup, INDIRECT_WORD_FETCH);
1010 core_read2 (cpup, address, result + 0, result + 1, __func__);
1011 if_sim_debug (DBG_FINAL, & cpu_dev) {
1012 for (uint i = 0; i < 2; i ++)
1013 sim_debug (DBG_FINAL, & cpu_dev,
1014 "Read2IndirectWordFetch (Actual) Read: abs address=%08o" " readData=%012"PRIo64"\n",
1015 address + i, result [i]);
1016 }
1017 # if defined(TESTING)
1018 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2IndirectWordFetch AB");
1019 HDBGMRead (cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch AB evn");
1020 HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2IndirectWordFetch AB odd");
1021 # endif
1022 return;
1023 }
1024 }
1025
1026 case APPEND_mode: {
1027 B29:;
1028 if (isBAR) {
1029 cpu.TPR.CA = get_BAR_address (cpup, address);
1030 cpu.TPR.TSR = cpu.PPR.PSR;
1031 cpu.TPR.TRR = cpu.PPR.PRR;
1032 cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (cpup, result, 2);
1033 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
1034 for (uint i = 0; i < 2; i ++)
1035 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1036 "Read2IndirectWordFetch (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n",
1037 cpu.iefpFinalAddress + i, result [i]);
1038 }
1039 # if defined(TESTING)
1040 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch BR");
1041 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch BR evn");
1042 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch BR odd");
1043 # endif
1044 return;
1045 } else {
1046 cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (cpup, result, 2);
1047 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
1048 for (uint i = 0; i < 2; i ++)
1049 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1050 "Read2IndirectWordFetch (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n",
1051 cpu.iefpFinalAddress + i, result [i]);
1052 }
1053 # if defined(TESTING)
1054 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch");
1055 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch evn");
1056 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch odd");
1057 return;
1058 # endif
1059 }
1060 }
1061 }
1062 }
1063 #endif
1064
1065 void Read8 (cpu_state_t * cpup, word18 address, word36 * result, bool isAR)
1066 {
1067 cpu.TPR.CA = cpu.iefpFinalAddress = address;
1068
1069 bool isBAR = get_bar_mode (cpup);
1070
1071 if (isAR || cpu.cu.XSF )
1072 {
1073 goto B29;
1074 }
1075
1076 switch (get_addr_mode (cpup))
1077 {
1078 case ABSOLUTE_mode:
1079 {
1080 if (isBAR)
1081 {
1082 set_apu_status (cpup, apuStatus_FABS);
1083 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1084
1085 fauxDoAppendCycle (cpup, APU_DATA_READ);
1086 core_readN (cpup, cpu.iefpFinalAddress, result, 8, __func__);
1087 if_sim_debug (DBG_FINAL, & cpu_dev)
1088 {
1089 for (uint i = 0; i < 8; i ++)
1090 sim_debug (DBG_FINAL, & cpu_dev,
1091 "Read8 (Actual) Read: bar address=%08o"
1092 " readData=%012"PRIo64"\n",
1093 address + i, result [i]);
1094 }
1095 #if defined(TESTING)
1096 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read8 ABBR");
1097 for (uint i = 0; i < 8; i ++)
1098 HDBGMRead (cpu.iefpFinalAddress + i, result [i], "Read8 ABBR");
1099 #endif
1100 return;
1101 }
1102 else
1103 {
1104 set_apu_status (cpup, apuStatus_FABS);
1105 fauxDoAppendCycle (cpup, APU_DATA_READ);
1106 core_readN (cpup, address, result, 8, __func__);
1107 if_sim_debug (DBG_FINAL, & cpu_dev)
1108 {
1109 for (uint i = 0; i < 8; i ++)
1110 sim_debug (DBG_FINAL, & cpu_dev,
1111 "Read8 (Actual) Read: abs address=%08o"
1112 " readData=%012"PRIo64"\n",
1113 address + i, result [i]);
1114 }
1115 #if defined(TESTING)
1116 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read8 ABS");
1117 for (uint i = 0; i < 8; i ++)
1118 HDBGMRead (address + i, result [i], "Read8 ABS");
1119 #endif
1120 return;
1121 }
1122 }
1123
1124 case APPEND_mode:
1125 {
1126 B29:;
1127 if (isBAR)
1128 {
1129 cpu.TPR.CA = get_BAR_address (cpup, address);
1130 cpu.TPR.TSR = cpu.PPR.PSR;
1131 cpu.TPR.TRR = cpu.PPR.PRR;
1132
1133 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (cpup, result, 8);
1134 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1135 {
1136 for (uint i = 0; i < 8; i ++)
1137 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1138 "Read8 (Actual) Read: bar iefpFinalAddress="
1139 "%08o readData=%012"PRIo64"\n",
1140 cpu.iefpFinalAddress + i, result [i]);
1141 }
1142 #if defined(TESTING)
1143 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read8 BAR");
1144 for (uint i = 0; i < 8; i ++)
1145 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result[i], "Read8 BAR");
1146 #endif
1147 return;
1148 }
1149 else
1150 {
1151
1152 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (cpup, result, 8);
1153
1154 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
1155 {
1156 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1157 {
1158 for (uint i = 0; i < 8; i ++)
1159 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1160 "Read8 (Actual) Read: iefpFinalAddress="
1161 "%08o readData=%012"PRIo64"\n",
1162 cpu.iefpFinalAddress + i, result [i]);
1163 }
1164 #if defined(TESTING)
1165 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read8");
1166 for (uint i = 0; i < 8; i ++)
1167 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "Read8");
1168 #endif
1169 }
1170 return;
1171 }
1172 }
1173 }
1174 }
1175
1176 void Read16 (cpu_state_t * cpup, word18 address, word36 * result)
1177 {
1178 address &= paragraphMask;
1179 Read8 (cpup, address, result, cpu.currentInstruction.b29);
1180 Read8 (cpup, address + 8, result + 8, cpu.currentInstruction.b29);
1181 return;
1182 }
1183
1184 void ReadPage (cpu_state_t * cpup, word18 address, word36 * result, bool isAR)
1185 {
1186 if ((address & PGMK) != 0)
1187 {
1188 sim_warn ("ReadPage not on boundary %06o\n", address);
1189 }
1190 address &= (word18) ~PGMK;
1191 cpu.TPR.CA = cpu.iefpFinalAddress = address;
1192
1193 bool isBAR = get_bar_mode (cpup);
1194
1195 if (isAR || cpu.cu.XSF )
1196 {
1197 goto B29;
1198 }
1199
1200 switch (get_addr_mode (cpup))
1201 {
1202 case ABSOLUTE_mode:
1203 {
1204 if (isBAR)
1205 {
1206 set_apu_status (cpup, apuStatus_FABS);
1207 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1208
1209 fauxDoAppendCycle (cpup, APU_DATA_READ);
1210 core_readN (cpup, cpu.iefpFinalAddress, result, PGSZ, __func__);
1211 if_sim_debug (DBG_FINAL, & cpu_dev)
1212 {
1213 for (uint i = 0; i < PGSZ; i ++)
1214 sim_debug (DBG_FINAL, & cpu_dev,
1215 "ReadPage (Actual) Read: bar address="
1216 "%08o readData=%012"PRIo64"\n",
1217 address + i, result [i]);
1218 }
1219 #if defined(TESTING)
1220 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadPage AB");
1221 for (uint i = 0; i < PGSZ; i ++)
1222 HDBGMRead (cpu.iefpFinalAddress + i, result [i], "ReadPage AB");
1223 #endif
1224 return;
1225 }
1226 else
1227 {
1228 set_apu_status (cpup, apuStatus_FABS);
1229 fauxDoAppendCycle (cpup, APU_DATA_READ);
1230 core_readN (cpup, address, result, PGSZ, __func__);
1231 if_sim_debug (DBG_FINAL, & cpu_dev)
1232 {
1233 for (uint i = 0; i < PGSZ; i ++)
1234 sim_debug (DBG_FINAL, & cpu_dev,
1235 "ReadPage (Actual) Read: abs address="
1236 "%08o readData=%012"PRIo64"\n",
1237 address + i, result [i]);
1238 }
1239 #if defined(TESTING)
1240 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadPage ABS");
1241 for (uint i = 0; i < PGSZ; i ++)
1242 HDBGMRead (address + i, result [i], "ReadPage ABS");
1243 #endif
1244 return;
1245 }
1246 }
1247
1248 case APPEND_mode:
1249 {
1250 B29:;
1251 if (isBAR)
1252 {
1253 cpu.TPR.CA = get_BAR_address (cpup, address);
1254 cpu.TPR.TSR = cpu.PPR.PSR;
1255 cpu.TPR.TRR = cpu.PPR.PRR;
1256
1257 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (cpup, result, PGSZ);
1258 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1259 {
1260 for (uint i = 0; i < PGSZ; i ++)
1261 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1262 "ReadPage (Actual) Read: bar iefpFinalAddress="
1263 "%08o readData=%012"PRIo64"\n",
1264 cpu.iefpFinalAddress + i, result [i]);
1265 }
1266 #if defined(TESTING)
1267 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadPage B");
1268 for (uint i = 0; i < PGSZ; i ++)
1269 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage B");
1270 #endif
1271
1272 return;
1273 }
1274 else
1275 {
1276
1277 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (cpup, result, PGSZ);
1278
1279 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
1280 {
1281 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1282 {
1283 for (uint i = 0; i < PGSZ; i ++)
1284 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1285 "ReadPage (Actual) Read: iefpFinalAddress"
1286 "=%08o readData=%012"PRIo64"\n",
1287 cpu.iefpFinalAddress + i, result [i]);
1288 }
1289 #if defined(TESTING)
1290 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadPage");
1291 for (uint i = 0; i < PGSZ; i ++)
1292 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage");
1293 #endif
1294 }
1295 return;
1296 }
1297 }
1298 }
1299 }
1300
1301 #if defined(OLDAPP)
1302 void Write (cpu_state_t * cpup, word18 address, word36 data, processor_cycle_type cyctyp) {
1303 cpu.TPR.CA = cpu.iefpFinalAddress = address;
1304
1305 bool isBAR = get_bar_mode ();
1306
1307 if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29))
1308 goto B29;
1309
1310 switch (get_addr_mode ()) {
1311 case ABSOLUTE_mode: {
1312 if (isBAR) {
1313 cpu.iefpFinalAddress = get_BAR_address (address);
1314 set_apu_status (apuStatus_FABS);
1315 fauxDoAppendCycle (cyctyp);
1316 if (cyctyp == OPERAND_STORE && cpu.useZone)
1317 core_write_zone (cpu.iefpFinalAddress, data, __func__);
1318 else
1319 core_write (cpu.iefpFinalAddress, data, __func__);
1320 sim_debug (DBG_FINAL, & cpu_dev, "Write(Actual) Write: bar address=%08o writeData=%012"PRIo64"\n", address, data);
1321 # if defined(TESTING)
1322 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write ABBR");
1323 HDBGMWrite (cpu.iefpFinalAddress, data, "Write ABBR");
1324 # endif
1325 return;
1326 } else {
1327 set_apu_status (apuStatus_FABS);
1328 fauxDoAppendCycle (cyctyp);
1329 if (cyctyp == OPERAND_STORE && cpu.useZone)
1330 core_write_zone (address, data, __func__);
1331 else
1332 core_write (address, data, __func__);
1333 sim_debug (DBG_FINAL, & cpu_dev,
1334 "Write(Actual) Write: abs address=%08o writeData=%012"PRIo64"\n",
1335 address, data);
1336 # if defined(TESTING)
1337 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write AB");
1338 HDBGMWrite (address, data, "Write AB");
1339 # endif
1340 return;
1341 }
1342 }
1343
1344 case APPEND_mode: {
1345 B29:
1346 if (isBAR) {
1347 cpu.TPR.CA = get_BAR_address (cpup, address);
1348 cpu.TPR.TSR = cpu.PPR.PSR;
1349 cpu.TPR.TRR = cpu.PPR.PRR;
1350 cpu.iefpFinalAddress = do_append_cycle (cpup, cyctyp, & data, 1);
1351 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1352 "Write(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n",
1353 cpu.iefpFinalAddress, data);
1354 # if defined(TESTING)
1355 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write BR");
1356 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write BR");
1357 # endif
1358 return;
1359 } else {
1360 cpu.iefpFinalAddress = do_append_cycle (cpup, cyctyp, & data, 1);
1361 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1362 "Write(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n",
1363 cpu.iefpFinalAddress, data);
1364 # if defined(TESTING)
1365 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write");
1366 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write");
1367 # endif
1368 return;
1369 }
1370 }
1371 }
1372 }
1373 #endif
1374
1375 #if !defined(OLDAPP)
1376 void WriteAPUDataStore (cpu_state_t * cpup, word18 address, word36 data) {
1377 cpu.TPR.CA = cpu.iefpFinalAddress = address;
1378
1379 bool isBAR = get_bar_mode (cpup);
1380
1381 if (cpu.cu.XSF || cpu.currentInstruction.b29)
1382 goto B29;
1383
1384 switch (get_addr_mode (cpup)) {
1385 case ABSOLUTE_mode: {
1386 if (isBAR) {
1387 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1388 set_apu_status (cpup, apuStatus_FABS);
1389 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1390 core_write (cpup, cpu.iefpFinalAddress, data, __func__);
1391 sim_debug (DBG_FINAL, & cpu_dev,
1392 "WriteAPUDataStore(Actual) Write: bar address=%08o writeData=%012"PRIo64"\n",
1393 address, data);
1394 # if defined(TESTING)
1395 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "WriteAPUDataStore ABBR");
1396 HDBGMWrite (cpu.iefpFinalAddress, data, "WriteAPUDataStore ABBR");
1397 # endif
1398 return;
1399 } else {
1400 set_apu_status (cpup, apuStatus_FABS);
1401 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1402 core_write (cpup, address, data, __func__);
1403 sim_debug (DBG_FINAL, & cpu_dev,
1404 "WriteAPUDataStore(Actual) Write: abs address=%08o writeData=%012"PRIo64"\n",
1405 address, data);
1406 # if defined(TESTING)
1407 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "WriteAPUDataStore AB");
1408 HDBGMWrite (address, data, "WriteAPUDataStore AB");
1409 # endif
1410 return;
1411 }
1412 }
1413
1414 case APPEND_mode: {
1415 B29:
1416 if (isBAR) {
1417 cpu.TPR.CA = get_BAR_address (cpup, address);
1418 cpu.TPR.TSR = cpu.PPR.PSR;
1419 cpu.TPR.TRR = cpu.PPR.PRR;
1420 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, & data, 1);
1421 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1422 "WriteAPUDataStore(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n",
1423 cpu.iefpFinalAddress, data);
1424 # if defined(TESTING)
1425 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteAPUDataStore BR");
1426 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore BR");
1427 # endif
1428 return;
1429 } else {
1430 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, & data, 1);
1431 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1432 "WriteAPUDataStore(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n",
1433 cpu.iefpFinalAddress, data);
1434 # if defined(TESTING)
1435 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteAPUDataStore");
1436 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore");
1437 # endif
1438 return;
1439 }
1440 }
1441 }
1442 }
1443
1444 void WriteOperandStore (cpu_state_t * cpup, word18 address, word36 data) {
1445 cpu.TPR.CA = cpu.iefpFinalAddress = address;
1446
1447 bool isBAR = get_bar_mode (cpup);
1448
1449 if (cpu.cu.XSF || cpu.currentInstruction.b29)
1450 goto B29;
1451
1452 switch (get_addr_mode (cpup)) {
1453 case ABSOLUTE_mode: {
1454 if (isBAR) {
1455 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1456 set_apu_status (cpup, apuStatus_FABS);
1457 fauxDoAppendCycle (cpup, OPERAND_STORE);
1458 if (cpu.useZone)
1459 core_write_zone (cpup, cpu.iefpFinalAddress, data, __func__);
1460 else
1461 core_write (cpup, cpu.iefpFinalAddress, data, __func__);
1462 sim_debug (DBG_FINAL, & cpu_dev,
1463 "WriteOperandStore(Actual) Write: bar address=%08o writeData=%012"PRIo64"\n",
1464 address, data);
1465 # if defined(TESTING)
1466 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "WriteOperandStore ABBR");
1467 HDBGMWrite (cpu.iefpFinalAddress, data, "WriteOperandStore ABBR");
1468 # endif
1469 return;
1470 } else {
1471 set_apu_status (cpup, apuStatus_FABS);
1472 fauxDoAppendCycle (cpup, OPERAND_STORE);
1473 if (cpu.useZone)
1474 core_write_zone (cpup, address, data, __func__);
1475 else
1476 core_write (cpup, address, data, __func__);
1477 sim_debug (DBG_FINAL, & cpu_dev,
1478 "WriteOperandStore(Actual) Write: abs address=%08o writeData=%012"PRIo64"\n",
1479 address, data);
1480 # if defined(TESTING)
1481 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "WriteOperandStore AB");
1482 HDBGMWrite (address, data, "WriteOperandStore AB");
1483 # endif
1484 return;
1485 }
1486 }
1487
1488 case APPEND_mode: {
1489 B29:
1490 if (isBAR) {
1491 cpu.TPR.CA = get_BAR_address (cpup, address);
1492 cpu.TPR.TSR = cpu.PPR.PSR;
1493 cpu.TPR.TRR = cpu.PPR.PRR;
1494 cpu.iefpFinalAddress = doAppendCycleOperandStore (cpup, & data, 1);
1495 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1496 "WriteOperandStore(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n",
1497 cpu.iefpFinalAddress, data);
1498 # if defined(TESTING)
1499 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteOperandStore BR");
1500 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore BR");
1501 # endif
1502 return;
1503 } else {
1504 cpu.iefpFinalAddress = doAppendCycleOperandStore (cpup, & data, 1);
1505 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1506 "WriteOperandStore(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n",
1507 cpu.iefpFinalAddress, data);
1508 # if defined(TESTING)
1509 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteOperandStore");
1510 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore");
1511 # endif
1512 return;
1513 }
1514 }
1515 }
1516 }
1517 #endif
1518
1519 #if defined(OLDAPP)
1520 void Write2 (cpu_state_t * cpup, word18 address, word36 * data, processor_cycle_type cyctyp)
1521 {
1522 cpu.TPR.CA = cpu.iefpFinalAddress = address;
1523 bool isBAR = get_bar_mode ();
1524
1525 if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29))
1526 goto B29;
1527
1528 switch (get_addr_mode ())
1529 {
1530 case ABSOLUTE_mode:
1531 {
1532 if (isBAR)
1533 {
1534 cpu.iefpFinalAddress = get_BAR_address (address);
1535 set_apu_status (apuStatus_FABS);
1536 fauxDoAppendCycle (cyctyp);
1537 core_write2 (cpu.iefpFinalAddress, data [0], data [1],
1538 __func__);
1539 # if defined(TESTING)
1540 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write2 ABBR");
1541 HDBGMWrite (cpu.iefpFinalAddress, data [0], "Write2 ABBR evn");
1542 HDBGMWrite (cpu.iefpFinalAddress+1, data [1], "Write2 ABBR odd");
1543 # endif
1544 sim_debug (DBG_FINAL, & cpu_dev,
1545 "Write2 (Actual) Write: bar address=%08o "
1546 "writeData=%012"PRIo64" %012"PRIo64"\n",
1547 address, data [0], data [1]);
1548 return;
1549 }
1550 else
1551 {
1552 set_apu_status (apuStatus_FABS);
1553 fauxDoAppendCycle (cyctyp);
1554 core_write2 (address, data [0], data [1], __func__);
1555 sim_debug (DBG_FINAL, & cpu_dev,
1556 "Write2 (Actual) Write: abs address=%08o "
1557 "writeData=%012"PRIo64" %012"PRIo64"\n",
1558 address, data [0], data [1]);
1559 # if defined(TESTING)
1560 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write2 AB");
1561 HDBGMWrite (address, data [0], "Write2 AB evn");
1562 HDBGMWrite (address+1, data [1], "Write2 AB odd");
1563 # endif
1564 return;
1565 }
1566 }
1567
1568 case APPEND_mode:
1569 {
1570 B29:
1571 if (isBAR)
1572 {
1573 cpu.TPR.CA = get_BAR_address (address);
1574 cpu.TPR.TSR = cpu.PPR.PSR;
1575 cpu.TPR.TRR = cpu.PPR.PRR;
1576 cpu.iefpFinalAddress = do_append_cycle (cyctyp, data, 2);
1577 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1578 "Write2 (Actual) Write: bar iefpFinalAddress=%08o "
1579 "writeData=%012"PRIo64" %012"PRIo64"\n",
1580 address, data [0], data [1]);
1581 # if defined(TESTING)
1582 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2 BR");
1583 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 BR evn");
1584 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 BR odd");
1585 # endif
1586 return;
1587 }
1588 else
1589 {
1590 cpu.iefpFinalAddress = do_append_cycle (cyctyp, data, 2);
1591 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1592 "Write2 (Actual) Write: iefpFinalAddress=%08o "
1593 "writeData=%012"PRIo64" %012"PRIo64"\n",
1594 address, data [0], data [1]);
1595 # if defined(TESTING)
1596 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2");
1597 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 evn");
1598 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 odd");
1599 # endif
1600 return;
1601 }
1602 }
1603 }
1604 }
1605 #endif
1606
1607 #if !defined(OLDAPP)
1608 void Write2OperandStore (cpu_state_t * cpup, word18 address, word36 * data) {
1609 cpu.TPR.CA = cpu.iefpFinalAddress = address;
1610 bool isBAR = get_bar_mode (cpup);
1611
1612 if (cpu.cu.XSF || cpu.currentInstruction.b29)
1613 goto B29;
1614
1615 switch (get_addr_mode (cpup)) {
1616 case ABSOLUTE_mode: {
1617 if (isBAR) {
1618 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1619 set_apu_status (cpup, apuStatus_FABS);
1620 fauxDoAppendCycle (cpup, OPERAND_STORE);
1621 core_write2 (cpup, cpu.iefpFinalAddress, data [0], data [1], __func__);
1622 # if defined(TESTING)
1623 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write2OperandStore ABBR");
1624 HDBGMWrite (cpu.iefpFinalAddress, data [0], "Write2OperandStore ABBR evn");
1625 HDBGMWrite (cpu.iefpFinalAddress+1, data [1], "Write2OperandStore ABBR odd");
1626 # endif
1627 sim_debug (DBG_FINAL, & cpu_dev,
1628 "Write2OperandStore (Actual) Write: bar address=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n",
1629 address, data [0], data [1]);
1630 return;
1631 } else {
1632 set_apu_status (cpup, apuStatus_FABS);
1633 fauxDoAppendCycle (cpup, OPERAND_STORE);
1634 core_write2 (cpup, address, data [0], data [1], __func__);
1635 sim_debug (DBG_FINAL, & cpu_dev,
1636 "Write2OperandStore (Actual) Write: abs address=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n",
1637 address, data [0], data [1]);
1638 # if defined(TESTING)
1639 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write2OperandStore AB");
1640 HDBGMWrite (address, data [0], "Write2OperandStore AB evn");
1641 HDBGMWrite (address+1, data [1], "Write2OperandStore AB odd");
1642 # endif
1643 return;
1644 }
1645 }
1646
1647 case APPEND_mode: {
1648 B29:
1649 if (isBAR) {
1650 cpu.TPR.CA = get_BAR_address (cpup, address);
1651 cpu.TPR.TSR = cpu.PPR.PSR;
1652 cpu.TPR.TRR = cpu.PPR.PRR;
1653 cpu.iefpFinalAddress = doAppendCycleOperandStore (cpup, data, 2);
1654 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1655 "Write2OperandStore (Actual) Write: bar iefpFinalAddress=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n",
1656 address, data [0], data [1]);
1657 # if defined(TESTING)
1658 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2OperandStore BR");
1659 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore BR evn");
1660 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore BR odd");
1661 # endif
1662 return;
1663 } else {
1664 cpu.iefpFinalAddress = doAppendCycleOperandStore (cpup, data, 2);
1665 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1666 "Write2OperandStore (Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n",
1667 address, data [0], data [1]);
1668 # if defined(TESTING)
1669 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2OperandStore");
1670 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore evn");
1671 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore odd");
1672 # endif
1673 return;
1674 }
1675 }
1676 }
1677 }
1678 #endif
1679
1680 void Write1 (cpu_state_t * cpup, word18 address, word36 data, bool isAR)
1681 {
1682 cpu.TPR.CA = cpu.iefpFinalAddress = address;
1683 bool isBAR = get_bar_mode (cpup);
1684 if (isAR || cpu.cu.XSF )
1685 goto B29;
1686 switch (get_addr_mode (cpup))
1687 {
1688 case ABSOLUTE_mode:
1689 {
1690 if (isBAR)
1691 {
1692 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1693 set_apu_status (cpup, apuStatus_FABS);
1694 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1695 core_write (cpup, cpu.iefpFinalAddress, data, __func__);
1696 sim_debug (DBG_FINAL, & cpu_dev,
1697 "Write1(Actual) Write: bar address=%08o "
1698 "writeData=%012"PRIo64"\n",
1699 address, data);
1700 #if defined(TESTING)
1701 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write1 ABBR");
1702 HDBGMWrite (cpu.iefpFinalAddress, data, "Write1 ABBR");
1703 #endif
1704 return;
1705 }
1706 else
1707 {
1708 set_apu_status (cpup, apuStatus_FABS);
1709 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1710 core_write (cpup, address, data, __func__);
1711 sim_debug (DBG_FINAL, & cpu_dev,
1712 "Write1(Actual) Write: abs address=%08o "
1713 "writeData=%012"PRIo64"\n",
1714 address, data);
1715 #if defined(TESTING)
1716 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write1 AB");
1717 HDBGMWrite (address, data, "Write1 AB");
1718 #endif
1719 return;
1720 }
1721 }
1722
1723 case APPEND_mode:
1724 {
1725 B29:
1726 if (isBAR)
1727 {
1728 cpu.TPR.CA = get_BAR_address (cpup, address);
1729 cpu.TPR.TSR = cpu.PPR.PSR;
1730 cpu.TPR.TRR = cpu.PPR.PRR;
1731
1732 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, & data, 1);
1733 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1734 "Write8(Actual) Write: bar iefpFinalAddress="
1735 "%08o writeData=%012"PRIo64"\n",
1736 cpu.iefpFinalAddress, data);
1737 #if defined(TESTING)
1738 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write1 BR");
1739 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1 BR");
1740 #endif
1741 return;
1742 }
1743 else
1744 {
1745
1746 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, & data, 1);
1747 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1748 "Write(Actual) Write: iefpFinalAddress=%08o "
1749 "writeData=%012"PRIo64"\n",
1750 cpu.iefpFinalAddress, data);
1751 #if defined(TESTING)
1752 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write1");
1753 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1");
1754 #endif
1755 return;
1756 }
1757 }
1758 }
1759 }
1760
1761 void Write8 (cpu_state_t * cpup, word18 address, word36 * data, bool isAR)
1762 {
1763 address &= paragraphMask;
1764 cpu.TPR.CA = cpu.iefpFinalAddress = address;
1765
1766 bool isBAR = get_bar_mode (cpup);
1767
1768 if (isAR || cpu.cu.XSF )
1769 goto B29;
1770
1771 switch (get_addr_mode (cpup))
1772 {
1773 case ABSOLUTE_mode:
1774 {
1775 if (isBAR)
1776 {
1777 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1778 set_apu_status (cpup, apuStatus_FABS);
1779 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1780 core_writeN (cpup, cpu.iefpFinalAddress, data, 8, __func__);
1781 if_sim_debug (DBG_FINAL, & cpu_dev)
1782 {
1783 for (uint i = 0; i < 8; i ++)
1784 sim_debug (DBG_FINAL, & cpu_dev,
1785 "Write8(Actual) Write: bar address=%08o "
1786 "writeData=%012"PRIo64"\n",
1787 address + i, data [i]);
1788 }
1789 #if defined(TESTING)
1790 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write8 ABBR");
1791 for (uint i = 0; i < 8; i ++)
1792 HDBGMWrite (cpu.iefpFinalAddress + i, data [i], "Write8 ABBR");
1793 #endif
1794 return;
1795 }
1796 else
1797 {
1798 set_apu_status (cpup, apuStatus_FABS);
1799 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1800 core_writeN (cpup, address, data, 8, __func__);
1801 if_sim_debug (DBG_FINAL, & cpu_dev)
1802 {
1803 for (uint i = 0; i < 8; i ++)
1804 sim_debug (DBG_FINAL, & cpu_dev,
1805 "Write8(Actual) Write: abs address=%08o "
1806 "writeData=%012"PRIo64"\n",
1807 address + i, data [i]);
1808 }
1809 #if defined(TESTING)
1810 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write8 AB");
1811 for (uint i = 0; i < 8; i ++)
1812 HDBGMWrite (address + i, data [i], "Write8 AB");
1813 #endif
1814 return;
1815 }
1816 }
1817
1818 case APPEND_mode:
1819 {
1820 B29:
1821 if (isBAR)
1822 {
1823 cpu.TPR.CA = get_BAR_address (cpup, address);
1824 cpu.TPR.TSR = cpu.PPR.PSR;
1825 cpu.TPR.TRR = cpu.PPR.PRR;
1826
1827 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, data, 8);
1828 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1829 {
1830 for (uint i = 0; i < 8; i ++)
1831 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1832 "Write8(Actual) Write: bar iefpFinalAddress="
1833 "%08o writeData=%012"PRIo64"\n",
1834 cpu.iefpFinalAddress + i, data [i]);
1835 }
1836 #if defined(TESTING)
1837 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write8 BR");
1838 for (uint i = 0; i < 8; i ++)
1839 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8 BR");
1840 #endif
1841
1842 return;
1843 }
1844 else
1845 {
1846
1847 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, data, 8);
1848 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1849 {
1850 for (uint i = 0; i < 8; i ++)
1851 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1852 "Write8(Actual) Write: iefpFinalAddress=%08o "
1853 "writeData=%012"PRIo64"\n",
1854 cpu.iefpFinalAddress + i, data [i]);
1855 }
1856 #if defined(TESTING)
1857 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write8");
1858 for (uint i = 0; i < 8; i ++)
1859 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8");
1860 #endif
1861
1862 return;
1863 }
1864 }
1865 }
1866 }
1867
1868 void Write16 (cpu_state_t * cpup, word18 address, word36 * data)
1869 {
1870 address &= paragraphMask;
1871 Write8 (cpup, address, data, cpu.currentInstruction.b29);
1872 Write8 (cpup, address + 8, data + 8, cpu.currentInstruction.b29);
1873 }
1874
1875 void Write32 (cpu_state_t * cpup, word18 address, word36 * data)
1876 {
1877
1878
1879 address &= 077777740;
1880 Write8 (cpup, address, data, cpu.currentInstruction.b29);
1881 Write8 (cpup, address + 8, data + 8, cpu.currentInstruction.b29);
1882 Write8 (cpup, address + 16, data + 16, cpu.currentInstruction.b29);
1883 Write8 (cpup, address + 24, data + 24, cpu.currentInstruction.b29);
1884 }
1885
1886 void WritePage (cpu_state_t * cpup, word18 address, word36 * data, bool isAR)
1887 {
1888 if ((address & PGMK) != 0)
1889 {
1890 sim_warn ("WritePage not on boundary %06o\n", address);
1891 }
1892 address &= (word18) ~PGMK;
1893 cpu.TPR.CA = cpu.iefpFinalAddress = address;
1894
1895 bool isBAR = get_bar_mode (cpup);
1896
1897 if (isAR || cpu.cu.XSF )
1898 goto B29;
1899
1900 switch (get_addr_mode (cpup))
1901 {
1902 case ABSOLUTE_mode:
1903 {
1904 if (isBAR)
1905 {
1906 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1907 set_apu_status (cpup, apuStatus_FABS);
1908 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1909 core_writeN (cpup, cpu.iefpFinalAddress, data, PGSZ, __func__);
1910 if_sim_debug (DBG_FINAL, & cpu_dev)
1911 {
1912 for (uint i = 0; i < PGSZ; i ++)
1913 sim_debug (DBG_FINAL, & cpu_dev,
1914 "WritePage(Actual) Write: bar address="
1915 "%08o writeData=%012"PRIo64"\n",
1916 address + i, data [i]);
1917 }
1918 #if defined(TESTING)
1919 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "WritePage ABBR");
1920 for (uint i = 0; i < PGSZ; i ++)
1921 HDBGMWrite (cpu.iefpFinalAddress + i, data [i], "WritePage ABBR");
1922 #endif
1923 return;
1924 }
1925 else
1926 {
1927 set_apu_status (cpup, apuStatus_FABS);
1928 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1929 core_writeN (cpup, address, data, PGSZ, __func__);
1930 if_sim_debug (DBG_FINAL, & cpu_dev)
1931 {
1932 for (uint i = 0; i < PGSZ; i ++)
1933 sim_debug (DBG_FINAL, & cpu_dev,
1934 "WritePage(Actual) Write: abs address="
1935 "%08o writeData=%012"PRIo64"\n",
1936 address + i, data [i]);
1937 }
1938 #if defined(TESTING)
1939 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "WritePage AB");
1940 for (uint i = 0; i < PGSZ; i ++)
1941 HDBGMWrite (address + i, data [i], "WritePage AB");
1942 #endif
1943 return;
1944 }
1945 }
1946
1947 case APPEND_mode:
1948 {
1949 B29:
1950 if (isBAR)
1951 {
1952 cpu.TPR.CA = get_BAR_address (cpup, address);
1953 cpu.TPR.TSR = cpu.PPR.PSR;
1954 cpu.TPR.TRR = cpu.PPR.PRR;
1955
1956 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, data, PGSZ);
1957 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1958 {
1959 for (uint i = 0; i < PGSZ; i ++)
1960 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1961 "WritePage(Actual) Write: bar "
1962 "iefpFinalAddress=%08o writeData=%012"PRIo64
1963 "\n",
1964 cpu.iefpFinalAddress + i, data [i]);
1965 }
1966 #if defined(TESTING)
1967 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WritePage BR");
1968 for (uint i = 0; i < PGSZ; i ++)
1969 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage BR");
1970 #endif
1971 return;
1972 }
1973 else
1974 {
1975
1976 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, data, PGSZ);
1977 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1978 {
1979 for (uint i = 0; i < PGSZ; i ++)
1980 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1981 "WritePage(Actual) Write: iefpFinalAddress="
1982 "%08o writeData=%012"PRIo64"\n",
1983 cpu.iefpFinalAddress + i, data [i]);
1984 }
1985 #if defined(TESTING)
1986 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WritePage");
1987 for (uint i = 0; i < PGSZ; i ++)
1988 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage");
1989 #endif
1990
1991 return;
1992 }
1993 }
1994 }
1995 }
1996
1997 void ReadIndirect (cpu_state_t * cpup)
1998 {
1999 if (cpu.TPR.CA & 1)
2000 {
2001 ReadIndirectWordFetch (cpup, cpu.TPR.CA, cpu.itxPair);
2002 cpu.itxPair[1] = MASK36;
2003 }
2004 else
2005 {
2006 Read2IndirectWordFetch (cpup, cpu.TPR.CA, cpu.itxPair);
2007 }
2008 }