root/src/dps8/dps8_iefp.c

/* */

DEFINITIONS

1. Read
2. ReadAPUDataRead
3. ReadOperandRead
4. ReadOperandRMW
5. ReadAPUDataRMW
6. ReadInstructionFetch
7. ReadIndirectWordFetch
8. Read2
9. Read2OperandRead
10. Read2OperandRMW
11. Read2InstructionFetch
12. Read2RTCDOperandFetch
13. Read2IndirectWordFetch
14. Read8
15. Read16
16. ReadPage
17. Write
18. WriteAPUDataStore
19. WriteOperandStore
20. Write2
21. Write2OperandStore
22. Write1
23. Write8
24. Write16
25. Write32
26. WritePage
27. ReadIndirect

   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * SPDX-License-Identifier: Multics
   5  * scspell-id: 755f1556-f62e-11ec-8184-80ee73e9b8e7
   6  *
   7  * ---------------------------------------------------------------------------
   8  *
   9  * Copyright (c) 2007-2013 Michael Mondy
  10  * Copyright (c) 2012-2016 Harry Reed
  11  * Copyright (c) 2013-2016 Charles Anthony
  12  * Copyright (c) 2015 Eric Swenson
  13  * Copyright (c) 2017 Michal Tomek
  14  * Copyright (c) 2021-2025 The DPS8M Development Team
  15  *
  16  * This software is made available under the terms of the ICU License.
  17  * See the LICENSE.md file at the top-level directory of this distribution.
  18  *
  19  * ---------------------------------------------------------------------------
  20  *
  21  * This source file may contain code comments that adapt, include, and/or
  22  * incorporate Multics program code and/or documentation distributed under
  23  * the Multics License.  In the event of any discrepancy between code
  24  * comments herein and the original Multics materials, the original Multics
  25  * materials should be considered authoritative unless otherwise noted.
  26  * For more details and historical background, see the LICENSE.md file at
  27  * the top-level directory of this distribution.
  28  *
  29  * ---------------------------------------------------------------------------
  30  */
  31 
  32 //-V::536
  33 
  34 #include "dps8.h"
  35 #include "dps8_sys.h"
  36 #include "dps8_iom.h"
  37 #include "dps8_cable.h"
  38 #include "dps8_cpu.h"
  39 #include "dps8_faults.h"
  40 #include "dps8_scu.h"
  41 #include "dps8_append.h"
  42 #include "dps8_iefp.h"
  43 #include "dps8_addrmods.h"
  44 #include "dps8_utils.h"
  45 
  46 #define DBG_CTR cpu.cycleCnt
  47 
  48 // new Read/Write stuff ...
  49 
  50 #if defined(OLDAPP)
  51 void Read (cpu_state_t * cpup, word18 address, word36 * result, processor_cycle_type cyctyp)
     /*  */
  52   {
  53     cpu.TPR.CA = cpu.iefpFinalAddress = address;
  54     bool isBAR = get_bar_mode (cpup);
  55 
  56     //if (get_went_appending () ||
  57     if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29))
  58       {
  59         goto B29;
  60       }
  61 
  62     switch (get_addr_mode (cpup))
  63       {
  64         case ABSOLUTE_mode:
  65           {
  66             if (isBAR)
  67               {
  68                 set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
  69                 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
  70                 fauxDoAppendCycle (cpup, cyctyp);
  71 # if defined(LOCKLESS)
  72                 if (cyctyp == OPERAND_RMW || cyctyp == APU_DATA_RMW)
  73                   core_read_lock (cpup, cpu.iefpFinalAddress, result, __func__);
  74                 else
  75                   core_read (cpup, cpu.iefpFinalAddress, result, __func__);
  76 # else
  77                 core_read (cpup, cpu.iefpFinalAddress, result, __func__);
  78 # endif
  79                 sim_debug (DBG_FINAL, & cpu_dev,
  80                            "Read (Actual) Read:       bar address=%08o  "
  81                            "readData=%012"PRIo64"\r\n", address, *result);
  82 # if defined(TESTING)
  83                 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read ABS BAR");
  84                 HDBGMRead (cpu.iefpFinalAddress, * result, "Read ABS BAR");
  85 # endif
  86                 return;
  87               }
  88             else
  89               {
  90                 set_apu_status (cpup, apuStatus_FABS);
  91                 fauxDoAppendCycle (cpup, cyctyp);
  92 # if defined(LOCKLESS)
  93                 if (cyctyp == OPERAND_RMW || cyctyp == APU_DATA_RMW)
  94                   core_read_lock (cpup, address, result, __func__);
  95                 else
  96                   core_read (cpup, address, result, __func__);
  97 # else
  98                 core_read (cpup, address, result, __func__);
  99 # endif
 100                 sim_debug (DBG_FINAL, & cpu_dev,
 101                            "Read (Actual) Read:       abs address=%08o  "
 102                            "readData=%012"PRIo64"\r\n", address, *result);
 103 # if defined(TESTING)
 104                 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read ABS");
 105                 HDBGMRead (address, * result, "Read ABS");
 106 # endif
 107                 return;
 108               }
 109           }
 110 
 111         case APPEND_mode:
 112           {
 113 B29:;
 114             if (isBAR)
 115               {
 116                 cpu.TPR.CA = get_BAR_address (address);
 117                 cpu.TPR.TSR = cpu.PPR.PSR;
 118                 cpu.TPR.TRR = cpu.PPR.PRR;
 119                 cpu.iefpFinalAddress = do_append_cycle (cpup, cyctyp, result, 1);
 120                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 121                            "Read (Actual) Read:  bar iefpFinalAddress=%08o  "
 122                            "readData=%012"PRIo64"\r\n",
 123                            cpu.iefpFinalAddress, * result);
 124 # if defined(TESTING)
 125                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read BAR");
 126                 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read BAR");
 127 # endif
 128 
 129                 return;
 130               }
 131             else
 132               {
 133                 cpu.iefpFinalAddress = do_append_cycle (cpup, cyctyp, result, 1);
 134                 // XXX Don't trace Multics idle loop
 135                 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
 136                   {
 137                     sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 138                                "Read (Actual) Read:  iefpFinalAddress=%08o  "
 139                                "readData=%012"PRIo64"\r\n",
 140                                cpu.iefpFinalAddress, * result);
 141 # if defined(TESTING)
 142                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read");
 143                     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read");
 144 # endif
 145                   }
 146               }
 147             return;
 148           }
 149       }
 150     return ;//SCPE_UNK;
 151   }
 152 #endif // OLDAPP
 153 
 154 #if !defined(OLDAPP)
 155 void ReadAPUDataRead (cpu_state_t * cpup, word18 address, word36 * result) {
     /*  */
 156   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 157   bool isBAR = get_bar_mode (cpup);
 158 
 159   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 160     goto B29;
 161 
 162   switch (get_addr_mode (cpup)) {
 163     case ABSOLUTE_mode: {
 164       if (isBAR) {
 165         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
 166         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
 167         fauxDoAppendCycle (cpup, APU_DATA_READ);
 168         core_read (cpup, cpu.iefpFinalAddress, result, __func__);
 169         sim_debug (DBG_FINAL, & cpu_dev,
 170                    "ReadAPUDataRead (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\r\n",
 171                    address, *result);
 172 # if defined(TESTING)
 173         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadAPUDataRead ABS BAR");
 174         HDBGMRead (cpu.iefpFinalAddress, * result, "ReadAPUDataRead ABS BAR");
 175 # endif
 176         return;
 177       } else {
 178         set_apu_status (cpup, apuStatus_FABS);
 179         fauxDoAppendCycle (cpup, APU_DATA_READ);
 180         core_read (cpup, address, result, __func__);
 181         sim_debug (DBG_FINAL, & cpu_dev,
 182                    "ReadAPUDataRead (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\r\n",
 183                    address, *result);
 184 # if defined(TESTING)
 185         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadAPUDataRead ABS");
 186         HDBGMRead (address, * result, "ReadAPUDataRead ABS");
 187 # endif
 188         return;
 189       }
 190     }
 191 
 192     case APPEND_mode: {
 193 B29:;
 194       if (isBAR) {
 195         cpu.TPR.CA = get_BAR_address (cpup, address);
 196         cpu.TPR.TSR = cpu.PPR.PSR;
 197         cpu.TPR.TRR = cpu.PPR.PRR;
 198         cpu.iefpFinalAddress = doAppendCycleAPUDataRead (cpup, result, 1);
 199         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 200                    "ReadAPUDataRead (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\r\n",
 201                    cpu.iefpFinalAddress, * result);
 202 # if defined(TESTING)
 203         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRead BAR");
 204         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead BAR");
 205 # endif
 206         return;
 207       } else {
 208         cpu.iefpFinalAddress = doAppendCycleAPUDataRead (cpup, result, 1);
 209         // XXX Don't trace Multics idle loop
 210         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
 211           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 212                      "ReadAPUDataRead (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\r\n",
 213                      cpu.iefpFinalAddress, * result);
 214 # if defined(TESTING)
 215           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRead");
 216           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead");
 217 # endif
 218         }
 219         return;
 220       }
 221     }
 222   }
 223 }
 224 
 225 void ReadOperandRead (cpu_state_t * cpup, word18 address, word36 * result) {
     /*  */
 226   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 227   bool isBAR = get_bar_mode (cpup);
 228 
 229   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 230     goto B29;
 231 
 232   switch (get_addr_mode (cpup)) {
 233     case ABSOLUTE_mode: {
 234       if (isBAR) {
 235         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
 236         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
 237         fauxDoAppendCycle (cpup, OPERAND_READ);
 238         core_read (cpup, cpu.iefpFinalAddress, result, __func__);
 239         sim_debug (DBG_FINAL, & cpu_dev,
 240                    "readOperandRead (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\r\n",
 241                    address, *result);
 242 # if defined(TESTING)
 243         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "readOperandRead ABS BAR");
 244         HDBGMRead (cpu.iefpFinalAddress, * result, "readOperandRead ABS BAR");
 245 # endif
 246         return;
 247       } else {
 248         set_apu_status (cpup, apuStatus_FABS);
 249         fauxDoAppendCycle (cpup, OPERAND_READ);
 250         core_read (cpup, address, result, __func__);
 251         sim_debug (DBG_FINAL, & cpu_dev,
 252                    "readOperandRead (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\r\n",
 253                    address, *result);
 254 # if defined(TESTING)
 255         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "readOperandRead ABS");
 256         HDBGMRead (address, * result, "readOperandRead ABS");
 257 # endif
 258         return;
 259       }
 260     }
 261 
 262     case APPEND_mode: {
 263 B29:;
 264       if (isBAR) {
 265         cpu.TPR.CA = get_BAR_address (cpup, address);
 266         cpu.TPR.TSR = cpu.PPR.PSR;
 267         cpu.TPR.TRR = cpu.PPR.PRR;
 268         cpu.iefpFinalAddress = doAppendCycleOperandRead (cpup, result, 1);
 269         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 270                    "readOperandRead (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\r\n",
 271                    cpu.iefpFinalAddress, * result);
 272 # if defined(TESTING)
 273         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "readOperandRead BAR");
 274         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead BAR");
 275 # endif
 276 
 277         return;
 278       } else {
 279         cpu.iefpFinalAddress = doAppendCycleOperandRead (cpup, result, 1);
 280         // XXX Don't trace Multics idle loop
 281         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
 282           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 283                      "readOperandRead (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\r\n",
 284                      cpu.iefpFinalAddress, * result);
 285 # if defined(TESTING)
 286           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "readOperandRead");
 287           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead");
 288 # endif
 289         }
 290         return;
 291       }
 292     }
 293   }
 294 }
 295 
 296 # if defined(LOCKLESS)
 297 void ReadOperandRMW (cpu_state_t * cpup, word18 address, word36 * result) {
     /*  */
 298   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 299   bool isBAR = get_bar_mode (cpup);
 300 
 301   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 302     goto B29;
 303 
 304   switch (get_addr_mode (cpup)) {
 305     case ABSOLUTE_mode: {
 306       if (isBAR) {
 307         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
 308         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
 309         fauxDoAppendCycle (cpup, OPERAND_RMW);
 310         core_read_lock (cpup, cpu.iefpFinalAddress, result, __func__);
 311         sim_debug (DBG_FINAL, & cpu_dev,
 312                    "ReadOperandRMW (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\r\n",
 313                    address, *result);
 314 #  if defined(TESTING)
 315         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadOperandRMW ABS BAR");
 316         HDBGMRead (cpu.iefpFinalAddress, * result, "ReadOperandRMW ABS BAR");
 317 #  endif
 318         return;
 319       } else {
 320         set_apu_status (cpup, apuStatus_FABS);
 321         fauxDoAppendCycle (cpup, OPERAND_RMW);
 322         core_read_lock (cpup, address, result, __func__);
 323         sim_debug (DBG_FINAL, & cpu_dev,
 324                    "ReadOperandRMW (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\r\n",
 325                    address, *result);
 326 #  if defined(TESTING)
 327         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadOperandRMW ABS");
 328         HDBGMRead (address, * result, "ReadOperandRMW ABS");
 329 #  endif
 330         return;
 331       }
 332     }
 333 
 334     case APPEND_mode: {
 335 B29:;
 336       if (isBAR) {
 337         cpu.TPR.CA = get_BAR_address (cpup, address);
 338         cpu.TPR.TSR = cpu.PPR.PSR;
 339         cpu.TPR.TRR = cpu.PPR.PRR;
 340         cpu.iefpFinalAddress = doAppendCycleOperandRMW (cpup, result, 1);
 341         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 342                    "ReadOperandRMW (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\r\n",
 343                    cpu.iefpFinalAddress, * result);
 344 #  if defined(TESTING)
 345         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadOperandRMW BAR");
 346         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW BAR");
 347 #  endif
 348         return;
 349       } else {
 350         cpu.iefpFinalAddress = doAppendCycleOperandRMW (cpup, result, 1);
 351         // XXX Don't trace Multics idle loop
 352         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
 353           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 354                      "ReadOperandRMW (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\r\n",
 355                      cpu.iefpFinalAddress, * result);
 356 #  if defined(TESTING)
 357           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadOperandRMW");
 358           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW");
 359 #  endif
 360         }
 361         return;
 362       }
 363     }
 364   }
 365 }
 366 
 367 void ReadAPUDataRMW (cpu_state_t * cpup, word18 address, word36 * result) {
     /*  */
 368   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 369   bool isBAR = get_bar_mode (cpup);
 370 
 371   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 372     goto B29;
 373 
 374   switch (get_addr_mode (cpup)) {
 375     case ABSOLUTE_mode: {
 376       if (isBAR) {
 377         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
 378         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
 379         fauxDoAppendCycle (cpup, APU_DATA_RMW);
 380         core_read_lock (cpup, cpu.iefpFinalAddress, result, __func__);
 381         sim_debug (DBG_FINAL, & cpu_dev,
 382                    "ReadAPUDataRMW (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\r\n",
 383                    address, *result);
 384 #  if defined(TESTING)
 385         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadAPUDataRMW ABS BAR");
 386         HDBGMRead (cpu.iefpFinalAddress, * result, "ReadAPUDataRMW ABS BAR");
 387 #  endif
 388         return;
 389       } else {
 390         set_apu_status (cpup, apuStatus_FABS);
 391         fauxDoAppendCycle (cpup, APU_DATA_RMW);
 392         core_read_lock (cpup, address, result, __func__);
 393         sim_debug (DBG_FINAL, & cpu_dev,
 394                    "ReadAPUDataRMW (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\r\n",
 395                    address, *result);
 396 #  if defined(TESTING)
 397         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadAPUDataRMW ABS");
 398         HDBGMRead (address, * result, "ReadAPUDataRMW ABS");
 399 #  endif
 400         return;
 401       }
 402     }
 403 
 404     case APPEND_mode: {
 405 B29:;
 406       if (isBAR) {
 407         cpu.TPR.CA = get_BAR_address (cpup, address);
 408         cpu.TPR.TSR = cpu.PPR.PSR;
 409         cpu.TPR.TRR = cpu.PPR.PRR;
 410         cpu.iefpFinalAddress = doAppendCycleAPUDataRMW (cpup, result, 1);
 411         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 412                    "ReadAPUDataRMW (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\r\n",
 413                    cpu.iefpFinalAddress, * result);
 414 #  if defined(TESTING)
 415         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRMW BAR");
 416         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW BAR");
 417 #  endif
 418         return;
 419       } else {
 420         cpu.iefpFinalAddress = doAppendCycleAPUDataRMW (cpup, result, 1);
 421         // XXX Don't trace Multics idle loop
 422         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
 423           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 424                      "ReadAPUDataRMW (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\r\n",
 425                      cpu.iefpFinalAddress, * result);
 426 #  if defined(TESTING)
 427           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRMW");
 428           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW");
 429 #  endif
 430         }
 431         return;
 432       }
 433     }
 434   }
 435   return ;//SCPE_UNK;
 436 }
 437 # endif
 438 
 439 void ReadInstructionFetch (cpu_state_t * cpup, word18 address, word36 * result) {
     /*  */
 440   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 441   bool isBAR = get_bar_mode (cpup);
 442 
 443   if (cpu.cu.XSF)
 444     goto B29;
 445 
 446   switch (get_addr_mode (cpup)) {
 447     case ABSOLUTE_mode: {
 448       if (isBAR) {
 449         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
 450         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
 451         fauxDoAppendCycle (cpup, INSTRUCTION_FETCH);
 452         core_read (cpup, cpu.iefpFinalAddress, result, __func__);
 453         sim_debug (DBG_FINAL, & cpu_dev,
 454                    "ReadInstructionFetch (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\r\n",
 455                    address, *result);
 456 # if defined(TESTING)
 457         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadInstructionFetch ABS BAR");
 458         HDBGMRead (cpu.iefpFinalAddress, * result, "ReadInstructionFetch ABS BAR");
 459 # endif
 460         return;
 461       } else {
 462         set_apu_status (cpup, apuStatus_FABS);
 463         fauxDoAppendCycle (cpup, INSTRUCTION_FETCH);
 464         core_read (cpup, address, result, __func__);
 465         sim_debug (DBG_FINAL, & cpu_dev,
 466                    "ReadInstructionFetch (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\r\n",
 467                    address, *result);
 468 # if defined(TESTING)
 469         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadInstructionFetch ABS");
 470         HDBGMRead (address, * result, "ReadInstructionFetch ABS");
 471 # endif
 472         return;
 473       }
 474     }
 475 
 476     case APPEND_mode: {
 477 B29:;
 478       if (isBAR) {
 479         cpu.TPR.CA = get_BAR_address (cpup, address);
 480         cpu.TPR.TSR = cpu.PPR.PSR;
 481         cpu.TPR.TRR = cpu.PPR.PRR;
 482         cpu.iefpFinalAddress = doAppendCycleInstructionFetch (cpup, result, 1);
 483         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 484                    "ReadInstructionFetch (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\r\n",
 485                    cpu.iefpFinalAddress, * result);
 486 # if defined(TESTING)
 487         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadInstructionFetch BAR");
 488         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch BAR");
 489 # endif
 490         return;
 491       } else {
 492         cpu.iefpFinalAddress = doAppendCycleInstructionFetch (cpup, result, 1);
 493         // XXX Don't trace Multics idle loop
 494         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
 495           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 496                      "ReadInstructionFetch (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\r\n",
 497                      cpu.iefpFinalAddress, * result);
 498 # if defined(TESTING)
 499           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadInstructionFetch");
 500           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch");
 501 # endif
 502         }
 503         return;
 504       }
 505     }
 506   }
 507 }
 508 
 509 void ReadIndirectWordFetch (cpu_state_t * cpup, word18 address, word36 * result) {
     /*  */
 510   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 511   bool isBAR = get_bar_mode (cpup);
 512 
 513   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 514     goto B29;
 515 
 516   switch (get_addr_mode (cpup)) {
 517     case ABSOLUTE_mode: {
 518       if (isBAR) {
 519         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
 520         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
 521         fauxDoAppendCycle (cpup, INDIRECT_WORD_FETCH);
 522         core_read (cpup, cpu.iefpFinalAddress, result, __func__);
 523         sim_debug (DBG_FINAL, & cpu_dev,
 524                    "ReadIndirectWordFetch (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\r\n",
 525                    address, *result);
 526 # if defined(TESTING)
 527         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadIndirectWordFetch ABS BAR");
 528         HDBGMRead (cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch ABS BAR");
 529 # endif
 530         return;
 531       } else {
 532         set_apu_status (cpup, apuStatus_FABS);
 533         fauxDoAppendCycle (cpup, INDIRECT_WORD_FETCH);
 534         core_read (cpup, address, result, __func__);
 535         sim_debug (DBG_FINAL, & cpu_dev,
 536                    "ReadIndirectWordFetch (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\r\n",
 537                    address, *result);
 538 # if defined(TESTING)
 539         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadIndirectWordFetch ABS");
 540         HDBGMRead (address, * result, "ReadIndirectWordFetch ABS");
 541 # endif
 542         return;
 543       }
 544   }
 545 
 546   case APPEND_mode: {
 547 B29:;
 548       if (isBAR) {
 549         cpu.TPR.CA = get_BAR_address (cpup, address);
 550         cpu.TPR.TSR = cpu.PPR.PSR;
 551         cpu.TPR.TRR = cpu.PPR.PRR;
 552         cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (cpup, result, 1);
 553         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 554                    "ReadIndirectWordFetch (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\r\n",
 555                    cpu.iefpFinalAddress, * result);
 556 # if defined(TESTING)
 557         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch BAR");
 558         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch BAR");
 559 # endif
 560         return;
 561       } else {
 562         cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (cpup, result, 1);
 563         // XXX Don't trace Multics idle loop
 564         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
 565           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 566                      "ReadIndirectWordFetch (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\r\n",
 567                      cpu.iefpFinalAddress, * result);
 568 # if defined(TESTING)
 569             HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch");
 570             HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch");
 571 # endif
 572           }
 573           return;
 574         }
 575     }
 576   }
 577 }
 578 #endif // !OLDAPP
 579 
 580 #if defined(OLDAPP)
 581 void Read2 (cpu_state_t * cpup, word18 address, word36 * result, processor_cycle_type cyctyp) {
     /*  */
 582   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 583 
 584   bool isBAR = get_bar_mode (cpup);
 585 
 586   if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29) || cyctyp == RTCD_OPERAND_FETCH) // ISOLTS-886
 587          // Another option would be to set_went_appending in ReadRTCDOp
 588     goto B29;
 589 
 590   switch (get_addr_mode (cpup)) {
 591     case ABSOLUTE_mode: {
 592       if (isBAR) {
 593         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
 594         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
 595 
 596         fauxDoAppendCycle (cpup, cyctyp);
 597         core_read2 (cpup, cpu.iefpFinalAddress, result + 0, result + 1, __func__);
 598         if_sim_debug (DBG_FINAL, & cpu_dev) {
 599             for (uint i = 0; i < 2; i ++)
 600               sim_debug (DBG_FINAL, & cpu_dev,
 601                          "Read2 (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\r\n",
 602                          address + i, result [i]);
 603         }
 604 # if defined(TESTING)
 605         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2 ABBR");
 606         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2 ABBR evn");
 607         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2 ABBR odd");
 608 # endif
 609         return;
 610       } else {
 611         set_apu_status (cpup, apuStatus_FABS);
 612         fauxDoAppendCycle (cpup, cyctyp);
 613         core_read2 (cpup, address, result + 0, result + 1, __func__);
 614         if_sim_debug (DBG_FINAL, & cpu_dev) {
 615           for (uint i = 0; i < 2; i ++)
 616             sim_debug (DBG_FINAL, & cpu_dev,
 617                        "Read2 (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\r\n",
 618                        address + i, result [i]);
 619         }
 620 # if defined(TESTING)
 621         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2 AB");
 622         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2 AB evn");
 623         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2 AB odd");
 624 # endif
 625         return;
 626       }
 627     }
 628 
 629     case APPEND_mode: {
 630 B29:;
 631       if (isBAR) {
 632         cpu.TPR.CA = get_BAR_address (cpup, address);
 633         cpu.TPR.TSR = cpu.PPR.PSR;
 634         cpu.TPR.TRR = cpu.PPR.PRR;
 635         cpu.iefpFinalAddress = do_append_cycle (cpup, cyctyp, result, 2);
 636         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 637           for (uint i = 0; i < 2; i ++)
 638            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 639                       "Read2 (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\r\n",
 640                       cpu.iefpFinalAddress + i, result [i]);
 641         }
 642 # if defined(TESTING)
 643         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR");
 644         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn");
 645         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd");
 646 # endif
 647         return;
 648       } else {
 649         cpu.iefpFinalAddress = do_append_cycle (cpup, cyctyp, result, 2);
 650         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 651           for (uint i = 0; i < 2; i ++)
 652             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 653                        "Read2 (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\r\n",
 654                        cpu.iefpFinalAddress + i, result [i]);
 655         }
 656         if_sim_debug (DBG_FINAL, & cpu_dev) {
 657           if (cyctyp == OPERAND_READ) {
 658             for (uint i = 0; i < 2; i ++)
 659               sim_debug (DBG_FINAL, & cpu_dev,
 660                          "Read2 (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\r\n",
 661                          cpu.iefpFinalAddress + i, result [i]);
 662           }
 663         }
 664 # if defined(TESTING)
 665         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2");
 666         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn");
 667         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd");
 668 # endif
 669       }
 670       return;
 671     }
 672   }
 673 }
 674 #endif // OLDAPP
 675 
 676 #if !defined(OLDAPP)
 677 void Read2OperandRead (cpu_state_t * cpup, word18 address, word36 * result) {
     /*  */
 678   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 679 
 680   bool isBAR = get_bar_mode (cpup);
 681 
 682   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 683     goto B29;
 684 
 685   switch (get_addr_mode (cpup)) {
 686     case ABSOLUTE_mode: {
 687       if (isBAR) {
 688         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
 689         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
 690 
 691         fauxDoAppendCycle (cpup, OPERAND_READ);
 692         core_read2 (cpup, cpu.iefpFinalAddress, result + 0, result + 1, __func__);
 693         if_sim_debug (DBG_FINAL, & cpu_dev) {
 694             for (uint i = 0; i < 2; i ++)
 695               sim_debug (DBG_FINAL, & cpu_dev,
 696                          "Read2OperandRead (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\r\n",
 697                          address + i, result [i]);
 698         }
 699 # if defined(TESTING)
 700         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2OperandRead ABBR");
 701         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRead ABBR evn");
 702         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRead ABBR odd");
 703 # endif
 704         return;
 705       } else {
 706         set_apu_status (cpup, apuStatus_FABS);
 707         fauxDoAppendCycle (cpup, OPERAND_READ);
 708         core_read2 (cpup, address, result + 0, result + 1, __func__);
 709         if_sim_debug (DBG_FINAL, & cpu_dev) {
 710           for (uint i = 0; i < 2; i ++)
 711             sim_debug (DBG_FINAL, & cpu_dev,
 712                        "Read2OperandRead (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\r\n",
 713                        address + i, result [i]);
 714         }
 715 # if defined(TESTING)
 716         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2OperandRead AB");
 717         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRead AB evn");
 718         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRead AB odd");
 719 # endif
 720         return;
 721       }
 722     }
 723 
 724     case APPEND_mode: {
 725 B29:;
 726       if (isBAR) {
 727         cpu.TPR.CA = get_BAR_address (cpup, address);
 728         cpu.TPR.TSR = cpu.PPR.PSR;
 729         cpu.TPR.TRR = cpu.PPR.PRR;
 730         cpu.iefpFinalAddress = doAppendCycleOperandRead (cpup, result, 2);
 731         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 732           for (uint i = 0; i < 2; i ++)
 733            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 734                       "Read2OperandRead (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\r\n",
 735                       cpu.iefpFinalAddress + i, result [i]);
 736         }
 737 # if defined(TESTING)
 738         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRead BR");
 739         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead BR evn");
 740         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead BR odd");
 741 # endif
 742         return;
 743       } else {
 744         cpu.iefpFinalAddress = doAppendCycleOperandRead (cpup, result, 2);
 745         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 746           for (uint i = 0; i < 2; i ++)
 747             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 748                        "Read2OperandRead (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\r\n",
 749                        cpu.iefpFinalAddress + i, result [i]);
 750         }
 751         if_sim_debug (DBG_FINAL, & cpu_dev) {
 752           for (uint i = 0; i < 2; i ++)
 753             sim_debug (DBG_FINAL, & cpu_dev,
 754                        "Read2OperandRead (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\r\n",
 755                        cpu.iefpFinalAddress + i, result [i]);
 756         }
 757 # if defined(TESTING)
 758         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRead");
 759         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead evn");
 760         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead odd");
 761 # endif
 762         return;
 763       }
 764     }
 765   }
 766 }
 767 
 768 # if defined(LOCKLESS)
 769 void Read2OperandRMW (cpu_state_t * cpup, word18 address, word36 * result) {
     /*  */
 770   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 771 
 772   bool isBAR = get_bar_mode (cpup);
 773 
 774   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 775     goto B29;
 776 
 777   switch (get_addr_mode (cpup)) {
 778     case ABSOLUTE_mode: {
 779       if (isBAR) {
 780         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
 781         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
 782 
 783         fauxDoAppendCycle (cpup, OPERAND_RMW);
 784         core_read2 (cpup, cpu.iefpFinalAddress, result + 0, result + 1, __func__);
 785         if_sim_debug (DBG_FINAL, & cpu_dev) {
 786             for (uint i = 0; i < 2; i ++)
 787               sim_debug (DBG_FINAL, & cpu_dev,
 788                          "Read2OperandRMW (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\r\n",
 789                          address + i, result [i]);
 790         }
 791 #  if defined(TESTING)
 792         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2OperandRMW ABBR");
 793         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRMW ABBR evn");
 794         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRMW ABBR odd");
 795 #  endif
 796         return;
 797       } else {
 798         set_apu_status (cpup, apuStatus_FABS);
 799         fauxDoAppendCycle (cpup, OPERAND_RMW);
 800         core_read2 (cpup, address, result + 0, result + 1, __func__);
 801         if_sim_debug (DBG_FINAL, & cpu_dev) {
 802           for (uint i = 0; i < 2; i ++)
 803             sim_debug (DBG_FINAL, & cpu_dev,
 804                        "Read2OperandRMW (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\r\n",
 805                        address + i, result [i]);
 806         }
 807 #  if defined(TESTING)
 808         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2OperandRMW AB");
 809         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRMW AB evn");
 810         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRMW AB odd");
 811 #  endif
 812         return;
 813       }
 814     }
 815 
 816     case APPEND_mode: {
 817 B29:;
 818       if (isBAR) {
 819         cpu.TPR.CA = get_BAR_address (cpup, address);
 820         cpu.TPR.TSR = cpu.PPR.PSR;
 821         cpu.TPR.TRR = cpu.PPR.PRR;
 822         cpu.iefpFinalAddress = doAppendCycleOperandRMW (cpup, result, 2);
 823         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 824           for (uint i = 0; i < 2; i ++)
 825            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 826                       "Read2OperandRMW (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\r\n",
 827                       cpu.iefpFinalAddress + i, result [i]);
 828         }
 829 #  if defined(TESTING)
 830         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRMW BR");
 831         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW BR evn");
 832         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW BR odd");
 833 #  endif
 834         return;
 835       } else {
 836         cpu.iefpFinalAddress = doAppendCycleOperandRMW (cpup, result, 2);
 837         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 838           for (uint i = 0; i < 2; i ++)
 839             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 840                        "Read2OperandRMW (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\r\n",
 841                        cpu.iefpFinalAddress + i, result [i]);
 842         }
 843 #  if defined(TESTING)
 844         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRMW");
 845         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW evn");
 846         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW odd");
 847 #  endif
 848         return;
 849       }
 850     }
 851   }
 852 }
 853 # endif
 854 
 855 void Read2InstructionFetch (cpu_state_t * cpup, word18 address, word36 * result) {
     /*  */
 856   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 857 
 858   bool isBAR = get_bar_mode (cpup);
 859 
 860   if (cpu.cu.XSF)
 861     goto B29;
 862 
 863   switch (get_addr_mode (cpup)) {
 864     case ABSOLUTE_mode: {
 865       if (isBAR) {
 866         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
 867         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
 868 
 869         fauxDoAppendCycle (cpup, INSTRUCTION_FETCH);
 870         core_read2 (cpup, cpu.iefpFinalAddress, result + 0, result + 1, __func__);
 871         if_sim_debug (DBG_FINAL, & cpu_dev) {
 872             for (uint i = 0; i < 2; i ++)
 873               sim_debug (DBG_FINAL, & cpu_dev,
 874                          "Read2InstructionFetch (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\r\n",
 875                          address + i, result [i]);
 876         }
 877 # if defined(TESTING)
 878         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2InstructionFetch ABBR");
 879         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2InstructionFetch ABBR evn");
 880         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2InstructionFetch ABBR odd");
 881 # endif
 882         return;
 883       } else {
 884         set_apu_status (cpup, apuStatus_FABS);
 885         fauxDoAppendCycle (cpup, INSTRUCTION_FETCH);
 886         core_read2 (cpup, address, result + 0, result + 1, __func__);
 887         if_sim_debug (DBG_FINAL, & cpu_dev) {
 888           for (uint i = 0; i < 2; i ++)
 889             sim_debug (DBG_FINAL, & cpu_dev,
 890                        "Read2InstructionFetch (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\r\n",
 891                        address + i, result [i]);
 892         }
 893 # if defined(TESTING)
 894         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2InstructionFetch AB");
 895         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2InstructionFetch AB evn");
 896         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2InstructionFetch AB odd");
 897 # endif
 898         return;
 899       }
 900     }
 901 
 902     case APPEND_mode: {
 903 B29:;
 904       if (isBAR) {
 905         cpu.TPR.CA = get_BAR_address (cpup, address);
 906         cpu.TPR.TSR = cpu.PPR.PSR;
 907         cpu.TPR.TRR = cpu.PPR.PRR;
 908         cpu.iefpFinalAddress = doAppendCycleInstructionFetch (cpup, result, 2);
 909         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 910           for (uint i = 0; i < 2; i ++)
 911            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 912                       "Read2InstructionFetch (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\r\n",
 913                       cpu.iefpFinalAddress + i, result [i]);
 914         }
 915 # if defined(TESTING)
 916         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2InstructionFetch BR");
 917         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch BR evn");
 918         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch BR odd");
 919 # endif
 920         return;
 921       } else {
 922         cpu.iefpFinalAddress = doAppendCycleInstructionFetch (cpup, result, 2);
 923         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 924           for (uint i = 0; i < 2; i ++)
 925             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 926                        "Read2InstructionFetch (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\r\n",
 927                        cpu.iefpFinalAddress + i, result [i]);
 928         }
 929 # if defined(TESTING)
 930         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2InstructionFetch");
 931         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch evn");
 932         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch odd");
 933 # endif
 934         return;
 935       }
 936     }
 937   }
 938 }
 939 
 940 void Read2RTCDOperandFetch (cpu_state_t * cpup, word18 address, word36 * result) {
     /*  */
 941   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 942 
 943   bool isBAR = get_bar_mode (cpup);
 944 
 945   if (isBAR) {
 946     cpu.TPR.CA = get_BAR_address (cpup, address);
 947     cpu.TPR.TSR = cpu.PPR.PSR;
 948     cpu.TPR.TRR = cpu.PPR.PRR;
 949     cpu.iefpFinalAddress = doAppendCycleRTCDOperandFetch (cpup, result, 2);
 950     if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 951       for (uint i = 0; i < 2; i ++)
 952        sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 953                   "Read2 (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\r\n",
 954                   cpu.iefpFinalAddress + i, result [i]);
 955     }
 956 # if defined(TESTING)
 957     HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR");
 958     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn");
 959     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd");
 960 # endif
 961     return;
 962   } else {
 963     cpu.iefpFinalAddress = doAppendCycleRTCDOperandFetch (cpup, result, 2);
 964     if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 965       for (uint i = 0; i < 2; i ++)
 966         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 967                    "Read2 (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\r\n",
 968                    cpu.iefpFinalAddress + i, result [i]);
 969     }
 970 # if defined(TESTING)
 971     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2");
 972     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn");
 973     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd");
 974 # endif
 975     return;
 976   }
 977 }
 978 
 979 void Read2IndirectWordFetch (cpu_state_t * cpup, word18 address, word36 * result) {
     /*  */
 980   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 981 
 982   bool isBAR = get_bar_mode (cpup);
 983 
 984   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 985     goto B29;
 986 
 987   switch (get_addr_mode (cpup)) {
 988     case ABSOLUTE_mode: {
 989       if (isBAR) {
 990         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
 991         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
 992 
 993         fauxDoAppendCycle (cpup, INDIRECT_WORD_FETCH);
 994         core_read2 (cpup, cpu.iefpFinalAddress, result + 0, result + 1, __func__);
 995         if_sim_debug (DBG_FINAL, & cpu_dev) {
 996             for (uint i = 0; i < 2; i ++)
 997               sim_debug (DBG_FINAL, & cpu_dev,
 998                          "Read2IndirectWordFetch (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\r\n",
 999                          address + i, result [i]);
1000         }
1001 # if defined(TESTING)
1002         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2IndirectWordFetch ABBR");
1003         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch ABBR evn");
1004         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2IndirectWordFetch ABBR odd");
1005 # endif
1006         return;
1007       } else {
1008         set_apu_status (cpup, apuStatus_FABS);
1009         fauxDoAppendCycle (cpup, INDIRECT_WORD_FETCH);
1010         core_read2 (cpup, address, result + 0, result + 1, __func__);
1011         if_sim_debug (DBG_FINAL, & cpu_dev) {
1012           for (uint i = 0; i < 2; i ++)
1013             sim_debug (DBG_FINAL, & cpu_dev,
1014                        "Read2IndirectWordFetch (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\r\n",
1015                        address + i, result [i]);
1016         }
1017 # if defined(TESTING)
1018         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2IndirectWordFetch AB");
1019         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch AB evn");
1020         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2IndirectWordFetch AB odd");
1021 # endif
1022         return;
1023       }
1024     }
1025 
1026     case APPEND_mode: {
1027 B29:;
1028       if (isBAR) {
1029         cpu.TPR.CA = get_BAR_address (cpup, address);
1030         cpu.TPR.TSR = cpu.PPR.PSR;
1031         cpu.TPR.TRR = cpu.PPR.PRR;
1032         cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (cpup, result, 2);
1033         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
1034           for (uint i = 0; i < 2; i ++)
1035            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1036                       "Read2IndirectWordFetch (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\r\n",
1037                       cpu.iefpFinalAddress + i, result [i]);
1038         }
1039 # if defined(TESTING)
1040         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch BR");
1041         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch BR evn");
1042         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch BR odd");
1043 # endif
1044         return;
1045       } else {
1046         cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (cpup, result, 2);
1047         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
1048           for (uint i = 0; i < 2; i ++)
1049             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1050                        "Read2IndirectWordFetch (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\r\n",
1051                        cpu.iefpFinalAddress + i, result [i]);
1052         }
1053 # if defined(TESTING)
1054         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch");
1055         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch evn");
1056         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch odd");
1057         return;
1058 # endif
1059       }
1060     }
1061   }
1062 }
1063 #endif // !OLDAPP
1064 
1065 void Read8 (cpu_state_t * cpup, word18 address, word36 * result, bool isAR)
     /*  */
1066   {
1067     cpu.TPR.CA = cpu.iefpFinalAddress = address;
1068 
1069     bool isBAR = get_bar_mode (cpup);
1070 
1071     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
1072       {
1073         goto B29;
1074       }
1075 
1076     switch (get_addr_mode (cpup))
1077       {
1078         case ABSOLUTE_mode:
1079           {
1080             if (isBAR)
1081               {
1082                 set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
1083                 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1084 
1085                 fauxDoAppendCycle (cpup, APU_DATA_READ);
1086                 core_readN (cpup, cpu.iefpFinalAddress, result, 8, __func__);
1087                 if_sim_debug (DBG_FINAL, & cpu_dev)
1088                   {
1089                     for (uint i = 0; i < 8; i ++)
1090                       sim_debug (DBG_FINAL, & cpu_dev,
1091                                  "Read8 (Actual) Read:       bar address=%08o"
1092                                  "  readData=%012"PRIo64"\r\n",
1093                                  address + i, result [i]);
1094                   }
1095 #if defined(TESTING)
1096                 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read8 ABBR");
1097                 for (uint i = 0; i < 8; i ++)
1098                   HDBGMRead (cpu.iefpFinalAddress + i, result [i], "Read8 ABBR");
1099 #endif
1100                 return;
1101               }
1102             else
1103               {
1104                 set_apu_status (cpup, apuStatus_FABS);
1105                 fauxDoAppendCycle (cpup, APU_DATA_READ);
1106                 core_readN (cpup, address, result, 8, __func__);
1107                 if_sim_debug (DBG_FINAL, & cpu_dev)
1108                   {
1109                     for (uint i = 0; i < 8; i ++)
1110                       sim_debug (DBG_FINAL, & cpu_dev,
1111                                  "Read8 (Actual) Read:       abs address=%08o"
1112                                  "  readData=%012"PRIo64"\r\n",
1113                                  address + i, result [i]);
1114                   }
1115 #if defined(TESTING)
1116                 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read8 ABS");
1117                 for (uint i = 0; i < 8; i ++)
1118                   HDBGMRead (address + i, result [i], "Read8 ABS");
1119 #endif
1120                 return;
1121               }
1122           }
1123 
1124         case APPEND_mode:
1125           {
1126 B29:;
1127             if (isBAR)
1128               {
1129                 cpu.TPR.CA = get_BAR_address (cpup, address);
1130                 cpu.TPR.TSR = cpu.PPR.PSR;
1131                 cpu.TPR.TRR = cpu.PPR.PRR;
1132                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_READ, result, 8);
1133                 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (cpup, result, 8);
1134                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1135                   {
1136                     for (uint i = 0; i < 8; i ++)
1137                      sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1138                                 "Read8 (Actual) Read:  bar iefpFinalAddress="
1139                                 "%08o  readData=%012"PRIo64"\r\n",
1140                                 cpu.iefpFinalAddress + i, result [i]);
1141                   }
1142 #if defined(TESTING)
1143                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read8 BAR");
1144                 for (uint i = 0; i < 8; i ++)
1145                   HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result[i], "Read8 BAR");
1146 #endif
1147                 return;
1148               }
1149             else
1150               {
1151                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_READ, result, 8);
1152                 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (cpup, result, 8);
1153                 // XXX Don't trace Multics idle loop
1154                 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
1155                   {
1156                     if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1157                       {
1158                         for (uint i = 0; i < 8; i ++)
1159                           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1160                                      "Read8 (Actual) Read:  iefpFinalAddress="
1161                                      "%08o  readData=%012"PRIo64"\r\n",
1162                                      cpu.iefpFinalAddress + i, result [i]);
1163                       }
1164 #if defined(TESTING)
1165                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read8");
1166                     for (uint i = 0; i < 8; i ++)
1167                       HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "Read8");
1168 #endif
1169                   }
1170                 return;
1171               }
1172           }
1173       }
1174   }
1175 
1176 void Read16 (cpu_state_t * cpup, word18 address, word36 * result)
     /*  */
1177   {
1178     address &= paragraphMask; // Round to 8 word boundary
1179     Read8 (cpup, address, result, cpu.currentInstruction.b29);
1180     Read8 (cpup, address + 8, result + 8, cpu.currentInstruction.b29);
1181     return;
1182   }
1183 
1184 void ReadPage (cpu_state_t * cpup, word18 address, word36 * result, bool isAR)
     /*  */
1185   {
1186     if ((address & PGMK) != 0)
1187       {
1188         sim_warn ("ReadPage not on boundary %06o\r\n", address);
1189       }
1190     address &= (word18) ~PGMK; // Round to page boundary
1191     cpu.TPR.CA = cpu.iefpFinalAddress = address;
1192 
1193     bool isBAR = get_bar_mode (cpup);
1194 
1195     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
1196       {
1197         goto B29;
1198       }
1199 
1200     switch (get_addr_mode (cpup))
1201       {
1202         case ABSOLUTE_mode:
1203           {
1204             if (isBAR)
1205               {
1206                 set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
1207                 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1208 
1209                 fauxDoAppendCycle (cpup, APU_DATA_READ);
1210                 core_readN (cpup, cpu.iefpFinalAddress, result, PGSZ, __func__);
1211                 if_sim_debug (DBG_FINAL, & cpu_dev)
1212                   {
1213                     for (uint i = 0; i < PGSZ; i ++)
1214                       sim_debug (DBG_FINAL, & cpu_dev,
1215                                  "ReadPage (Actual) Read:       bar address="
1216                                  "%08o  readData=%012"PRIo64"\r\n",
1217                                   address + i, result [i]);
1218                   }
1219 #if defined(TESTING)
1220                 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadPage AB");
1221                 for (uint i = 0; i < PGSZ; i ++)
1222                   HDBGMRead (cpu.iefpFinalAddress + i, result [i], "ReadPage AB");
1223 #endif
1224                 return;
1225               }
1226             else
1227               {
1228                 set_apu_status (cpup, apuStatus_FABS);
1229                 fauxDoAppendCycle (cpup, APU_DATA_READ);
1230                 core_readN (cpup, address, result, PGSZ, __func__);
1231                 if_sim_debug (DBG_FINAL, & cpu_dev)
1232                   {
1233                     for (uint i = 0; i < PGSZ; i ++)
1234                       sim_debug (DBG_FINAL, & cpu_dev,
1235                                  "ReadPage (Actual) Read:       abs address="
1236                                  "%08o  readData=%012"PRIo64"\r\n",
1237                                  address + i, result [i]);
1238                   }
1239 #if defined(TESTING)
1240                 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadPage ABS");
1241                 for (uint i = 0; i < PGSZ; i ++)
1242                   HDBGMRead (address + i, result [i], "ReadPage ABS");
1243 #endif
1244                 return;
1245               }
1246           }
1247 
1248         case APPEND_mode:
1249           {
1250 B29:;
1251             if (isBAR)
1252               {
1253                 cpu.TPR.CA = get_BAR_address (cpup, address);
1254                 cpu.TPR.TSR = cpu.PPR.PSR;
1255                 cpu.TPR.TRR = cpu.PPR.PRR;
1256                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_READ, result, PGSZ);
1257                 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (cpup, result, PGSZ);
1258                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1259                   {
1260                     for (uint i = 0; i < PGSZ; i ++)
1261                      sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1262                                 "ReadPage (Actual) Read:  bar iefpFinalAddress="
1263                                 "%08o  readData=%012"PRIo64"\r\n",
1264                                 cpu.iefpFinalAddress + i, result [i]);
1265                   }
1266 #if defined(TESTING)
1267                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadPage B");
1268                 for (uint i = 0; i < PGSZ; i ++)
1269                   HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage B");
1270 #endif
1271 
1272                 return;
1273               }
1274             else
1275               {
1276                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_READ, result, PGSZ);
1277                 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (cpup, result, PGSZ);
1278                 // XXX Don't trace Multics idle loop
1279                 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
1280                   {
1281                     if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1282                       {
1283                         for (uint i = 0; i < PGSZ; i ++)
1284                           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1285                                      "ReadPage (Actual) Read:  iefpFinalAddress"
1286                                      "=%08o  readData=%012"PRIo64"\r\n",
1287                                      cpu.iefpFinalAddress + i, result [i]);
1288                       }
1289 #if defined(TESTING)
1290                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadPage");
1291                     for (uint i = 0; i < PGSZ; i ++)
1292                       HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage");
1293 #endif
1294                   }
1295                 return;
1296               }
1297           }
1298       }
1299   }
1300 
1301 #if defined(OLDAPP)
1302 void Write (cpu_state_t * cpup, word18 address, word36 data, processor_cycle_type cyctyp) {
     /*  */
1303   cpu.TPR.CA = cpu.iefpFinalAddress = address;
1304 
1305   bool isBAR = get_bar_mode ();
1306 
1307   if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29))
1308     goto B29;
1309 
1310   switch (get_addr_mode ()) {
1311     case ABSOLUTE_mode: {
1312       if (isBAR) {
1313         cpu.iefpFinalAddress = get_BAR_address (address);
1314         set_apu_status (apuStatus_FABS); // XXX maybe...
1315         fauxDoAppendCycle (cyctyp);
1316         if (cyctyp == OPERAND_STORE && cpu.useZone)
1317           core_write_zone (cpu.iefpFinalAddress, data, __func__);
1318         else
1319           core_write (cpu.iefpFinalAddress, data, __func__);
1320         sim_debug (DBG_FINAL, & cpu_dev, "Write(Actual) Write:      bar address=%08o writeData=%012"PRIo64"\r\n", address, data);
1321 # if defined(TESTING)
1322         HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write ABBR");
1323         HDBGMWrite (cpu.iefpFinalAddress, data, "Write ABBR");
1324 # endif
1325         return;
1326       } else {
1327         set_apu_status (apuStatus_FABS);
1328         fauxDoAppendCycle (cyctyp);
1329         if (cyctyp == OPERAND_STORE && cpu.useZone)
1330           core_write_zone (address, data, __func__);
1331         else
1332           core_write (address, data, __func__);
1333         sim_debug (DBG_FINAL, & cpu_dev,
1334                    "Write(Actual) Write:      abs address=%08o writeData=%012"PRIo64"\r\n",
1335                    address, data);
1336 # if defined(TESTING)
1337         HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write AB");
1338         HDBGMWrite (address, data, "Write AB");
1339 # endif
1340         return;
1341       }
1342     }
1343 
1344     case APPEND_mode: {
1345 B29:
1346       if (isBAR) {
1347         cpu.TPR.CA = get_BAR_address (cpup, address);
1348         cpu.TPR.TSR = cpu.PPR.PSR;
1349         cpu.TPR.TRR = cpu.PPR.PRR;
1350         cpu.iefpFinalAddress = do_append_cycle (cpup, cyctyp, & data, 1);
1351         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1352                    "Write(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\r\n",
1353                    cpu.iefpFinalAddress, data);
1354 # if defined(TESTING)
1355         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write BR");
1356         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write BR");
1357 # endif
1358         return;
1359       } else {
1360         cpu.iefpFinalAddress = do_append_cycle (cpup, cyctyp, & data, 1);
1361         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1362                    "Write(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\r\n",
1363                    cpu.iefpFinalAddress, data);
1364 # if defined(TESTING)
1365         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write");
1366         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write");
1367 # endif
1368         return;
1369       }
1370     }
1371   }
1372 }
1373 #endif // OLDAPP
1374 
1375 #if !defined(OLDAPP)
1376 void WriteAPUDataStore (cpu_state_t * cpup, word18 address, word36 data) {
     /*  */
1377   cpu.TPR.CA = cpu.iefpFinalAddress = address;
1378 
1379   bool isBAR = get_bar_mode (cpup);
1380 
1381   if (cpu.cu.XSF || cpu.currentInstruction.b29)
1382     goto B29;
1383 
1384   switch (get_addr_mode (cpup)) {
1385     case ABSOLUTE_mode: {
1386       if (isBAR) {
1387         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1388         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
1389         fauxDoAppendCycle (cpup, APU_DATA_STORE);
1390         if (! sdpap_store (cpup, cpu.iefpFinalAddress, & data, 1))
1391           core_write (cpup, cpu.iefpFinalAddress, data, __func__);
1392         sim_debug (DBG_FINAL, & cpu_dev,
1393                    "WriteAPUDataStore(Actual) Write:      bar address=%08o writeData=%012"PRIo64"\r\n",
1394                    address, data);
1395 # if defined(TESTING)
1396         HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "WriteAPUDataStore ABBR");
1397         HDBGMWrite (cpu.iefpFinalAddress, data, "WriteAPUDataStore ABBR");
1398 # endif
1399         return;
1400       } else {
1401         set_apu_status (cpup, apuStatus_FABS);
1402         fauxDoAppendCycle (cpup, APU_DATA_STORE);
1403         if (! sdpap_store (cpup, address, & data, 1))
1404           core_write (cpup, address, data, __func__);
1405         sim_debug (DBG_FINAL, & cpu_dev,
1406                    "WriteAPUDataStore(Actual) Write:      abs address=%08o writeData=%012"PRIo64"\r\n",
1407                    address, data);
1408 # if defined(TESTING)
1409         HDBGIEFP (hdbgIEFP_abs_write, 0, address, "WriteAPUDataStore AB");
1410         HDBGMWrite (address, data, "WriteAPUDataStore AB");
1411 # endif
1412         return;
1413       }
1414     }
1415 
1416     case APPEND_mode: {
1417 B29:
1418       if (isBAR) {
1419         cpu.TPR.CA = get_BAR_address (cpup, address);
1420         cpu.TPR.TSR = cpu.PPR.PSR;
1421         cpu.TPR.TRR = cpu.PPR.PRR;
1422         cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, & data, 1);
1423         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1424                    "WriteAPUDataStore(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\r\n",
1425                    cpu.iefpFinalAddress, data);
1426 # if defined(TESTING)
1427         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteAPUDataStore BR");
1428         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore BR");
1429 # endif
1430         return;
1431       } else {
1432         cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, & data, 1);
1433         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1434                    "WriteAPUDataStore(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\r\n",
1435                    cpu.iefpFinalAddress, data);
1436 # if defined(TESTING)
1437         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteAPUDataStore");
1438         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore");
1439 # endif
1440         return;
1441       }
1442     }
1443   }
1444 }
1445 
1446 void WriteOperandStore (cpu_state_t * cpup, word18 address, word36 data) {
     /*  */
1447   cpu.TPR.CA = cpu.iefpFinalAddress = address;
1448 
1449   bool isBAR = get_bar_mode (cpup);
1450 
1451   if (cpu.cu.XSF || cpu.currentInstruction.b29)
1452     goto B29;
1453 
1454   switch (get_addr_mode (cpup)) {
1455     case ABSOLUTE_mode: {
1456       if (isBAR) {
1457         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1458         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
1459         fauxDoAppendCycle (cpup, OPERAND_STORE);
1460         if (cpu.useZone)
1461           { if (! sdpap_store (cpup, cpu.iefpFinalAddress, & data, 1)) core_write_zone (cpup, cpu.iefpFinalAddress, data, __func__); }
1462         else
1463           { if (! sdpap_store (cpup, cpu.iefpFinalAddress, & data, 1)) core_write (cpup, cpu.iefpFinalAddress, data, __func__); }
1464         sim_debug (DBG_FINAL, & cpu_dev,
1465                    "WriteOperandStore(Actual) Write:      bar address=%08o writeData=%012"PRIo64"\r\n",
1466                    address, data);
1467 # if defined(TESTING)
1468         HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "WriteOperandStore ABBR");
1469         HDBGMWrite (cpu.iefpFinalAddress, data, "WriteOperandStore ABBR");
1470 # endif
1471         return;
1472       } else {
1473         set_apu_status (cpup, apuStatus_FABS);
1474         fauxDoAppendCycle (cpup, OPERAND_STORE);
1475         if (cpu.useZone)
1476           { if (! sdpap_store (cpup, address, & data, 1)) core_write_zone (cpup, address, data, __func__); }
1477         else
1478           { if (! sdpap_store (cpup, address, & data, 1)) core_write (cpup, address, data, __func__); }
1479         sim_debug (DBG_FINAL, & cpu_dev,
1480                    "WriteOperandStore(Actual) Write:      abs address=%08o writeData=%012"PRIo64"\r\n",
1481                    address, data);
1482 # if defined(TESTING)
1483         HDBGIEFP (hdbgIEFP_abs_write, 0, address, "WriteOperandStore AB");
1484         HDBGMWrite (address, data, "WriteOperandStore AB");
1485 # endif
1486         return;
1487       }
1488     }
1489 
1490     case APPEND_mode: {
1491 B29:
1492       if (isBAR) {
1493         cpu.TPR.CA = get_BAR_address (cpup, address);
1494         cpu.TPR.TSR = cpu.PPR.PSR;
1495         cpu.TPR.TRR = cpu.PPR.PRR;
1496         cpu.iefpFinalAddress = doAppendCycleOperandStore (cpup, & data, 1);
1497         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1498                    "WriteOperandStore(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\r\n",
1499                    cpu.iefpFinalAddress, data);
1500 # if defined(TESTING)
1501         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteOperandStore BR");
1502         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore BR");
1503 # endif
1504         return;
1505       } else {
1506         cpu.iefpFinalAddress = doAppendCycleOperandStore (cpup, & data, 1);
1507         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1508                    "WriteOperandStore(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\r\n",
1509                    cpu.iefpFinalAddress, data);
1510 # if defined(TESTING)
1511         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteOperandStore");
1512         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore");
1513 # endif
1514         return;
1515       }
1516     }
1517   }
1518 }
1519 #endif // !OLDAPP
1520 
1521 #if defined(OLDAPP)
1522 void Write2 (cpu_state_t * cpup, word18 address, word36 * data, processor_cycle_type cyctyp)
     /*  */
1523   {
1524     cpu.TPR.CA = cpu.iefpFinalAddress = address;
1525     bool isBAR = get_bar_mode ();
1526 
1527     if (cpu.cu.XSF /*get_went_appending ()*/ || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29))
1528       goto B29;
1529 
1530     switch (get_addr_mode ())
1531       {
1532         case ABSOLUTE_mode:
1533           {
1534             if (isBAR)
1535               {
1536                 cpu.iefpFinalAddress = get_BAR_address (address);
1537                 set_apu_status (apuStatus_FABS); // XXX maybe...
1538                 fauxDoAppendCycle (cyctyp);
1539                 core_write2 (cpu.iefpFinalAddress, data [0], data [1],
1540                               __func__);
1541 # if defined(TESTING)
1542                 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write2 ABBR");
1543                 HDBGMWrite (cpu.iefpFinalAddress, data [0], "Write2 ABBR evn");
1544                 HDBGMWrite (cpu.iefpFinalAddress+1, data [1], "Write2 ABBR odd");
1545 # endif
1546                 sim_debug (DBG_FINAL, & cpu_dev,
1547                            "Write2 (Actual) Write:      bar address=%08o "
1548                            "writeData=%012"PRIo64" %012"PRIo64"\r\n",
1549                            address, data [0], data [1]);
1550                 return;
1551               }
1552             else
1553               {
1554                 set_apu_status (apuStatus_FABS);
1555                 fauxDoAppendCycle (cyctyp);
1556                 core_write2 (address, data [0], data [1], __func__);
1557                 sim_debug (DBG_FINAL, & cpu_dev,
1558                            "Write2 (Actual) Write:      abs address=%08o "
1559                            "writeData=%012"PRIo64" %012"PRIo64"\r\n",
1560                            address, data [0], data [1]);
1561 # if defined(TESTING)
1562                 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write2 AB");
1563                 HDBGMWrite (address, data [0], "Write2 AB evn");
1564                 HDBGMWrite (address+1, data [1], "Write2 AB odd");
1565 # endif
1566                 return;
1567               }
1568           }
1569 
1570         case APPEND_mode:
1571           {
1572 B29:
1573             if (isBAR)
1574               {
1575                 cpu.TPR.CA = get_BAR_address (address);
1576                 cpu.TPR.TSR = cpu.PPR.PSR;
1577                 cpu.TPR.TRR = cpu.PPR.PRR;
1578                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, data, 2);
1579                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1580                            "Write2 (Actual) Write: bar iefpFinalAddress=%08o "
1581                            "writeData=%012"PRIo64" %012"PRIo64"\r\n",
1582                            address, data [0], data [1]);
1583 # if defined(TESTING)
1584                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2 BR");
1585                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 BR evn");
1586                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 BR odd");
1587 # endif
1588                 return;
1589               }
1590             else
1591               {
1592                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, data, 2);
1593                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1594                            "Write2 (Actual) Write: iefpFinalAddress=%08o "
1595                            "writeData=%012"PRIo64" %012"PRIo64"\r\n",
1596                            address, data [0], data [1]);
1597 # if defined(TESTING)
1598                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2");
1599                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 evn");
1600                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 odd");
1601 # endif
1602                 return;
1603               }
1604           }
1605       }
1606   }
1607 #endif // OLDAPP
1608 
1609 #if !defined(OLDAPP)
1610 void Write2OperandStore (cpu_state_t * cpup, word18 address, word36 * data) {
     /*  */
1611   cpu.TPR.CA = cpu.iefpFinalAddress = address;
1612   bool isBAR = get_bar_mode (cpup);
1613 
1614   if (cpu.cu.XSF || cpu.currentInstruction.b29)
1615     goto B29;
1616 
1617   switch (get_addr_mode (cpup)) {
1618     case ABSOLUTE_mode: {
1619       if (isBAR) {
1620         cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1621         set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
1622         fauxDoAppendCycle (cpup, OPERAND_STORE);
1623         if (! sdpap_store (cpup, cpu.iefpFinalAddress, data, 2))
1624           core_write2 (cpup, cpu.iefpFinalAddress, data [0], data [1], __func__);
1625 # if defined(TESTING)
1626         HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write2OperandStore ABBR");
1627         HDBGMWrite (cpu.iefpFinalAddress, data [0], "Write2OperandStore ABBR evn");
1628         HDBGMWrite (cpu.iefpFinalAddress+1, data [1], "Write2OperandStore ABBR odd");
1629 # endif
1630         sim_debug (DBG_FINAL, & cpu_dev,
1631                    "Write2OperandStore (Actual) Write:      bar address=%08o " "writeData=%012"PRIo64" %012"PRIo64"\r\n",
1632                    address, data [0], data [1]);
1633         return;
1634       } else {
1635         set_apu_status (cpup, apuStatus_FABS);
1636         fauxDoAppendCycle (cpup, OPERAND_STORE);
1637         if (! sdpap_store (cpup, address, data, 2))
1638           core_write2 (cpup, address, data [0], data [1], __func__);
1639         sim_debug (DBG_FINAL, & cpu_dev,
1640                    "Write2OperandStore (Actual) Write:      abs address=%08o " "writeData=%012"PRIo64" %012"PRIo64"\r\n",
1641                    address, data [0], data [1]);
1642 # if defined(TESTING)
1643         HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write2OperandStore AB");
1644         HDBGMWrite (address, data [0], "Write2OperandStore AB evn");
1645         HDBGMWrite (address+1, data [1], "Write2OperandStore AB odd");
1646 # endif
1647         return;
1648       }
1649     }
1650 
1651     case APPEND_mode: {
1652 B29:
1653       if (isBAR) {
1654         cpu.TPR.CA = get_BAR_address (cpup, address);
1655         cpu.TPR.TSR = cpu.PPR.PSR;
1656         cpu.TPR.TRR = cpu.PPR.PRR;
1657         cpu.iefpFinalAddress = doAppendCycleOperandStore (cpup, data, 2);
1658         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1659                    "Write2OperandStore (Actual) Write: bar iefpFinalAddress=%08o " "writeData=%012"PRIo64" %012"PRIo64"\r\n",
1660                    address, data [0], data [1]);
1661 # if defined(TESTING)
1662         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2OperandStore BR");
1663         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore BR evn");
1664         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore BR odd");
1665 # endif
1666         return;
1667       } else {
1668         cpu.iefpFinalAddress = doAppendCycleOperandStore (cpup, data, 2);
1669         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1670                    "Write2OperandStore (Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64" %012"PRIo64"\r\n",
1671                    address, data [0], data [1]);
1672 # if defined(TESTING)
1673         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2OperandStore");
1674         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore evn");
1675         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore odd");
1676 # endif
1677         return;
1678       }
1679     }
1680   }
1681 }
1682 #endif // !OLDAPP
1683 
1684 void Write1 (cpu_state_t * cpup, word18 address, word36 data, bool isAR)
     /*  */
1685   {
1686     cpu.TPR.CA = cpu.iefpFinalAddress = address;
1687     bool isBAR = get_bar_mode (cpup);
1688     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
1689       goto B29;
1690     switch (get_addr_mode (cpup))
1691       {
1692         case ABSOLUTE_mode:
1693           {
1694             if (isBAR)
1695              {
1696                 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1697                 set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
1698                 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1699                 if (! sdpap_store (cpup, cpu.iefpFinalAddress, & data, 1))
1700                   core_write (cpup, cpu.iefpFinalAddress, data, __func__);
1701                 sim_debug (DBG_FINAL, & cpu_dev,
1702                            "Write1(Actual) Write:      bar address=%08o "
1703                            "writeData=%012"PRIo64"\r\n",
1704                            address, data);
1705 #if defined(TESTING)
1706                 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write1 ABBR");
1707                 HDBGMWrite (cpu.iefpFinalAddress, data, "Write1 ABBR");
1708 #endif
1709                 return;
1710               }
1711             else
1712               {
1713                 set_apu_status (cpup, apuStatus_FABS);
1714                 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1715                 if (! sdpap_store (cpup, address, & data, 1))
1716                   core_write (cpup, address, data, __func__);
1717                 sim_debug (DBG_FINAL, & cpu_dev,
1718                            "Write1(Actual) Write:      abs address=%08o "
1719                            "writeData=%012"PRIo64"\r\n",
1720                            address, data);
1721 #if defined(TESTING)
1722                 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write1 AB");
1723                 HDBGMWrite (address, data, "Write1 AB");
1724 #endif
1725                 return;
1726               }
1727           }
1728 
1729         case APPEND_mode:
1730           {
1731 B29:
1732             if (isBAR)
1733               {
1734                 cpu.TPR.CA = get_BAR_address (cpup, address);
1735                 cpu.TPR.TSR = cpu.PPR.PSR;
1736                 cpu.TPR.TRR = cpu.PPR.PRR;
1737                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, & data, 1);
1738                 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, & data, 1);
1739                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1740                            "Write8(Actual) Write: bar iefpFinalAddress="
1741                            "%08o writeData=%012"PRIo64"\r\n",
1742                            cpu.iefpFinalAddress, data);
1743 #if defined(TESTING)
1744                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write1 BR");
1745                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1 BR");
1746 #endif
1747                 return;
1748               }
1749             else
1750               {
1751                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, & data, 1);
1752                 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, & data, 1);
1753                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1754                            "Write(Actual) Write: iefpFinalAddress=%08o "
1755                            "writeData=%012"PRIo64"\r\n",
1756                            cpu.iefpFinalAddress, data);
1757 #if defined(TESTING)
1758                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write1");
1759                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1");
1760 #endif
1761                 return;
1762               }
1763           }
1764       }
1765   }
1766 
1767 void Write8 (cpu_state_t * cpup, word18 address, word36 * data, bool isAR)
     /*  */
1768   {
1769     address &= paragraphMask; // Round to 8 word boundarryt
1770     cpu.TPR.CA = cpu.iefpFinalAddress = address;
1771 
1772     bool isBAR = get_bar_mode (cpup);
1773 
1774     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
1775       goto B29;
1776 
1777     switch (get_addr_mode (cpup))
1778      {
1779         case ABSOLUTE_mode:
1780           {
1781             if (isBAR)
1782              {
1783                 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1784                 set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
1785                 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1786                 if (! sdpap_store (cpup, cpu.iefpFinalAddress, data, 8))
1787                   core_writeN (cpup, cpu.iefpFinalAddress, data, 8, __func__);
1788                 if_sim_debug (DBG_FINAL, & cpu_dev)
1789                   {
1790                     for (uint i = 0; i < 8; i ++)
1791                       sim_debug (DBG_FINAL, & cpu_dev,
1792                                  "Write8(Actual) Write:      bar address=%08o "
1793                                  "writeData=%012"PRIo64"\r\n",
1794                                  address + i, data [i]);
1795                   }
1796 #if defined(TESTING)
1797                 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write8 ABBR");
1798                 for (uint i = 0; i < 8; i ++)
1799                   HDBGMWrite (cpu.iefpFinalAddress + i, data [i], "Write8 ABBR");
1800 #endif
1801                 return;
1802               }
1803             else
1804               {
1805                 set_apu_status (cpup, apuStatus_FABS);
1806                 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1807                 if (! sdpap_store (cpup, address, data, 8))
1808                   core_writeN (cpup, address, data, 8, __func__);
1809                 if_sim_debug (DBG_FINAL, & cpu_dev)
1810                   {
1811                     for (uint i = 0; i < 8; i ++)
1812                       sim_debug (DBG_FINAL, & cpu_dev,
1813                                  "Write8(Actual) Write:      abs address=%08o "
1814                                  "writeData=%012"PRIo64"\r\n",
1815                                   address + i, data [i]);
1816                   }
1817 #if defined(TESTING)
1818                 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write8 AB");
1819                 for (uint i = 0; i < 8; i ++)
1820                   HDBGMWrite (address + i, data [i], "Write8 AB");
1821 #endif
1822                 return;
1823               }
1824           }
1825 
1826         case APPEND_mode:
1827           {
1828 B29:
1829             if (isBAR)
1830               {
1831                 cpu.TPR.CA = get_BAR_address (cpup, address);
1832                 cpu.TPR.TSR = cpu.PPR.PSR;
1833                 cpu.TPR.TRR = cpu.PPR.PRR;
1834                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, data, 8);
1835                 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, data, 8);
1836                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1837                   {
1838                     for (uint i = 0; i < 8; i ++)
1839                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1840                                  "Write8(Actual) Write: bar iefpFinalAddress="
1841                                  "%08o writeData=%012"PRIo64"\r\n",
1842                                  cpu.iefpFinalAddress + i, data [i]);
1843                   }
1844 #if defined(TESTING)
1845                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write8 BR");
1846                 for (uint i = 0; i < 8; i ++)
1847                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8 BR");
1848 #endif
1849 
1850                 return;
1851               }
1852             else
1853               {
1854                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, data, 8);
1855                 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, data, 8);
1856                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1857                   {
1858                     for (uint i = 0; i < 8; i ++)
1859                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1860                                  "Write8(Actual) Write: iefpFinalAddress=%08o "
1861                                  "writeData=%012"PRIo64"\r\n",
1862                                  cpu.iefpFinalAddress + i, data [i]);
1863                   }
1864 #if defined(TESTING)
1865                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write8");
1866                 for (uint i = 0; i < 8; i ++)
1867                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8");
1868 #endif
1869 
1870                 return;
1871               }
1872           }
1873       }
1874   }
1875 
1876 void Write16 (cpu_state_t * cpup, word18 address, word36 * data)
     /*  */
1877   {
1878     address &= paragraphMask; // Round to 8 word boundary
1879     Write8 (cpup, address, data, cpu.currentInstruction.b29);
1880     Write8 (cpup, address + 8, data + 8, cpu.currentInstruction.b29);
1881   }
1882 
1883 void Write32 (cpu_state_t * cpup, word18 address, word36 * data)
     /*  */
1884   {
1885 //#define paragraphMask 077777770
1886     //address &= paragraphMask; // Round to 8 word boundary
1887     address &= 077777740; // Round to 32 word boundary
1888     Write8 (cpup, address, data, cpu.currentInstruction.b29);
1889     Write8 (cpup, address + 8, data + 8, cpu.currentInstruction.b29);
1890     Write8 (cpup, address + 16, data + 16, cpu.currentInstruction.b29);
1891     Write8 (cpup, address + 24, data + 24, cpu.currentInstruction.b29);
1892   }
1893 
1894 void WritePage (cpu_state_t * cpup, word18 address, word36 * data, bool isAR)
     /*  */
1895   {
1896     if ((address & PGMK) != 0)
1897       {
1898         sim_warn ("WritePage not on boundary %06o\r\n", address);
1899       }
1900     address &= (word18) ~PGMK; // Round to page boundary
1901     cpu.TPR.CA = cpu.iefpFinalAddress = address;
1902 
1903     bool isBAR = get_bar_mode (cpup);
1904 
1905     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
1906       goto B29;
1907 
1908     switch (get_addr_mode (cpup))
1909      {
1910         case ABSOLUTE_mode:
1911           {
1912             if (isBAR)
1913              {
1914                 cpu.iefpFinalAddress = get_BAR_address (cpup, address);
1915                 set_apu_status (cpup, apuStatus_FABS); // XXX maybe...
1916                 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1917                 if (! sdpap_store (cpup, cpu.iefpFinalAddress, data, PGSZ))
1918                   core_writeN (cpup, cpu.iefpFinalAddress, data, PGSZ, __func__);
1919                 if_sim_debug (DBG_FINAL, & cpu_dev)
1920                   {
1921                     for (uint i = 0; i < PGSZ; i ++)
1922                       sim_debug (DBG_FINAL, & cpu_dev,
1923                                  "WritePage(Actual) Write:      bar address="
1924                                  "%08o writeData=%012"PRIo64"\r\n",
1925                                  address + i, data [i]);
1926                   }
1927 #if defined(TESTING)
1928                 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "WritePage ABBR");
1929                 for (uint i = 0; i < PGSZ; i ++)
1930                   HDBGMWrite (cpu.iefpFinalAddress + i, data [i], "WritePage ABBR");
1931 #endif
1932                 return;
1933               }
1934             else
1935               {
1936                 set_apu_status (cpup, apuStatus_FABS);
1937                 fauxDoAppendCycle (cpup, APU_DATA_STORE);
1938                 if (! sdpap_store (cpup, address, data, PGSZ))
1939                   core_writeN (cpup, address, data, PGSZ, __func__);
1940                 if_sim_debug (DBG_FINAL, & cpu_dev)
1941                   {
1942                     for (uint i = 0; i < PGSZ; i ++)
1943                       sim_debug (DBG_FINAL, & cpu_dev,
1944                                  "WritePage(Actual) Write:      abs address="
1945                                  "%08o writeData=%012"PRIo64"\r\n",
1946                                  address + i, data [i]);
1947                   }
1948 #if defined(TESTING)
1949                 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "WritePage AB");
1950                 for (uint i = 0; i < PGSZ; i ++)
1951                   HDBGMWrite (address + i, data [i], "WritePage AB");
1952 #endif
1953                 return;
1954               }
1955           }
1956 
1957         case APPEND_mode:
1958           {
1959 B29:
1960             if (isBAR)
1961               {
1962                 cpu.TPR.CA = get_BAR_address (cpup, address);
1963                 cpu.TPR.TSR = cpu.PPR.PSR;
1964                 cpu.TPR.TRR = cpu.PPR.PRR;
1965                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, data, PGSZ);
1966                 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, data, PGSZ);
1967                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1968                   {
1969                     for (uint i = 0; i < PGSZ; i ++)
1970                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1971                                  "WritePage(Actual) Write: bar "
1972                                  "iefpFinalAddress=%08o writeData=%012"PRIo64
1973                                  "\r\n",
1974                                  cpu.iefpFinalAddress + i, data [i]);
1975                   }
1976 #if defined(TESTING)
1977                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WritePage BR");
1978                 for (uint i = 0; i < PGSZ; i ++)
1979                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage BR");
1980 #endif
1981                 return;
1982               }
1983             else
1984               {
1985                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, data, PGSZ);
1986                 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (cpup, data, PGSZ);
1987                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1988                   {
1989                     for (uint i = 0; i < PGSZ; i ++)
1990                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1991                                  "WritePage(Actual) Write: iefpFinalAddress="
1992                                  "%08o writeData=%012"PRIo64"\r\n",
1993                                  cpu.iefpFinalAddress + i, data [i]);
1994                   }
1995 #if defined(TESTING)
1996                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WritePage");
1997                 for (uint i = 0; i < PGSZ; i ++)
1998                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage");
1999 #endif
2000 
2001                 return;
2002               }
2003           }
2004       }
2005   }
2006 
2007 void ReadIndirect (cpu_state_t * cpup)
     /*  */
2008   {
2009     if (cpu.TPR.CA & 1) // is odd?
2010       {
2011         ReadIndirectWordFetch (cpup, cpu.TPR.CA, cpu.itxPair);
2012         cpu.itxPair[1] = MASK36; // fill with ones for debugging
2013       }
2014     else
2015       {
2016         Read2IndirectWordFetch (cpup, cpu.TPR.CA, cpu.itxPair);
2017       }
2018   }