This source file includes following definitions.
- SIGNEXT6_int
- SIGNEXT8_int
- SIGNEXT15_32
- SIGNEXT18_32
- SIGNEXT21_32
- SIGNEXT22_32
- SIGNEXT24_32
- SIGNEXT36_64
- SIGNEXT18_64
- SIGNEXT21_64
- SIGNEXT22_64
- SIGNEXT24_64
- SIGNEXT72_128
- SIGNEXT36_128
- SIGNEXT15_18
- SIGNEXT18_24
- SIGNEXT36_72
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19 #if !defined(DPS8_HW_CONSTS_H)
20 # define DPS8_HW_CONSTS_H
21
22 # include "dps8_math128.h"
23
24
25
26
27
28
29 # define XXX_TEMP_SCU_SUBPORT 0
30
31 enum { N_SCU_PORTS = 8 };
32 enum { N_SCU_SUBPORTS = 4 };
33 enum { N_ASSIGNMENTS = 2 };
34
35 enum { N_CELL_INTERRUPTS = 32 };
36
37 # define PASIZE 24
38 # define PAMASK ((1U << PASIZE) - 1U)
39
40 # define PAEVEN (((1U << (PASIZE - 1)) - 1U) << 1)
41 # define MEM_SIZE_MAX (1U << PASIZE)
42
43
44
45 # define SCBANK_SZ (1U << 16)
46
47
48
49 # define N_SCBANKS ((MEM_SIZE_MAX) / (SCBANK_SZ))
50
51
52
53
54
55 # define VASIZE 18
56 # define AMASK ((1U << VASIZE) - 1U)
57 # define DPS8_SEGSIZE (1U << VASIZE)
58
59
60
61
62
63
64 # define PGSZ 1024u
65 # define PGMK 1023u
66 # define PG18MASK 0776000u
67 # define PG24MASK 077776000u
68 # define OS18MASK 0001777u
69
70
71
72
73
74 enum { MAX_CHANNELS = 64 };
75 enum { N_IOM_PORTS = 8 };
76
77 enum { N_DEV_CODES = 64 };
78 enum { IOM_CONNECT_CHAN = 2 };
79
80
81
82
83
84
85 # define MAX18 0777777U
86 # define MAX18POS 0377777U
87 # define MAX18NEG 0400000U
88 # define SIGN18 0400000U
89
90 # define BIT19 01000000U
91 # define BIT20 02000000U
92 # define MASK36 0777777777777LLU
93 # define DMASK MASK36
94 # define MASK10 0001777U
95 # define MASK14 0037777U
96 # define MASK16 0177777U
97 # define MASK17 0377777U
98 # define MASK18 0777777U
99 # define WMASK MASK18
100 # define MASKLO18 0000000777777LLU
101 # define MASKHI18 0777777000000LLU
102 # define MASK20 03777777U
103 # define MASK24 077777777U
104 # define MASK28 01777777777U
105 # define SIGN24 040000000U
106 # define SIGN36 0400000000000LLU
107
108 # define BIT37 01000000000000LLU
109 # define BIT38 02000000000000LLU
110 # define BIT35 0200000000000LLU
111 # define MASK32 037777777777U
112 # define MASK15 077777U
113 # define SMASK MASK15
114 # define SIGN15 040000U
115 # define MAGMASK 0377777777777LLU
116 # define ONES 0777777777777LLU
117 # define NEG136 0777777777777LLU
118 # define MAXPOS 0377777777777LLU
119 # define MAXNEG 0400000000000LLU
120 # define MAX36 0777777777777LLU
121 # define MAX72 (((word72)1U << 72) - 1U)
122
123 # define CARRY 01000000000000LLU
124 # define ZEROEXT 0777777777777LLU
125 # define ZEROEXT18 0777777U
126
127 # if defined(NEED_128)
128
129 # define SIGN72 (construct_128 (0200U, 0U))
130
131 # define BIT68 (construct_128 (010U, 0U))
132 # define BIT69 (construct_128 (020U, 0U))
133 # define BIT70 (construct_128 (040U, 0U))
134 # define BIT71 (construct_128 (0100U, 0U))
135 # define BIT73 (construct_128 (0400U, 0U))
136 # define BIT74 (construct_128 (01000U, 0U))
137 # define MASK63 0x7FFFFFFFFFFFFFFF
138 # define MASK64 0xFFFFFFFFFFFFFFFF
139 # define MASK68 (construct_128 (017U, MASK64))
140 # define MASK70 (construct_128 (0077U, MASK64))
141 # define MASK71 (construct_128 (0177U, MASK64))
142 # define MASK72 (construct_128 (0377U, MASK64))
143
144 # else
145
146 # define SIGN72 ((word72)1U << 71)
147
148 # define BIT68 ((word72)1U << 67)
149 # define BIT69 ((word72)1U << 68)
150 # define BIT70 ((word72)1U << 69)
151 # define BIT71 ((word72)1U << 70)
152 # define BIT73 ((word72)1U << 72)
153 # define BIT74 ((word72)1U << 73)
154
155 # define MASK68 (((word72)1U << 68) - 1U)
156 # define MASK70 (((word72)1U << 70) - 1U)
157 # define MASK71 (((word72)1U << 71) - 1U)
158 # define MASK72 (((word72)1U << 72) - 1U)
159 # define ZEROEXT72 (((word72)1U << 72) - 1U)
160
161 # endif
162
163 # define SIGN64 ((uint64)1U << 63)
164
165 # define MASK2 03U
166 # define MASK3 07U
167 # define MASK4 017U
168 # define MASK5 037U
169 # define MASK6 077U
170 # define MASK7 0177U
171
172 # define SIGN8 0200U
173 # define MASK8 0377U
174 # define MASK9 0777U
175
176 # define MASK11 03777U
177
178 # define SIGN12 0x800U
179 # define MASK12 07777U
180
181 # define SIGN6 0040U
182
183 # define MASK35 0377777777777llu
184
185 # define MASKBITS(x) ( ~(~((uint64)0)<<x) )
186 # define MASKBITS18(x) ( ~(~((word18)0)<<x) )
187 # define MASKBITS72(x) ( ~(~((word72)0)<<x) )
188
189 # define GETHI36(a) ((word18) (((a) >> 18) & MASK18))
190 # define GETLO36(a) ((word18) ((a) & MASK18))
191 # define SETHI36(a,b) (((a) &= MASKLO18), ((a) |= ((((word36)(b) & MASKLO18) << 18))))
192 # define SETLO36(a,b) (((a) &= MASKHI18), ((a) |= ((word36)(b) & MASKLO18)))
193 # define GETHI(a) GETHI36((a))
194 # define GETLO(a) GETLO36((a))
195 # define SETHI(a,b) SETHI36((a),(b))
196 # define SETLO(a,b) SETLO36((a),(b))
197
198 # define GETHI72(a) ((word36) (((a) >> 36) & MASK36))
199 # define GETLO72(a) ((word36) ((a) & MASK36))
200 # define SETHI72(a,b) ((a) &= MASK36, (a) |= ((((word72)(b) & MASK36)) << 36))
201 # define SETLO72(a,b) ((a) &= MASK36 << 36, (a) |= ((word72)(b) & MASK36))
202
203 # define GET24(a) ((word24) ((a) & MASK24))
204 # define MASK21 07777777llu
205 # define SIGN21 04000000llu
206 # define MASK22 017777777llu
207 # define SIGN22 010000000llu
208 # define MASK27 0777777777llu
209
210
211
212 static inline int SIGNEXT6_int (word6 w)
213 {
214 if (w & SIGN6)
215 {
216 return ((int) w) | (int) (((uint) -1) << 6);
217 }
218 return w & MASK6;
219 }
220
221 static inline int SIGNEXT8_int (word8 w)
222 {
223 if (w & SIGN8)
224 {
225 return ((int) w) | (int) (((uint) -1) << 8);
226 }
227 return w & MASK8;
228 }
229
230 static inline int32 SIGNEXT15_32 (word15 w)
231 {
232 if (w & SIGN15)
233 {
234 return ((int32) w) | (int32) (((uint32) -1) << 15);
235 }
236 return w & MASK15;
237 }
238
239 static inline int32 SIGNEXT18_32 (word18 w)
240 {
241 if (w & SIGN18)
242 {
243 return ((int32) w) | (int32) (((uint32) -1) << 18);
244 }
245 return w & MASK18;
246 }
247
248 static inline int32 SIGNEXT21_32 (word21 w)
249 {
250 if (w & SIGN21)
251 {
252 return ((int32) w) | (int32) (((uint32) -1) << 21);
253 }
254 return w & MASK21;
255 }
256
257 static inline int32 SIGNEXT22_32 (word22 w)
258 {
259 if (w & SIGN22)
260 {
261 return ((int32) w) | (int32) (((uint32) -1) << 22);
262 }
263 return w & MASK22;
264 }
265
266 static inline int32 SIGNEXT24_32 (word24 w)
267 {
268 if (w & SIGN24)
269 {
270 return ((int32) w) | (int32) (((uint32) -1) << 24);
271 }
272 return w & MASK24;
273 }
274
275 static inline t_int64 SIGNEXT36_64 (word36 w)
276 {
277 if (w & SIGN36)
278 {
279 return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 36);
280 }
281 return w & MASK36;
282 }
283
284 static inline t_int64 SIGNEXT18_64 (word36 w)
285 {
286 if (w & SIGN18)
287 {
288 return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 18);
289 }
290 return w & MASK18;
291 }
292
293 static inline t_int64 SIGNEXT21_64 (word36 w)
294 {
295 if (w & SIGN21)
296 {
297 return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 21);
298 }
299 return w & MASK21;
300 }
301
302 static inline t_int64 SIGNEXT22_64 (word36 w)
303 {
304 if (w & SIGN22)
305 {
306 return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 22);
307 }
308 return w & MASK22;
309 }
310
311 static inline t_int64 SIGNEXT24_64 (word36 w)
312 {
313 if (w & SIGN24)
314 {
315 return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 24);
316 }
317 return w & MASK24;
318 }
319
320 static inline int128 SIGNEXT72_128 (word72 w)
321 {
322 # if defined(NEED_128)
323 if (isnonzero_128 (and_128 (w, SIGN72)))
324 {
325 uint128 v = or_128 (w, construct_128 (0xFFFFFFFFFFFFFF80, 0));
326 return cast_s128 (v);
327 }
328 uint128 v = and_128 (w, MASK72);
329 # if defined(__sun__) || defined(_AIX)
330 return (int128) { (uint64_t) v.h, v.l};
331 # elif defined(__MINGW32__)
332 return (int128) { (int64_t) v.h, v.l};
333 # else
334 return (int128) { (__int64_t) v.h, v.l};
335 # endif
336 # else
337 if (w & SIGN72)
338 {
339 return ((int128) w) | (int128) (((uint128) -1ll) << 72);
340 }
341 return w & MASK72;
342 # endif
343 }
344
345 # if defined(NEED_128)
346 static inline int128 SIGNEXT36_128 (word36 w)
347 {
348 if (w & SIGN36)
349 {
350 return construct_s128 ((int64_t) MASK64, w | 0xFFFFFFF000000000);
351 }
352 return construct_s128 (0, w);
353 }
354 # endif
355
356
357
358
359
360
361 static inline word18 SIGNEXT15_18 (word15 w)
362 {
363 if (w & SIGN15)
364 {
365 return (w | ((word18) -1) << 15) & MASK18;
366 }
367 return w & MASK15;
368 }
369
370 static inline word24 SIGNEXT18_24 (word18 w)
371 {
372 if (w & SIGN18)
373 {
374 return (w | ((word24) -1) << 18) & MASK24;
375 }
376 return w & MASK18;
377 }
378
379 static inline word72 SIGNEXT36_72 (word36 w)
380 {
381 # if defined(NEED_128)
382 if (w & SIGN36)
383 {
384
385 return construct_128 (0377U, (w & MASK36) | 0xFFFFFFF000000000);
386 }
387
388 return construct_128 (0, w & MASK36);
389 # else
390 if (w & SIGN36)
391 {
392 return (w | ((word72) DMASK) << 36) & MASK72;
393 }
394 return w & MASK36;
395 # endif
396 }
397
398 # define SETS36(x) ((x) | SIGN36)
399 # define CLRS36(x) ((x) & ~SIGN36)
400 # define TSTS36(x) ((x) & SIGN36)
401
402
403
404
405
406
407 # define INST_V_TAG 0
408 # define INST_M_TAG 077U
409 # define INST_V_A 6
410 # define INST_M_A 1U
411 # define INST_V_I 7
412 # define INST_M_I 1U
413 # define INST_V_OP 9
414 # define INST_M_OP 0777U
415 # define INST_V_OPX 8
416 # define INST_M_OPX 1U
417
418 # define INST_V_ADDR 18
419 # define INST_M_ADDR 0777777U
420 # define INST_V_OFFSET 18
421 # define INST_M_OFFSET 077777U
422 # define INST_V_PRN 33
423 # define INST_M_PRN 07U
424 # define INST_V_ARN 33
425 # define INST_M_ARN 07U
426
427 # define GET_TAG(x) ((word6) ( (x) & INST_M_TAG ))
428 # define GET_A(x) ((word1) (((x) >> INST_V_A) & INST_M_A ))
429 # define GET_I(x) ((int32) (((x) >> INST_V_I) & INST_M_I ))
430 # define GET_OP(x) ((word9) (((x) >> INST_V_OP) & INST_M_OP ))
431 # define GET_OPX(x) ((bool) (((x) >> INST_V_OPX) & INST_M_OPX))
432
433 # define GET_OFFSET(x) ((word15) (((x) >> INST_V_OFFSET) & INST_M_OFFSET))
434 # define GET_PRN(x) ((word3) (((x) >> INST_V_PRN) & INST_M_PRN))
435 # define GET_ARN(x) ((word3) (((x) >> INST_V_ARN) & INST_M_ARN))
436
437 # define GET_TM(x) ( (GET_TAG(x) & 060U))
438 # define GET_TD(x) ( (GET_TAG(x) & 017U))
439
440 # define GET_ADDR(x) ((uint32) (((x) >> INST_V_ADDR) & INST_M_ADDR))
441
442
443 # define TAG_R 0U
444 # define TAG_RI 1U
445 # define TAG_IT 2U
446 # define TAG_IR 3U
447
448 # define _TD(tag) ((tag) & 017U)
449 # define _TM(tag) ((tag) & 060U)
450
451 enum {
452 TD_N = 000U,
453 TD_AU = 001U,
454 TD_QU = 002U,
455 TD_DU = 003U,
456 TD_IC = 004U,
457 TD_AL = 005U,
458 TD_QL = 006U,
459 TD_DL = 007U,
460 TD_X0 = 010U,
461 TD_X1 = 011U,
462 TD_X2 = 012U,
463 TD_X3 = 013U,
464 TD_X4 = 014U,
465 TD_X5 = 015U,
466 TD_X6 = 016U,
467 TD_X7 = 017U
468 };
469
470 enum {
471 TM_R = 000U,
472 TM_RI = 020U,
473 TM_IT = 040U,
474 TM_IR = 060U
475 };
476
477
478 enum {
479 IT_F1 = 000U,
480 IT_SD = 004U,
481 IT_SCR = 005U,
482 IT_F2 = 006U,
483 IT_F3 = 007U,
484 IT_CI = 010U,
485 IT_I = 011U,
486 IT_SC = 012U,
487 IT_AD = 013U,
488 IT_DI = 014U,
489 IT_DIC = 015U,
490 IT_ID = 016U,
491 IT_IDC = 017U,
492
493
494 SPEC_ITP = 001U,
495 SPEC_ITS = 003U
496 };
497
498 # define GET_TB(tag) ((tag) & 040U)
499 # define GET_CF(tag) ((tag) & 007U)
500
501 # define _TB(tag) GET_TB((tag))
502 # define _CF(tag) GET_CF((tag))
503
504 # define TB6 000U
505 # define TB9 040U
506
507
508
509
510
511
512 # define ISITP(x) (((x) & INST_M_TAG) == 041U)
513 # define GET_ITP_PRNUM(Ypair) ((word3) (((Ypair)[0] >> 33) & 07U))
514 # define GET_ITP_WORDNO(Ypair) ((word18) (((Ypair)[1] >> 18) & WMASK))
515 # define GET_ITP_BITNO(Ypair) ((word6) (((Ypair)[1] >> 9) & 077U))
516 # define GET_ITP_MOD(Ypair) (GET_TAG((Ypair)[1]))
517
518 # define ISITS(x) (((x) & INST_M_TAG) == 043U)
519 # define GET_ITS_SEGNO(Ypair) ((word15) (((Ypair)[0] >> 18) & SMASK))
520 # define GET_ITS_RN(Ypair) ((word3) (((Ypair)[0] >> 15) & 07))
521 # define GET_ITS_WORDNO(Ypair) ((word18) (((Ypair)[1] >> 18) & WMASK))
522 # define GET_ITS_BITNO(Ypair) ((word6) (((Ypair)[1] >> 9) & 077))
523 # define GET_ITS_MOD(Ypair) (GET_TAG((Ypair)[1]))
524
525
526
527
528
529
530 # define F_V_A 17
531 # define F_V_B 16
532 # define F_V_C 15
533 # define F_V_D 14
534 # define F_V_E 13
535 # define F_V_F 12
536 # define F_V_G 11
537 # define F_V_H 10
538 # define F_V_I 9
539 # define F_V_J 8
540 # define F_V_K 7
541 # define F_V_L 6
542 # define F_V_M 5
543 # define F_V_N 4
544 # define F_V_O 3
545
546 # define F_A (1LLU << F_V_A)
547 # define F_B (1LLU << F_V_B)
548 # define F_C (1LLU << F_V_C)
549 # define F_D (1LLU << F_V_D)
550 # define F_E (1LLU << F_V_E)
551 # define F_F (1LLU << F_V_F)
552 # define F_G (1LLU << F_V_G)
553 # define F_H (1LLU << F_V_H)
554 # define F_I (1LLU << F_V_I)
555 # define F_J (1LLU << F_V_J)
556 # define F_K (1LLU << F_V_K)
557 # define F_L (1LLU << F_V_L)
558 # define F_M (1LLU << F_V_M)
559 # define F_N (1LLU << F_V_N)
560 # define F_O (1LLU << F_V_O)
561
562 # define I_HEX F_O
563 # define I_ABS F_N
564 # define I_MIF F_M
565 # define I_TRUNC F_L
566 # define I_NBAR F_K
567 # define I_PMASK F_J
568 # define I_PERR F_I
569 # define I_TALLY F_H
570 # define I_OMASK F_G
571 # define I_EUFL F_F
572 # define I_EOFL F_E
573 # define I_OFLOW F_D
574 # define I_CARRY F_C
575 # define I_NEG F_B
576 # define I_ZERO F_A
577
578 # define I_ZNOC (I_ZERO | I_NEG | I_OFLOW | I_CARRY)
579 # define I_ZNC (I_ZERO | I_NEG | I_CARRY)
580
581 # define CLR_I_ABS CLRF (cpu.cu.IR, I_ABS)
582 # define CLR_I_MIF CLRF (cpu.cu.IR, I_MIF)
583 # define CLR_I_TRUNC CLRF (cpu.cu.IR, I_TRUNC)
584 # define CLR_I_NBAR CLRF (cpu.cu.IR, I_NBAR)
585 # define CLR_I_TALLY CLRF (cpu.cu.IR, I_TALLY)
586 # define CLR_I_PMASK CLRF (cpu.cu.IR, I_PMASK)
587 # define CLR_I_EOFL CLRF (cpu.cu.IR, I_EOFL)
588 # define CLR_I_EUFL CLRF (cpu.cu.IR, I_EUFL)
589 # define CLR_I_OFLOW CLRF (cpu.cu.IR, I_OFLOW)
590 # define CLR_I_CARRY CLRF (cpu.cu.IR, I_CARRY)
591 # define CLR_I_NEG CLRF (cpu.cu.IR, I_NEG)
592 # define CLR_I_ZERO CLRF (cpu.cu.IR, I_ZERO)
593
594 # define SET_I_ABS SETF (cpu.cu.IR, I_ABS)
595 # define SET_I_NBAR SETF (cpu.cu.IR, I_NBAR)
596 # define SET_I_TRUNC SETF (cpu.cu.IR, I_TRUNC)
597 # define SET_I_TALLY SETF (cpu.cu.IR, I_TALLY)
598 # define SET_I_EOFL SETF (cpu.cu.IR, I_EOFL)
599 # define SET_I_EUFL SETF (cpu.cu.IR, I_EUFL)
600 # define SET_I_OFLOW SETF (cpu.cu.IR, I_OFLOW)
601 # define SET_I_CARRY SETF (cpu.cu.IR, I_CARRY)
602 # define SET_I_NEG SETF (cpu.cu.IR, I_NEG)
603 # define SET_I_ZERO SETF (cpu.cu.IR, I_ZERO)
604
605 # define TST_I_ABS TSTF (cpu.cu.IR, I_ABS)
606 # define TST_I_MIF TSTF (cpu.cu.IR, I_MIF)
607 # define TST_I_NBAR TSTF (cpu.cu.IR, I_NBAR)
608 # define TST_I_PMASK TSTF (cpu.cu.IR, I_PMASK)
609 # define TST_I_TRUNC TSTF (cpu.cu.IR, I_TRUNC)
610 # define TST_I_TALLY TSTF (cpu.cu.IR, I_TALLY)
611 # define TST_I_OMASK TSTF (cpu.cu.IR, I_OMASK)
612 # define TST_I_EUFL TSTF (cpu.cu.IR, I_EUFL )
613 # define TST_I_EOFL TSTF (cpu.cu.IR, I_EOFL )
614 # define TST_I_OFLOW TSTF (cpu.cu.IR, I_OFLOW)
615 # define TST_I_CARRY TSTF (cpu.cu.IR, I_CARRY)
616 # define TST_I_NEG TSTF (cpu.cu.IR, I_NEG)
617 # define TST_I_ZERO TSTF (cpu.cu.IR, I_ZERO)
618 # define TST_I_HEX TSTF (cpu.cu.IR, I_HEX)
619
620 # define SC_I_HEX(v) SCF (v, cpu.cu.IR, I_HEX)
621 # define SC_I_MIF(v) SCF (v, cpu.cu.IR, I_MIF)
622 # define SC_I_TALLY(v) SCF (v, cpu.cu.IR, I_TALLY)
623 # define SC_I_NEG(v) SCF (v, cpu.cu.IR, I_NEG)
624 # define SC_I_ZERO(v) SCF (v, cpu.cu.IR, I_ZERO)
625 # define SC_I_CARRY(v) SCF (v, cpu.cu.IR, I_CARRY);
626 # define SC_I_OFLOW(v) SCF (v, cpu.cu.IR, I_OFLOW);
627 # define SC_I_EOFL(v) SCF (v, cpu.cu.IR, I_EOFL);
628 # define SC_I_EUFL(v) SCF (v, cpu.cu.IR, I_EUFL);
629 # define SC_I_OMASK(v) SCF (v, cpu.cu.IR, I_OMASK);
630 # define SC_I_PERR(v) SCF (v, cpu.cu.IR, I_PERR);
631 # define SC_I_PMASK(v) SCF (v, cpu.cu.IR, I_PMASK);
632 # define SC_I_TRUNC(v) SCF (v, cpu.cu.IR, I_TRUNC);
633
634
635
636
637
638
639 # define FLOAT36MASK 01777777777LLU
640 # define FLOAT72MASK 01777777777777777777777LLU
641 # define FLOAT72SIGN (1LLU << 63)
642
643
644
645
646
647
648
649 # define N_FAULT_GROUPS 7
650 # define N_FAULTS 32
651
652 enum _fault
653 {
654 FAULT_SDF = 0U,
655 FAULT_STR = 1U,
656 FAULT_MME = 2U,
657 FAULT_F1 = 3U,
658 FAULT_TRO = 4U,
659 FAULT_CMD = 5U,
660 FAULT_DRL = 6U,
661 FAULT_LUF = 7U,
662 FAULT_CON = 8U,
663 FAULT_PAR = 9U,
664 FAULT_IPR = 10U,
665 FAULT_ONC = 11U,
666 FAULT_SUF = 12U,
667 FAULT_OFL = 13U,
668 FAULT_DIV = 14U,
669 FAULT_EXF = 15U,
670 FAULT_DF0 = 16U,
671 FAULT_DF1 = 17U,
672 FAULT_DF2 = 18U,
673 FAULT_DF3 = 19U,
674 FAULT_ACV = 20U,
675 FAULT_MME2 = 21U,
676 FAULT_MME3 = 22U,
677 FAULT_MME4 = 23U,
678 FAULT_F2 = 24U,
679 FAULT_F3 = 25U,
680 FAULT_UN1 = 26U,
681 FAULT_UN2 = 27U,
682 FAULT_UN3 = 28U,
683 FAULT_UN4 = 29U,
684 FAULT_UN5 = 30U,
685 FAULT_TRB = 31U
686 };
687
688 # define FAULTBASE_MASK 07740U
689
690 typedef enum _fault _fault;
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747 typedef enum fault_onc_subtype_
748 {
749 flt_onc_nem,
750 flt_onc_FORCE = 0400000000000llu
751 } fault_onc_subtype_;
752
753 typedef enum fault_str_subtype_
754 {
755 flt_str_oob,
756 flt_str_ill_ptr,
757 flt_str_nea,
758 flt_str_FORCE = 0400000000000llu
759 } fault_str_subtype_;
760
761 typedef enum fault_con_subtype_
762 {
763 con_a = 0,
764 con_b = 1,
765 con_c = 2,
766 con_d = 3,
767 flt_con_FORCE = 0400000000000llu
768 } fault_con_subtype_;
769
770 typedef enum fault_acv_subtype_
771 {
772 ACV0 = (1U << 15),
773 ACV1 = (1U << 14),
774 ACV2 = (1U << 13),
775 ACV3 = (1U << 12),
776 ACV4 = (1U << 11),
777 ACV5 = (1U << 10),
778 ACV6 = (1U << 9),
779 ACV7 = (1U << 8),
780 ACV8 = (1U << 7),
781 ACV9 = (1U << 6),
782 ACV10 = (1U << 5),
783 ACV11 = (1U << 4),
784 ACV12 = (1U << 3),
785 ACV13 = (1U << 2),
786 ACV14 = (1U << 1),
787 ACV15 = (1U << 0),
788 flt_acv_FORCE = 0400000000000llu
789 } fault_acv_subtype_;
790
791 # define FR_ILL_OP_CONST 0400000000000llu
792 # define FR_ILL_MOD_CONST 0200000000000llu
793 # define FR_ILL_SLV_CONST 0100000000000llu
794
795 typedef enum fault_ipr_subtype_
796 {
797 FR_ILL_OP = FR_ILL_OP_CONST,
798 FR_ILL_MOD = FR_ILL_MOD_CONST,
799 FR_ILL_SLV = FR_ILL_SLV_CONST,
800 FR_ILL_PROC = 0040000000000llu,
801 FR_ILL_PROC_MOD = 0240000000000llu,
802 FR_NEM = 0020000000000llu,
803 FR_OOB = 0010000000000llu,
804 FR_ILL_DIG = 0004000000000llu,
805 FR_PROC_PARU = 0002000000000llu,
806 FR_PROC_PARL = 0001000000000llu,
807 FR_CON_A = 0000400000000llu,
808 FR_CON_B = 0000200000000llu,
809 FR_CON_C = 0000100000000llu,
810 FR_CON_D = 0000040000000llu,
811 FR_DA_ERR = 0000020000000llu,
812 FR_DA_ERR2 = 0000010000000llu
813 } fault_ipr_subtype_;
814
815 typedef enum fault_cmd_subtype_
816 {
817 flt_cmd_lprpn_bits,
818 flt_cmd_not_control,
819 flt_cmd_FORCE = 0400000000000llu
820 } fault_cmd_subtype_;
821
822 typedef union _fault_subtype
823 {
824 fault_onc_subtype_ fault_onc_subtype;
825 fault_str_subtype_ fault_str_subtype;
826 fault_con_subtype_ fault_con_subtype;
827 fault_acv_subtype_ fault_acv_subtype;
828 fault_ipr_subtype_ fault_ipr_subtype;
829 fault_cmd_subtype_ fault_cmd_subtype;
830 word36 bits;
831 } _fault_subtype;
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888 # define N_INTERRUPTS 32
889
890
891
892
893
894
895 # define IOM_MBX_LOW 01200
896 # define IOM_MBX_LEN 02200
897 # define DN355_MBX_LOW 03400
898 # define DN355_MBX_LEN 03000
899
900
901
902
903
904
905
906
907
908 typedef enum {
909 opcode0_mme = 0001U,
910 opcode0_drl = 0002U,
911 opcode0_mme2 = 0004U,
912 opcode0_mme3 = 0005U,
913 opcode0_mme4 = 0007U,
914 opcode0_nop = 0011U,
915 opcode0_puls1 = 0012U,
916 opcode0_puls2 = 0013U,
917 opcode0_cioc = 0015U,
918 opcode0_adlx0 = 0020U,
919 opcode0_adlx1 = 0021U,
920 opcode0_adlx2 = 0022U,
921 opcode0_adlx3 = 0023U,
922 opcode0_adlx4 = 0024U,
923 opcode0_adlx5 = 0025U,
924 opcode0_adlx6 = 0026U,
925 opcode0_adlx7 = 0027U,
926 opcode0_ldqc = 0032U,
927 opcode0_adl = 0033U,
928 opcode0_ldac = 0034U,
929 opcode0_adla = 0035U,
930 opcode0_adlq = 0036U,
931 opcode0_adlaq = 0037U,
932 opcode0_asx0 = 0040U,
933 opcode0_asx1 = 0041U,
934 opcode0_asx2 = 0042U,
935 opcode0_asx3 = 0043U,
936 opcode0_asx4 = 0044U,
937 opcode0_asx5 = 0045U,
938 opcode0_asx6 = 0046U,
939 opcode0_asx7 = 0047U,
940 opcode0_adwp0 = 0050U,
941 opcode0_adwp1 = 0051U,
942 opcode0_adwp2 = 0052U,
943 opcode0_adwp3 = 0053U,
944 opcode0_aos = 0054U,
945 opcode0_asa = 0055U,
946 opcode0_asq = 0056U,
947 opcode0_sscr = 0057U,
948 opcode0_adx0 = 0060U,
949 opcode0_adx1 = 0061U,
950 opcode0_adx2 = 0062U,
951 opcode0_adx3 = 0063U,
952 opcode0_adx4 = 0064U,
953 opcode0_adx5 = 0065U,
954 opcode0_adx6 = 0066U,
955 opcode0_adx7 = 0067U,
956 opcode0_awca = 0071U,
957 opcode0_awcq = 0072U,
958 opcode0_lreg = 0073U,
959 opcode0_ada = 0075U,
960 opcode0_adq = 0076U,
961 opcode0_adaq = 0077U,
962 opcode0_cmpx0 = 0100U,
963 opcode0_cmpx1 = 0101U,
964 opcode0_cmpx2 = 0102U,
965 opcode0_cmpx3 = 0103U,
966 opcode0_cmpx4 = 0104U,
967 opcode0_cmpx5 = 0105U,
968 opcode0_cmpx6 = 0106U,
969 opcode0_cmpx7 = 0107U,
970 opcode0_cwl = 0111U,
971 opcode0_cmpa = 0115U,
972 opcode0_cmpq = 0116U,
973 opcode0_cmpaq = 0117U,
974 opcode0_sblx0 = 0120U,
975 opcode0_sblx1 = 0121U,
976 opcode0_sblx2 = 0122U,
977 opcode0_sblx3 = 0123U,
978 opcode0_sblx4 = 0124U,
979 opcode0_sblx5 = 0125U,
980 opcode0_sblx6 = 0126U,
981 opcode0_sblx7 = 0127U,
982 opcode0_sbla = 0135U,
983 opcode0_sblq = 0136U,
984 opcode0_sblaq = 0137U,
985 opcode0_ssx0 = 0140U,
986 opcode0_ssx1 = 0141U,
987 opcode0_ssx2 = 0142U,
988 opcode0_ssx3 = 0143U,
989 opcode0_ssx4 = 0144U,
990 opcode0_ssx5 = 0145U,
991 opcode0_ssx6 = 0146U,
992 opcode0_ssx7 = 0147U,
993 opcode0_adwp4 = 0150U,
994 opcode0_adwp5 = 0151U,
995 opcode0_adwp6 = 0152U,
996 opcode0_adwp7 = 0153U,
997 opcode0_sdbr = 0154U,
998 opcode0_ssa = 0155U,
999 opcode0_ssq = 0156U,
1000 opcode0_sbx0 = 0160U,
1001 opcode0_sbx1 = 0161U,
1002 opcode0_sbx2 = 0162U,
1003 opcode0_sbx3 = 0163U,
1004 opcode0_sbx4 = 0164U,
1005 opcode0_sbx5 = 0165U,
1006 opcode0_sbx6 = 0166U,
1007 opcode0_sbx7 = 0167U,
1008 opcode0_swca = 0171U,
1009 opcode0_swcq = 0172U,
1010 opcode0_lpri = 0173U,
1011 opcode0_sba = 0175U,
1012 opcode0_sbq = 0176U,
1013 opcode0_sbaq = 0177U,
1014 opcode0_cnax0 = 0200U,
1015 opcode0_cnax1 = 0201U,
1016 opcode0_cnax2 = 0202U,
1017 opcode0_cnax3 = 0203U,
1018 opcode0_cnax4 = 0204U,
1019 opcode0_cnax5 = 0205U,
1020 opcode0_cnax6 = 0206U,
1021 opcode0_cnax7 = 0207U,
1022 opcode0_cmk = 0211U,
1023 opcode0_absa = 0212U,
1024 opcode0_epaq = 0213U,
1025 opcode0_sznc = 0214U,
1026 opcode0_cnaa = 0215U,
1027 opcode0_cnaq = 0216U,
1028 opcode0_cnaaq = 0217U,
1029 opcode0_ldx0 = 0220U,
1030 opcode0_ldx1 = 0221U,
1031 opcode0_ldx2 = 0222U,
1032 opcode0_ldx3 = 0223U,
1033 opcode0_ldx4 = 0224U,
1034 opcode0_ldx5 = 0225U,
1035 opcode0_ldx6 = 0226U,
1036 opcode0_ldx7 = 0227U,
1037 opcode0_lbar = 0230U,
1038 opcode0_rsw = 0231U,
1039 opcode0_ldbr = 0232U,
1040 opcode0_rmcm = 0233U,
1041 opcode0_szn = 0234U,
1042 opcode0_lda = 0235U,
1043 opcode0_ldq = 0236U,
1044 opcode0_ldaq = 0237U,
1045 opcode0_orsx0 = 0240U,
1046 opcode0_orsx1 = 0241U,
1047 opcode0_orsx2 = 0242U,
1048 opcode0_orsx3 = 0243U,
1049 opcode0_orsx4 = 0244U,
1050 opcode0_orsx5 = 0245U,
1051 opcode0_orsx6 = 0246U,
1052 opcode0_orsx7 = 0247U,
1053 opcode0_spri0 = 0250U,
1054 opcode0_spbp1 = 0251U,
1055 opcode0_spri2 = 0252U,
1056 opcode0_spbp3 = 0253U,
1057 opcode0_spri = 0254U,
1058 opcode0_orsa = 0255U,
1059 opcode0_orsq = 0256U,
1060 opcode0_lsdp = 0257U,
1061 opcode0_orx0 = 0260U,
1062 opcode0_orx1 = 0261U,
1063 opcode0_orx2 = 0262U,
1064 opcode0_orx3 = 0263U,
1065 opcode0_orx4 = 0264U,
1066 opcode0_orx5 = 0265U,
1067 opcode0_orx6 = 0266U,
1068 opcode0_orx7 = 0267U,
1069 opcode0_tsp0 = 0270U,
1070 opcode0_tsp1 = 0271U,
1071 opcode0_tsp2 = 0272U,
1072 opcode0_tsp3 = 0273U,
1073 opcode0_ora = 0275U,
1074 opcode0_orq = 0276U,
1075 opcode0_oraq = 0277U,
1076 opcode0_canx0 = 0300U,
1077 opcode0_canx1 = 0301U,
1078 opcode0_canx2 = 0302U,
1079 opcode0_canx3 = 0303U,
1080 opcode0_canx4 = 0304U,
1081 opcode0_canx5 = 0305U,
1082 opcode0_canx6 = 0306U,
1083 opcode0_canx7 = 0307U,
1084 opcode0_eawp0 = 0310U,
1085 opcode0_easp0 = 0311U,
1086 opcode0_eawp2 = 0312U,
1087 opcode0_easp2 = 0313U,
1088 opcode0_cana = 0315U,
1089 opcode0_canq = 0316U,
1090 opcode0_canaq = 0317U,
1091 opcode0_lcx0 = 0320U,
1092 opcode0_lcx1 = 0321U,
1093 opcode0_lcx2 = 0322U,
1094 opcode0_lcx3 = 0323U,
1095 opcode0_lcx4 = 0324U,
1096 opcode0_lcx5 = 0325U,
1097 opcode0_lcx6 = 0326U,
1098 opcode0_lcx7 = 0327U,
1099 opcode0_eawp4 = 0330U,
1100 opcode0_easp4 = 0331U,
1101 opcode0_eawp6 = 0332U,
1102 opcode0_easp6 = 0333U,
1103 opcode0_lca = 0335U,
1104 opcode0_lcq = 0336U,
1105 opcode0_lcaq = 0337U,
1106 opcode0_ansx0 = 0340U,
1107 opcode0_ansx1 = 0341U,
1108 opcode0_ansx2 = 0342U,
1109 opcode0_ansx3 = 0343U,
1110 opcode0_ansx4 = 0344U,
1111 opcode0_ansx5 = 0345U,
1112 opcode0_ansx6 = 0346U,
1113 opcode0_ansx7 = 0347U,
1114 opcode0_epp0 = 0350U,
1115 opcode0_epbp1 = 0351U,
1116 opcode0_epp2 = 0352U,
1117 opcode0_epbp3 = 0353U,
1118 opcode0_stac = 0354U,
1119 opcode0_ansa = 0355U,
1120 opcode0_ansq = 0356U,
1121 opcode0_stcd = 0357U,
1122 opcode0_anx0 = 0360U,
1123 opcode0_anx1 = 0361U,
1124 opcode0_anx2 = 0362U,
1125 opcode0_anx3 = 0363U,
1126 opcode0_anx4 = 0364U,
1127 opcode0_anx5 = 0365U,
1128 opcode0_anx6 = 0366U,
1129 opcode0_anx7 = 0367U,
1130 opcode0_epp4 = 0370U,
1131 opcode0_epbp5 = 0371U,
1132 opcode0_epp6 = 0372U,
1133 opcode0_epbp7 = 0373U,
1134 opcode0_ana = 0375U,
1135 opcode0_anq = 0376U,
1136 opcode0_anaq = 0377U,
1137 opcode0_mpf = 0401U,
1138 opcode0_mpy = 0402U,
1139 opcode0_cmg = 0405U,
1140 opcode0_lde = 0411U,
1141 opcode0_rscr = 0413U,
1142 opcode0_ade = 0415U,
1143 opcode0_ufm = 0421U,
1144 opcode0_dufm = 0423U,
1145 opcode0_fcmg = 0425U,
1146 opcode0_dfcmg = 0427U,
1147 opcode0_fszn = 0430U,
1148 opcode0_fld = 0431U,
1149 opcode0_dfld = 0433U,
1150 opcode0_ufa = 0435U,
1151 opcode0_dufa = 0437U,
1152 opcode0_sxl0 = 0440U,
1153 opcode0_sxl1 = 0441U,
1154 opcode0_sxl2 = 0442U,
1155 opcode0_sxl3 = 0443U,
1156 opcode0_sxl4 = 0444U,
1157 opcode0_sxl5 = 0445U,
1158 opcode0_sxl6 = 0446U,
1159 opcode0_sxl7 = 0447U,
1160 opcode0_stz = 0450U,
1161 opcode0_smic = 0451U,
1162 opcode0_scpr = 0452U,
1163 opcode0_stt = 0454U,
1164 opcode0_fst = 0455U,
1165 opcode0_ste = 0456U,
1166 opcode0_dfst = 0457U,
1167 opcode0_fmp = 0461U,
1168 opcode0_dfmp = 0463U,
1169 opcode0_fstr = 0470U,
1170 opcode0_frd = 0471U,
1171 opcode0_dfstr = 0472U,
1172 opcode0_dfrd = 0473U,
1173 opcode0_fad = 0475U,
1174 opcode0_dfad = 0477U,
1175 opcode0_rpl = 0500U,
1176 opcode0_bcd = 0505U,
1177 opcode0_div = 0506U,
1178 opcode0_dvf = 0507U,
1179 opcode0_fneg = 0513U,
1180 opcode0_fcmp = 0515U,
1181 opcode0_dfcmp = 0517U,
1182 opcode0_rpt = 0520U,
1183 opcode0_fdi = 0525U,
1184 opcode0_dfdi = 0527U,
1185 opcode0_neg = 0531U,
1186 opcode0_cams = 0532U,
1187 opcode0_negl = 0533U,
1188 opcode0_ufs = 0535U,
1189 opcode0_dufs = 0537U,
1190 opcode0_sprp0 = 0540U,
1191 opcode0_sprp1 = 0541U,
1192 opcode0_sprp2 = 0542U,
1193 opcode0_sprp3 = 0543U,
1194 opcode0_sprp4 = 0544U,
1195 opcode0_sprp5 = 0545U,
1196 opcode0_sprp6 = 0546U,
1197 opcode0_sprp7 = 0547U,
1198 opcode0_sbar = 0550U,
1199 opcode0_stba = 0551U,
1200 opcode0_stbq = 0552U,
1201 opcode0_smcm = 0553U,
1202 opcode0_stc1 = 0554U,
1203 opcode0_ssdp = 0557U,
1204 opcode0_rpd = 0560U,
1205 opcode0_fdv = 0565U,
1206 opcode0_dfdv = 0567U,
1207 opcode0_fno = 0573U,
1208 opcode0_fsb = 0575U,
1209 opcode0_dfsb = 0577U,
1210 opcode0_tze = 0600U,
1211 opcode0_tnz = 0601U,
1212 opcode0_tnc = 0602U,
1213 opcode0_trc = 0603U,
1214 opcode0_tmi = 0604U,
1215 opcode0_tpl = 0605U,
1216 opcode0_ttf = 0607U,
1217 opcode0_rtcd = 0610U,
1218 opcode0_rcu = 0613U,
1219 opcode0_teo = 0614U,
1220 opcode0_teu = 0615U,
1221 opcode0_dis = 0616U,
1222 opcode0_tov = 0617U,
1223 opcode0_eax0 = 0620U,
1224 opcode0_eax1 = 0621U,
1225 opcode0_eax2 = 0622U,
1226 opcode0_eax3 = 0623U,
1227 opcode0_eax4 = 0624U,
1228 opcode0_eax5 = 0625U,
1229 opcode0_eax6 = 0626U,
1230 opcode0_eax7 = 0627U,
1231 opcode0_ret = 0630U,
1232 opcode0_rccl = 0633U,
1233 opcode0_ldi = 0634U,
1234 opcode0_eaa = 0635U,
1235 opcode0_eaq = 0636U,
1236 opcode0_ldt = 0637U,
1237 opcode0_ersx0 = 0640U,
1238 opcode0_ersx1 = 0641U,
1239 opcode0_ersx2 = 0642U,
1240 opcode0_ersx3 = 0643U,
1241 opcode0_ersx4 = 0644U,
1242 opcode0_ersx5 = 0645U,
1243 opcode0_ersx6 = 0646U,
1244 opcode0_ersx7 = 0647U,
1245 opcode0_spri4 = 0650U,
1246 opcode0_spbp5 = 0651U,
1247 opcode0_spri6 = 0652U,
1248 opcode0_spbp7 = 0653U,
1249 opcode0_stacq = 0654U,
1250 opcode0_ersa = 0655U,
1251 opcode0_ersq = 0656U,
1252 opcode0_scu = 0657U,
1253 opcode0_erx0 = 0660U,
1254 opcode0_erx1 = 0661U,
1255 opcode0_erx2 = 0662U,
1256 opcode0_erx3 = 0663U,
1257 opcode0_erx4 = 0664U,
1258 opcode0_erx5 = 0665U,
1259 opcode0_erx6 = 0666U,
1260 opcode0_erx7 = 0667U,
1261 opcode0_tsp4 = 0670U,
1262 opcode0_tsp5 = 0671U,
1263 opcode0_tsp6 = 0672U,
1264 opcode0_tsp7 = 0673U,
1265 opcode0_lcpr = 0674U,
1266 opcode0_era = 0675U,
1267 opcode0_erq = 0676U,
1268 opcode0_eraq = 0677U,
1269 opcode0_tsx0 = 0700U,
1270 opcode0_tsx1 = 0701U,
1271 opcode0_tsx2 = 0702U,
1272 opcode0_tsx3 = 0703U,
1273 opcode0_tsx4 = 0704U,
1274 opcode0_tsx5 = 0705U,
1275 opcode0_tsx6 = 0706U,
1276 opcode0_tsx7 = 0707U,
1277 opcode0_tra = 0710U,
1278 opcode0_call6 = 0713U,
1279 opcode0_tss = 0715U,
1280 opcode0_xec = 0716U,
1281 opcode0_xed = 0717U,
1282 opcode0_lxl0 = 0720U,
1283 opcode0_lxl1 = 0721U,
1284 opcode0_lxl2 = 0722U,
1285 opcode0_lxl3 = 0723U,
1286 opcode0_lxl4 = 0724U,
1287 opcode0_lxl5 = 0725U,
1288 opcode0_lxl6 = 0726U,
1289 opcode0_lxl7 = 0727U,
1290 opcode0_ars = 0731U,
1291 opcode0_qrs = 0732U,
1292 opcode0_lrs = 0733U,
1293 opcode0_als = 0735U,
1294 opcode0_qls = 0736U,
1295 opcode0_lls = 0737U,
1296 opcode0_stx0 = 0740U,
1297 opcode0_stx1 = 0741U,
1298 opcode0_stx2 = 0742U,
1299 opcode0_stx3 = 0743U,
1300 opcode0_stx4 = 0744U,
1301 opcode0_stx5 = 0745U,
1302 opcode0_stx6 = 0746U,
1303 opcode0_stx7 = 0747U,
1304 opcode0_stc2 = 0750U,
1305 opcode0_stca = 0751U,
1306 opcode0_stcq = 0752U,
1307 opcode0_sreg = 0753U,
1308 opcode0_sti = 0754U,
1309 opcode0_sta = 0755U,
1310 opcode0_stq = 0756U,
1311 opcode0_staq = 0757U,
1312 opcode0_lprp0 = 0760U,
1313 opcode0_lprp1 = 0761U,
1314 opcode0_lprp2 = 0762U,
1315 opcode0_lprp3 = 0763U,
1316 opcode0_lprp4 = 0764U,
1317 opcode0_lprp5 = 0765U,
1318 opcode0_lprp6 = 0766U,
1319 opcode0_lprp7 = 0767U,
1320 opcode0_arl = 0771U,
1321 opcode0_qrl = 0772U,
1322 opcode0_lrl = 0773U,
1323 opcode0_gtb = 0774U,
1324 opcode0_alr = 0775U,
1325 opcode0_qlr = 0776U,
1326 opcode0_llr = 0777U
1327 } opcode0_t;
1328
1329
1330 typedef enum {
1331 opcode1_mve = 0020U,
1332 opcode1_mvne = 0024U,
1333 opcode1_csl = 0060U,
1334 opcode1_csr = 0061U,
1335 opcode1_sztl = 0064U,
1336 opcode1_sztr = 0065U,
1337 opcode1_cmpb = 0066U,
1338 opcode1_mlr = 0100U,
1339 opcode1_mrl = 0101U,
1340 opcode1_cmpc = 0106U,
1341 opcode1_scd = 0120U,
1342 opcode1_scdr = 0121U,
1343 opcode1_scm = 0124U,
1344 opcode1_scmr = 0125U,
1345 opcode1_sptr = 0154U,
1346 opcode1_mvt = 0160U,
1347 opcode1_tct = 0164U,
1348 opcode1_tctr = 0165U,
1349 opcode1_lptr = 0173U,
1350 opcode1_ad2d = 0202U,
1351 opcode1_sb2d = 0203U,
1352 opcode1_mp2d = 0206U,
1353 opcode1_dv2d = 0207U,
1354 opcode1_ad3d = 0222U,
1355 opcode1_sb3d = 0223U,
1356 opcode1_mp3d = 0226U,
1357 opcode1_dv3d = 0227U,
1358 opcode1_lsdr = 0232U,
1359 opcode1_spbp0 = 0250U,
1360 opcode1_spri1 = 0251U,
1361 opcode1_spbp2 = 0252U,
1362 opcode1_spri3 = 0253U,
1363 opcode1_ssdr = 0254U,
1364 opcode1_lptp = 0257U,
1365 opcode1_mvn = 0300U,
1366 opcode1_btd = 0301U,
1367 opcode1_cmpn = 0303U,
1368 opcode1_dtb = 0305U,
1369 opcode1_easp1 = 0310U,
1370 opcode1_eawp1 = 0311U,
1371 opcode1_easp3 = 0312U,
1372 opcode1_eawp3 = 0313U,
1373 opcode1_easp5 = 0330U,
1374 opcode1_eawp5 = 0331U,
1375 opcode1_easp7 = 0332U,
1376 opcode1_eawp7 = 0333U,
1377 opcode1_epbp0 = 0350U,
1378 opcode1_epp1 = 0351U,
1379 opcode1_epbp2 = 0352U,
1380 opcode1_epp3 = 0353U,
1381 opcode1_epbp4 = 0370U,
1382 opcode1_epp5 = 0371U,
1383 opcode1_epbp6 = 0372U,
1384 opcode1_epp7 = 0373U,
1385 opcode1_sareg = 0443U,
1386 opcode1_spl = 0447U,
1387 opcode1_lareg = 0463U,
1388 opcode1_lpl = 0467U,
1389 opcode1_a9bd = 0500U,
1390 opcode1_a6bd = 0501U,
1391 opcode1_a4bd = 0502U,
1392 opcode1_abd = 0503U,
1393 opcode1_awd = 0507U,
1394 opcode1_s9bd = 0520U,
1395 opcode1_s6bd = 0521U,
1396 opcode1_s4bd = 0522U,
1397 opcode1_sbd = 0523U,
1398 opcode1_swd = 0527U,
1399 opcode1_camp = 0532U,
1400 opcode1_ara0 = 0540U,
1401 opcode1_ara1 = 0541U,
1402 opcode1_ara2 = 0542U,
1403 opcode1_ara3 = 0543U,
1404 opcode1_ara4 = 0544U,
1405 opcode1_ara5 = 0545U,
1406 opcode1_ara6 = 0546U,
1407 opcode1_ara7 = 0547U,
1408 opcode1_sptp = 0557U,
1409 opcode1_aar0 = 0560U,
1410 opcode1_aar1 = 0561U,
1411 opcode1_aar2 = 0562U,
1412 opcode1_aar3 = 0563U,
1413 opcode1_aar4 = 0564U,
1414 opcode1_aar5 = 0565U,
1415 opcode1_aar6 = 0566U,
1416 opcode1_aar7 = 0567U,
1417 opcode1_trtn = 0600U,
1418 opcode1_trtf = 0601U,
1419 opcode1_tmoz = 0604U,
1420 opcode1_tpnz = 0605U,
1421 opcode1_ttn = 0606U,
1422 opcode1_arn0 = 0640U,
1423 opcode1_arn1 = 0641U,
1424 opcode1_arn2 = 0642U,
1425 opcode1_arn3 = 0643U,
1426 opcode1_arn4 = 0644U,
1427 opcode1_arn5 = 0645U,
1428 opcode1_arn6 = 0646U,
1429 opcode1_arn7 = 0647U,
1430 opcode1_spbp4 = 0650U,
1431 opcode1_spri5 = 0651U,
1432 opcode1_spbp6 = 0652U,
1433 opcode1_spri7 = 0653U,
1434 opcode1_nar0 = 0660U,
1435 opcode1_nar1 = 0661U,
1436 opcode1_nar2 = 0662U,
1437 opcode1_nar3 = 0663U,
1438 opcode1_nar4 = 0664U,
1439 opcode1_nar5 = 0665U,
1440 opcode1_nar6 = 0666U,
1441 opcode1_nar7 = 0667U,
1442 opcode1_sar0 = 0740U,
1443 opcode1_sar1 = 0741U,
1444 opcode1_sar2 = 0742U,
1445 opcode1_sar3 = 0743U,
1446 opcode1_sar4 = 0744U,
1447 opcode1_sar5 = 0745U,
1448 opcode1_sar6 = 0746U,
1449 opcode1_sar7 = 0747U,
1450 opcode1_sra = 0754U,
1451 opcode1_lar0 = 0760U,
1452 opcode1_lar1 = 0761U,
1453 opcode1_lar2 = 0762U,
1454 opcode1_lar3 = 0763U,
1455 opcode1_lar4 = 0764U,
1456 opcode1_lar5 = 0765U,
1457 opcode1_lar6 = 0766U,
1458 opcode1_lar7 = 0767U,
1459 opcode1_lra = 0774U
1460 } opcode1_t;
1461
1462
1463
1464
1465
1466
1467 enum { N_HIST_SETS = 4 };
1468 enum { N_DPS8M_HIST_SIZE = 64 };
1469 enum { N_L68_HIST_SIZE = 16 };
1470 enum { N_MAX_HIST_SIZE = 64 };
1471
1472 # define N_MODEL_HIST_SIZE (cpu.tweaks.l68_mode ? N_L68_HIST_SIZE : N_DPS8M_HIST_SIZE)
1473
1474
1475
1476
1477 enum
1478 {
1479 CU_HIST_PIA = 0400000000000,
1480 CU_HIST_POA = 0200000000000,
1481 CU_HIST_RIW = 0100000000000,
1482 CU_HIST_SIW = 0040000000000,
1483 CU_HIST_POT = 0020000000000,
1484 CU_HIST_PON = 0010000000000,
1485 CU_HIST_RAW = 0004000000000,
1486 CU_HIST_SAW = 0002000000000,
1487 CU_HIST_TRGO = 0001000000000,
1488 CU_HIST_XDE = 0000400000000,
1489 CU_HIST_XDO = 0000200000000,
1490 CU_HIST_IC = 0000100000000,
1491 CU_HIST_RPTS = 0000040000000,
1492 CU_HIST_PORTF = 0000020000000,
1493 CU_HIST_INTERNAL = 0000010000000,
1494 CU_HIST_PAI = 0000004000000,
1495 CU_HIST_PFA = 0000002000000,
1496 CU_HIST_PRIV = 0000001000000
1497 };
1498
1499
1500 enum
1501 {
1502 CU_HIST_XINT = 0100,
1503 CU_HIST_IFT = 0040,
1504 CU_HIST_CRD = 0020,
1505 CU_HIST_MRD = 0010,
1506 CU_HIST_MSTO = 0004,
1507 CU_HIST_PIB = 0002,
1508 };
1509
1510 enum
1511 {
1512 DU_FANLD1 = 0400000000000ull,
1513 DU_FANLD2 = 0200000000000ull,
1514 DU_FANSTR = 0100000000000ull,
1515 DU_FLDWRT1 = 0040000000000ull,
1516 DU_FLDWRT2 = 0020000000000ull,
1517 DU_FNLD1 = 0010000000000ull,
1518 DU_FNLD2 = 0004000000000ull,
1519 DU_NOSEQF = 0002000000000ull,
1520 DU_FDUD = 0001000000000ull,
1521 DU_FGSTR = 0000400000000ull,
1522 DU_NOSEQ = 0000200000000ull,
1523 DU_NINE = 0000100000000ull,
1524 DU_SIX = 0000040000000ull,
1525 DU_FOUR = 0000020000000ull,
1526 DU_DUBIT = 0000010000000ull,
1527 DU_UWORD = 0000004000000ull,
1528 DU_PTR1 = 0000002000000ull,
1529 DU_PTR2 = 0000001000000ull,
1530 DU_PRT3 = 0000000400000ull,
1531 DU_FPOP = 0000000200000ull,
1532 DU_GEAM = 0000000100000ull,
1533 DU_LPD12 = 0000000040000ull,
1534 DU_GEMAE = 0000000020000ull,
1535 DU_BTDS = 0000000010000ull,
1536 DU_SP15 = 0000000004000ull,
1537 DU_FSWEQ = 0000000002000ull,
1538 DU_FGCH = 0000000001000ull,
1539 DU_DFRST = 0000000000400ull,
1540 DU_EXH = 0000000000200ull,
1541 DU_FGADO = 0000000000100ull,
1542 DU_INTRPTD = 0000000000040ull,
1543 DU_GLDP2 = 0000000000020ull,
1544 DU_GEMC = 0000000000010ull,
1545 DU_GBDA = 0000000000004ull,
1546 DU_GSP5 = 0000000000002ull
1547 };
1548
1549
1550 enum
1551 {
1552 APU_PIA_OVF = 04000000,
1553 APU_PIA_OOB = 02000000,
1554 APU_FDSPTW = 01000000,
1555 APU_MDSPTW = 00400000,
1556 APU_FSDW = 00200000,
1557 APU_FPTW = 00100000,
1558 APU_FPTW2 = 00040000,
1559 APU_MPTW = 00020000,
1560 APU_FANP = 00010000,
1561 APU_FAP = 00004000,
1562 APU_MTCHSDW = 00002000,
1563 APU_SDWMF = 00001000,
1564
1565 APU_BSY_IC = 00000000,
1566 APU_BSY_TSE = 00000200,
1567 APU_BSY_SWR = 00000400,
1568 APU_BSY_CA = 00000600,
1569 APU_MTCHPTW = 00000100,
1570
1571
1572 };
1573
1574
1575 enum
1576 {
1577 APU_SDWME = 0400,
1578
1579 APU_CACHE = 0040,
1580 APU_PTW = 0020,
1581
1582 APU_FLTHLD = 0002,
1583
1584 };
1585
1586 enum { CU_HIST_REG = 0, DPS8M_DU_OU_HIST_REG = 1, DPS8M_APU_HIST_REG = 2, DPS8M_EAPU_HIST_REG = 3 };
1587 enum { L68_DU_HIST_REG = 1, L68_OU_HIST_REG = 2, L68_APU_HIST_REG = 3 };
1588
1589 #endif