PPR 26 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 151 src/dps8/doAppendCycleABSA.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 154 src/dps8/doAppendCycleABSA.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 280 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 24 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 165 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 168 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 186 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TSR == cpu.PPR.PSR) PPR 187 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 200 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 347 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 24 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 160 src/dps8/doAppendCycleAPUDataRead.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 163 src/dps8/doAppendCycleAPUDataRead.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 298 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 24 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 151 src/dps8/doAppendCycleAPUDataStore.h if (cpu.TPR.TSR == cpu.PPR.PSR) PPR 152 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 165 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 300 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 60 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 256 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 259 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 469 src/dps8/doAppendCycleIndirectWordFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 71 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 329 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR > cpu.PPR.PRR) PPR 330 src/dps8/doAppendCycleInstructionFetch.h sim_warn ("rtcd: outbound call cpu.TPR.TRR %d cpu.PPR.PRR %d\n", cpu.TPR.TRR, cpu.PPR.PRR); PPR 332 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.PPR.PRR) { PPR 352 src/dps8/doAppendCycleInstructionFetch.h if (! (cpu.PPR.PRR < cpu.rRALR)) { PPR 354 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(D) C(PPR.PRR) %o < RALR %o\n", cpu.PPR.PRR, cpu.rRALR); PPR 394 src/dps8/doAppendCycleInstructionFetch.h if (cpu.PPR.PRR != cpu.TPR.TRR) { PPR 633 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.PSR = cpu.TPR.TSR; PPR 635 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.IC = cpu.TPR.CA; PPR 646 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.P = p; PPR 649 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.P = 0; PPR 658 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 24 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 165 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 168 src/dps8/doAppendCycleOperandRMW.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 186 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TSR == cpu.PPR.PSR) PPR 187 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 200 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 351 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 66 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 118 src/dps8/doAppendCycleOperandRead.h if (cpu.rRALR && (cpu.PPR.PRR >= cpu.rRALR)) { PPR 328 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 331 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 362 src/dps8/doAppendCycleOperandRead.h if (! (cpu.PPR.PRR < cpu.rRALR)) { PPR 364 src/dps8/doAppendCycleOperandRead.h DBGAPP ("acvFaults(D) C(PPR.PRR) %o < RALR %o\n", cpu.PPR.PRR, cpu.rRALR); PPR 387 src/dps8/doAppendCycleOperandRead.h cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu.SDW->EB, PPR 388 src/dps8/doAppendCycleOperandRead.h cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.TPR.TRR, cpu.PPR.PRR); PPR 405 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS) PPR 444 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.PPR.PRR) { PPR 446 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PRR < cpu.SDW->R2) { PPR 501 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PRR != cpu.TPR.TRR) { PPR 737 src/dps8/doAppendCycleOperandRead.h cpu.PR[n].RNR = cpu.PPR.PRR; PPR 741 src/dps8/doAppendCycleOperandRead.h cpu.PR[n].SNR = cpu.PPR.PSR; PPR 742 src/dps8/doAppendCycleOperandRead.h cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; PPR 753 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PSR = cpu.TPR.TSR; PPR 755 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; PPR 765 src/dps8/doAppendCycleOperandRead.h cpu.PPR.P = p; PPR 768 src/dps8/doAppendCycleOperandRead.h cpu.PPR.P = 0; PPR 777 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR == cpu.PPR.PRR) { PPR 798 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PRR = cpu.TPR.TRR; PPR 800 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PSR = cpu.TPR.TSR; PPR 802 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; PPR 813 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 24 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 146 src/dps8/doAppendCycleOperandStore.h if (cpu.TPR.TSR == cpu.PPR.PSR) PPR 147 src/dps8/doAppendCycleOperandStore.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 160 src/dps8/doAppendCycleOperandStore.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 303 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 24 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 189 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 192 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 350 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1); PPR 364 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PSR = cpu.TPR.TSR; PPR 366 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.IC = cpu.TPR.CA; PPR 376 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.P = cpu.SDW->P; PPR 379 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.P = 0; PPR 390 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 84 src/dps8/dps8_addrmods.c return cpu.PPR.IC; PPR 1204 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.PPR.PSR); PPR 1441 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1444 src/dps8/dps8_append.c if (cpu.PPR.PSR != cpu.TPR.TSR) PPR 1474 src/dps8/dps8_append.c if (cpu.TPR.TSR == cpu.PPR.PSR) PPR 1475 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1491 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1541 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.PPR.PRR) PPR 1543 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.PPR.PRR); PPR 1545 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.PPR.PRR) PPR 1566 src/dps8/dps8_append.c if (! (cpu.PPR.PRR < cpu.rRALR)) PPR 1570 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.rRALR); PPR 1594 src/dps8/dps8_append.c cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, PPR 1596 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.PPR.PRR); PPR 1614 src/dps8/dps8_append.c if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS) PPR 1656 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.PPR.PRR) PPR 1659 src/dps8/dps8_append.c if (cpu.PPR.PRR < cpu.SDW->R2) PPR 1722 src/dps8/dps8_append.c if (cpu.PPR.PRR != cpu.TPR.TRR) PPR 2029 src/dps8/dps8_append.c cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1); PPR 2058 src/dps8/dps8_append.c cpu.PR[n].RNR = cpu.PPR.PRR; PPR 2062 src/dps8/dps8_append.c cpu.PR[n].SNR = cpu.PPR.PSR; PPR 2063 src/dps8/dps8_append.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; PPR 2110 src/dps8/dps8_append.c cpu.PPR.PSR = cpu.TPR.TSR; PPR 2112 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; PPR 2123 src/dps8/dps8_append.c cpu.PPR.P = cpu.SDW->P; PPR 2128 src/dps8/dps8_append.c cpu.PPR.P = 0; PPR 2137 src/dps8/dps8_append.c if (cpu.TPR.TRR == cpu.PPR.PRR) PPR 2162 src/dps8/dps8_append.c cpu.PPR.PRR = cpu.TPR.TRR; PPR 2164 src/dps8/dps8_append.c cpu.PPR.PSR = cpu.TPR.TSR; PPR 2166 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; PPR 2212 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 941 src/dps8/dps8_cpu.c cpu.PPR.IC = 0; PPR 942 src/dps8/dps8_cpu.c cpu.PPR.PRR = 0; PPR 943 src/dps8/dps8_cpu.c cpu.PPR.PSR = 0; PPR 944 src/dps8/dps8_cpu.c cpu.PPR.P = 1; PPR 984 src/dps8/dps8_cpu.c (void)memset (& cpu.PPR, 0, sizeof (struct ppr_s)); PPR 1637 src/dps8/dps8_cpu.c { ORDATA (IC, cpus[0].PPR.IC, VASIZE), 0, 0, 0 }, PPR 1771 src/dps8/dps8_cpu.c sim_brk_test ((cpu.PPR.IC & 0777777) | PPR 1772 src/dps8/dps8_cpu.c ((((t_addr) cpu.PPR.PSR) & 037777) << 18), PPR 2152 src/dps8/dps8_cpu.c cpus [0].PPR.IC = dummy_IC; PPR 2368 src/dps8/dps8_cpu.c cpu.PPR.PRR = 0; PPR 2470 src/dps8/dps8_cpu.c get_BAR_address (cpup, cpu.PPR.IC); PPR 2493 src/dps8/dps8_cpu.c (cpu.PPR.IC & 1) == 0 && PPR 2510 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 1) PPR 2644 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 2645 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 2659 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 2660 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 2663 src/dps8/dps8_cpu.c fetchInstruction (cpup, cpu.PPR.IC); PPR 2681 src/dps8/dps8_cpu.c if (stall_points[i].segno && stall_points[i].segno == cpu.PPR.PSR && PPR 2682 src/dps8/dps8_cpu.c stall_points[i].offset && stall_points[i].offset == cpu.PPR.IC) PPR 2727 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 2728 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 2958 src/dps8/dps8_cpu.c (cpu.cu.rd && (cpu.PPR.IC & 1)) || PPR 2963 src/dps8/dps8_cpu.c -- cpu.PPR.IC; PPR 2984 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; PPR 2985 src/dps8/dps8_cpu.c cpu.PPR.IC ++; PPR 3019 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 3020 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 3031 src/dps8/dps8_cpu.c cpu.PPR.IC ++; PPR 3033 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; PPR 3056 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 0 && PPR 3060 src/dps8/dps8_cpu.c (cpu.PPR.IC & ~3u) != (cpu.last_write & ~3u)) PPR 3062 src/dps8/dps8_cpu.c cpu.PPR.IC ++; PPR 3069 src/dps8/dps8_cpu.c cpu.PPR.IC ++; PPR 3071 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; PPR 3086 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; PPR 3087 src/dps8/dps8_cpu.c cpu.PPR.IC ++; PPR 3146 src/dps8/dps8_cpu.c cpu.PPR.PRR = 0; PPR 3300 src/dps8/dps8_cpu.c dummy_IC = cpu.PPR.IC; PPR 3516 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); PPR 3523 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, addr, PPR 3557 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PPR 3600 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PPR 3624 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PPR 3640 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PPR 3682 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PPR 3720 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); PPR 3727 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PPR 3738 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PPR 3757 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); PPR 3764 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PPR 3775 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PPR 3816 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PPR 3839 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PPR 3930 src/dps8/dps8_cpu.c else if (cpu.PPR.P) PPR 3995 src/dps8/dps8_cpu.c cpu.PPR.P = 1; PPR 4353 src/dps8/dps8_cpu.c putbits36_18 (& w1, 54 - 36, cpu.PPR.IC); PPR 1029 src/dps8/dps8_cpu.h #define USE_IRODD (cpu.cu.rd && ((cpu. PPR.IC & 1) != 0)) PPR 1656 src/dps8/dps8_cpu.h struct ppr_s PPR; // Procedure Pointer Register PPR 347 src/dps8/dps8_eis.c return cpu.PPR.IC; PPR 444 src/dps8/dps8_eis.c return cpu.PPR.IC; PPR 519 src/dps8/dps8_eis.c return cpu.PPR.IC; PPR 589 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 590 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 659 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 660 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 826 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 827 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 888 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 889 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1271 src/dps8/dps8_eis.c cpu.PPR.PRR); PPR 1419 src/dps8/dps8_eis.c e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); PPR 1624 src/dps8/dps8_eis.c e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); PPR 1676 src/dps8/dps8_eis.c e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); PPR 1863 src/dps8/dps8_eis.c e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); PPR 380 src/dps8/dps8_faults.c sim_printf (" TRO PSR:IC %05o:%06o\r\n", cpu.PPR.PSR, cpu.PPR.IC); PPR 385 src/dps8/dps8_faults.c sim_printf (" ACV %012llo PSR:IC %05o:%06o\r\n", subFault.bits, cpu.PPR.PSR, cpu.PPR.IC); PPR 416 src/dps8/dps8_faults.c fault_psr = cpu . PPR.PSR; PPR 417 src/dps8/dps8_faults.c fault_ic = cpu . PPR.IC; PPR 689 src/dps8/dps8_faults.c cpu.PPR.IC); PPR 835 src/dps8/dps8_faults.c cpu.PPR.IC); PPR 117 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 118 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 135 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) PPR 196 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 197 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 210 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PPR 266 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 267 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 281 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PPR 338 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 339 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 352 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PPR 408 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 409 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 422 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PPR 480 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 481 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 494 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PPR 550 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 551 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 564 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PPR 633 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 634 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 728 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 729 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 820 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 821 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 906 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 907 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 947 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 948 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1030 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1031 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1130 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1131 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1154 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) PPR 1254 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1255 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1279 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) PPR 1348 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1349 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1418 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1419 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1492 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1493 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1574 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1575 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1651 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1652 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1729 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1730 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1824 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1825 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1953 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1954 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 307 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.PPR.PRR; PPR 311 src/dps8/dps8_ins.c cpu.PR[n].SNR = cpu.PPR.PSR; PPR 312 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; PPR 318 src/dps8/dps8_ins.c cpu.PPR.IC = cpu.TPR.CA; PPR 323 src/dps8/dps8_ins.c __func__, cpu.PPR.PSR, cpu.PPR.IC); PPR 324 src/dps8/dps8_ins.c if (cpu.PPR.IC & 1) PPR 360 src/dps8/dps8_ins.c putbits36_3 (& words[0], 0, cpu.PPR.PRR); PPR 361 src/dps8/dps8_ins.c putbits36_15 (& words[0], 3, cpu.PPR.PSR); PPR 362 src/dps8/dps8_ins.c putbits36_1 (& words[0], 18, cpu.PPR.P); PPR 437 src/dps8/dps8_ins.c putbits36_18 (& words[4], 0, cpu.PPR.IC); PPR 604 src/dps8/dps8_ins.c cpu.cu_data.PSR = cpu.PPR.PSR; PPR 605 src/dps8/dps8_ins.c cpu.cu_data.PRR = cpu.PPR.PRR; PPR 606 src/dps8/dps8_ins.c cpu.cu_data.IC = cpu.PPR.IC; PPR 636 src/dps8/dps8_ins.c cpu.PPR.PRR = getbits36_3 (words[0], 0); PPR 637 src/dps8/dps8_ins.c cpu.PPR.PSR = getbits36_15 (words[0], 3); PPR 638 src/dps8/dps8_ins.c cpu.PPR.P = getbits36_1 (words[0], 18); PPR 716 src/dps8/dps8_ins.c cpu.PPR.IC = getbits36_18 (words[4], 0); PPR 1158 src/dps8/dps8_ins.c if (cpu.cu.rd && ((cpu.PPR.IC & 1) != 0)) PPR 1194 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) // Even PPR 1222 src/dps8/dps8_ins.c char * where = lookup_address (cpu.PPR.PSR, cpu.PPR.IC, & compname, PPR 1232 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); PPR 1236 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o %s\n", cpu.PPR.IC, where); PPR 1244 src/dps8/dps8_ins.c cpu.PPR.PSR, PPR 1245 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); PPR 1250 src/dps8/dps8_ins.c cpu.PPR.PSR, cpu.PPR.IC, where); PPR 1264 src/dps8/dps8_ins.c cpu.PPR.IC, PPR 1281 src/dps8/dps8_ins.c cpu.PPR.IC, PPR 1301 src/dps8/dps8_ins.c cpu.PPR.PSR, PPR 1303 src/dps8/dps8_ins.c cpu.PPR.IC, PPR 1304 src/dps8/dps8_ins.c cpu.PPR.PRR, PPR 1320 src/dps8/dps8_ins.c cpu.PPR.PSR, PPR 1321 src/dps8/dps8_ins.c cpu.PPR.IC, PPR 1322 src/dps8/dps8_ins.c cpu.PPR.PRR, PPR 1373 src/dps8/dps8_ins.c trk (cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IWB_IRODD); PPR 1536 src/dps8/dps8_ins.c if (!cpu.cu.xde && cpu.cu.xdo /* odd instr being executed */ && !(cpu.PPR.IC & 1)) PPR 1543 src/dps8/dps8_ins.c if (opcode == 0560 && !opcodeX && cpu.cu.xde && !(cpu.PPR.IC & 1)) PPR 1744 src/dps8/dps8_ins.c if (n_dbgevents && (dbgevt = (dbgevent_lookup (cpu.PPR.PSR, cpu.PPR.IC))) >= 0) { PPR 1837 src/dps8/dps8_ins.c cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], PPR 1849 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); PPR 1910 src/dps8/dps8_ins.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1911 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1920 src/dps8/dps8_ins.c word18 saveIC = cpu.PPR.IC; PPR 1922 src/dps8/dps8_ins.c ReadInstructionFetch (cpup, cpu.PPR.IC + 1 + n, & cpu.currentEISinstruction.op[n]); PPR 1923 src/dps8/dps8_ins.c cpu.PPR.IC = saveIC; PPR 1964 src/dps8/dps8_ins.c cpu.TPR.TRR = max (cpu.PAR[n].RNR, cpu.PPR.PRR); PPR 1966 src/dps8/dps8_ins.c cpu.TPR.TRR = max3 (cpu.PAR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); PPR 1987 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 2078 src/dps8/dps8_ins.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 2079 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 2090 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); PPR 2321 src/dps8/dps8_ins.c cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 2992 src/dps8/dps8_ins.c word18 ret = (cpu.PPR.IC + 1) & MASK18; PPR 3932 src/dps8/dps8_ins.c SETHI (cpu.CY, (cpu.PPR.IC + 1) & MASK18); PPR 3945 src/dps8/dps8_ins.c cpu.CY = ((word36) ((cpu.PPR.IC + 2) & MASK18)) << 18; PPR 4011 src/dps8/dps8_ins.c putbits36_15 (& cpu.Ypair[0], 3, cpu.PPR.PSR); PPR 4012 src/dps8/dps8_ins.c putbits36_3 (& cpu.Ypair[0], 18, cpu.PPR.PRR); PPR 4016 src/dps8/dps8_ins.c putbits36_18 (& cpu.Ypair[1], 0, cpu.PPR.IC + 2); PPR 6459 src/dps8/dps8_ins.c "call6 PRR %o PSR %o\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 6478 src/dps8/dps8_ins.c cpu.PPR.IC = GETHI (cpu.CY); PPR 7265 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) PPR 7568 src/dps8/dps8_ins.c sim_printf (" ldt %d PSR:IC %05o:%06o\r\n", cpu.rTR, cpu.PPR.PSR, cpu.PPR.IC); PPR 7619 src/dps8/dps8_ins.c sim_printf (" RALR set to %o PSR:IC %05o:%06o\r\n", cpu.rRALR, cpu.PPR.PSR, cpu.PPR.IC); PPR 8685 src/dps8/dps8_ins.c " no events in queue\n", cpu.PPR.IC); PPR 8702 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 0430 && cpu.PPR.IC == 012) PPR 8722 src/dps8/dps8_ins.c PPR 8732 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 034 && cpu.PPR.IC == 03535) PPR 9765 src/dps8/dps8_ins.c (cpu.Yblock8[0]>>18)&MASK15, (cpu.Yblock8[4]>>18)&MASK18, cpu.PPR.PSR, cpu.PPR.IC); PPR 9783 src/dps8/dps8_ins.c word1 saveP = cpu.PPR.P; // ISOLTS-870 02m PPR 9788 src/dps8/dps8_ins.c cpu.PPR.P = saveP; PPR 3513 src/dps8/dps8_iom.c __func__, iomChar (iom_unit_idx), cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC); PPR 23 src/dps8/dps8_mp.h struct ppr_s PPR; PPR 30 src/dps8/dps8_simh.h (! sim_deb_segno_on) || sim_deb_segno[cpu.PPR.PSR & (DEBUG_SEGNO_LIMIT - 1)]) && \ PPR 31 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || sim_deb_ringno == NO_SUCH_RINGNO || sim_deb_ringno == cpu . PPR. PRR) && \ PPR 2725 src/dps8/dps8_sys.c word15 icSegno = cpu.PPR.PSR; PPR 2726 src/dps8/dps8_sys.c word18 icOffset = cpu.PPR.IC; PPR 4053 src/dps8/dps8_sys.c { "cpus[].PPR", SYM_STRUCT_OFFSET, SYM_PTR, offsetof (cpu_state_t, PPR) }, PPR 169 src/dps8/hdbg.c if (filter && hdbgSegNum >= 0 && hdbgSegNum != cpu.PPR.PSR) \ PPR 171 src/dps8/hdbg.c if (filter && hdbgSegNum > 0 && blacklist[cpu.PPR.IC]) \ PPR 193 src/dps8/hdbg.c hevents[p].trace.segno = cpu.PPR.PSR; PPR 194 src/dps8/hdbg.c hevents[p].trace.ic = cpu.PPR.IC; PPR 195 src/dps8/hdbg.c hevents[p].trace.ring = cpu.PPR.PRR; PPR 383 src/dps8/panelScraper.c SETL (bank_a, 0+3, cpu.PPR.PRR, 3); PPR 384 src/dps8/panelScraper.c SETL (bank_a, 3+3, cpu.PPR.PSR, 15); PPR 385 src/dps8/panelScraper.c SETL1 (bank_a, 18+3, cpu.PPR.P); PPR 663 src/dps8/panelScraper.c SETL (bank_e, 0+3, cpu.PPR.IC, 18); PPR 923 src/dps8/panelScraper.c SETL (bank_g, 0, cpu.PPR.IC, 18); PPR 957 src/dps8/panelScraper.c SETL (bank_j, 3, cpu.PPR.IC, 18);