CA 24 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) CA %06o\n", cpu.TPR.CA); CA 69 src/dps8/doAppendCycleABSA.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 175 src/dps8/doAppendCycleABSA.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 183 src/dps8/doAppendCycleABSA.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 200 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(G) CA %06o\n", cpu.TPR.CA); CA 201 src/dps8/doAppendCycleABSA.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { //TPR.CA)) CA 202 src/dps8/doAppendCycleABSA.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 203 src/dps8/doAppendCycleABSA.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 213 src/dps8/doAppendCycleABSA.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 236 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 238 src/dps8/doAppendCycleABSA.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 242 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 252 src/dps8/doAppendCycleABSA.h word24 y2 = cpu.TPR.CA % 1024; CA 264 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 275 src/dps8/doAppendCycleABSA.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 281 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 22 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) CA %06o\n", cpu.TPR.CA); CA 73 src/dps8/doAppendCycleAPUDataRMW.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 222 src/dps8/doAppendCycleAPUDataRMW.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 229 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 246 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(G) CA %06o\n", cpu.TPR.CA); CA 247 src/dps8/doAppendCycleAPUDataRMW.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 248 src/dps8/doAppendCycleAPUDataRMW.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 253 src/dps8/doAppendCycleAPUDataRMW.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 263 src/dps8/doAppendCycleAPUDataRMW.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 288 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 290 src/dps8/doAppendCycleAPUDataRMW.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 294 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 304 src/dps8/doAppendCycleAPUDataRMW.h modify_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 310 src/dps8/doAppendCycleAPUDataRMW.h word24 y2 = cpu.TPR.CA % 1024; CA 322 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 342 src/dps8/doAppendCycleAPUDataRMW.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 348 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 22 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) CA %06o\n", cpu.TPR.CA); CA 74 src/dps8/doAppendCycleAPUDataRead.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 184 src/dps8/doAppendCycleAPUDataRead.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 191 src/dps8/doAppendCycleAPUDataRead.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 208 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(G) CA %06o\n", cpu.TPR.CA); CA 209 src/dps8/doAppendCycleAPUDataRead.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 210 src/dps8/doAppendCycleAPUDataRead.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 214 src/dps8/doAppendCycleAPUDataRead.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 224 src/dps8/doAppendCycleAPUDataRead.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 248 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 250 src/dps8/doAppendCycleAPUDataRead.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 254 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 268 src/dps8/doAppendCycleAPUDataRead.h word24 y2 = cpu.TPR.CA % 1024; CA 280 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 293 src/dps8/doAppendCycleAPUDataRead.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 299 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 22 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) CA %06o\n", cpu.TPR.CA); CA 72 src/dps8/doAppendCycleAPUDataStore.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 183 src/dps8/doAppendCycleAPUDataStore.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 190 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 207 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(G) CA %06o\n", cpu.TPR.CA); CA 208 src/dps8/doAppendCycleAPUDataStore.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 209 src/dps8/doAppendCycleAPUDataStore.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 214 src/dps8/doAppendCycleAPUDataStore.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 224 src/dps8/doAppendCycleAPUDataStore.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 248 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 250 src/dps8/doAppendCycleAPUDataStore.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 254 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 264 src/dps8/doAppendCycleAPUDataStore.h modify_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 270 src/dps8/doAppendCycleAPUDataStore.h word24 y2 = cpu.TPR.CA % 1024; CA 282 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 295 src/dps8/doAppendCycleAPUDataStore.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 301 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 58 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) CA %06o\n", cpu.TPR.CA); CA 94 src/dps8/doAppendCycleIndirectWordFetch.h if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) CA 98 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); CA 100 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = pageAddress + cpu.TPR.CA; CA 165 src/dps8/doAppendCycleIndirectWordFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 285 src/dps8/doAppendCycleIndirectWordFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 292 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 311 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(G) CA %06o\n", cpu.TPR.CA); CA 313 src/dps8/doAppendCycleIndirectWordFetch.h ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 314 src/dps8/doAppendCycleIndirectWordFetch.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 319 src/dps8/doAppendCycleIndirectWordFetch.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 329 src/dps8/doAppendCycleIndirectWordFetch.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 355 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 358 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 362 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 378 src/dps8/doAppendCycleIndirectWordFetch.h word24 y2 = cpu.TPR.CA % 1024; CA 391 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 398 src/dps8/doAppendCycleIndirectWordFetch.h ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); CA 418 src/dps8/doAppendCycleIndirectWordFetch.h if ((GET_TM (tag) == TM_IR || GET_TM (tag) == TM_RI) && (cpu.TPR.CA & 1) == 0) { CA 463 src/dps8/doAppendCycleIndirectWordFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 471 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 69 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) CA %06o\n", cpu.TPR.CA); CA 148 src/dps8/doAppendCycleInstructionFetch.h ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); CA 151 src/dps8/doAppendCycleInstructionFetch.h if (! ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) CA 156 src/dps8/doAppendCycleInstructionFetch.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); CA 158 src/dps8/doAppendCycleInstructionFetch.h finalAddress = pageAddress + cpu.TPR.CA; CA 216 src/dps8/doAppendCycleInstructionFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 416 src/dps8/doAppendCycleInstructionFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 423 src/dps8/doAppendCycleInstructionFetch.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 442 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(G) CA %06o\n", cpu.TPR.CA); CA 444 src/dps8/doAppendCycleInstructionFetch.h ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 445 src/dps8/doAppendCycleInstructionFetch.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 450 src/dps8/doAppendCycleInstructionFetch.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 462 src/dps8/doAppendCycleInstructionFetch.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 488 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 491 src/dps8/doAppendCycleInstructionFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 495 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 511 src/dps8/doAppendCycleInstructionFetch.h word24 y2 = cpu.TPR.CA % 1024; CA 524 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 552 src/dps8/doAppendCycleInstructionFetch.h sim_printf ("ins fetch err %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 557 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 562 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 577 src/dps8/doAppendCycleInstructionFetch.h ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); CA 635 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.IC = cpu.TPR.CA; CA 652 src/dps8/doAppendCycleInstructionFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 660 src/dps8/doAppendCycleInstructionFetch.h cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 22 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) CA %06o\n", cpu.TPR.CA); CA 74 src/dps8/doAppendCycleOperandRMW.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 222 src/dps8/doAppendCycleOperandRMW.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 229 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 246 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(G) CA %06o\n", cpu.TPR.CA); CA 247 src/dps8/doAppendCycleOperandRMW.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 248 src/dps8/doAppendCycleOperandRMW.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 253 src/dps8/doAppendCycleOperandRMW.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 263 src/dps8/doAppendCycleOperandRMW.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 286 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 288 src/dps8/doAppendCycleOperandRMW.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 292 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 302 src/dps8/doAppendCycleOperandRMW.h modify_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 308 src/dps8/doAppendCycleOperandRMW.h word24 y2 = cpu.TPR.CA % 1024; CA 320 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 346 src/dps8/doAppendCycleOperandRMW.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 352 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 64 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) CA %06o\n", cpu.TPR.CA); CA 135 src/dps8/doAppendCycleOperandRead.h ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); CA 138 src/dps8/doAppendCycleOperandRead.h cacheHit ? "hit" : "miss", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, cachedBound, CA 143 src/dps8/doAppendCycleOperandRead.h if (! ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) { CA 145 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 152 src/dps8/doAppendCycleOperandRead.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); CA 154 src/dps8/doAppendCycleOperandRead.h finalAddress = pageAddress + cpu.TPR.CA; CA 161 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 171 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "skip %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 229 src/dps8/doAppendCycleOperandRead.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 387 src/dps8/doAppendCycleOperandRead.h cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu.SDW->EB, CA 411 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.CA >= (word18) cpu.SDW->EB) { CA 523 src/dps8/doAppendCycleOperandRead.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 530 src/dps8/doAppendCycleOperandRead.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 550 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(G) CA %06o\n", cpu.TPR.CA); CA 552 src/dps8/doAppendCycleOperandRead.h ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 553 src/dps8/doAppendCycleOperandRead.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 559 src/dps8/doAppendCycleOperandRead.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 569 src/dps8/doAppendCycleOperandRead.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 597 src/dps8/doAppendCycleOperandRead.h cpu.SDW->ADDR, cpu.TPR.CA); CA 600 src/dps8/doAppendCycleOperandRead.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 605 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 624 src/dps8/doAppendCycleOperandRead.h word24 y2 = cpu.TPR.CA % 1024; CA 638 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 673 src/dps8/doAppendCycleOperandRead.h evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 679 src/dps8/doAppendCycleOperandRead.h evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 685 src/dps8/doAppendCycleOperandRead.h evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 690 src/dps8/doAppendCycleOperandRead.h ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); CA 694 src/dps8/doAppendCycleOperandRead.h evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); CA 755 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; CA 802 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; CA 808 src/dps8/doAppendCycleOperandRead.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 814 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 22 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) CA %06o\n", cpu.TPR.CA); CA 73 src/dps8/doAppendCycleOperandStore.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 182 src/dps8/doAppendCycleOperandStore.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 189 src/dps8/doAppendCycleOperandStore.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 206 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(G) CA %06o\n", cpu.TPR.CA); CA 207 src/dps8/doAppendCycleOperandStore.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 208 src/dps8/doAppendCycleOperandStore.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 213 src/dps8/doAppendCycleOperandStore.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 223 src/dps8/doAppendCycleOperandStore.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 246 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 248 src/dps8/doAppendCycleOperandStore.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 252 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 262 src/dps8/doAppendCycleOperandStore.h modify_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 268 src/dps8/doAppendCycleOperandStore.h word24 y2 = cpu.TPR.CA % 1024; CA 280 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 298 src/dps8/doAppendCycleOperandStore.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 304 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 22 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) CA %06o\n", cpu.TPR.CA); CA 104 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 217 src/dps8/doAppendCycleRTCDOperandFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 224 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 241 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(G) CA %06o\n", cpu.TPR.CA); CA 242 src/dps8/doAppendCycleRTCDOperandFetch.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 243 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 248 src/dps8/doAppendCycleRTCDOperandFetch.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 258 src/dps8/doAppendCycleRTCDOperandFetch.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 281 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); CA 284 src/dps8/doAppendCycleRTCDOperandFetch.h finalAddress = cpu.TPR.CA; CA 286 src/dps8/doAppendCycleRTCDOperandFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 291 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 305 src/dps8/doAppendCycleRTCDOperandFetch.h word24 y2 = cpu.TPR.CA % 1024; CA 317 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 354 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.CA = GET_ITS_WORDNO (data); CA 366 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.IC = cpu.TPR.CA; CA 384 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 392 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 224 src/dps8/dps8_addrmods.c cpu.TPR.CA = cpu.PAR[n].WORDNO + GET_ITP_WORDNO (cpu.itxPair); CA 225 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; CA 226 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; CA 266 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ITS_WORDNO (cpu.itxPair); CA 267 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; CA 269 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; CA 361 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ADDR (IWB_IRODD); CA 370 src/dps8/dps8_addrmods.c cpu.TPR.CA = (cpu.PAR[n].WORDNO + SIGNEXT15_18 (offset)) CA 376 src/dps8/dps8_addrmods.c __func__, op_desc_str (cpup, buf), cpu.TPR.CA); CA 419 src/dps8/dps8_addrmods.c cpu.cu.pot == 1 && GET_ADDR (IWB_IRODD) == cpu.TPR.CA) CA 421 src/dps8/dps8_addrmods.c cpu.TPR.CA--; CA 491 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO; CA 492 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; CA 496 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr; CA 501 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; CA 502 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits CA 505 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 527 src/dps8/dps8_addrmods.c "RI_MOD: Cr=%06o CA(Before)=%06o\n", Cr, cpu.TPR.CA); CA 538 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO; CA 542 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr; CA 544 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; CA 548 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; CA 549 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits CA 552 src/dps8/dps8_addrmods.c "RI_MOD: CA(After)=%06o\n", cpu.TPR.CA); CA 566 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 572 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); CA 600 src/dps8/dps8_addrmods.c cpu.TPR.CA = GETHI (cpu.itxPair[0]); CA 601 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; CA 613 src/dps8/dps8_addrmods.c cpu.itxPair[0], cpu.TPR.CA, cpu.rTAG); CA 640 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 642 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 662 src/dps8/dps8_addrmods.c cpu.TPR.CA = GETHI (cpu.itxPair[0]); CA 663 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; CA 675 src/dps8/dps8_addrmods.c cpu.itxPair[0], cpu.TPR.CA, Tm, Td, CA 688 src/dps8/dps8_addrmods.c updateIWB(cpup, cpu.TPR.CA, cpu.rTAG); CA 693 src/dps8/dps8_addrmods.c cpu.TPR.CA = saveCA; CA 698 src/dps8/dps8_addrmods.c cpu.TPR.CA = saveCA; CA 720 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); CA 734 src/dps8/dps8_addrmods.c Td, Cr, cpu.TPR.CA); CA 736 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; CA 737 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits CA 740 src/dps8/dps8_addrmods.c "IR_MOD(TM_RI): TPR.CA=%06o\n", cpu.TPR.CA); CA 744 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 747 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_RI|TD_N)); CA 753 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); // XXX guessing here... CA 832 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 839 src/dps8/dps8_addrmods.c word18 indaddr = cpu.TPR.CA; CA 873 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 921 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 944 src/dps8/dps8_addrmods.c Read (cpu.TPR.CA, & cpu.ou.character_data, (i->info->flags & RMW) == \ CA 947 src/dps8/dps8_addrmods.c ReadOperandRead (cpup, cpu.TPR.CA, & cpu.ou.character_data); CA 1019 src/dps8/dps8_addrmods.c indword, cpu.TPR.CA); CA 1024 src/dps8/dps8_addrmods.c cpu.TPR.CA = cpu.ou.character_address; CA 1032 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1041 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ADDR (cpu.itxPair[0]); CA 1042 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); CA 1060 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1066 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1068 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); CA 1082 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1083 src/dps8/dps8_addrmods.c word18 computedAddress = cpu.TPR.CA; CA 1112 src/dps8/dps8_addrmods.c cpu.TPR.CA = computedAddress; CA 1113 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); CA 1133 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1135 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); CA 1139 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1154 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1180 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1181 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); CA 1198 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1204 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1206 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); CA 1221 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1229 src/dps8/dps8_addrmods.c indword = (word36) (((word36) cpu.TPR.CA << 18) | CA 1247 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1248 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); CA 1263 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1267 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1274 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); CA 1285 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1286 src/dps8/dps8_addrmods.c word18 computedAddress = cpu.TPR.CA; CA 1319 src/dps8/dps8_addrmods.c cpu.TPR.CA = computedAddress; CA 1320 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); CA 1349 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1355 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1357 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); CA 1408 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1432 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); CA 1461 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1467 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1469 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); CA 1522 src/dps8/dps8_addrmods.c cpu.TPR.CA = YiSafe; CA 1543 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); CA 678 src/dps8/dps8_append.c static ptw_s * fetch_ptw_from_ptwam (cpu_state_t * cpup, word15 segno, word18 CA) CA 690 src/dps8/dps8_append.c if (cpu.PTWAM[_n].FE && ((CA >> 6) & 07760) == cpu.PTWAM[_n].PAGENO && CA 724 src/dps8/dps8_append.c uint setno = (CA >> 10) & 017; CA 731 src/dps8/dps8_append.c if (p->FE && ((CA >> 6) & 07760) == p->PAGENO && p->POINTER == segno) CA 1200 src/dps8/dps8_append.c cpu.TPR.CA); CA 1294 src/dps8/dps8_append.c PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 1594 src/dps8/dps8_append.c cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, CA 1620 src/dps8/dps8_append.c if (cpu.TPR.CA >= (word18) cpu.SDW->EB) CA 1745 src/dps8/dps8_append.c if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) CA 1754 src/dps8/dps8_append.c cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 1773 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(G) CA %06o\n", cpu.TPR.CA); CA 1775 src/dps8/dps8_append.c ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) //TPR.CA)) CA 1777 src/dps8/dps8_append.c fetch_ptw (cpu.SDW, cpu.TPR.CA); CA 1787 src/dps8/dps8_append.c loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 1798 src/dps8/dps8_append.c do_ptw2 (cpu.SDW, cpu.TPR.CA); CA 1824 src/dps8/dps8_append.c cpu.SDW->ADDR, cpu.TPR.CA); CA 1830 src/dps8/dps8_append.c finalAddress = cpu.TPR.CA; CA 1834 src/dps8/dps8_append.c finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 1840 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 1859 src/dps8/dps8_append.c modify_ptw (cpu.SDW, cpu.TPR.CA); CA 1866 src/dps8/dps8_append.c word24 y2 = cpu.TPR.CA % 1024; CA 1878 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 1956 src/dps8/dps8_append.c (cpu.TPR.CA & 1) == 0) CA 2033 src/dps8/dps8_append.c cpu.TPR.CA = GET_ITS_WORDNO (data); CA 2112 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; CA 2166 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; CA 2206 src/dps8/dps8_append.c PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 2214 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 4423 src/dps8/dps8_cpu.c putbits36_18 (& w1, 0, cpu.TPR.CA); CA 85 src/dps8/dps8_cpu.h word18 CA; // The current computed address relative to the origin of the CA 53 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 116 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 126 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read BAR"); CA 143 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read"); CA 156 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 195 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 204 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead BAR"); CA 216 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead"); CA 226 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 265 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 274 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead BAR"); CA 287 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead"); CA 298 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 337 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 346 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW BAR"); CA 358 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW"); CA 368 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 407 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 416 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW BAR"); CA 428 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW"); CA 440 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 479 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 488 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch BAR"); CA 500 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch"); CA 510 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 549 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 558 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch BAR"); CA 570 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch"); CA 582 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 632 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 644 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn"); CA 645 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd"); CA 666 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn"); CA 667 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd"); CA 678 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 727 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 739 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead BR evn"); CA 740 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead BR odd"); CA 759 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead evn"); CA 760 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead odd"); CA 770 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 819 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 831 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW BR evn"); CA 832 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW BR odd"); CA 845 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW evn"); CA 846 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW odd"); CA 856 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 905 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 917 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch BR evn"); CA 918 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch BR odd"); CA 931 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch evn"); CA 932 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch odd"); CA 941 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 946 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 958 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn"); CA 959 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd"); CA 972 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn"); CA 973 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd"); CA 980 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1029 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1041 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch BR evn"); CA 1042 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch BR odd"); CA 1055 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch evn"); CA 1056 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch odd"); CA 1067 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1129 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1145 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result[i], "Read8 BAR"); CA 1167 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "Read8"); CA 1191 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1253 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1269 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage B"); CA 1292 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage"); CA 1303 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1347 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1356 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write BR"); CA 1366 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write"); CA 1377 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1417 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1426 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore BR"); CA 1436 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore"); CA 1445 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1491 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1500 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore BR"); CA 1510 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore"); CA 1522 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1573 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 1583 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 BR evn"); CA 1584 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 BR odd"); CA 1597 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 evn"); CA 1598 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 odd"); CA 1609 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1650 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1659 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore BR evn"); CA 1660 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore BR odd"); CA 1670 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore evn"); CA 1671 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore odd"); CA 1682 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1728 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1739 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1 BR"); CA 1753 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1"); CA 1764 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1823 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1839 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8 BR"); CA 1859 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8"); CA 1893 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1952 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1969 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage BR"); CA 1988 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage"); CA 1999 src/dps8/dps8_iefp.c if (cpu.TPR.CA & 1) // is odd? CA 2001 src/dps8/dps8_iefp.c ReadIndirectWordFetch (cpup, cpu.TPR.CA, cpu.itxPair); CA 2006 src/dps8/dps8_iefp.c Read2IndirectWordFetch (cpup, cpu.TPR.CA, cpu.itxPair); CA 187 src/dps8/dps8_ins.c cpu.TPR.CA = cpu.ou.character_address; CA 191 src/dps8/dps8_ins.c write_operand (cpup, cpu.TPR.CA, OPERAND_STORE); CA 207 src/dps8/dps8_ins.c "%s a %d address %08o\n", __func__, i->b29, cpu.TPR.CA); CA 224 src/dps8/dps8_ins.c SETHI (cpu.CY, cpu.TPR.CA); CA 237 src/dps8/dps8_ins.c SETLO (cpu.CY, cpu.TPR.CA); CA 270 src/dps8/dps8_ins.c cpu.TPR.CA = cpu.ou.character_address; CA 276 src/dps8/dps8_ins.c readOperandRMW (cpup, cpu.TPR.CA); CA 278 src/dps8/dps8_ins.c readOperandRead (cpup, cpu.TPR.CA); CA 280 src/dps8/dps8_ins.c readOperandRead (cpup, cpu.TPR.CA); CA 288 src/dps8/dps8_ins.c if (cpu.TPR.CA & 1) CA 289 src/dps8/dps8_ins.c ReadOperandRead (cpup, cpu.TPR.CA, &cpu.CY); CA 291 src/dps8/dps8_ins.c Read2OperandRead (cpup, cpu.TPR.CA, cpu.Ypair); CA 318 src/dps8/dps8_ins.c cpu.PPR.IC = cpu.TPR.CA; CA 479 src/dps8/dps8_ins.c putbits36 (& words[5], 0, 18, cpu.TPR.CA); CA 1835 src/dps8/dps8_ins.c "RPT/RPD CA %06o\n", cpu.TPR.CA); CA 1867 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + offset) & AMASK; CA 1868 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; CA 1965 src/dps8/dps8_ins.c n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR); CA 2004 src/dps8/dps8_ins.c cpu.iefpFinalAddress = cpu.TPR.CA; CA 2051 src/dps8/dps8_ins.c cpu.last_write = cpu.TPR.CA; CA 2117 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; CA 2118 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; CA 2133 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; CA 2134 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; CA 2145 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; CA 2146 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; CA 2717 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = cpu.TPR.CA; CA 2961 src/dps8/dps8_ins.c cpu.rX[n] = cpu.TPR.CA; CA 2966 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); CA 2967 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); CA 3159 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 3186 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 3213 src/dps8/dps8_ins.c Read2RTCDOperandFetch (cpup, cpu.TPR.CA, cpu.Ypair); CA 3472 src/dps8/dps8_ins.c cpu.rQ |= (word36) (cpu.TPR.CA & MASK18) << 18; CA 3489 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 3515 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 3569 src/dps8/dps8_ins.c SETHI (cpu.rA, cpu.TPR.CA); CA 3573 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); CA 3574 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); CA 3580 src/dps8/dps8_ins.c SETHI (cpu.rQ, cpu.TPR.CA); CA 3585 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); CA 3586 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); CA 4079 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4089 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4119 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4141 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4159 src/dps8/dps8_ins.c word18 tmp18 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4189 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4204 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4239 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4284 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4322 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4353 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4387 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4424 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4462 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4472 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4501 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4525 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4543 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 6472 src/dps8/dps8_ins.c ReadOperandRead (cpup, cpu.TPR.CA, & cpu.CY); CA 6656 src/dps8/dps8_ins.c cpu.TPR.CA = get_BAR_address (cpup, cpu.TPR.CA); CA 6711 src/dps8/dps8_ins.c cpu.PR[0].SNR = cpu.TPR.CA & MASK15; CA 6720 src/dps8/dps8_ins.c cpu.PR[1].SNR = cpu.TPR.CA & MASK15; CA 6729 src/dps8/dps8_ins.c cpu.PR[2].SNR = cpu.TPR.CA & MASK15; CA 6738 src/dps8/dps8_ins.c cpu.PR[3].SNR = cpu.TPR.CA & MASK15; CA 6747 src/dps8/dps8_ins.c cpu.PR[4].SNR = cpu.TPR.CA & MASK15; CA 6756 src/dps8/dps8_ins.c cpu.PR[5].SNR = cpu.TPR.CA & MASK15; CA 6765 src/dps8/dps8_ins.c cpu.PR[6].SNR = cpu.TPR.CA & MASK15; CA 6774 src/dps8/dps8_ins.c cpu.PR[7].SNR = cpu.TPR.CA & MASK15; CA 6787 src/dps8/dps8_ins.c cpu.PR[0].WORDNO = cpu.TPR.CA; CA 6799 src/dps8/dps8_ins.c cpu.PR[1].WORDNO = cpu.TPR.CA; CA 6811 src/dps8/dps8_ins.c cpu.PR[2].WORDNO = cpu.TPR.CA; CA 6823 src/dps8/dps8_ins.c cpu.PR[3].WORDNO = cpu.TPR.CA; CA 6835 src/dps8/dps8_ins.c cpu.PR[4].WORDNO = cpu.TPR.CA; CA 6847 src/dps8/dps8_ins.c cpu.PR[5].WORDNO = cpu.TPR.CA; CA 6859 src/dps8/dps8_ins.c cpu.PR[6].WORDNO = cpu.TPR.CA; CA 6871 src/dps8/dps8_ins.c cpu.PR[7].WORDNO = cpu.TPR.CA; CA 7089 src/dps8/dps8_ins.c cpu_port_num = (cpu.TPR.CA >> 15) & 07; CA 7091 src/dps8/dps8_ins.c cpu_port_num = (cpu.TPR.CA >> 15) & 03; CA 7815 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) CA 7853 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) CA 7873 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) CA 7911 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 5) & 03;) CA 7979 src/dps8/dps8_ins.c DPS8M_ (if (cpu.TPR.CA != 0000002 && (cpu.TPR.CA & 3) != 0) CA 7980 src/dps8/dps8_ins.c sim_warn ("CAMP ignores enable/disable %06o\n", cpu.TPR.CA);) CA 7981 src/dps8/dps8_ins.c if ((cpu.TPR.CA & 3) == 02) CA 7983 src/dps8/dps8_ins.c else if ((cpu.TPR.CA & 3) == 01) CA 8024 src/dps8/dps8_ins.c DPS8M_ (if (cpu.TPR.CA != 0000006 && (cpu.TPR.CA & 3) != 0) CA 8025 src/dps8/dps8_ins.c sim_warn ("CAMS ignores enable/disable %06o\n", cpu.TPR.CA);) CA 8026 src/dps8/dps8_ins.c if ((cpu.TPR.CA & 3) == 02) CA 8028 src/dps8/dps8_ins.c else if ((cpu.TPR.CA & 3) == 01) CA 8048 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) CA 8049 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) CA 8107 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 10) & 03;) CA 8108 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 10) & 07;) CA 8157 src/dps8/dps8_ins.c cpu.rA = PROM[cpu.TPR.CA & 1023]; CA 8161 src/dps8/dps8_ins.c uint select = cpu.TPR.CA & 0x7; CA 8575 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) CA 8576 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) CA 8603 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) CA 8604 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) CA 8634 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 10) & 03;) CA 8635 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 10) & 07;) CA 9819 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, & cpu_dev, "absa CA:%08o\n", cpu.TPR.CA); CA 9825 src/dps8/dps8_ins.c * result = ((word36) (cpu.TPR.CA & MASK18)) << 12; // 24:12 format CA 31 src/dps8/dps8_mp.h word18 CA; CA 4094 src/dps8/dps8_sys.c { "cpus[].TPR.CA", SYM_STRUCT_OFFSET, SYM_UINT32_18, offsetof (struct tpr_s, CA) }, CA 462 src/dps8/panelScraper.c SETL (bank_a, 0+3, cpu.TPR.CA, 18); CA 991 src/dps8/panelScraper.c SETL (bank_l, 3, cpu.TPR.CA, 18);