CA 24 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) CA %06o\r\n", cpu.TPR.CA); CA 69 src/dps8/doAppendCycleABSA.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 175 src/dps8/doAppendCycleABSA.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 183 src/dps8/doAppendCycleABSA.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 200 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(G) CA %06o\r\n", cpu.TPR.CA); CA 201 src/dps8/doAppendCycleABSA.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { //TPR.CA)) CA 202 src/dps8/doAppendCycleABSA.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 203 src/dps8/doAppendCycleABSA.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 213 src/dps8/doAppendCycleABSA.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 236 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H): SDW->ADDR=%08o CA=%06o\r\n", cpu.SDW->ADDR, cpu.TPR.CA); CA 238 src/dps8/doAppendCycleABSA.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 242 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H:FANP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 252 src/dps8/doAppendCycleABSA.h word24 y2 = cpu.TPR.CA % 1024; CA 265 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H:FAP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 276 src/dps8/doAppendCycleABSA.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 282 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 22 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) CA %06o\r\n", cpu.TPR.CA); CA 71 src/dps8/doAppendCycleAPUDataRMW.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 220 src/dps8/doAppendCycleAPUDataRMW.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 227 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 244 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(G) CA %06o\r\n", cpu.TPR.CA); CA 245 src/dps8/doAppendCycleAPUDataRMW.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 246 src/dps8/doAppendCycleAPUDataRMW.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 251 src/dps8/doAppendCycleAPUDataRMW.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 261 src/dps8/doAppendCycleAPUDataRMW.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 286 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H): SDW->ADDR=%08o CA=%06o\r\n", cpu.SDW->ADDR, cpu.TPR.CA); CA 288 src/dps8/doAppendCycleAPUDataRMW.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 292 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H:FANP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 302 src/dps8/doAppendCycleAPUDataRMW.h modify_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 308 src/dps8/doAppendCycleAPUDataRMW.h word24 y2 = cpu.TPR.CA % 1024; CA 321 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H:FAP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 342 src/dps8/doAppendCycleAPUDataRMW.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 348 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 22 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) CA %06o\r\n", cpu.TPR.CA); CA 74 src/dps8/doAppendCycleAPUDataRead.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 184 src/dps8/doAppendCycleAPUDataRead.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 191 src/dps8/doAppendCycleAPUDataRead.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 208 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(G) CA %06o\r\n", cpu.TPR.CA); CA 209 src/dps8/doAppendCycleAPUDataRead.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 210 src/dps8/doAppendCycleAPUDataRead.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 214 src/dps8/doAppendCycleAPUDataRead.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 224 src/dps8/doAppendCycleAPUDataRead.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 248 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H): SDW->ADDR=%08o CA=%06o\r\n", cpu.SDW->ADDR, cpu.TPR.CA); CA 250 src/dps8/doAppendCycleAPUDataRead.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 254 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H:FANP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 268 src/dps8/doAppendCycleAPUDataRead.h word24 y2 = cpu.TPR.CA % 1024; CA 281 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H:FAP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 295 src/dps8/doAppendCycleAPUDataRead.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 301 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 22 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) CA %06o\r\n", cpu.TPR.CA); CA 72 src/dps8/doAppendCycleAPUDataStore.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 183 src/dps8/doAppendCycleAPUDataStore.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 190 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 207 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(G) CA %06o\r\n", cpu.TPR.CA); CA 208 src/dps8/doAppendCycleAPUDataStore.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 209 src/dps8/doAppendCycleAPUDataStore.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 214 src/dps8/doAppendCycleAPUDataStore.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 224 src/dps8/doAppendCycleAPUDataStore.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 248 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H): SDW->ADDR=%08o CA=%06o\r\n", cpu.SDW->ADDR, cpu.TPR.CA); CA 250 src/dps8/doAppendCycleAPUDataStore.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 254 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H:FANP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 264 src/dps8/doAppendCycleAPUDataStore.h modify_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 270 src/dps8/doAppendCycleAPUDataStore.h word24 y2 = cpu.TPR.CA % 1024; CA 283 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H:FAP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 298 src/dps8/doAppendCycleAPUDataStore.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 304 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 58 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) CA %06o\r\n", cpu.TPR.CA); CA 94 src/dps8/doAppendCycleIndirectWordFetch.h if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) CA 98 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); CA 100 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = pageAddress + cpu.TPR.CA; CA 167 src/dps8/doAppendCycleIndirectWordFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 287 src/dps8/doAppendCycleIndirectWordFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 294 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 313 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(G) CA %06o\r\n", cpu.TPR.CA); CA 315 src/dps8/doAppendCycleIndirectWordFetch.h ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 316 src/dps8/doAppendCycleIndirectWordFetch.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 321 src/dps8/doAppendCycleIndirectWordFetch.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 331 src/dps8/doAppendCycleIndirectWordFetch.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 357 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H): SDW->ADDR=%08o CA=%06o \r\n", cpu.SDW->ADDR, cpu.TPR.CA); CA 360 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 364 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H:FANP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 380 src/dps8/doAppendCycleIndirectWordFetch.h word24 y2 = cpu.TPR.CA % 1024; CA 394 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H:FAP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 401 src/dps8/doAppendCycleIndirectWordFetch.h ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); CA 422 src/dps8/doAppendCycleIndirectWordFetch.h if ((GET_TM (tag) == TM_IR || GET_TM (tag) == TM_RI) && (cpu.TPR.CA & 1) == 0) { CA 467 src/dps8/doAppendCycleIndirectWordFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 475 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 74 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) CA %06o\r\n", cpu.TPR.CA); CA 153 src/dps8/doAppendCycleInstructionFetch.h ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); CA 156 src/dps8/doAppendCycleInstructionFetch.h if (! ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) CA 161 src/dps8/doAppendCycleInstructionFetch.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); CA 163 src/dps8/doAppendCycleInstructionFetch.h finalAddress = pageAddress + cpu.TPR.CA; CA 224 src/dps8/doAppendCycleInstructionFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 424 src/dps8/doAppendCycleInstructionFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 431 src/dps8/doAppendCycleInstructionFetch.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 450 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(G) CA %06o\r\n", cpu.TPR.CA); CA 452 src/dps8/doAppendCycleInstructionFetch.h ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 453 src/dps8/doAppendCycleInstructionFetch.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 458 src/dps8/doAppendCycleInstructionFetch.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 470 src/dps8/doAppendCycleInstructionFetch.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 497 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H): SDW->ADDR=%08o CA=%06o\r\n", cpu.SDW->ADDR, cpu.TPR.CA); CA 500 src/dps8/doAppendCycleInstructionFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 504 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H:FANP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 521 src/dps8/doAppendCycleInstructionFetch.h word24 y2 = cpu.TPR.CA % 1024; CA 535 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H:FAP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 563 src/dps8/doAppendCycleInstructionFetch.h sim_printf ("ins fetch err %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 568 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 573 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 588 src/dps8/doAppendCycleInstructionFetch.h ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); CA 646 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.IC = cpu.TPR.CA; CA 663 src/dps8/doAppendCycleInstructionFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 671 src/dps8/doAppendCycleInstructionFetch.h cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 22 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) CA %06o\r\n", cpu.TPR.CA); CA 74 src/dps8/doAppendCycleOperandRMW.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 222 src/dps8/doAppendCycleOperandRMW.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 229 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 246 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(G) CA %06o\r\n", cpu.TPR.CA); CA 247 src/dps8/doAppendCycleOperandRMW.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 248 src/dps8/doAppendCycleOperandRMW.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 253 src/dps8/doAppendCycleOperandRMW.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 263 src/dps8/doAppendCycleOperandRMW.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 286 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H): SDW->ADDR=%08o CA=%06o\r\n", cpu.SDW->ADDR, cpu.TPR.CA); CA 288 src/dps8/doAppendCycleOperandRMW.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 292 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H:FANP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 302 src/dps8/doAppendCycleOperandRMW.h modify_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 308 src/dps8/doAppendCycleOperandRMW.h word24 y2 = cpu.TPR.CA % 1024; CA 321 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H:FAP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 349 src/dps8/doAppendCycleOperandRMW.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 355 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 64 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) CA %06o\r\n", cpu.TPR.CA); CA 135 src/dps8/doAppendCycleOperandRead.h ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); CA 138 src/dps8/doAppendCycleOperandRead.h cacheHit ? "hit" : "miss", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, cachedBound, CA 143 src/dps8/doAppendCycleOperandRead.h if (! ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) { CA 145 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 152 src/dps8/doAppendCycleOperandRead.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); CA 154 src/dps8/doAppendCycleOperandRead.h finalAddress = pageAddress + cpu.TPR.CA; CA 161 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 173 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "skip %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 231 src/dps8/doAppendCycleOperandRead.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 389 src/dps8/doAppendCycleOperandRead.h cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu.SDW->EB, CA 413 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.CA >= (word18) cpu.SDW->EB) { CA 525 src/dps8/doAppendCycleOperandRead.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 532 src/dps8/doAppendCycleOperandRead.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 552 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(G) CA %06o\r\n", cpu.TPR.CA); CA 554 src/dps8/doAppendCycleOperandRead.h ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 555 src/dps8/doAppendCycleOperandRead.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 561 src/dps8/doAppendCycleOperandRead.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 571 src/dps8/doAppendCycleOperandRead.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 599 src/dps8/doAppendCycleOperandRead.h cpu.SDW->ADDR, cpu.TPR.CA); CA 602 src/dps8/doAppendCycleOperandRead.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 607 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 626 src/dps8/doAppendCycleOperandRead.h word24 y2 = cpu.TPR.CA % 1024; CA 641 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 676 src/dps8/doAppendCycleOperandRead.h evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 682 src/dps8/doAppendCycleOperandRead.h evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 688 src/dps8/doAppendCycleOperandRead.h evcnt, cpu.TPR.TSR, cpu.TPR.CA); CA 693 src/dps8/doAppendCycleOperandRead.h ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); CA 697 src/dps8/doAppendCycleOperandRead.h evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); CA 760 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; CA 807 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; CA 813 src/dps8/doAppendCycleOperandRead.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 819 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 22 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) CA %06o\r\n", cpu.TPR.CA); CA 73 src/dps8/doAppendCycleOperandStore.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 182 src/dps8/doAppendCycleOperandStore.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 189 src/dps8/doAppendCycleOperandStore.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 206 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(G) CA %06o\r\n", cpu.TPR.CA); CA 207 src/dps8/doAppendCycleOperandStore.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 208 src/dps8/doAppendCycleOperandStore.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 213 src/dps8/doAppendCycleOperandStore.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 223 src/dps8/doAppendCycleOperandStore.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 246 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H): SDW->ADDR=%08o CA=%06o\r\n", cpu.SDW->ADDR, cpu.TPR.CA); CA 248 src/dps8/doAppendCycleOperandStore.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 252 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H:FANP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 262 src/dps8/doAppendCycleOperandStore.h modify_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 268 src/dps8/doAppendCycleOperandStore.h word24 y2 = cpu.TPR.CA % 1024; CA 281 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H:FAP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 303 src/dps8/doAppendCycleOperandStore.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 309 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 22 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) CA %06o\r\n", cpu.TPR.CA); CA 104 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 217 src/dps8/doAppendCycleRTCDOperandFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { CA 224 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 241 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(G) CA %06o\r\n", cpu.TPR.CA); CA 242 src/dps8/doAppendCycleRTCDOperandFetch.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { CA 243 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); CA 248 src/dps8/doAppendCycleRTCDOperandFetch.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 258 src/dps8/doAppendCycleRTCDOperandFetch.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); CA 281 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H): SDW->ADDR=%08o CA=%06o\r\n", cpu.SDW->ADDR, cpu.TPR.CA); CA 284 src/dps8/doAppendCycleRTCDOperandFetch.h finalAddress = cpu.TPR.CA; CA 286 src/dps8/doAppendCycleRTCDOperandFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 291 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H:FANP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 305 src/dps8/doAppendCycleRTCDOperandFetch.h word24 y2 = cpu.TPR.CA % 1024; CA 318 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H:FAP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 356 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.CA = GET_ITS_WORDNO (data); CA 368 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.IC = cpu.TPR.CA; CA 386 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 394 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 224 src/dps8/dps8_addrmods.c cpu.TPR.CA = cpu.PAR[n].WORDNO + GET_ITP_WORDNO (cpu.itxPair); CA 225 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; CA 226 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; CA 266 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ITS_WORDNO (cpu.itxPair); CA 267 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; CA 269 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; CA 362 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ADDR (IWB_IRODD); CA 371 src/dps8/dps8_addrmods.c cpu.TPR.CA = (cpu.PAR[n].WORDNO + SIGNEXT15_18 (offset)) CA 377 src/dps8/dps8_addrmods.c __func__, op_desc_str (cpup, buf), cpu.TPR.CA); CA 420 src/dps8/dps8_addrmods.c cpu.cu.pot == 1 && GET_ADDR (IWB_IRODD) == cpu.TPR.CA) CA 422 src/dps8/dps8_addrmods.c cpu.TPR.CA--; CA 492 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO; CA 493 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; CA 497 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr; CA 502 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; CA 503 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits CA 506 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 528 src/dps8/dps8_addrmods.c "RI_MOD: Cr=%06o CA(Before)=%06o\r\n", Cr, cpu.TPR.CA); CA 539 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO; CA 543 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr; CA 545 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; CA 549 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; CA 550 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits CA 553 src/dps8/dps8_addrmods.c "RI_MOD: CA(After)=%06o\r\n", cpu.TPR.CA); CA 567 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 573 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); CA 601 src/dps8/dps8_addrmods.c cpu.TPR.CA = GETHI (cpu.itxPair[0]); CA 602 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; CA 614 src/dps8/dps8_addrmods.c cpu.itxPair[0], cpu.TPR.CA, cpu.rTAG); CA 641 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 643 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 663 src/dps8/dps8_addrmods.c cpu.TPR.CA = GETHI (cpu.itxPair[0]); CA 664 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; CA 676 src/dps8/dps8_addrmods.c cpu.itxPair[0], cpu.TPR.CA, Tm, Td, CA 689 src/dps8/dps8_addrmods.c updateIWB(cpup, cpu.TPR.CA, cpu.rTAG); CA 694 src/dps8/dps8_addrmods.c cpu.TPR.CA = saveCA; CA 699 src/dps8/dps8_addrmods.c cpu.TPR.CA = saveCA; CA 721 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); CA 735 src/dps8/dps8_addrmods.c Td, Cr, cpu.TPR.CA); CA 737 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; CA 738 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits CA 741 src/dps8/dps8_addrmods.c "IR_MOD(TM_RI): TPR.CA=%06o\r\n", cpu.TPR.CA); CA 745 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 748 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_RI|TD_N)); CA 754 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); // XXX guessing here... CA 833 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 840 src/dps8/dps8_addrmods.c word18 indaddr = cpu.TPR.CA; CA 874 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 922 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 945 src/dps8/dps8_addrmods.c Read (cpu.TPR.CA, & cpu.ou.character_data, (i->info->flags & RMW) == \ CA 948 src/dps8/dps8_addrmods.c ReadOperandRead (cpup, cpu.TPR.CA, & cpu.ou.character_data); CA 1020 src/dps8/dps8_addrmods.c indword, cpu.TPR.CA); CA 1025 src/dps8/dps8_addrmods.c cpu.TPR.CA = cpu.ou.character_address; CA 1033 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1042 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ADDR (cpu.itxPair[0]); CA 1043 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); CA 1061 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1067 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1069 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); CA 1083 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1084 src/dps8/dps8_addrmods.c word18 computedAddress = cpu.TPR.CA; CA 1113 src/dps8/dps8_addrmods.c cpu.TPR.CA = computedAddress; CA 1114 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); CA 1134 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1136 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); CA 1140 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1155 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1181 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1182 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); CA 1199 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1205 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1207 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); CA 1222 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1230 src/dps8/dps8_addrmods.c indword = (word36) (((word36) cpu.TPR.CA << 18) | CA 1248 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1249 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); CA 1264 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1268 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1275 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); CA 1286 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1287 src/dps8/dps8_addrmods.c word18 computedAddress = cpu.TPR.CA; CA 1320 src/dps8/dps8_addrmods.c cpu.TPR.CA = computedAddress; CA 1321 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); CA 1350 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1356 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1358 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); CA 1409 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; CA 1433 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); CA 1462 src/dps8/dps8_addrmods.c cpu.TPR.CA); CA 1468 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; CA 1470 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); CA 1523 src/dps8/dps8_addrmods.c cpu.TPR.CA = YiSafe; CA 1544 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); CA 1563 src/dps8/dps8_addrmods.c cpu.TPR.CA == cpu.switches.addr_switches)) CA 693 src/dps8/dps8_append.c static ptw_s * fetch_ptw_from_ptwam (cpu_state_t * cpup, word15 segno, word18 CA) CA 705 src/dps8/dps8_append.c if (cpu.PTWAM[_n].FE && ((CA >> 6) & 07760) == cpu.PTWAM[_n].PAGENO && CA 739 src/dps8/dps8_append.c uint setno = (CA >> 10) & 017; CA 746 src/dps8/dps8_append.c if (p->FE && ((CA >> 6) & 07760) == p->PAGENO && p->POINTER == segno) CA 1214 src/dps8/dps8_append.c cpu.TPR.CA); CA 1308 src/dps8/dps8_append.c PNL (cpu.APUMemAddr = cpu.TPR.CA;) CA 1608 src/dps8/dps8_append.c cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, CA 1634 src/dps8/dps8_append.c if (cpu.TPR.CA >= (word18) cpu.SDW->EB) CA 1759 src/dps8/dps8_append.c if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) CA 1768 src/dps8/dps8_append.c cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); CA 1787 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(G) CA %06o\r\n", cpu.TPR.CA); CA 1789 src/dps8/dps8_append.c ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) //TPR.CA)) CA 1791 src/dps8/dps8_append.c fetch_ptw (cpu.SDW, cpu.TPR.CA); CA 1801 src/dps8/dps8_append.c loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM CA 1812 src/dps8/dps8_append.c do_ptw2 (cpu.SDW, cpu.TPR.CA); CA 1838 src/dps8/dps8_append.c cpu.SDW->ADDR, cpu.TPR.CA); CA 1844 src/dps8/dps8_append.c finalAddress = cpu.TPR.CA; CA 1848 src/dps8/dps8_append.c finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; CA 1854 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 1873 src/dps8/dps8_append.c modify_ptw (cpu.SDW, cpu.TPR.CA); CA 1880 src/dps8/dps8_append.c word24 y2 = cpu.TPR.CA % 1024; CA 1892 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.CA, finalAddress); CA 1972 src/dps8/dps8_append.c (cpu.TPR.CA & 1) == 0) CA 2049 src/dps8/dps8_append.c cpu.TPR.CA = GET_ITS_WORDNO (data); CA 2128 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; CA 2182 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; CA 2222 src/dps8/dps8_append.c PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) CA 2230 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); CA 5059 src/dps8/dps8_cpu.c putbits36_18 (& w1, 0, cpu.TPR.CA); CA 87 src/dps8/dps8_cpu.h word18 CA; // The current computed address relative to the origin of the CA 53 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 116 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 126 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read BAR"); CA 143 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read"); CA 156 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 195 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 204 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead BAR"); CA 216 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead"); CA 226 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 265 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 274 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead BAR"); CA 287 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead"); CA 298 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 337 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 346 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW BAR"); CA 358 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW"); CA 368 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 407 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 416 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW BAR"); CA 428 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW"); CA 440 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 479 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 488 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch BAR"); CA 500 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch"); CA 510 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 549 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 558 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch BAR"); CA 570 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch"); CA 582 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 632 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 644 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn"); CA 645 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd"); CA 666 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn"); CA 667 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd"); CA 678 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 727 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 739 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead BR evn"); CA 740 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead BR odd"); CA 759 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead evn"); CA 760 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead odd"); CA 770 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 819 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 831 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW BR evn"); CA 832 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW BR odd"); CA 845 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW evn"); CA 846 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW odd"); CA 856 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 905 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 917 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch BR evn"); CA 918 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch BR odd"); CA 931 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch evn"); CA 932 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch odd"); CA 941 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 946 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 958 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn"); CA 959 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd"); CA 972 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn"); CA 973 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd"); CA 980 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1029 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1041 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch BR evn"); CA 1042 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch BR odd"); CA 1055 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch evn"); CA 1056 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch odd"); CA 1067 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1129 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1145 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result[i], "Read8 BAR"); CA 1167 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "Read8"); CA 1191 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1253 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1269 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage B"); CA 1292 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage"); CA 1303 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1347 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1356 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write BR"); CA 1366 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write"); CA 1377 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1419 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1428 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore BR"); CA 1438 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore"); CA 1447 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1493 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1502 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore BR"); CA 1512 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore"); CA 1524 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1575 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); CA 1585 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 BR evn"); CA 1586 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 BR odd"); CA 1599 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 evn"); CA 1600 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 odd"); CA 1611 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1654 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1663 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore BR evn"); CA 1664 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore BR odd"); CA 1674 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore evn"); CA 1675 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore odd"); CA 1686 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1734 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1745 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1 BR"); CA 1759 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1"); CA 1770 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1831 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1847 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8 BR"); CA 1867 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8"); CA 1901 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; CA 1962 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); CA 1979 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage BR"); CA 1998 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage"); CA 2009 src/dps8/dps8_iefp.c if (cpu.TPR.CA & 1) // is odd? CA 2011 src/dps8/dps8_iefp.c ReadIndirectWordFetch (cpup, cpu.TPR.CA, cpu.itxPair); CA 2016 src/dps8/dps8_iefp.c Read2IndirectWordFetch (cpup, cpu.TPR.CA, cpu.itxPair); CA 188 src/dps8/dps8_ins.c cpu.TPR.CA = cpu.ou.character_address; CA 192 src/dps8/dps8_ins.c write_operand (cpup, cpu.TPR.CA, OPERAND_STORE); CA 208 src/dps8/dps8_ins.c "%s a %d address %08o\r\n", __func__, i->b29, cpu.TPR.CA); CA 225 src/dps8/dps8_ins.c SETHI (cpu.CY, cpu.TPR.CA); CA 238 src/dps8/dps8_ins.c SETLO (cpu.CY, cpu.TPR.CA); CA 271 src/dps8/dps8_ins.c cpu.TPR.CA = cpu.ou.character_address; CA 277 src/dps8/dps8_ins.c readOperandRMW (cpup, cpu.TPR.CA); CA 279 src/dps8/dps8_ins.c readOperandRead (cpup, cpu.TPR.CA); CA 281 src/dps8/dps8_ins.c readOperandRead (cpup, cpu.TPR.CA); CA 289 src/dps8/dps8_ins.c if (cpu.TPR.CA & 1) CA 290 src/dps8/dps8_ins.c ReadOperandRead (cpup, cpu.TPR.CA, &cpu.CY); CA 292 src/dps8/dps8_ins.c Read2OperandRead (cpup, cpu.TPR.CA, cpu.Ypair); CA 325 src/dps8/dps8_ins.c cpu.PPR.IC = cpu.TPR.CA; CA 492 src/dps8/dps8_ins.c putbits36 (& words[5], 0, 18, cpu.TPR.CA); CA 1879 src/dps8/dps8_ins.c "RPT/RPD CA %06o\r\n", cpu.TPR.CA); CA 1911 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + offset) & AMASK; CA 1918 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; CA 2020 src/dps8/dps8_ins.c n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR); CA 2059 src/dps8/dps8_ins.c cpu.iefpFinalAddress = cpu.TPR.CA; CA 2106 src/dps8/dps8_ins.c cpu.last_write = cpu.TPR.CA; CA 2180 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; CA 2181 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; CA 2197 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; CA 2198 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; CA 2210 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; CA 2211 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; CA 2791 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = cpu.TPR.CA; CA 3035 src/dps8/dps8_ins.c cpu.rX[n] = cpu.TPR.CA; CA 3040 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); CA 3041 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); CA 3233 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 3260 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 3287 src/dps8/dps8_ins.c Read2RTCDOperandFetch (cpup, cpu.TPR.CA, cpu.Ypair); CA 3546 src/dps8/dps8_ins.c cpu.rQ |= (word36) (cpu.TPR.CA & MASK18) << 18; CA 3563 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 3589 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 3643 src/dps8/dps8_ins.c SETHI (cpu.rA, cpu.TPR.CA); CA 3647 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); CA 3648 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); CA 3654 src/dps8/dps8_ins.c SETHI (cpu.rQ, cpu.TPR.CA); CA 3659 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); CA 3660 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); CA 4153 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4163 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4193 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4215 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4233 src/dps8/dps8_ins.c word18 tmp18 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4263 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4278 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4317 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4427 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4465 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4496 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4530 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4567 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4605 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4615 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4644 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 4668 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 CA 4686 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 CA 6615 src/dps8/dps8_ins.c ReadOperandRead (cpup, cpu.TPR.CA, & cpu.CY); CA 6799 src/dps8/dps8_ins.c cpu.TPR.CA = get_BAR_address (cpup, cpu.TPR.CA); CA 6854 src/dps8/dps8_ins.c cpu.PR[0].SNR = cpu.TPR.CA & MASK15; CA 6863 src/dps8/dps8_ins.c cpu.PR[1].SNR = cpu.TPR.CA & MASK15; CA 6872 src/dps8/dps8_ins.c cpu.PR[2].SNR = cpu.TPR.CA & MASK15; CA 6881 src/dps8/dps8_ins.c cpu.PR[3].SNR = cpu.TPR.CA & MASK15; CA 6890 src/dps8/dps8_ins.c cpu.PR[4].SNR = cpu.TPR.CA & MASK15; CA 6899 src/dps8/dps8_ins.c cpu.PR[5].SNR = cpu.TPR.CA & MASK15; CA 6908 src/dps8/dps8_ins.c cpu.PR[6].SNR = cpu.TPR.CA & MASK15; CA 6917 src/dps8/dps8_ins.c cpu.PR[7].SNR = cpu.TPR.CA & MASK15; CA 6930 src/dps8/dps8_ins.c cpu.PR[0].WORDNO = cpu.TPR.CA; CA 6942 src/dps8/dps8_ins.c cpu.PR[1].WORDNO = cpu.TPR.CA; CA 6954 src/dps8/dps8_ins.c cpu.PR[2].WORDNO = cpu.TPR.CA; CA 6966 src/dps8/dps8_ins.c cpu.PR[3].WORDNO = cpu.TPR.CA; CA 6978 src/dps8/dps8_ins.c cpu.PR[4].WORDNO = cpu.TPR.CA; CA 6990 src/dps8/dps8_ins.c cpu.PR[5].WORDNO = cpu.TPR.CA; CA 7002 src/dps8/dps8_ins.c cpu.PR[6].WORDNO = cpu.TPR.CA; CA 7014 src/dps8/dps8_ins.c cpu.PR[7].WORDNO = cpu.TPR.CA; CA 7232 src/dps8/dps8_ins.c cpu_port_num = (cpu.TPR.CA >> 15) & 07; CA 7234 src/dps8/dps8_ins.c cpu_port_num = (cpu.TPR.CA >> 15) & 03; CA 7987 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) CA 8026 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) CA 8046 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) CA 8085 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 5) & 03;) CA 8153 src/dps8/dps8_ins.c DPS8M_ (if (cpu.TPR.CA != 0000002 && (cpu.TPR.CA & 3) != 0) CA 8155 src/dps8/dps8_ins.c if (! warned) { warned = true; sim_warn ("CAMP ignores enable/disable %06o\r\n", cpu.TPR.CA); } }) CA 8156 src/dps8/dps8_ins.c if ((cpu.TPR.CA & 3) == 02) CA 8158 src/dps8/dps8_ins.c else if ((cpu.TPR.CA & 3) == 01) CA 8199 src/dps8/dps8_ins.c DPS8M_ (if (cpu.TPR.CA != 0000006 && (cpu.TPR.CA & 3) != 0) CA 8201 src/dps8/dps8_ins.c if (! warned) { warned = true; sim_warn ("CAMS ignores enable/disable %06o\r\n", cpu.TPR.CA); } }) CA 8202 src/dps8/dps8_ins.c if ((cpu.TPR.CA & 3) == 02) CA 8204 src/dps8/dps8_ins.c else if ((cpu.TPR.CA & 3) == 01) CA 8224 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) CA 8225 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) CA 8291 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> shift) & 03;) CA 8292 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> shift) & 07;) CA 8342 src/dps8/dps8_ins.c cpu.rA = PROM[cpu.TPR.CA & 1023]; CA 8346 src/dps8/dps8_ins.c uint select = cpu.TPR.CA & 0x7; CA 8764 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) CA 8765 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) CA 8795 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) CA 8796 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) CA 8837 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> shift) & 03;) CA 8838 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> shift) & 07;) CA 10067 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, & cpu_dev, "absa CA:%08o\r\n", cpu.TPR.CA); CA 10073 src/dps8/dps8_ins.c * result = ((word36) (cpu.TPR.CA & MASK18)) << 12; // 24:12 format CA 31 src/dps8/dps8_mp.h word18 CA; CA 4139 src/dps8/dps8_sys.c { "cpus[].TPR.CA", SYM_STRUCT_OFFSET, SYM_UINT32_18, offsetof (struct tpr_s, CA) }, CA 456 src/dps8/panelScraper.c SETL (bank_a, 0+3, cpu.TPR.CA, 18); CA 985 src/dps8/panelScraper.c SETL (bank_l, 3, cpu.TPR.CA, 18);