root/src/dps8/doAppendCycleRTCDOperandFetch.h

/* */

INCLUDED FROM

DEFINITIONS

1. doAppendCycleRTCDOperandFetch

   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 24c12472-171d-11ee-b2a6-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2022-2023 Charles Anthony
   9  * Copyright (c) 2022-2023 Jeffrey H. Johnson <trnsz@pobox.com>
  10  * Copyright (c) 2023-2023 The DPS8M Development Team
  11  *
  12  * All rights reserved.
  13  *
  14  * This software is made available under the terms of the ICU
  15  * License, version 1.8.1 or later.  For more details, see the
  16  * LICENSE.md file at the top-level directory of this distribution.
  17  *
  18  * ---------------------------------------------------------------------------
  19  */
  20 
  21 word24 doAppendCycleRTCDOperandFetch (word36 * data, uint nWords) {
     /*  */
  22   DCDstruct * i = & cpu.currentInstruction;
  23   DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) thisCycle=RTCD_OPERAND_FETCH\n");
  24   DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle));
  25   DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) CA %06o\n", cpu.TPR.CA);
  26   DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) n=%2u\n", nWords);
  27   DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR);
  28   DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
  29 
  30   if (i->b29) {
  31     DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) isb29 PRNO %o\n", GET_PRN (IWB_IRODD));
  32   }
  33 
  34   bool nomatch = true;
  35   if (cpu.tweaks.enable_wam) {
  36     // AL39: The associative memory is ignored (forced to "no match") during
  37     // address preparation.
  38     // lptp,lptr,lsdp,lsdr,sptp,sptr,ssdp,ssdr
  39     // Unfortunately, ISOLTS doesn't try to execute any of these in append mode.
  40     // XXX should this be only for OPERAND_READ and OPERAND_STORE?
  41     nomatch = ((i->opcode == 0232 || i->opcode == 0254 ||
  42                 i->opcode == 0154 || i->opcode == 0173) &&
  43                 i->opcodeX ) ||
  44                ((i->opcode == 0557 || i->opcode == 0257) &&
  45                 ! i->opcodeX);
  46   }
  47 
  48   processor_cycle_type lastCycle = cpu.apu.lastCycle;
  49   cpu.apu.lastCycle = RTCD_OPERAND_FETCH;
  50 
  51   DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) XSF %o\n", cpu.cu.XSF);
  52 
  53   PNL (L68_ (cpu.apu.state = 0;))
  54 
  55   cpu.RSDWH_R1 = 0;
  56 
  57   cpu.acvFaults = 0;
  58 
  59 //#define FMSG(x) x
  60 #define FMSG(x)
  61   FMSG (char * acvFaultsMsg = "<unknown>";)
  62 
  63   word24 finalAddress = (word24) -1;  // not everything requires a final
  64                                       // address
  65 
  66 ////////////////////////////////////////
  67 //
  68 // Sheet 1: "START APPEND"
  69 //
  70 ////////////////////////////////////////
  71 
  72 // START APPEND
  73 
  74   // If the rtcd instruction is executed with the processor in absolute
  75   // mode with bit 29 of the instruction word set OFF and without
  76   // indirection through an ITP or ITS pair, then:
  77   //
  78   //   appending mode is entered for address preparation for the
  79   //   rtcd operand and is retained if the instruction executes
  80   //   successfully, and the effective segment number generated for
  81   //   the SDW fetch and subsequent loading into C(TPR.TSR) is equal
  82   //   to C(PPR.PSR) and may be undefined in absolute mode, and the
  83   //   effective ring number loaded into C(TPR.TRR) prior to the SDW
  84   //   fetch is equal to C(PPR.PRR) (which is 0 in absolute mode)
  85   //   implying that control is always transferred into ring 0.
  86   //
  87   if (get_addr_mode() == ABSOLUTE_mode && ! (cpu.cu.XSF || cpu.currentInstruction.b29)) {
  88     cpu.TPR.TSR = 0;
  89     DBGAPP ("RTCD_OPERAND_FETCH ABSOLUTE mode set TSR %05o TRR %o\n", cpu.TPR.TSR, cpu.TPR.TRR);
  90   }
  91 
  92   goto A;
  93 
  94 ////////////////////////////////////////
  95 //
  96 // Sheet 2: "A"
  97 //
  98 ////////////////////////////////////////
  99 
 100 //
 101 //  A:
 102 //    Get SDW
 103 
 104 A:;
 105 
 106   //PNL (cpu.APUMemAddr = address;)
 107   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
 108 
 109   DBGAPP ("doAppendCycleRTCDOperandFetch(A)\n");
 110 
 111   // is SDW for C(TPR.TSR) in SDWAM?
 112   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
 113     // No
 114     DBGAPP ("doAppendCycleRTCDOperandFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
 115     DBGAPP ("doAppendCycleRTCDOperandFetch(A):DSBR.U=%o\n", cpu.DSBR.U);
 116 
 117     if (cpu.DSBR.U == 0) {
 118       fetch_dsptw (cpu.TPR.TSR);
 119 
 120       if (! cpu.PTW0.DF)
 121         doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleRTCDOperandFetch(A): PTW0.F == 0");
 122 
 123       if (! cpu.PTW0.U)
 124         modify_dsptw (cpu.TPR.TSR);
 125 
 126       fetch_psdw (cpu.TPR.TSR);
 127     } else
 128       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
 129 
 130     if (cpu.SDW0.DF == 0) {
 131       DBGAPP ("doAppendCycleRTCDOperandFetch(A): SDW0.F == 0! " "Initiating directed fault\n");
 132       // initiate a directed fault ...
 133       doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0");
 134     }
 135     // load SDWAM .....
 136     load_sdwam (cpu.TPR.TSR, nomatch);
 137   }
 138   DBGAPP ("doAppendCycleRTCDOperandFetch(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E);
 139 
 140   // Yes...
 141   cpu.RSDWH_R1 = cpu.SDW->R1;
 142 
 143 ////////////////////////////////////////
 144 //
 145 // Sheet 3: "B"
 146 //
 147 ////////////////////////////////////////
 148 
 149 //
 150 // B: Check the ring
 151 //
 152 
 153   DBGAPP ("doAppendCycleRTCDOperandFetch(B)\n");
 154 
 155   // check ring bracket consistency
 156 
 157   //C(SDW.R1) <= C(SDW.R2) <= C(SDW .R3)?
 158   if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) {
 159     // Set fault ACV0 = IRO
 160     cpu.acvFaults |= ACV0;
 161     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 162     FMSG (acvFaultsMsg = "acvFaults(B) C(SDW.R1) <= C(SDW.R2) <= C(SDW .R3)";)
 163   }
 164 
 165   if (lastCycle == RTCD_OPERAND_FETCH)
 166     sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\n", __func__, i->opcode);
 167 
 168   //
 169   // B1: The operand is one of: an instruction, data to be read or data to be
 170   //     written
 171   //
 172 
 173   //
 174   // check read bracket for read access
 175   //
 176 
 177   DBGAPP ("doAppendCycleRTCDOperandFetch(B):!STR-OP\n");
 178 
 179   // No
 180   // C(TPR.TRR) > C(SDW .R2)?
 181   if (cpu.TPR.TRR > cpu.SDW->R2) {
 182     DBGAPP ("ACV3\n");
 183     DBGAPP ("doAppendCycleRTCDOperandFetch(B) ACV3\n");
 184     //Set fault ACV3 = ORB
 185     cpu.acvFaults |= ACV3;
 186     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 187     FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R2)";)
 188   }
 189 
 190   if (cpu.SDW->R == 0) {
 191     // isolts 870
 192     cpu.TPR.TRR = cpu.PPR.PRR;
 193 
 194     //C(PPR.PSR) = C(TPR.TSR)?
 195     if (cpu.PPR.PSR != cpu.TPR.TSR) {
 196       DBGAPP ("ACV4\n");
 197       DBGAPP ("doAppendCycleRTCDOperandFetch(B) ACV4\n");
 198       //Set fault ACV4 = R-OFF
 199       cpu.acvFaults |= ACV4;
 200       PNL (L68_ (cpu.apu.state |= apu_FLT;))
 201       FMSG (acvFaultsMsg = "acvFaults(B) C(PPR.PSR) = C(TPR.TSR)";)
 202     //} else {
 203       // sim_warn ("doAppendCycleRTCDOperandFetch(B) SDW->R == 0 && cpu.PPR.PSR == cpu.TPR.TSR: %0#o\n", cpu.PPR.PSR);
 204     }
 205   }
 206 
 207   goto G;
 208 
 209 ////////////////////////////////////////
 210 //
 211 // Sheet 7: "G"
 212 //
 213 ////////////////////////////////////////
 214 
 215 G:;
 216 
 217   DBGAPP ("doAppendCycleRTCDOperandFetch(G)\n");
 218 
 219   //C(TPR.CA)0,13 > SDW.BOUND?
 220   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
 221     DBGAPP ("ACV15\n");
 222     DBGAPP ("doAppendCycleRTCDOperandFetch(G) ACV15\n");
 223     cpu.acvFaults |= ACV15;
 224     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 225     FMSG (acvFaultsMsg = "acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND";)
 226     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
 227     }
 228 
 229   if (cpu.acvFaults) {
 230     DBGAPP ("doAppendCycleRTCDOperandFetch(G) acvFaults\n");
 231     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 232     // Initiate an access violation fault
 233     doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault");
 234   }
 235 
 236   // is segment C(TPR.TSR) paged?
 237   if (cpu.SDW->U)
 238     goto H; // Not paged
 239 
 240   // Yes. segment is paged ...
 241   // is PTW for C(TPR.CA) in PTWAM?
 242 
 243   DBGAPP ("doAppendCycleRTCDOperandFetch(G) CA %06o\n", cpu.TPR.CA);
 244   if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) {
 245     fetch_ptw (cpu.SDW, cpu.TPR.CA);
 246     if (! cpu.PTW0.DF) {
 247       // initiate a directed fault
 248       doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0");
 249     }
 250     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
 251   }
 252 
 253   // Prepage mode?
 254   // check for "uninterruptible" EIS instruction
 255   // ISOLTS-878 02: mvn,cmpn,mvne,ad3d; obviously also
 256   // ad2/3d,sb2/3d,mp2/3d,dv2/3d
 257   // DH03 p.8-13: probably also mve,btd,dtb
 258   if (i->opcodeX && ((i->opcode & 0770)== 0200|| (i->opcode & 0770) == 0220
 259       || (i->opcode & 0770)== 020|| (i->opcode & 0770) == 0300)) {
 260     do_ptw2 (cpu.SDW, cpu.TPR.CA);
 261   }
 262   goto I;
 263 
 264 ////////////////////////////////////////
 265 //
 266 // Sheet 8: "H", "I"
 267 //
 268 ////////////////////////////////////////
 269 
 270 H:;
 271   DBGAPP ("doAppendCycleRTCDOperandFetch(H): FANP\n");
 272 
 273   PNL (L68_ (cpu.apu.state |= apu_FANP;))
 274 
 275 
 276 
 277 
 278 
 279 
 280 
 281   set_apu_status (apuStatus_FANP);
 282 
 283   DBGAPP ("doAppendCycleRTCDOperandFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
 284 
 285   if (get_addr_mode () == ABSOLUTE_mode && ! (cpu.cu.XSF || cpu.currentInstruction.b29)) {
 286     finalAddress = cpu.TPR.CA;
 287   } else {
 288     finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
 289     finalAddress &= 0xffffff;
 290   }
 291   PNL (cpu.APUMemAddr = finalAddress;)
 292 
 293   DBGAPP ("doAppendCycleRTCDOperandFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 294 
 295   goto HI;
 296 
 297 I:;
 298 
 299 // Set PTW.M
 300 
 301   DBGAPP ("doAppendCycleRTCDOperandFetch(I): FAP\n");
 302 
 303   // final address paged
 304   set_apu_status (apuStatus_FAP);
 305   PNL (L68_ (cpu.apu.state |= apu_FAP;))
 306 
 307   word24 y2 = cpu.TPR.CA % 1024;
 308 
 309   // AL39: The hardware ignores low order bits of the main memory page
 310   // address according to page size
 311   finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2;
 312   finalAddress &= 0xffffff;
 313   PNL (cpu.APUMemAddr = finalAddress;)
 314 
 315 #ifdef L68
 316   if (cpu.MR_cache.emr && cpu.MR_cache.ihr)
 317     add_APU_history (APUH_FAP);
 318 #endif
 319   DBGAPP ("doAppendCycleRTCDOperandFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 320 
 321   goto HI;
 322 
 323 HI:
 324   DBGAPP ("doAppendCycleRTCDOperandFetch(HI)\n");
 325 
 326   // isolts 870
 327   cpu.cu.XSF = 1;
 328   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
 329 
 330   core_readN (finalAddress, data, nWords, "RTCD_OPERAND_FETCH");
 331 
 332   goto K;
 333 
 334 ////////////////////////////////////////
 335 //
 336 // Sheet 10: "K", "L", "M", "N"
 337 //
 338 ////////////////////////////////////////
 339 
 340 K:; // RTCD operand fetch
 341   DBGAPP ("doAppendCycleRTCDOperandFetch(K)\n");
 342 
 343   word3 y = GET_ITS_RN (data);
 344 
 345   // C(Y-pair)3,17 -> C(PPR.PSR)
 346   // We set TSR here; TSR will be copied to PSR at KL
 347   cpu.TPR.TSR = GET_ITS_SEGNO (data);
 348 
 349   // Maximum of
 350   // C(Y-pair)18,20; C(TPR.TRR); C(SDW.R1) -> C(PPR.PRR)
 351   // We set TRR here as well
 352   cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1);
 353 
 354   // C(Y-pair)36,53 -> C(PPR.IC)
 355   // We set CA here; copied to IC  at KL
 356   cpu.TPR.CA = GET_ITS_WORDNO (data);
 357 
 358   // If C(PPR.PRR) = 0 then C(SDW.P) -> C(PPR.P);
 359   //     otherwise 0 -> C(PPR.P)
 360   // Done at M
 361 
 362 //KL:
 363   DBGAPP ("doAppendCycleRTCDOperandFetch(KL)\n");
 364 
 365   // C(TPR.TSR) -> C(PPR.PSR)
 366   cpu.PPR.PSR = cpu.TPR.TSR;
 367   // C(TPR.CA) -> C(PPR.IC)
 368   cpu.PPR.IC = cpu.TPR.CA;
 369 
 370   goto M;
 371 
 372 M: // Set P
 373   DBGAPP ("doAppendCycleRTCDOperandFetch(M)\n");
 374 
 375   // C(TPR.TRR) = 0?
 376   if (cpu.TPR.TRR == 0) {
 377     // C(SDW.P) -> C(PPR.P)
 378     cpu.PPR.P = cpu.SDW->P;
 379   } else {
 380     // 0 C(PPR.P)
 381     cpu.PPR.P = 0;
 382   }
 383 
 384 //Exit:;
 385 
 386   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
 387   PNL (cpu.APUDataBusAddr = finalAddress;)
 388 
 389   PNL (L68_ (cpu.apu.state |= apu_FA;))
 390 
 391   DBGAPP ("doAppendCycleRTCDOperandFetch (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
 392   DBGAPP ("doAppendCycleRTCDOperandFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
 393 
 394   return finalAddress;
 395 }

/* */