root/src/dps8/doAppendCycleOperandStore.h

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INCLUDED FROM

DEFINITIONS

This source file includes following definitions.
  1. doAppendCycleOperandStore
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 2b0da7ec-171d-11ee-a633-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2022-2023 Charles Anthony
   9  * Copyright (c) 2022-2023 Jeffrey H. Johnson <trnsz@pobox.com>
  10  * Copyright (c) 2023-2023 The DPS8M Development Team
  11  *
  12  * All rights reserved.
  13  *
  14  * This software is made available under the terms of the ICU
  15  * License, version 1.8.1 or later.  For more details, see the
  16  * LICENSE.md file at the top-level directory of this distribution.
  17  *
  18  * ---------------------------------------------------------------------------
  19  */
  20 
  21 word24 doAppendCycleOperandStore (word36 * data, uint nWords) {
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  22   DCDstruct * i = & cpu.currentInstruction;
  23   DBGAPP ("doAppendCycleOperandStore(Entry) thisCycle=OPERAND_STORE\n");
  24   DBGAPP ("doAppendCycleOperandStore(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle));
  25   DBGAPP ("doAppendCycleOperandStore(Entry) CA %06o\n", cpu.TPR.CA);
  26   DBGAPP ("doAppendCycleOperandStore(Entry) n=%2u\n", nWords);
  27   DBGAPP ("doAppendCycleOperandStore(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR);
  28   DBGAPP ("doAppendCycleOperandStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
  29 
  30   if (i->b29) {
  31     DBGAPP ("doAppendCycleOperandStore(Entry) isb29 PRNO %o\n", GET_PRN (IWB_IRODD));
  32   }
  33 
  34   bool nomatch = true;
  35   if (cpu.tweaks.enable_wam) {
  36     // AL39: The associative memory is ignored (forced to "no match") during
  37     // address preparation.
  38     // lptp,lptr,lsdp,lsdr,sptp,sptr,ssdp,ssdr
  39     // Unfortunately, ISOLTS doesn't try to execute any of these in append mode.
  40     // XXX should this be only for OPERAND_READ and OPERAND_STORE?
  41     nomatch = ((i->opcode == 0232 || i->opcode == 0254 ||
  42                 i->opcode == 0154 || i->opcode == 0173) &&
  43                 i->opcodeX ) ||
  44                ((i->opcode == 0557 || i->opcode == 0257) &&
  45                 ! i->opcodeX);
  46   }
  47 
  48   processor_cycle_type lastCycle = cpu.apu.lastCycle;
  49   cpu.apu.lastCycle = OPERAND_STORE;
  50 
  51   DBGAPP ("doAppendCycleOperandStore(Entry) XSF %o\n", cpu.cu.XSF);
  52 
  53   PNL (L68_ (cpu.apu.state = 0;))
  54 
  55   cpu.RSDWH_R1 = 0;
  56 
  57   cpu.acvFaults = 0;
  58 
  59 //#define FMSG(x) x
  60 #define FMSG(x)
  61   FMSG (char * acvFaultsMsg = "<unknown>";)
  62 
  63   word24 finalAddress = (word24) -1;  // not everything requires a final address
  64 
  65 ////////////////////////////////////////
  66 //
  67 // Sheet 2: "A"
  68 //
  69 ////////////////////////////////////////
  70 
  71 //
  72 //  A:
  73 //    Get SDW
  74 
  75   //PNL (cpu.APUMemAddr = address;)
  76   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
  77 
  78   DBGAPP ("doAppendCycleOperandStore(A)\n");
  79 
  80   // is SDW for C(TPR.TSR) in SDWAM?
  81   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
  82     // No
  83     DBGAPP ("doAppendCycleOperandStore(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
  84 
  85     DBGAPP ("doAppendCycleOperandStore(A):DSBR.U=%o\n", cpu.DSBR.U);
  86 
  87     if (cpu.DSBR.U == 0) {
  88       fetch_dsptw (cpu.TPR.TSR);
  89 
  90       if (! cpu.PTW0.DF)
  91         doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleOperandStore(A): PTW0.F == 0");
  92 
  93       if (! cpu.PTW0.U)
  94         modify_dsptw (cpu.TPR.TSR);
  95 
  96       fetch_psdw (cpu.TPR.TSR);
  97     } else
  98       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
  99 
 100     if (cpu.SDW0.DF == 0) {
 101       DBGAPP ("doAppendCycleOperandStore(A): SDW0.F == 0! " "Initiating directed fault\n");
 102       // initiate a directed fault ...
 103       doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0");
 104     }
 105     // load SDWAM .....
 106     load_sdwam (cpu.TPR.TSR, nomatch);
 107   }
 108   DBGAPP ("doAppendCycleOperandStore(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E);
 109 
 110   // Yes...
 111   cpu.RSDWH_R1 = cpu.SDW->R1;
 112 
 113 ////////////////////////////////////////
 114 //
 115 // Sheet 3: "B"
 116 //
 117 ////////////////////////////////////////
 118 
 119 //
 120 // B: Check the ring
 121 //
 122 
 123   DBGAPP ("doAppendCycleOperandStore(B)\n");
 124 
 125   // check ring bracket consistency
 126 
 127   //C(SDW.R1) <= C(SDW.R2) <= C(SDW .R3)?
 128   if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) {
 129     // Set fault ACV0 = IRO
 130     cpu.acvFaults |= ACV0;
 131     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 132     FMSG (acvFaultsMsg = "acvFaults(B) C(SDW.R1) <= C(SDW.R2) <= " "C(SDW .R3)";)
 133   }
 134 
 135   if (lastCycle == RTCD_OPERAND_FETCH)
 136     sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\n", __func__, i->opcode);
 137 
 138   //
 139   // B1: The operand is one of: an instruction, data to be read or data to be
 140   //     written
 141   //
 142 
 143   //
 144   // check write bracket for write access
 145   //
 146   DBGAPP ("doAppendCycleOperandStore(B):STR-OP\n");
 147 
 148   // isolts 870
 149   if (cpu.TPR.TSR == cpu.PPR.PSR)
 150     cpu.TPR.TRR = cpu.PPR.PRR;
 151 
 152   // C(TPR.TRR) > C(SDW .R1)? Note typo in AL39, R2 should be R1
 153   if (cpu.TPR.TRR > cpu.SDW->R1) {
 154     DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1);
 155     //Set fault ACV5 = OWB
 156     cpu.acvFaults |= ACV5;
 157     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 158     FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R1)";)
 159   }
 160 
 161   if (! cpu.SDW->W) {
 162     // isolts 870
 163     cpu.TPR.TRR = cpu.PPR.PRR;
 164 
 165     DBGAPP ("ACV6\n");
 166     // Set fault ACV6 = W-OFF
 167     cpu.acvFaults |= ACV6;
 168     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 169     FMSG (acvFaultsMsg = "acvFaults(B) ACV6 = W-OFF";)
 170   }
 171 
 172   goto G;
 173 
 174 ////////////////////////////////////////
 175 //
 176 // Sheet 7: "G"
 177 //
 178 ////////////////////////////////////////
 179 
 180 G:;
 181 
 182   DBGAPP ("doAppendCycleOperandStore(G)\n");
 183 
 184   //C(TPR.CA)0,13 > SDW.BOUND?
 185   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
 186     DBGAPP ("ACV15\n");
 187     DBGAPP ("doAppendCycleOperandStore(G) ACV15\n");
 188     cpu.acvFaults |= ACV15;
 189     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 190     FMSG (acvFaultsMsg = "acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND";)
 191     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
 192   }
 193 
 194   if (cpu.acvFaults) {
 195     DBGAPP ("doAppendCycleOperandStore(G) acvFaults\n");
 196     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 197     // Initiate an access violation fault
 198     doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault");
 199   }
 200 
 201   // is segment C(TPR.TSR) paged?
 202   if (cpu.SDW->U)
 203     goto H; // Not paged
 204 
 205   // Yes. segment is paged ...
 206   // is PTW for C(TPR.CA) in PTWAM?
 207 
 208   DBGAPP ("doAppendCycleOperandStore(G) CA %06o\n", cpu.TPR.CA);
 209   if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) {
 210     fetch_ptw (cpu.SDW, cpu.TPR.CA);
 211     if (! cpu.PTW0.DF) {
 212       // initiate a directed fault
 213       doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0");
 214     }
 215     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
 216   }
 217 
 218   // Prepage mode?
 219   // check for "uninterruptible" EIS instruction
 220   // ISOLTS-878 02: mvn,cmpn,mvne,ad3d; obviously also
 221   // ad2/3d,sb2/3d,mp2/3d,dv2/3d
 222   // DH03 p.8-13: probably also mve,btd,dtb
 223   if (i->opcodeX && ((i->opcode & 0770)== 0200|| (i->opcode & 0770) == 0220
 224       || (i->opcode & 0770)== 020|| (i->opcode & 0770) == 0300)) {
 225     do_ptw2 (cpu.SDW, cpu.TPR.CA);
 226   }
 227   goto I;
 228 
 229 ////////////////////////////////////////
 230 //
 231 // Sheet 8: "H", "I"
 232 //
 233 ////////////////////////////////////////
 234 
 235 H:;
 236   DBGAPP ("doAppendCycleOperandStore(H): FANP\n");
 237 
 238   PNL (L68_ (cpu.apu.state |= apu_FANP;))
 239 
 240 
 241 
 242 
 243 
 244 
 245 
 246   set_apu_status (apuStatus_FANP);
 247 
 248   DBGAPP ("doAppendCycleOperandStore(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
 249 
 250   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
 251   finalAddress &= 0xffffff;
 252   PNL (cpu.APUMemAddr = finalAddress;)
 253 
 254   DBGAPP ("doAppendCycleOperandStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 255 
 256   goto HI;
 257 
 258 I:;
 259 
 260 // Set PTW.M
 261 
 262   DBGAPP ("doAppendCycleOperandStore(I): FAP\n");
 263   if (cpu.PTW->M == 0)  // is this the right way to do this?
 264    modify_ptw (cpu.SDW, cpu.TPR.CA);
 265 
 266   // final address paged
 267   set_apu_status (apuStatus_FAP);
 268   PNL (L68_ (cpu.apu.state |= apu_FAP;))
 269 
 270   word24 y2 = cpu.TPR.CA % 1024;
 271 
 272   // AL39: The hardware ignores low order bits of the main memory page
 273   // address according to page size
 274   finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2;
 275   finalAddress &= 0xffffff;
 276   PNL (cpu.APUMemAddr = finalAddress;)
 277 
 278 #ifdef L68
 279   if (cpu.MR_cache.emr && cpu.MR_cache.ihr)
 280     add_APU_history (APUH_FAP);
 281 #endif
 282   DBGAPP ("doAppendCycleOperandStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 283 
 284   goto HI;
 285 
 286 HI:
 287   DBGAPP ("doAppendCycleOperandStore(HI)\n");
 288 
 289   // isolts 870
 290   cpu.cu.XSF = 1;
 291   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
 292 
 293   if (cpu.useZone)
 294     core_write_zone (finalAddress, * data, "OPERAND_STORE");
 295   else
 296     core_writeN (finalAddress, data, nWords, "OPERAND_STORE");
 297 
 298 //Exit:;
 299 
 300   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
 301   PNL (cpu.APUDataBusAddr = finalAddress;)
 302 
 303   PNL (L68_ (cpu.apu.state |= apu_FA;))
 304 
 305   DBGAPP ("doAppendCycleOperandStore (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
 306   DBGAPP ("doAppendCycleOperandStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
 307 
 308   return finalAddress;
 309 }
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