root/src/dps8/doAppendCycleOperandRMW.h

/* */

INCLUDED FROM

DEFINITIONS

1. doAppendCycleOperandRMW

   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 339b75b0-171d-11ee-bb9f-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2022-2023 Charles Anthony
   9  * Copyright (c) 2022-2023 Jeffrey H. Johnson <trnsz@pobox.com>
  10  * Copyright (c) 2023-2023 The DPS8M Development Team
  11  *
  12  * All rights reserved.
  13  *
  14  * This software is made available under the terms of the ICU
  15  * License, version 1.8.1 or later.  For more details, see the
  16  * LICENSE.md file at the top-level directory of this distribution.
  17  *
  18  * ---------------------------------------------------------------------------
  19  */
  20 
  21 word24 doAppendCycleOperandRMW (word36 * data, uint nWords) {
     /*  */
  22   DCDstruct * i = & cpu.currentInstruction;
  23   DBGAPP ("doAppendCycleOperandRMW(Entry) thisCycle=OPERAND_RMW\n");
  24   DBGAPP ("doAppendCycleOperandRMW(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle));
  25   DBGAPP ("doAppendCycleOperandRMW(Entry) CA %06o\n", cpu.TPR.CA);
  26   DBGAPP ("doAppendCycleOperandRMW(Entry) n=%2u\n", nWords);
  27   DBGAPP ("doAppendCycleOperandRMW(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR);
  28   DBGAPP ("doAppendCycleOperandRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
  29 
  30   if (i->b29) {
  31     DBGAPP ("doAppendCycleOperandRMW(Entry) isb29 PRNO %o\n", GET_PRN (IWB_IRODD));
  32   }
  33 
  34   bool nomatch = true;
  35   if (cpu.tweaks.enable_wam) {
  36     // AL39: The associative memory is ignored (forced to "no match") during
  37     // address preparation.
  38     // lptp,lptr,lsdp,lsdr,sptp,sptr,ssdp,ssdr
  39     // Unfortunately, ISOLTS doesn't try to execute any of these in append mode.
  40     // XXX should this be only for OPERAND_READ and OPERAND_STORE?
  41     nomatch = ((i->opcode == 0232 || i->opcode == 0254 ||
  42                 i->opcode == 0154 || i->opcode == 0173) &&
  43                 i->opcodeX ) ||
  44                ((i->opcode == 0557 || i->opcode == 0257) &&
  45                 ! i->opcodeX);
  46   }
  47 
  48   processor_cycle_type lastCycle = cpu.apu.lastCycle;
  49   cpu.apu.lastCycle = OPERAND_RMW;
  50 
  51   DBGAPP ("doAppendCycleOperandRMW(Entry) XSF %o\n", cpu.cu.XSF);
  52 
  53   PNL (L68_ (cpu.apu.state = 0;))
  54 
  55   cpu.RSDWH_R1 = 0;
  56 
  57   cpu.acvFaults = 0;
  58 
  59 //#define FMSG(x) x
  60 #define FMSG(x)
  61   FMSG (char * acvFaultsMsg = "<unknown>";)
  62 
  63   word24 finalAddress = (word24) -1;  // not everything requires a final
  64                                       // address
  65 
  66 ////////////////////////////////////////
  67 //
  68 // Sheet 2: "A"
  69 //
  70 ////////////////////////////////////////
  71 
  72 //
  73 //  A:
  74 //    Get SDW
  75 
  76   //PNL (cpu.APUMemAddr = address;)
  77   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
  78 
  79   DBGAPP ("doAppendCycleOperandRMW(A)\n");
  80 
  81   // is SDW for C(TPR.TSR) in SDWAM?
  82   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
  83     // No
  84     DBGAPP ("doAppendCycleOperandRMW(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
  85     DBGAPP ("doAppendCycleOperandRMW(A):DSBR.U=%o\n", cpu.DSBR.U);
  86 
  87     if (cpu.DSBR.U == 0) {
  88       fetch_dsptw (cpu.TPR.TSR);
  89 
  90       if (! cpu.PTW0.DF)
  91         doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleOperandRMW(A): PTW0.F == 0");
  92 
  93       if (! cpu.PTW0.U)
  94         modify_dsptw (cpu.TPR.TSR);
  95 
  96       fetch_psdw (cpu.TPR.TSR);
  97     } else
  98       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
  99 
 100     if (cpu.SDW0.DF == 0) {
 101       DBGAPP ("doAppendCycleOperandRMW(A): SDW0.F == 0! Initiating directed fault\n");
 102       // initiate a directed fault ...
 103       doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0");
 104     }
 105     // load SDWAM .....
 106     load_sdwam (cpu.TPR.TSR, nomatch);
 107   }
 108   DBGAPP ("doAppendCycleOperandRMW(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E);
 109 
 110   // Yes...
 111   cpu.RSDWH_R1 = cpu.SDW->R1;
 112 
 113 ////////////////////////////////////////
 114 //
 115 // Sheet 3: "B"
 116 //
 117 ////////////////////////////////////////
 118 
 119 //
 120 // B: Check the ring
 121 //
 122 
 123   DBGAPP ("doAppendCycleOperandRMW(B)\n");
 124 
 125   // check ring bracket consistency
 126 
 127   //C(SDW.R1) <= C(SDW.R2) <= C(SDW .R3)?
 128   if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) {
 129     // Set fault ACV0 = IRO
 130     cpu.acvFaults |= ACV0;
 131     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 132     FMSG (acvFaultsMsg = "acvFaults(B) C(SDW.R1) <= C(SDW.R2) <= " "C(SDW .R3)";)
 133   }
 134 
 135   // lastCycle == RTCD_OPERAND_FETCH
 136   // if a fault happens between the RTCD_OPERAND_FETCH and the INSTRUCTION_FETCH
 137   // of the next instruction - this happens about 35 time for just booting  and
 138   // shutting down multics -- a stored lastCycle is useless.
 139   // the opcode is preserved across faults and only replaced as the
 140   // INSTRUCTION_FETCH succeeds.
 141   if (lastCycle == RTCD_OPERAND_FETCH)
 142     sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\n", __func__, i->opcode);
 143 
 144   //
 145   // B1: The operand is one of: an instruction, data to be read or data to be
 146   //     written
 147   //
 148 
 149   //
 150   // check read bracket for read access
 151   //
 152 
 153   DBGAPP ("doAppendCycleOperandRMW(B):!STR-OP\n");
 154 
 155   // No
 156   // C(TPR.TRR) > C(SDW .R2)?
 157   if (cpu.TPR.TRR > cpu.SDW->R2) {
 158     DBGAPP ("ACV3\n");
 159     DBGAPP ("doAppendCycleOperandRMW(B) ACV3\n");
 160     //Set fault ACV3 = ORB
 161     cpu.acvFaults |= ACV3;
 162     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 163     FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R2)";)
 164   }
 165 
 166   if (cpu.SDW->R == 0) {
 167     // isolts 870
 168     cpu.TPR.TRR = cpu.PPR.PRR;
 169 
 170     //C(PPR.PSR) = C(TPR.TSR)?
 171     if (cpu.PPR.PSR != cpu.TPR.TSR) {
 172       DBGAPP ("ACV4\n");
 173       DBGAPP ("doAppendCycleOperandRMW(B) ACV4\n");
 174       //Set fault ACV4 = R-OFF
 175       cpu.acvFaults |= ACV4;
 176       PNL (L68_ (cpu.apu.state |= apu_FLT;))
 177       FMSG (acvFaultsMsg = "acvFaults(B) C(PPR.PSR) = C(TPR.TSR)";)
 178     //} else {
 179       // sim_warn ("doAppendCycleOperandRMW(B) SDW->R == 0 && cpu.PPR.PSR == cpu.TPR.TSR: %0#o\n", cpu.PPR.PSR);
 180     }
 181   }
 182 
 183   //
 184   // check write bracket for write access
 185   //
 186   DBGAPP ("doAppendCycleOperandRMW(B):STR-OP\n");
 187 
 188   // isolts 870
 189   if (cpu.TPR.TSR == cpu.PPR.PSR)
 190     cpu.TPR.TRR = cpu.PPR.PRR;
 191 
 192   // C(TPR.TRR) > C(SDW .R1)? Note typo in AL39, R2 should be R1
 193   if (cpu.TPR.TRR > cpu.SDW->R1) {
 194     DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1);
 195     //Set fault ACV5 = OWB
 196     cpu.acvFaults |= ACV5;
 197     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 198     FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R1)";)
 199   }
 200 
 201   if (! cpu.SDW->W) {
 202     // isolts 870
 203     cpu.TPR.TRR = cpu.PPR.PRR;
 204 
 205     DBGAPP ("ACV6\n");
 206     // Set fault ACV6 = W-OFF
 207     cpu.acvFaults |= ACV6;
 208     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 209     FMSG (acvFaultsMsg = "acvFaults(B) ACV6 = W-OFF";)
 210   }
 211 
 212   goto G;
 213 
 214 ////////////////////////////////////////
 215 //
 216 // Sheet 7: "G"
 217 //
 218 ////////////////////////////////////////
 219 
 220 G:;
 221 
 222   DBGAPP ("doAppendCycleOperandRMW(G)\n");
 223 
 224   //C(TPR.CA)0,13 > SDW.BOUND?
 225   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
 226     DBGAPP ("ACV15\n");
 227     DBGAPP ("doAppendCycleOperandRMW(G) ACV15\n");
 228     cpu.acvFaults |= ACV15;
 229     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 230     FMSG (acvFaultsMsg = "acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND";)
 231     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
 232   }
 233 
 234   if (cpu.acvFaults) {
 235     DBGAPP ("doAppendCycleOperandRMW(G) acvFaults\n");
 236     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 237     // Initiate an access violation fault
 238     doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault");
 239   }
 240 
 241   // is segment C(TPR.TSR) paged?
 242   if (cpu.SDW->U)
 243     goto H; // Not paged
 244 
 245   // Yes. segment is paged ...
 246   // is PTW for C(TPR.CA) in PTWAM?
 247 
 248   DBGAPP ("doAppendCycleOperandRMW(G) CA %06o\n", cpu.TPR.CA);
 249   if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA))  {
 250     fetch_ptw (cpu.SDW, cpu.TPR.CA);
 251     if (! cpu.PTW0.DF) {
 252       // initiate a directed fault
 253       doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0");
 254     }
 255     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
 256   }
 257 
 258   // Prepage mode?
 259   // check for "uninterruptible" EIS instruction
 260   // ISOLTS-878 02: mvn,cmpn,mvne,ad3d; obviously also
 261   // ad2/3d,sb2/3d,mp2/3d,dv2/3d
 262   // DH03 p.8-13: probably also mve,btd,dtb
 263   if (i->opcodeX && ((i->opcode & 0770)== 0200|| (i->opcode & 0770) == 0220
 264       || (i->opcode & 0770)== 020|| (i->opcode & 0770) == 0300)) {
 265     do_ptw2 (cpu.SDW, cpu.TPR.CA);
 266   }
 267   goto I;
 268 
 269 ////////////////////////////////////////
 270 //
 271 // Sheet 8: "H", "I"
 272 //
 273 ////////////////////////////////////////
 274 
 275 H:;
 276   DBGAPP ("doAppendCycleOperandRMW(H): FANP\n");
 277 
 278   PNL (L68_ (cpu.apu.state |= apu_FANP;))
 279 
 280 
 281 
 282 
 283 
 284 
 285 
 286   set_apu_status (apuStatus_FANP);
 287 
 288   DBGAPP ("doAppendCycleOperandRMW(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
 289 
 290   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
 291   finalAddress &= 0xffffff;
 292   PNL (cpu.APUMemAddr = finalAddress;)
 293 
 294   DBGAPP ("doAppendCycleOperandRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 295 
 296   goto HI;
 297 
 298 I:;
 299 
 300 // Set PTW.M
 301 
 302   DBGAPP ("doAppendCycleOperandRMW(I): FAP\n");
 303   if (cpu.PTW->M == 0)  // is this the right way to do this?
 304     modify_ptw (cpu.SDW, cpu.TPR.CA);
 305 
 306   // final address paged
 307   set_apu_status (apuStatus_FAP);
 308   PNL (L68_ (cpu.apu.state |= apu_FAP;))
 309 
 310   word24 y2 = cpu.TPR.CA % 1024;
 311 
 312   // AL39: The hardware ignores low order bits of the main memory page
 313   // address according to page size
 314   finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2;
 315   finalAddress &= 0xffffff;
 316   PNL (cpu.APUMemAddr = finalAddress;)
 317 
 318 #ifdef L68
 319   if (cpu.MR_cache.emr && cpu.MR_cache.ihr)
 320     add_APU_history (APUH_FAP);
 321 #endif
 322   DBGAPP ("doAppendCycleOperandRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 323 
 324   goto HI;
 325 
 326 HI:
 327   DBGAPP ("doAppendCycleOperandRMW(HI)\n");
 328 
 329   // isolts 870
 330   cpu.cu.XSF = 1;
 331   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
 332 
 333   if (nWords == 1) {
 334     core_read_lock (finalAddress, data, "OPERAND_RMW");
 335   } else {
 336     sim_warn("doAppendCycleOperandRMW: RMW nWords %d !=1\n", nWords);
 337     core_readN (finalAddress, data, nWords, "OPERAND_RMW");
 338   }
 339 
 340 ////////////////////////////////////////
 341 //
 342 // Sheet 11: "O", "P"
 343 //
 344 ////////////////////////////////////////
 345 
 346 //Exit:;
 347 
 348   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
 349   PNL (cpu.APUDataBusAddr = finalAddress;)
 350 
 351   PNL (L68_ (cpu.apu.state |= apu_FA;))
 352 
 353   DBGAPP ("doAppendCycleOperandRMW (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
 354   DBGAPP ("doAppendCycleOperandRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
 355 
 356   return finalAddress;
 357 }

/* */