src/dps8/doAppendCycleAPUDataRead.h

/* */
This source file includes following definitions.
doAppendCycleAPUDataRead
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 90fcb7d2-171d-11ee-a18f-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2022-2023 Charles Anthony
   9  * Copyright (c) 2022-2023 Jeffrey H. Johnson <trnsz@pobox.com>
  10  * Copyright (c) 2023-2023 The DPS8M Development Team
  11  *
  12  * All rights reserved.
  13  *
  14  * This software is made available under the terms of the ICU
  15  * License, version 1.8.1 or later.  For more details, see the
  16  * LICENSE.md file at the top-level directory of this distribution.
  17  *
  18  * ---------------------------------------------------------------------------
  19  */
  20 
  21 word24 doAppendCycleAPUDataRead (word36 * data, uint nWords) {
     /*  */
  22   DCDstruct * i = & cpu.currentInstruction;
  23   DBGAPP ("doAppendCycleAPUDataRead(Entry) thisCycle=APU_DATA_READ\n");
  24   DBGAPP ("doAppendCycleAPUDataRead(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle));
  25   DBGAPP ("doAppendCycleAPUDataRead(Entry) CA %06o\n", cpu.TPR.CA);
  26   DBGAPP ("doAppendCycleAPUDataRead(Entry) n=%2u\n", nWords);
  27   DBGAPP ("doAppendCycleAPUDataRead(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR);
  28   DBGAPP ("doAppendCycleAPUDataRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
  29 
  30   if (i->b29) {
  31     DBGAPP ("doAppendCycleAPUDataRead(Entry) isb29 PRNO %o\n", GET_PRN (IWB_IRODD));
  32   }
  33 
  34   bool nomatch = true;
  35   if (cpu.tweaks.enable_wam) {
  36     // AL39: The associative memory is ignored (forced to "no match") during
  37     // address preparation.
  38     // lptp,lptr,lsdp,lsdr,sptp,sptr,ssdp,ssdr
  39     // Unfortunately, ISOLTS doesn't try to execute any of these in append mode.
  40     // XXX should this be only for OPERAND_READ and OPERAND_STORE?
  41     nomatch = ((i->opcode == 0232 || i->opcode == 0254 ||
  42                 i->opcode == 0154 || i->opcode == 0173) &&
  43                 i->opcodeX ) ||
  44               ((i->opcode == 0557 || i->opcode == 0257) &&
  45                 ! i->opcodeX);
  46   }
  47 
  48   processor_cycle_type lastCycle = cpu.apu.lastCycle;
  49   cpu.apu.lastCycle = APU_DATA_READ;
  50 
  51   DBGAPP ("doAppendCycleAPUDataRead(Entry) XSF %o\n", cpu.cu.XSF);
  52 
  53   PNL (L68_ (cpu.apu.state = 0;))
  54 
  55   cpu.RSDWH_R1 = 0;
  56 
  57   cpu.acvFaults = 0;
  58 
  59 //#define FMSG(x) x
  60 #define FMSG(x)
  61   FMSG (char * acvFaultsMsg = "<unknown>";)
  62 
  63   word24 finalAddress = (word24) -1;  // not everything requires a final
  64                                         // address
  65 
  66 ////////////////////////////////////////
  67 //
  68 // Sheet 2: "A"
  69 //
  70 ////////////////////////////////////////
  71 
  72 //
  73 //  A:
  74 //    Get SDW
  75 
  76   //PNL (cpu.APUMemAddr = address;)
  77   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
  78 
  79   DBGAPP ("doAppendCycleAPUDataRead(A)\n");
  80 
  81     // is SDW for C(TPR.TSR) in SDWAM?
  82   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
  83     // No
  84     DBGAPP ("doAppendCycleAPUDataRead(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
  85 
  86     DBGAPP ("doAppendCycleAPUDataRead(A):DSBR.U=%o\n", cpu.DSBR.U);
  87 
  88     if (cpu.DSBR.U == 0) {
  89       fetch_dsptw (cpu.TPR.TSR);
  90 
  91       if (! cpu.PTW0.DF)
  92         doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleAPUDataRead(A): PTW0.F == 0");
  93 
  94       if (! cpu.PTW0.U)
  95         modify_dsptw (cpu.TPR.TSR);
  96 
  97       fetch_psdw (cpu.TPR.TSR);
  98     } else
  99       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
 100 
 101     if (cpu.SDW0.DF == 0) {
 102       DBGAPP ("doAppendCycleAPUDataRead(A): SDW0.F == 0! " "Initiating directed fault\n");
 103       // initiate a directed fault ...
 104       doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0");
 105     }
 106     // load SDWAM .....
 107     load_sdwam (cpu.TPR.TSR, nomatch);
 108   }
 109   DBGAPP ("doAppendCycleAPUDataRead(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E);
 110 
 111   // Yes...
 112   cpu.RSDWH_R1 = cpu.SDW->R1;
 113 
 114 ////////////////////////////////////////
 115 //
 116 // Sheet 3: "B"
 117 //
 118 ////////////////////////////////////////
 119 
 120 //
 121 // B: Check the ring
 122 //
 123 
 124   DBGAPP ("doAppendCycleAPUDataRead(B)\n");
 125 
 126   // check ring bracket consistency
 127 
 128   //C(SDW.R1) <= C(SDW.R2) <= C(SDW .R3)?
 129   if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) {
 130     // Set fault ACV0 = IRO
 131     cpu.acvFaults |= ACV0;
 132     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 133     FMSG (acvFaultsMsg = "acvFaults(B) C(SDW.R1) <= C(SDW.R2) <= " "C(SDW .R3)";)
 134   }
 135 
 136   if (lastCycle == RTCD_OPERAND_FETCH)
 137     sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\n", __func__, i->opcode);
 138 
 139   //
 140   // B1: The operand is one of: an instruction, data to be read or data to be
 141   //     written
 142   //
 143 
 144   //
 145   // check read bracket for read access
 146   //
 147 
 148   DBGAPP ("doAppendCycleAPUDataRead(B):!STR-OP\n");
 149 
 150   // No
 151   // C(TPR.TRR) > C(SDW .R2)?
 152   if (cpu.TPR.TRR > cpu.SDW->R2) {
 153     DBGAPP ("ACV3\n");
 154     DBGAPP ("doAppendCycleAPUDataRead(B) ACV3\n");
 155     //Set fault ACV3 = ORB
 156     cpu.acvFaults |= ACV3;
 157     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 158     FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R2)";)
 159   }
 160 
 161   if (cpu.SDW->R == 0) {
 162     // isolts 870
 163     cpu.TPR.TRR = cpu.PPR.PRR;
 164 
 165     //C(PPR.PSR) = C(TPR.TSR)?
 166     if (cpu.PPR.PSR != cpu.TPR.TSR) {
 167       DBGAPP ("ACV4\n");
 168       DBGAPP ("doAppendCycleAPUDataRead(B) ACV4\n");
 169       //Set fault ACV4 = R-OFF
 170       cpu.acvFaults |= ACV4;
 171       PNL (L68_ (cpu.apu.state |= apu_FLT;))
 172       FMSG (acvFaultsMsg = "acvFaults(B) C(PPR.PSR) = C(TPR.TSR)";)
 173     //} else {
 174       // sim_warn ("doAppendCycleAPUDataRead(B) SDW->R == 0 && cpu.PPR.PSR == cpu.TPR.TSR: %0#o\n", cpu.PPR.PSR);
 175     }
 176   }
 177 
 178 ////////////////////////////////////////
 179 //
 180 // Sheet 7: "G"
 181 //
 182 ////////////////////////////////////////
 183 
 184   DBGAPP ("doAppendCycleAPUDataRead(G)\n");
 185 
 186   //C(TPR.CA)0,13 > SDW.BOUND?
 187   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
 188     DBGAPP ("ACV15\n");
 189     DBGAPP ("doAppendCycleAPUDataRead(G) ACV15\n");
 190     cpu.acvFaults |= ACV15;
 191     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 192     FMSG (acvFaultsMsg = "acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND";)
 193     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
 194   }
 195 
 196   if (cpu.acvFaults) {
 197     DBGAPP ("doAppendCycleAPUDataRead(G) acvFaults\n");
 198     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 199     // Initiate an access violation fault
 200     doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault");
 201   }
 202 
 203   // is segment C(TPR.TSR) paged?
 204   if (cpu.SDW->U)
 205     goto H; // Not paged
 206 
 207   // Yes. segment is paged ...
 208   // is PTW for C(TPR.CA) in PTWAM?
 209 
 210   DBGAPP ("doAppendCycleAPUDataRead(G) CA %06o\n", cpu.TPR.CA);
 211   if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) {
 212     fetch_ptw (cpu.SDW, cpu.TPR.CA);
 213     if (! cpu.PTW0.DF)
 214       // initiate a directed fault
 215       doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0");
 216     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
 217   }
 218 
 219   // Prepage mode?
 220   // check for "uninterruptible" EIS instruction
 221   // ISOLTS-878 02: mvn,cmpn,mvne,ad3d; obviously also
 222   // ad2/3d,sb2/3d,mp2/3d,dv2/3d
 223   // DH03 p.8-13: probably also mve,btd,dtb
 224   if (i->opcodeX && ((i->opcode & 0770)== 0200|| (i->opcode & 0770) == 0220 || (i->opcode & 0770)== 020|| (i->opcode & 0770) == 0300)) {
 225     do_ptw2 (cpu.SDW, cpu.TPR.CA);
 226   }
 227   goto I;
 228 
 229 ////////////////////////////////////////
 230 //
 231 // Sheet 8: "H", "I"
 232 //
 233 ////////////////////////////////////////
 234 
 235 H:;
 236   DBGAPP ("doAppendCycleAPUDataRead(H): FANP\n");
 237 
 238   PNL (L68_ (cpu.apu.state |= apu_FANP;))
 239 
 240 
 241 
 242 
 243 
 244 
 245 
 246 
 247   set_apu_status (apuStatus_FANP);
 248 
 249   DBGAPP ("doAppendCycleAPUDataRead(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
 250 
 251   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
 252   finalAddress &= 0xffffff;
 253   PNL (cpu.APUMemAddr = finalAddress;)
 254 
 255   DBGAPP ("doAppendCycleAPUDataRead(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 256 
 257   goto HI;
 258 
 259 I:;
 260 
 261 // Set PTW.M
 262 
 263   DBGAPP ("doAppendCycleAPUDataRead(I): FAP\n");
 264 
 265     // final address paged
 266   set_apu_status (apuStatus_FAP);
 267   PNL (L68_ (cpu.apu.state |= apu_FAP;))
 268 
 269   word24 y2 = cpu.TPR.CA % 1024;
 270 
 271   // AL39: The hardware ignores low order bits of the main memory page
 272   // address according to page size
 273   finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2;
 274   finalAddress &= 0xffffff;
 275   PNL (cpu.APUMemAddr = finalAddress;)
 276 
 277 #ifdef L68
 278   if (cpu.MR_cache.emr && cpu.MR_cache.ihr)
 279     add_APU_history (APUH_FAP);
 280 #endif
 281   DBGAPP ("doAppendCycleAPUDataRead(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 282 
 283 HI:
 284   DBGAPP ("doAppendCycleAPUDataRead(HI)\n");
 285 
 286   // isolts 870
 287   cpu.cu.XSF = 1;
 288   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
 289 
 290   core_readN (finalAddress, data, nWords, "APU_DATA_READ");
 291 
 292 //Exit:;
 293 
 294   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
 295   PNL (cpu.APUDataBusAddr = finalAddress;)
 296 
 297   PNL (L68_ (cpu.apu.state |= apu_FA;))
 298 
 299   DBGAPP ("doAppendCycleAPUDataRead (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
 300   DBGAPP ("doAppendCycleAPUDataRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
 301 
 302   return finalAddress;    // or 0 or -1???
 303 }
/* */
root/src/dps8/doAppendCycleAPUDataRead.h

INCLUDED FROM

DEFINITIONS
