PPR 26 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 151 src/dps8/doAppendCycleABSA.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 154 src/dps8/doAppendCycleABSA.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 281 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 24 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 163 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 166 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 184 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TSR == cpu.PPR.PSR) PPR 185 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 198 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 347 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 24 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 160 src/dps8/doAppendCycleAPUDataRead.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 163 src/dps8/doAppendCycleAPUDataRead.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 300 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 24 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 151 src/dps8/doAppendCycleAPUDataStore.h if (cpu.TPR.TSR == cpu.PPR.PSR) PPR 152 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 165 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 303 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 60 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 258 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 261 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 473 src/dps8/doAppendCycleIndirectWordFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 76 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 337 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR > cpu.PPR.PRR) PPR 338 src/dps8/doAppendCycleInstructionFetch.h sim_warn ("rtcd: outbound call cpu.TPR.TRR %d cpu.PPR.PRR %d\r\n", cpu.TPR.TRR, cpu.PPR.PRR); PPR 340 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.PPR.PRR) { PPR 360 src/dps8/doAppendCycleInstructionFetch.h if (! (cpu.PPR.PRR < cpu.rRALR)) { PPR 362 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(D) C(PPR.PRR) %o < RALR %o\r\n", cpu.PPR.PRR, cpu.rRALR); PPR 402 src/dps8/doAppendCycleInstructionFetch.h if (cpu.PPR.PRR != cpu.TPR.TRR) { PPR 644 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.PSR = cpu.TPR.TSR; PPR 646 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.IC = cpu.TPR.CA; PPR 657 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.P = p; PPR 660 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.P = 0; PPR 669 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 24 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 165 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 168 src/dps8/doAppendCycleOperandRMW.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 186 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TSR == cpu.PPR.PSR) PPR 187 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 200 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 354 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 66 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 118 src/dps8/doAppendCycleOperandRead.h if (cpu.rRALR && (cpu.PPR.PRR >= cpu.rRALR)) { PPR 330 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 333 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 364 src/dps8/doAppendCycleOperandRead.h if (! (cpu.PPR.PRR < cpu.rRALR)) { PPR 366 src/dps8/doAppendCycleOperandRead.h DBGAPP ("acvFaults(D) C(PPR.PRR) %o < RALR %o\r\n", cpu.PPR.PRR, cpu.rRALR); PPR 389 src/dps8/doAppendCycleOperandRead.h cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu.SDW->EB, PPR 390 src/dps8/doAppendCycleOperandRead.h cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.TPR.TRR, cpu.PPR.PRR); PPR 407 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS) PPR 446 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.PPR.PRR) { PPR 448 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PRR < cpu.SDW->R2) { PPR 503 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PRR != cpu.TPR.TRR) { PPR 742 src/dps8/doAppendCycleOperandRead.h cpu.PR[n].RNR = cpu.PPR.PRR; PPR 746 src/dps8/doAppendCycleOperandRead.h cpu.PR[n].SNR = cpu.PPR.PSR; PPR 747 src/dps8/doAppendCycleOperandRead.h cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; PPR 758 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PSR = cpu.TPR.TSR; PPR 760 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; PPR 770 src/dps8/doAppendCycleOperandRead.h cpu.PPR.P = p; PPR 773 src/dps8/doAppendCycleOperandRead.h cpu.PPR.P = 0; PPR 782 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR == cpu.PPR.PRR) { PPR 803 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PRR = cpu.TPR.TRR; PPR 805 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PSR = cpu.TPR.TSR; PPR 807 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; PPR 818 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 24 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 146 src/dps8/doAppendCycleOperandStore.h if (cpu.TPR.TSR == cpu.PPR.PSR) PPR 147 src/dps8/doAppendCycleOperandStore.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 160 src/dps8/doAppendCycleOperandStore.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 308 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 24 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 189 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TRR = cpu.PPR.PRR; PPR 192 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PPR 352 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1); PPR 366 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PSR = cpu.TPR.TSR; PPR 368 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.IC = cpu.TPR.CA; PPR 378 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.P = cpu.SDW->P; PPR 381 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.P = 0; PPR 392 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 84 src/dps8/dps8_addrmods.c return cpu.PPR.IC; PPR 1218 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.PPR.PSR); PPR 1455 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1458 src/dps8/dps8_append.c if (cpu.PPR.PSR != cpu.TPR.TSR) PPR 1488 src/dps8/dps8_append.c if (cpu.TPR.TSR == cpu.PPR.PSR) PPR 1489 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1505 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1555 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.PPR.PRR) PPR 1557 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.PPR.PRR); PPR 1559 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.PPR.PRR) PPR 1580 src/dps8/dps8_append.c if (! (cpu.PPR.PRR < cpu.rRALR)) PPR 1584 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.rRALR); PPR 1608 src/dps8/dps8_append.c cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, PPR 1610 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.PPR.PRR); PPR 1628 src/dps8/dps8_append.c if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS) PPR 1670 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.PPR.PRR) PPR 1673 src/dps8/dps8_append.c if (cpu.PPR.PRR < cpu.SDW->R2) PPR 1736 src/dps8/dps8_append.c if (cpu.PPR.PRR != cpu.TPR.TRR) PPR 2045 src/dps8/dps8_append.c cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1); PPR 2074 src/dps8/dps8_append.c cpu.PR[n].RNR = cpu.PPR.PRR; PPR 2078 src/dps8/dps8_append.c cpu.PR[n].SNR = cpu.PPR.PSR; PPR 2079 src/dps8/dps8_append.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; PPR 2126 src/dps8/dps8_append.c cpu.PPR.PSR = cpu.TPR.TSR; PPR 2128 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; PPR 2139 src/dps8/dps8_append.c cpu.PPR.P = cpu.SDW->P; PPR 2144 src/dps8/dps8_append.c cpu.PPR.P = 0; PPR 2153 src/dps8/dps8_append.c if (cpu.TPR.TRR == cpu.PPR.PRR) PPR 2178 src/dps8/dps8_append.c cpu.PPR.PRR = cpu.TPR.TRR; PPR 2180 src/dps8/dps8_append.c cpu.PPR.PSR = cpu.TPR.TSR; PPR 2182 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; PPR 2228 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 987 src/dps8/dps8_console.c cpus[i].PPR.PSR, PPR 988 src/dps8/dps8_console.c cpus[i].PPR.IC, PPR 980 src/dps8/dps8_cpu.c cpu.PPR.IC = 0; PPR 981 src/dps8/dps8_cpu.c cpu.PPR.PRR = 0; PPR 982 src/dps8/dps8_cpu.c cpu.PPR.PSR = 0; PPR 983 src/dps8/dps8_cpu.c cpu.PPR.P = 1; PPR 1023 src/dps8/dps8_cpu.c (void)memset (& cpu.PPR, 0, sizeof (struct ppr_s)); PPR 2059 src/dps8/dps8_cpu.c { ORDATA (IC, cpus[0].PPR.IC, VASIZE), 0, 0, 0 }, PPR 2176 src/dps8/dps8_cpu.c sim_brk_test ((cpu.PPR.IC & 0777777) | PPR 2177 src/dps8/dps8_cpu.c ((((t_addr) cpu.PPR.PSR) & 037777) << 18), PPR 2513 src/dps8/dps8_cpu.c cpu.PPR.IC = cpu.lufXferIC; PPR 2683 src/dps8/dps8_cpu.c cpus [0].PPR.IC = dummy_IC; PPR 2926 src/dps8/dps8_cpu.c cpu.PPR.PRR = 0; PPR 3047 src/dps8/dps8_cpu.c get_BAR_address (cpup, cpu.PPR.IC); PPR 3064 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 3065 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 3068 src/dps8/dps8_cpu.c fetchInstruction (cpup, cpu.PPR.IC); PPR 3096 src/dps8/dps8_cpu.c (cpu.PPR.IC & 1) == 0 && PPR 3113 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 1) PPR 3266 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 3267 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 3285 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 3286 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 3289 src/dps8/dps8_cpu.c fetchInstruction (cpup, cpu.PPR.IC); PPR 3441 src/dps8/dps8_cpu.c if (stall_points[i].segno && stall_points[i].segno == cpu.PPR.PSR && PPR 3442 src/dps8/dps8_cpu.c stall_points[i].offset && stall_points[i].offset == cpu.PPR.IC) PPR 3460 src/dps8/dps8_cpu.c cpu.lufExecIC = cpu.PPR.IC; PPR 3497 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 3498 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 3739 src/dps8/dps8_cpu.c (cpu.cu.rd && (cpu.PPR.IC & 1)) || PPR 3744 src/dps8/dps8_cpu.c -- cpu.PPR.IC; PPR 3769 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; PPR 3770 src/dps8/dps8_cpu.c cpu.PPR.IC ++; PPR 3805 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 3806 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 3817 src/dps8/dps8_cpu.c cpu.PPR.IC ++; PPR 3819 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; PPR 3842 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 0 && PPR 3846 src/dps8/dps8_cpu.c (cpu.PPR.IC & ~3u) != (cpu.last_write & ~3u)) PPR 3848 src/dps8/dps8_cpu.c cpu.PPR.IC ++; PPR 3855 src/dps8/dps8_cpu.c cpu.PPR.IC ++; PPR 3857 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; PPR 3872 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; PPR 3873 src/dps8/dps8_cpu.c cpu.PPR.IC ++; PPR 3949 src/dps8/dps8_cpu.c cpu.PPR.PRR = 0; PPR 4119 src/dps8/dps8_cpu.c dummy_IC = cpu.PPR.IC; PPR 4337 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); PPR 4344 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, addr, PPR 4379 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PPR 4424 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PPR 4447 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PPR 4463 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PPR 4507 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PPR 4546 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); PPR 4553 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PPR 4564 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PPR 4583 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); PPR 4590 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PPR 4601 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PPR 4643 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PPR 4666 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PPR 4759 src/dps8/dps8_cpu.c else if (cpu.PPR.P) PPR 4824 src/dps8/dps8_cpu.c cpu.PPR.P = 1; PPR 5203 src/dps8/dps8_cpu.c putbits36_18 (& w1, 54 - 36, cpu.PPR.IC); PPR 1042 src/dps8/dps8_cpu.h #define USE_IRODD (cpu.cu.rd && ((cpu. PPR.IC & 1) != 0)) PPR 1728 src/dps8/dps8_cpu.h struct ppr_s PPR; // Procedure Pointer Register PPR 347 src/dps8/dps8_eis.c return cpu.PPR.IC; PPR 444 src/dps8/dps8_eis.c return cpu.PPR.IC; PPR 519 src/dps8/dps8_eis.c return cpu.PPR.IC; PPR 589 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 590 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 659 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 660 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 826 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 827 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 888 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 889 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1271 src/dps8/dps8_eis.c cpu.PPR.PRR); PPR 1419 src/dps8/dps8_eis.c e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); PPR 1639 src/dps8/dps8_eis.c e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); PPR 1691 src/dps8/dps8_eis.c e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); PPR 1881 src/dps8/dps8_eis.c e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); PPR 388 src/dps8/dps8_faults.c sim_printf (" TRO PSR:IC %05o:%06o\r\n", cpu.PPR.PSR, cpu.PPR.IC); PPR 393 src/dps8/dps8_faults.c sim_printf (" ACV %012llo PSR:IC %05o:%06o\r\n", subFault.bits, cpu.PPR.PSR, cpu.PPR.IC); PPR 425 src/dps8/dps8_faults.c fault_psr = cpu . PPR.PSR; PPR 426 src/dps8/dps8_faults.c fault_ic = cpu . PPR.IC; PPR 542 src/dps8/dps8_faults.c (cpu.PPR.IC & 1) && cpu.l68PairValid && PPR 596 src/dps8/dps8_faults.c cpu.PPR.IC = (cpu.PPR.IC - 1) & MASK18; PPR 796 src/dps8/dps8_faults.c cpu.PPR.IC); PPR 954 src/dps8/dps8_faults.c cpu.PPR.IC); PPR 117 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 118 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 135 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) PPR 196 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 197 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 210 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PPR 266 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 267 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 281 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PPR 338 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 339 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 352 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PPR 408 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 409 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 422 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PPR 480 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 481 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 494 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PPR 550 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 551 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 564 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PPR 633 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 634 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 728 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 729 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 820 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 821 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 906 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 907 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 947 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 948 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1030 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1031 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1130 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1131 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1154 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) PPR 1254 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1255 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1279 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) PPR 1348 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1349 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1420 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1421 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1494 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1495 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1576 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1577 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1655 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1656 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1735 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1736 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1832 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1833 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1963 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1964 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 314 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.PPR.PRR; PPR 318 src/dps8/dps8_ins.c cpu.PR[n].SNR = cpu.PPR.PSR; PPR 319 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; PPR 325 src/dps8/dps8_ins.c cpu.PPR.IC = cpu.TPR.CA; PPR 330 src/dps8/dps8_ins.c __func__, cpu.PPR.PSR, cpu.PPR.IC); PPR 331 src/dps8/dps8_ins.c if (cpu.PPR.IC & 1) PPR 367 src/dps8/dps8_ins.c putbits36_3 (& words[0], 0, cpu.PPR.PRR); PPR 368 src/dps8/dps8_ins.c putbits36_15 (& words[0], 3, cpu.PPR.PSR); PPR 369 src/dps8/dps8_ins.c putbits36_1 (& words[0], 18, cpu.PPR.P); PPR 450 src/dps8/dps8_ins.c putbits36_18 (& words[4], 0, cpu.PPR.IC); PPR 503 src/dps8/dps8_ins.c putbits36_1 (& words[5], 25, cpu.cu.xdo && (! cpu.cu.xde || (cpu.PPR.IC & 1))); PPR 625 src/dps8/dps8_ins.c cpu.cu_data.PSR = cpu.PPR.PSR; PPR 626 src/dps8/dps8_ins.c cpu.cu_data.PRR = cpu.PPR.PRR; PPR 627 src/dps8/dps8_ins.c cpu.cu_data.IC = cpu.PPR.IC; PPR 657 src/dps8/dps8_ins.c cpu.PPR.PRR = getbits36_3 (words[0], 0); PPR 658 src/dps8/dps8_ins.c cpu.PPR.PSR = getbits36_15 (words[0], 3); PPR 659 src/dps8/dps8_ins.c cpu.PPR.P = getbits36_1 (words[0], 18); PPR 737 src/dps8/dps8_ins.c cpu.PPR.IC = getbits36_18 (words[4], 0); PPR 1187 src/dps8/dps8_ins.c if (cpu.cu.rd && ((cpu.PPR.IC & 1) != 0)) PPR 1223 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) // Even PPR 1260 src/dps8/dps8_ins.c char * where = lookup_address (cpu.PPR.PSR, cpu.PPR.IC, & compname, PPR 1270 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); PPR 1274 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o %s\r\n", cpu.PPR.IC, where); PPR 1282 src/dps8/dps8_ins.c cpu.PPR.PSR, PPR 1283 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); PPR 1288 src/dps8/dps8_ins.c cpu.PPR.PSR, cpu.PPR.IC, where); PPR 1302 src/dps8/dps8_ins.c cpu.PPR.IC, PPR 1319 src/dps8/dps8_ins.c cpu.PPR.IC, PPR 1339 src/dps8/dps8_ins.c cpu.PPR.PSR, PPR 1341 src/dps8/dps8_ins.c cpu.PPR.IC, PPR 1342 src/dps8/dps8_ins.c cpu.PPR.PRR, PPR 1358 src/dps8/dps8_ins.c cpu.PPR.PSR, PPR 1359 src/dps8/dps8_ins.c cpu.PPR.IC, PPR 1360 src/dps8/dps8_ins.c cpu.PPR.PRR, PPR 1411 src/dps8/dps8_ins.c trk (cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IWB_IRODD); PPR 1575 src/dps8/dps8_ins.c if (!cpu.cu.xde && cpu.cu.xdo /* odd instr being executed */ && !(cpu.PPR.IC & 1)) PPR 1582 src/dps8/dps8_ins.c if (opcode == 0560 && !opcodeX && cpu.cu.xde && !(cpu.PPR.IC & 1)) PPR 1783 src/dps8/dps8_ins.c if (n_dbgevents && (dbgevt = (dbgevent_lookup (cpu.PPR.PSR, cpu.PPR.IC))) >= 0) { PPR 1876 src/dps8/dps8_ins.c cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], PPR 1888 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); PPR 1960 src/dps8/dps8_ins.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 1961 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 1970 src/dps8/dps8_ins.c word18 saveIC = cpu.PPR.IC; PPR 1972 src/dps8/dps8_ins.c ReadInstructionFetch (cpup, cpu.PPR.IC + 1 + n, & cpu.currentEISinstruction.op[n]); PPR 1973 src/dps8/dps8_ins.c cpu.PPR.IC = saveIC; PPR 2014 src/dps8/dps8_ins.c cpu.TPR.TRR = max (cpu.PAR[n].RNR, cpu.PPR.PRR); PPR 2016 src/dps8/dps8_ins.c cpu.TPR.TRR = max3 (cpu.PAR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); PPR 2037 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 2128 src/dps8/dps8_ins.c cpu.TPR.TRR = cpu.PPR.PRR; PPR 2129 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; PPR 2140 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); PPR 2382 src/dps8/dps8_ins.c cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PPR 3061 src/dps8/dps8_ins.c word18 ret = (cpu.PPR.IC + 1) & MASK18; PPR 4002 src/dps8/dps8_ins.c SETHI (cpu.CY, (cpu.PPR.IC + 1) & MASK18); PPR 4015 src/dps8/dps8_ins.c cpu.CY = ((word36) ((cpu.PPR.IC + 2) & MASK18)) << 18; PPR 4081 src/dps8/dps8_ins.c putbits36_15 (& cpu.Ypair[0], 3, cpu.PPR.PSR); PPR 4082 src/dps8/dps8_ins.c putbits36_3 (& cpu.Ypair[0], 18, cpu.PPR.PRR); PPR 4086 src/dps8/dps8_ins.c putbits36_18 (& cpu.Ypair[1], 0, cpu.PPR.IC + 2); PPR 6598 src/dps8/dps8_ins.c "call6 PRR %o PSR %o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PPR 6617 src/dps8/dps8_ins.c cpu.PPR.IC = GETHI (cpu.CY); PPR 7404 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) PPR 7730 src/dps8/dps8_ins.c sim_printf (" ldt %d PSR:IC %05o:%06o\r\n", cpu.rTR, cpu.PPR.PSR, cpu.PPR.IC); PPR 7781 src/dps8/dps8_ins.c sim_printf (" RALR set to %o PSR:IC %05o:%06o\r\n", cpu.rRALR, cpu.PPR.PSR, cpu.PPR.IC); PPR 8887 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 034 && cpu.PPR.IC == 03535) { PPR 8921 src/dps8/dps8_ins.c " no events in queue\r\n", cpu.PPR.IC); PPR 8938 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 0430 && cpu.PPR.IC == 012) PPR 8978 src/dps8/dps8_ins.c (cpu.PPR.PSR !=0 || cpu.PPR.IC != 0)) { PPR 8980 src/dps8/dps8_ins.c sim_printf ("CPU%c DIS %o:%o gives up master\r\n", cpu.cpuIdx + 'A', cpu.PPR.PSR, cpu.PPR.IC); PPR 8997 src/dps8/dps8_ins.c PPR 10096 src/dps8/dps8_ins.c (cpu.Yblock8[0]>>18)&MASK15, (cpu.Yblock8[4]>>18)&MASK18, cpu.PPR.PSR, cpu.PPR.IC); PPR 10141 src/dps8/dps8_ins.c word1 saveP = cpu.PPR.P; // ISOLTS-870 02m PPR 10146 src/dps8/dps8_ins.c cpu.PPR.P = saveP; PPR 3757 src/dps8/dps8_iom.c __func__, iomChar (iom_unit_idx), cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC); PPR 23 src/dps8/dps8_mp.h struct ppr_s PPR; PPR 30 src/dps8/dps8_simh.h (! sim_deb_segno_on) || sim_deb_segno[cpu.PPR.PSR & (DEBUG_SEGNO_LIMIT - 1)]) && \ PPR 31 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || sim_deb_ringno == NO_SUCH_RINGNO || sim_deb_ringno == cpu . PPR. PRR) && \ PPR 2770 src/dps8/dps8_sys.c word15 icSegno = cpu.PPR.PSR; PPR 2771 src/dps8/dps8_sys.c word18 icOffset = cpu.PPR.IC; PPR 4099 src/dps8/dps8_sys.c { "cpus[].PPR", SYM_STRUCT_OFFSET, SYM_PTR, offsetof (cpu_state_t, PPR) }, PPR 177 src/dps8/hdbg.c if (filter && hdbgSegNum >= 0 && hdbgSegNum != cpu.PPR.PSR) \ PPR 179 src/dps8/hdbg.c if (filter && hdbgSegNum > 0 && blacklist[cpu.PPR.IC]) \ PPR 201 src/dps8/hdbg.c hevp[p].trace.segno = cpu.PPR.PSR; PPR 202 src/dps8/hdbg.c hevp[p].trace.ic = cpu.PPR.IC; PPR 203 src/dps8/hdbg.c hevp[p].trace.ring = cpu.PPR.PRR; PPR 377 src/dps8/panelScraper.c SETL (bank_a, 0+3, cpu.PPR.PRR, 3); PPR 378 src/dps8/panelScraper.c SETL (bank_a, 3+3, cpu.PPR.PSR, 15); PPR 379 src/dps8/panelScraper.c SETL1 (bank_a, 18+3, cpu.PPR.P); PPR 657 src/dps8/panelScraper.c SETL (bank_e, 0+3, cpu.PPR.IC, 18); PPR 917 src/dps8/panelScraper.c SETL (bank_g, 0, cpu.PPR.IC, 18); PPR 951 src/dps8/panelScraper.c SETL (bank_j, 3, cpu.PPR.IC, 18);