src/dps8/doAppendCycleAPUDataStore.h

/* */
This source file includes following definitions.
doAppendCycleAPUDataStore
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 83d28596-171d-11ee-88df-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2022-2023 Charles Anthony
   9  * Copyright (c) 2022-2023 Jeffrey H. Johnson
  10  * Copyright (c) 2022-2024 The DPS8M Development Team
  11  *
  12  * This software is made available under the terms of the ICU License.
  13  * See the LICENSE.md file at the top-level directory of this distribution.
  14  *
  15  * ---------------------------------------------------------------------------
  16  */
  17 
  18 word24 doAppendCycleAPUDataStore (cpu_state_t * cpup, word36 * data, uint nWords) {
     /*  */
  19   DCDstruct * i = & cpu.currentInstruction;
  20   DBGAPP ("doAppendCycleAPUDataStore(Entry) thisCycle=APU_DATA_STORE\n");
  21   DBGAPP ("doAppendCycleAPUDataStore(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle));
  22   DBGAPP ("doAppendCycleAPUDataStore(Entry) CA %06o\n", cpu.TPR.CA);
  23   DBGAPP ("doAppendCycleAPUDataStore(Entry) n=%2u\n", nWords);
  24   DBGAPP ("doAppendCycleAPUDataStore(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR);
  25   DBGAPP ("doAppendCycleAPUDataStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
  26 
  27   if (i->b29) {
  28     DBGAPP ("doAppendCycleAPUDataStore(Entry) isb29 PRNO %o\n", GET_PRN (IWB_IRODD));
  29   }
  30 
  31   bool nomatch = true;
  32   if (cpu.tweaks.enable_wam) {
  33     // AL39: The associative memory is ignored (forced to "no match") during
  34     // address preparation.
  35     // lptp,lptr,lsdp,lsdr,sptp,sptr,ssdp,ssdr
  36     // Unfortunately, ISOLTS doesn't try to execute any of these in append mode.
  37     // XXX should this be only for OPERAND_READ and OPERAND_STORE?
  38     nomatch = ((i->opcode == 0232 || i->opcode == 0254 ||
  39                 i->opcode == 0154 || i->opcode == 0173) &&
  40                 i->opcodeX ) ||
  41                ((i->opcode == 0557 || i->opcode == 0257) &&
  42                 ! i->opcodeX);
  43   }
  44 
  45   processor_cycle_type lastCycle = cpu.apu.lastCycle;
  46   cpu.apu.lastCycle = APU_DATA_STORE;
  47 
  48   DBGAPP ("doAppendCycleAPUDataStore(Entry) XSF %o\n", cpu.cu.XSF);
  49 
  50   PNL (L68_ (cpu.apu.state = 0;))
  51 
  52   cpu.RSDWH_R1 = 0;
  53 
  54   cpu.acvFaults = 0;
  55 
  56 //#define FMSG(x) x
  57 #define FMSG(x)
  58   FMSG (char * acvFaultsMsg = "<unknown>";)
  59 
  60   word24 finalAddress = (word24) -1;  // not everything requires a final address
  61 
  62 ////////////////////////////////////////
  63 //
  64 // Sheet 2: "A"
  65 //
  66 ////////////////////////////////////////
  67 
  68 //
  69 //  A:
  70 //    Get SDW
  71 
  72   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
  73 
  74   DBGAPP ("doAppendCycleAPUDataStore(A)\n");
  75 
  76   // is SDW for C(TPR.TSR) in SDWAM?
  77   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
  78     // No
  79     DBGAPP ("doAppendCycleAPUDataStore(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
  80 
  81     DBGAPP ("doAppendCycleAPUDataStore(A):DSBR.U=%o\n", cpu.DSBR.U);
  82 
  83     if (cpu.DSBR.U == 0) {
  84       fetch_dsptw (cpup, cpu.TPR.TSR);
  85 
  86       if (! cpu.PTW0.DF)
  87         doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleAPUDataStore(A): PTW0.F == 0");
  88 
  89       if (! cpu.PTW0.U)
  90           modify_dsptw (cpup, cpu.TPR.TSR);
  91 
  92       fetch_psdw (cpup, cpu.TPR.TSR);
  93     } else
  94       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
  95 
  96     if (cpu.SDW0.DF == 0) {
  97       DBGAPP ("doAppendCycleAPUDataStore(A): SDW0.F == 0! " "Initiating directed fault\n");
  98       // initiate a directed fault ...
  99       doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0");
 100     }
 101     // load SDWAM .....
 102     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
 103   }
 104   DBGAPP ("doAppendCycleAPUDataStore(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E);
 105 
 106   // Yes...
 107   cpu.RSDWH_R1 = cpu.SDW->R1;
 108 
 109 ////////////////////////////////////////
 110 //
 111 // Sheet 3: "B"
 112 //
 113 ////////////////////////////////////////
 114 
 115 //
 116 // B: Check the ring
 117 //
 118 
 119   DBGAPP ("doAppendCycleAPUDataStore(B)\n");
 120 
 121   // check ring bracket consistency
 122 
 123   //C(SDW.R1) <= C(SDW.R2) <= C(SDW .R3)?
 124   if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) {
 125     // Set fault ACV0 = IRO
 126     cpu.acvFaults |= ACV0;
 127     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 128     FMSG (acvFaultsMsg = "acvFaults(B) C(SDW.R1) <= C(SDW.R2) <= " "C(SDW .R3)";)
 129   }
 130 
 131   // lastCycle == RTCD_OPERAND_FETCH
 132   // if a fault happens between the RTCD_OPERAND_FETCH and the INSTRUCTION_FETCH
 133   // of the next instruction - this happens about 35 time for just booting  and
 134   // shutting down multics -- a stored lastCycle is useless.
 135   // the opcode is preserved across faults and only replaced as the
 136   // INSTRUCTION_FETCH succeeds.
 137   if (lastCycle == RTCD_OPERAND_FETCH)
 138     sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\n", __func__, i->opcode);
 139 
 140   //
 141   // B1: The operand is one of: an instruction, data to be read or data to be
 142   //     written
 143   //
 144 
 145   //
 146   // check write bracket for write access
 147   //
 148   DBGAPP ("doAppendCycleAPUDataStore(B):STR-OP\n");
 149 
 150   // isolts 870
 151   if (cpu.TPR.TSR == cpu.PPR.PSR)
 152     cpu.TPR.TRR = cpu.PPR.PRR;
 153 
 154   // C(TPR.TRR) > C(SDW .R1)? Note typo in AL39, R2 should be R1
 155   if (cpu.TPR.TRR > cpu.SDW->R1) {
 156     DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1);
 157     //Set fault ACV5 = OWB
 158     cpu.acvFaults |= ACV5;
 159     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 160     FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R1)";)
 161   }
 162 
 163   if (! cpu.SDW->W) {
 164     // isolts 870
 165     cpu.TPR.TRR = cpu.PPR.PRR;
 166 
 167     DBGAPP ("ACV6\n");
 168     // Set fault ACV6 = W-OFF
 169     cpu.acvFaults |= ACV6;
 170     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 171     FMSG (acvFaultsMsg = "acvFaults(B) ACV6 = W-OFF";)
 172   }
 173 
 174 ////////////////////////////////////////
 175 //
 176 // Sheet 7: "G"
 177 //
 178 ////////////////////////////////////////
 179 
 180   DBGAPP ("doAppendCycleAPUDataStore(G)\n");
 181 
 182   //C(TPR.CA)0,13 > SDW.BOUND?
 183   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
 184     DBGAPP ("ACV15\n");
 185     DBGAPP ("doAppendCycleAPUDataStore(G) ACV15\n");
 186     cpu.acvFaults |= ACV15;
 187     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 188     FMSG (acvFaultsMsg = "acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND";)
 189     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o",
 190             cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
 191   }
 192 
 193   if (cpu.acvFaults) {
 194     DBGAPP ("doAppendCycleAPUDataStore(G) acvFaults\n");
 195     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 196     // Initiate an access violation fault
 197     doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault");
 198   }
 199 
 200   // is segment C(TPR.TSR) paged?
 201   if (cpu.SDW->U)
 202     goto H; // Not paged
 203 
 204   // Yes. segment is paged ...
 205   // is PTW for C(TPR.CA) in PTWAM?
 206 
 207   DBGAPP ("doAppendCycleAPUDataStore(G) CA %06o\n", cpu.TPR.CA);
 208   if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) {
 209     fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA);
 210     if (! cpu.PTW0.DF) {
 211       // initiate a directed fault
 212       doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0");
 213     }
 214     loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
 215   }
 216 
 217   // Prepage mode?
 218   // check for "uninterruptible" EIS instruction
 219   // ISOLTS-878 02: mvn,cmpn,mvne,ad3d; obviously also
 220   // ad2/3d,sb2/3d,mp2/3d,dv2/3d
 221   // DH03 p.8-13: probably also mve,btd,dtb
 222   if (i->opcodeX && ((i->opcode & 0770)== 0200|| (i->opcode & 0770) == 0220
 223       || (i->opcode & 0770)== 020|| (i->opcode & 0770) == 0300)) {
 224     do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA);
 225   }
 226   goto I;
 227 
 228 ////////////////////////////////////////
 229 //
 230 // Sheet 8: "H", "I"
 231 //
 232 ////////////////////////////////////////
 233 
 234 H:;
 235   DBGAPP ("doAppendCycleAPUDataStore(H): FANP\n");
 236 
 237   PNL (L68_ (cpu.apu.state |= apu_FANP;))
 238 
 239 
 240 
 241 
 242 
 243 
 244 
 245 
 246   set_apu_status (cpup, apuStatus_FANP);
 247 
 248   DBGAPP ("doAppendCycleAPUDataStore(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
 249 
 250   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
 251   finalAddress &= 0xffffff;
 252   PNL (cpu.APUMemAddr = finalAddress;)
 253 
 254   DBGAPP ("doAppendCycleAPUDataStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 255 
 256   goto HI;
 257 
 258 I:;
 259 
 260 // Set PTW.M
 261 
 262   DBGAPP ("doAppendCycleAPUDataStore(I): FAP\n");
 263   if (cpu.PTW->M == 0)  // is this the right way to do this?
 264      modify_ptw (cpup, cpu.SDW, cpu.TPR.CA);
 265 
 266     // final address paged
 267   set_apu_status (cpup, apuStatus_FAP);
 268   PNL (L68_ (cpu.apu.state |= apu_FAP;))
 269 
 270   word24 y2 = cpu.TPR.CA % 1024;
 271 
 272   // AL39: The hardware ignores low order bits of the main memory page
 273   // address according to page size
 274   finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2;
 275   finalAddress &= 0xffffff;
 276   PNL (cpu.APUMemAddr = finalAddress;)
 277 
 278 #if defined(L68)
 279   if (cpu.MR_cache.emr && cpu.MR_cache.ihr)
 280     add_APU_history (APUH_FAP);
 281 #endif /* if defined(L68) */
 282   DBGAPP ("doAppendCycleAPUDataStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 283 
 284   goto HI;
 285 
 286 HI:
 287   DBGAPP ("doAppendCycleAPUDataStore(HI)\n");
 288 
 289   // isolts 870
 290   cpu.cu.XSF = 1;
 291   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
 292 
 293   core_writeN (cpup, finalAddress, data, nWords, "APU_DATA_STORE");
 294 
 295   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
 296   PNL (cpu.APUDataBusAddr = finalAddress;)
 297 
 298   PNL (L68_ (cpu.apu.state |= apu_FA;))
 299 
 300   DBGAPP ("doAppendCycleAPUDataStore (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
 301   DBGAPP ("doAppendCycleAPUDataStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
 302 
 303   return finalAddress;    // or 0 or -1???
 304 }
/* */
root/src/dps8/doAppendCycleAPUDataStore.h

INCLUDED FROM

DEFINITIONS
