This source file includes following definitions.
- doAppendCycleRTCDOperandFetch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 word24 doAppendCycleRTCDOperandFetch (cpu_state_t * cpup, word36 * data, uint nWords) {
19 DCDstruct * i = & cpu.currentInstruction;
20 DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) thisCycle=RTCD_OPERAND_FETCH\n");
21 DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle));
22 DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) CA %06o\n", cpu.TPR.CA);
23 DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) n=%2u\n", nWords);
24 DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR);
25 DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
26
27 if (i->b29) {
28 DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) isb29 PRNO %o\n", GET_PRN (IWB_IRODD));
29 }
30
31 bool nomatch = true;
32 if (cpu.tweaks.enable_wam) {
33
34
35
36
37
38 nomatch = ((i->opcode == 0232 || i->opcode == 0254 ||
39 i->opcode == 0154 || i->opcode == 0173) &&
40 i->opcodeX ) ||
41 ((i->opcode == 0557 || i->opcode == 0257) &&
42 ! i->opcodeX);
43 }
44
45 processor_cycle_type lastCycle = cpu.apu.lastCycle;
46 cpu.apu.lastCycle = RTCD_OPERAND_FETCH;
47
48 DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) XSF %o\n", cpu.cu.XSF);
49
50 PNL (L68_ (cpu.apu.state = 0;))
51
52 cpu.RSDWH_R1 = 0;
53
54 cpu.acvFaults = 0;
55
56
57 #define FMSG(x)
58 FMSG (char * acvFaultsMsg = "<unknown>";)
59
60 word24 finalAddress = (word24) -1;
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84 if (get_addr_mode(cpup) == ABSOLUTE_mode && ! (cpu.cu.XSF || cpu.currentInstruction.b29)) {
85 cpu.TPR.TSR = 0;
86 DBGAPP ("RTCD_OPERAND_FETCH ABSOLUTE mode set TSR %05o TRR %o\n", cpu.TPR.TSR, cpu.TPR.TRR);
87 }
88
89 goto A;
90
91
92
93
94
95
96
97
98
99
100
101 A:;
102
103
104 PNL (cpu.APUMemAddr = cpu.TPR.CA;)
105
106 DBGAPP ("doAppendCycleRTCDOperandFetch(A)\n");
107
108
109 if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
110
111 DBGAPP ("doAppendCycleRTCDOperandFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
112 DBGAPP ("doAppendCycleRTCDOperandFetch(A):DSBR.U=%o\n", cpu.DSBR.U);
113
114 if (cpu.DSBR.U == 0) {
115 fetch_dsptw (cpup, cpu.TPR.TSR);
116
117 if (! cpu.PTW0.DF)
118 doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleRTCDOperandFetch(A): PTW0.F == 0");
119
120 if (! cpu.PTW0.U)
121 modify_dsptw (cpup, cpu.TPR.TSR);
122
123 fetch_psdw (cpup, cpu.TPR.TSR);
124 } else
125 fetch_nsdw (cpup, cpu.TPR.TSR);
126
127 if (cpu.SDW0.DF == 0) {
128 DBGAPP ("doAppendCycleRTCDOperandFetch(A): SDW0.F == 0! " "Initiating directed fault\n");
129
130 doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0");
131 }
132
133 load_sdwam (cpup, cpu.TPR.TSR, nomatch);
134 }
135 DBGAPP ("doAppendCycleRTCDOperandFetch(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E);
136
137
138 cpu.RSDWH_R1 = cpu.SDW->R1;
139
140
141
142
143
144
145
146
147
148
149
150 DBGAPP ("doAppendCycleRTCDOperandFetch(B)\n");
151
152
153
154
155 if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) {
156
157 cpu.acvFaults |= ACV0;
158 PNL (L68_ (cpu.apu.state |= apu_FLT;))
159 FMSG (acvFaultsMsg = "acvFaults(B) C(SDW.R1) <= C(SDW.R2) <= C(SDW .R3)";)
160 }
161
162 if (lastCycle == RTCD_OPERAND_FETCH)
163 sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\n", __func__, i->opcode);
164
165
166
167
168
169
170
171
172
173
174 DBGAPP ("doAppendCycleRTCDOperandFetch(B):!STR-OP\n");
175
176
177
178 if (cpu.TPR.TRR > cpu.SDW->R2) {
179 DBGAPP ("ACV3\n");
180 DBGAPP ("doAppendCycleRTCDOperandFetch(B) ACV3\n");
181
182 cpu.acvFaults |= ACV3;
183 PNL (L68_ (cpu.apu.state |= apu_FLT;))
184 FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R2)";)
185 }
186
187 if (cpu.SDW->R == 0) {
188
189 cpu.TPR.TRR = cpu.PPR.PRR;
190
191
192 if (cpu.PPR.PSR != cpu.TPR.TSR) {
193 DBGAPP ("ACV4\n");
194 DBGAPP ("doAppendCycleRTCDOperandFetch(B) ACV4\n");
195
196 cpu.acvFaults |= ACV4;
197 PNL (L68_ (cpu.apu.state |= apu_FLT;))
198 FMSG (acvFaultsMsg = "acvFaults(B) C(PPR.PSR) = C(TPR.TSR)";)
199
200
201 }
202 }
203
204 goto G;
205
206
207
208
209
210
211
212 G:;
213
214 DBGAPP ("doAppendCycleRTCDOperandFetch(G)\n");
215
216
217 if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
218 DBGAPP ("ACV15\n");
219 DBGAPP ("doAppendCycleRTCDOperandFetch(G) ACV15\n");
220 cpu.acvFaults |= ACV15;
221 PNL (L68_ (cpu.apu.state |= apu_FLT;))
222 FMSG (acvFaultsMsg = "acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND";)
223 DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o",
224 cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
225 }
226
227 if (cpu.acvFaults) {
228 DBGAPP ("doAppendCycleRTCDOperandFetch(G) acvFaults\n");
229 PNL (L68_ (cpu.apu.state |= apu_FLT;))
230
231 doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault");
232 }
233
234
235 if (cpu.SDW->U)
236 goto H;
237
238
239
240
241 DBGAPP ("doAppendCycleRTCDOperandFetch(G) CA %06o\n", cpu.TPR.CA);
242 if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) {
243 fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA);
244 if (! cpu.PTW0.DF) {
245
246 doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0");
247 }
248 loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch);
249 }
250
251
252
253
254
255
256 if (i->opcodeX && ((i->opcode & 0770)== 0200|| (i->opcode & 0770) == 0220
257 || (i->opcode & 0770)== 020|| (i->opcode & 0770) == 0300)) {
258 do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA);
259 }
260 goto I;
261
262
263
264
265
266
267
268 H:;
269 DBGAPP ("doAppendCycleRTCDOperandFetch(H): FANP\n");
270
271 PNL (L68_ (cpu.apu.state |= apu_FANP;))
272
273
274
275
276
277
278
279 set_apu_status (cpup, apuStatus_FANP);
280
281 DBGAPP ("doAppendCycleRTCDOperandFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
282
283 if (get_addr_mode (cpup) == ABSOLUTE_mode && ! (cpu.cu.XSF || cpu.currentInstruction.b29)) {
284 finalAddress = cpu.TPR.CA;
285 } else {
286 finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
287 finalAddress &= 0xffffff;
288 }
289 PNL (cpu.APUMemAddr = finalAddress;)
290
291 DBGAPP ("doAppendCycleRTCDOperandFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
292
293 goto HI;
294
295 I:;
296
297
298
299 DBGAPP ("doAppendCycleRTCDOperandFetch(I): FAP\n");
300
301
302 set_apu_status (cpup, apuStatus_FAP);
303 PNL (L68_ (cpu.apu.state |= apu_FAP;))
304
305 word24 y2 = cpu.TPR.CA % 1024;
306
307
308
309 finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2;
310 finalAddress &= 0xffffff;
311 PNL (cpu.APUMemAddr = finalAddress;)
312
313 #if defined(L68)
314 if (cpu.MR_cache.emr && cpu.MR_cache.ihr)
315 add_APU_history (APUH_FAP);
316 #endif
317 DBGAPP ("doAppendCycleRTCDOperandFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
318
319 goto HI;
320
321 HI:
322 DBGAPP ("doAppendCycleRTCDOperandFetch(HI)\n");
323
324
325 cpu.cu.XSF = 1;
326 sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
327
328 core_readN (cpup, finalAddress, data, nWords, "RTCD_OPERAND_FETCH");
329
330 goto K;
331
332
333
334
335
336
337
338 K:;
339 DBGAPP ("doAppendCycleRTCDOperandFetch(K)\n");
340
341 word3 y = GET_ITS_RN (data);
342
343
344
345 cpu.TPR.TSR = GET_ITS_SEGNO (data);
346
347
348
349
350 cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1);
351
352
353
354 cpu.TPR.CA = GET_ITS_WORDNO (data);
355
356
357
358
359
360
361 DBGAPP ("doAppendCycleRTCDOperandFetch(KL)\n");
362
363
364 cpu.PPR.PSR = cpu.TPR.TSR;
365
366 cpu.PPR.IC = cpu.TPR.CA;
367
368 goto M;
369
370 M:
371 DBGAPP ("doAppendCycleRTCDOperandFetch(M)\n");
372
373
374 if (cpu.TPR.TRR == 0) {
375
376 cpu.PPR.P = cpu.SDW->P;
377 } else {
378
379 cpu.PPR.P = 0;
380 }
381
382
383
384 PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
385 PNL (cpu.APUDataBusAddr = finalAddress;)
386
387 PNL (L68_ (cpu.apu.state |= apu_FA;))
388
389 DBGAPP ("doAppendCycleRTCDOperandFetch (Exit) PRR %o PSR %05o P %o IC %06o\n",
390 cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
391 DBGAPP ("doAppendCycleRTCDOperandFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n",
392 cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
393
394 return finalAddress;
395 }