src/dps8/doAppendCycleOperandRead.h

/* */
This source file includes following definitions.
doAppendCycleOperandRead
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 3b4b8be2-171d-11ee-84fd-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2022-2023 Charles Anthony
   9  * Copyright (c) 2022-2023 Jeffrey H. Johnson
  10  * Copyright (c) 2022-2024 The DPS8M Development Team
  11  *
  12  * This software is made available under the terms of the ICU License.
  13  * See the LICENSE.md file at the top-level directory of this distribution.
  14  *
  15  * ---------------------------------------------------------------------------
  16  */
  17 
  18 //
  19 //        A:   fetch sdw
  20 //        B:   check RB consistency
  21 //        B1:  Is CALL6? Yes---------------------------------------+
  22 //               No                                                |
  23 //             Is transfer? Yes---------------+                E: Check RB
  24 //               No                           |                    |
  25 //             Check Read RB             F: Check Execute RB       |
  26 //                |                      D: Check RALR             |
  27 //                |                           |                    |
  28 //                +<--------------------------+<-------------------+
  29 //                |
  30 //                V
  31 //        G:   Check bound
  32 //             Paged? No----------------------+
  33 //               Yes                          |
  34 //             Fetch PTW                      |
  35 //        I:   Compute final address     H:   Compute Final Address
  36 //                |                           |
  37 //                +<--------------------------+
  38 //                |
  39 //                V
  40 //        HI:  Read operand
  41 //             CALL6? Yes--------------------------------------+
  42 //               No                                            |
  43 //             Transfer? Yes -----------------+                |
  44 //               No                           |                |
  45 //                |                           |                |
  46 //                |                      L:  Handle TSPn   N: Handle CALL6
  47 //                |                      KL: Set IC           Set IC
  48 //                |                           |                |
  49 //                |                           +<---------------+
  50 //                |                           |
  51 //                |                      M: Set P
  52 //                |                           |
  53 //                +<--------------------------+
  54 //                |
  55 //                V
  56 //              Exit
  57 
  58 word24 doAppendCycleOperandRead (cpu_state_t * cpup, word36 * data, uint nWords) {
     /*  */
  59 static int evcnt = 0;
  60   DCDstruct * i = & cpu.currentInstruction;
  61   (void)evcnt;
  62   DBGAPP ("doAppendCycleOperandRead(Entry) thisCycle=OPERAND_READ\n");
  63   DBGAPP ("doAppendCycleOperandRead(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle));
  64   DBGAPP ("doAppendCycleOperandRead(Entry) CA %06o\n", cpu.TPR.CA);
  65   DBGAPP ("doAppendCycleOperandRead(Entry) n=%2u\n", nWords);
  66   DBGAPP ("doAppendCycleOperandRead(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR);
  67   DBGAPP ("doAppendCycleOperandRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
  68 
  69   if (i->b29) {
  70     DBGAPP ("doAppendCycleOperandRead(Entry) isb29 PRNO %o\n", GET_PRN (IWB_IRODD));
  71   }
  72 
  73   uint this = UC_OPERAND_READ;
  74   if (i->info->flags & TRANSFER_INS)
  75     this = UC_OPERAND_READ_TRA;
  76   if (i->info->flags & CALL6_INS)
  77     this = UC_OPERAND_READ_CALL6;
  78 
  79   word24 finalAddress = 0;
  80   word24 pageAddress = 0;
  81   word3 RSDWH_R1 = 0;
  82   word14 bound = 0;
  83   word1 p = 0;
  84   bool paged;
  85 
  86 // Is this cycle a candidate for ucache?
  87 
  88 //#define TEST_UCACHE
  89 #if defined(TEST_UCACHE)
  90   bool cacheHit;
  91   cacheHit = false; // Assume skip...
  92 #endif /* if defined(TEST_UCACHE) */
  93 
  94 
  95   // Is OPCODE call6?
  96 
  97   // See E1; The TRR needs to be checked and set to R2; this will vary across different
  98   // CALL6 calls.
  99   if (i->info->flags & CALL6_INS) {
 100 # if defined(UCACHE_STATS)
 101     cpu.uCache.call6Skips ++;
 102 # endif /* if defined(UCACHE_STATS) */
 103     goto skip;
 104   }
 105 
 106 
 107 
 108 
 109 
 110 
 111 
 112 
 113 
 114 
 115   // Transfer?
 116   if (i->info->flags & TRANSFER_INS) {
 117     // check ring alarm to catch outbound transfers
 118     if (cpu.rRALR && (cpu.PPR.PRR >= cpu.rRALR)) {
 119 #if defined(UCACHE_STATS)
 120       cpu.uCache.ralrSkips ++;
 121 #endif /* if defined(UCACHE_STATS) */
 122       goto skip;
 123     }
 124   }
 125 
 126 // Yes; check the ucache
 127 
 128 #if defined(TEST_UCACHE)
 129   word24 cachedAddress;
 130   word3 cachedR1;
 131   word14 cachedBound;
 132   word1 cachedP;
 133   bool cachedPaged;
 134   cacheHit =
 135       ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged);
 136 # if defined(HDBG)
 137   hdbgNote ("doAppendCycleOperandRead.h", "test cache check %s %d %u %05o:%06o %05o %o %08o %o %o",
 138             cacheHit ? "hit" : "miss", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, cachedBound,
 139             cachedP, cachedAddress, cachedR1, cachedPaged);
 140 # endif /* if defined(HDBG) */
 141   goto miss;
 142 #else
 143   if (! ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) {
 144 # if defined(HDBG)
 145     hdbgNote ("doAppendCycleOperandRead.h", "miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
 146 # endif /* if defined(HDBG) */
 147     goto miss;
 148   }
 149 #endif /* if defined(TEST_UCACHE) */
 150 
 151   if (paged) {
 152     finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK);
 153   } else {
 154     finalAddress = pageAddress + cpu.TPR.CA;
 155   }
 156   cpu.RSDWH_R1 = RSDWH_R1;
 157 
 158 // ucache hit; housekeeping...
 159   //sim_printf ("hit  %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
 160 #if defined(HDBG)
 161   hdbgNote ("doAppendCycleOperandRead.h", "hit  %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
 162 #endif /* if defined(HDBG) */
 163 
 164   cpu.apu.lastCycle = OPERAND_READ;
 165   goto HI;
 166 
 167 
 168 skip:;
 169   //sim_printf ("miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
 170 # if defined(HDBG)
 171   hdbgNote ("doAppendCycleOperandRead.h", "skip %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
 172 # endif /* if defined(HDBG) */
 173 # if defined(UCACHE_STATS)
 174   cpu.uCache.skips[this] ++;
 175 # endif /* if defined(UCACHE_STATS) */
 176 
 177 
 178 miss:;
 179 
 180   bool nomatch = true;
 181   if (cpu.tweaks.enable_wam) {
 182     // AL39: The associative memory is ignored (forced to "no match") during
 183     // address preparation.
 184     // lptp,lptr,lsdp,lsdr,sptp,sptr,ssdp,ssdr
 185     // Unfortunately, ISOLTS doesn't try to execute any of these in append mode.
 186     // XXX should this be only for OPERAND_READ and OPERAND_STORE?
 187     nomatch = ((i->opcode == 0232 || i->opcode == 0254 ||
 188                 i->opcode == 0154 || i->opcode == 0173) &&
 189                 i->opcodeX ) ||
 190                ((i->opcode == 0557 || i->opcode == 0257) &&
 191                 ! i->opcodeX);
 192   }
 193 
 194   processor_cycle_type lastCycle = cpu.apu.lastCycle;
 195   cpu.apu.lastCycle = OPERAND_READ;
 196 
 197   DBGAPP ("doAppendCycleOperandRead(Entry) XSF %o\n", cpu.cu.XSF);
 198 
 199   PNL (L68_ (cpu.apu.state = 0;))
 200 
 201   cpu.RSDWH_R1 = 0;
 202 
 203   cpu.acvFaults = 0;
 204 
 205 //#define FMSG(x) x
 206 #define FMSG(x)
 207   FMSG (char * acvFaultsMsg = "<unknown>";)
 208 
 209 ////////////////////////////////////////
 210 //
 211 // Sheet 1: "START APPEND"
 212 //
 213 ////////////////////////////////////////
 214 
 215 // START APPEND
 216   word3 n = 0; // PRn to be saved to TSN_PRNO
 217 
 218 ////////////////////////////////////////
 219 //
 220 // Sheet 2: "A"
 221 //
 222 ////////////////////////////////////////
 223 
 224 //
 225 //  A:
 226 //    Get SDW
 227 
 228   //PNL (cpu.APUMemAddr = address;)
 229   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
 230 
 231   DBGAPP ("doAppendCycleOperandRead(A)\n");
 232 
 233   // is SDW for C(TPR.TSR) in SDWAM?
 234   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
 235     // No
 236     DBGAPP ("doAppendCycleOperandRead(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
 237     DBGAPP ("doAppendCycleOperandRead(A):DSBR.U=%o\n", cpu.DSBR.U);
 238 
 239     if (cpu.DSBR.U == 0) {
 240       fetch_dsptw (cpup, cpu.TPR.TSR);
 241 
 242       if (! cpu.PTW0.DF)
 243         doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleOperandRead(A): PTW0.F == 0");
 244 
 245       if (! cpu.PTW0.U)
 246         modify_dsptw (cpup, cpu.TPR.TSR);
 247 
 248       fetch_psdw (cpup, cpu.TPR.TSR);
 249     } else
 250       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
 251 
 252     if (cpu.SDW0.DF == 0) {
 253       DBGAPP ("doAppendCycleOperandRead(A): SDW0.F == 0! " "Initiating directed fault\n");
 254       // initiate a directed fault ...
 255       doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0");
 256     }
 257     // load SDWAM .....
 258     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
 259   }
 260   DBGAPP ("doAppendCycleOperandRead(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E);
 261 
 262   // Yes...
 263   RSDWH_R1 = cpu.RSDWH_R1 = cpu.SDW->R1;
 264 
 265 ////////////////////////////////////////
 266 //
 267 // Sheet 3: "B"
 268 //
 269 ////////////////////////////////////////
 270 
 271 //
 272 // B: Check the ring
 273 //
 274 
 275   DBGAPP ("doAppendCycleOperandRead(B)\n");
 276 
 277   // check ring bracket consistency
 278 
 279   //C(SDW.R1) <= C(SDW.R2) <= C(SDW .R3)?
 280   if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) {
 281     // Set fault ACV0 = IRO
 282     cpu.acvFaults |= ACV0;
 283     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 284     FMSG (acvFaultsMsg = "acvFaults(B) C(SDW.R1) <= C(SDW.R2) <= " "C(SDW .R3)";)
 285   }
 286 
 287   // lastCycle == RTCD_OPERAND_FETCH
 288   // if a fault happens between the RTCD_OPERAND_FETCH and the INSTRUCTION_FETCH
 289   // of the next instruction - this happens about 35 time for just booting  and
 290   // shutting down multics -- a stored lastCycle is useless.
 291   // the opcode is preserved across faults and only replaced as the
 292   // INSTRUCTION_FETCH succeeds.
 293   if (lastCycle == RTCD_OPERAND_FETCH)
 294     sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\n", __func__, i->opcode);
 295 
 296   //
 297   // B1: The operand is one of: an instruction, data to be read or data to be
 298   //     written
 299   //
 300 
 301   // Is OPCODE call6?
 302   if (i->info->flags & CALL6_INS)
 303     goto E;
 304 
 305   // Transfer
 306   if (i->info->flags & TRANSFER_INS)
 307     goto F;
 308 
 309   //
 310   // check read bracket for read access
 311   //
 312 
 313   DBGAPP ("doAppendCycleOperandRead(B):!STR-OP\n");
 314 
 315   // No
 316   // C(TPR.TRR) > C(SDW .R2)?
 317   if (cpu.TPR.TRR > cpu.SDW->R2) {
 318     DBGAPP ("ACV3\n");
 319     DBGAPP ("doAppendCycleOperandRead(B) ACV3\n");
 320     //Set fault ACV3 = ORB
 321     cpu.acvFaults |= ACV3;
 322     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 323     FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R2)";)
 324   }
 325 
 326   if (cpu.SDW->R == 0) {
 327     // isolts 870
 328     cpu.TPR.TRR = cpu.PPR.PRR;
 329 
 330     //C(PPR.PSR) = C(TPR.TSR)?
 331     if (cpu.PPR.PSR != cpu.TPR.TSR) {
 332       DBGAPP ("ACV4\n");
 333       DBGAPP ("doAppendCycleOperandRead(B) ACV4\n");
 334       //Set fault ACV4 = R-OFF
 335       cpu.acvFaults |= ACV4;
 336       PNL (L68_ (cpu.apu.state |= apu_FLT;))
 337       FMSG (acvFaultsMsg = "acvFaults(B) C(PPR.PSR) = C(TPR.TSR)";)
 338     //} else {
 339       // sim_warn ("doAppendCycleOperandRead(B) SDW->R == 0 && cpu.PPR.PSR == cpu.TPR.TSR: %0#o\n", cpu.PPR.PSR);
 340     }
 341   }
 342 
 343   goto G;
 344 
 345 ////////////////////////////////////////
 346 //
 347 // Sheet 4: "C" "D"
 348 //
 349 ////////////////////////////////////////
 350 
 351 D:;
 352   DBGAPP ("doAppendCycleOperandRead(D)\n");
 353 
 354   // transfer or instruction fetch
 355 
 356   // check ring alarm to catch outbound transfers
 357 
 358   if (cpu.rRALR == 0)
 359     goto G;
 360 
 361   // C(PPR.PRR) < RALR?
 362   if (! (cpu.PPR.PRR < cpu.rRALR)) {
 363     DBGAPP ("ACV13\n");
 364     DBGAPP ("acvFaults(D) C(PPR.PRR) %o < RALR %o\n", cpu.PPR.PRR, cpu.rRALR);
 365     cpu.acvFaults |= ACV13;
 366     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 367     FMSG (acvFaultsMsg = "acvFaults(D) C(PPR.PRR) < RALR";)
 368   }
 369 
 370   goto G;
 371 
 372 ////////////////////////////////////////
 373 //
 374 // Sheet 5: "E"
 375 //
 376 ////////////////////////////////////////
 377 
 378 E:;
 379 
 380   //
 381   // check ring bracket for instruction fetch after call6 instruction
 382   //   (this is the call6 read operand)
 383   //
 384 
 385   DBGAPP ("doAppendCycleOperandRead(E): CALL6\n");
 386   DBGAPP ("doAppendCycleOperandRead(E): E %o G %o PSR %05o TSR %05o CA %06o " "EB %06o R %o%o%o TRR %o PRR %o\n",
 387           cpu.SDW->E,  cpu.SDW->G,  cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu.SDW->EB,
 388           cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.TPR.TRR, cpu.PPR.PRR);
 389 
 390   //SDW.E set ON?
 391   if (! cpu.SDW->E) {
 392     DBGAPP ("ACV2 b\n");
 393     DBGAPP ("doAppendCycleOperandRead(E) ACV2\n");
 394     // Set fault ACV2 = E-OFF
 395     cpu.acvFaults |= ACV2;
 396     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 397     FMSG (acvFaultsMsg = "acvFaults(E) SDW .E set OFF";)
 398   }
 399 
 400   //SDW .G set ON?
 401   if (cpu.SDW->G)
 402     goto E1;
 403 
 404   // C(PPR.PSR) = C(TPR.TSR)?
 405   if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS)
 406     goto E1;
 407 
 408   // XXX This doesn't seem right
 409   // EB is word 15; masking address makes no sense; rather 0-extend EB
 410   // Fixes ISOLTS 880-01
 411   if (cpu.TPR.CA >= (word18) cpu.SDW->EB) {
 412     DBGAPP ("ACV7\n");
 413     DBGAPP ("doAppendCycleOperandRead(E) ACV7\n");
 414     // Set fault ACV7 = NO GA
 415     cpu.acvFaults |= ACV7;
 416     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 417     FMSG (acvFaultsMsg = "acvFaults(E) TPR.CA4-17 >= SDW.CL";)
 418   }
 419 
 420 E1:
 421   DBGAPP ("doAppendCycleOperandRead(E1): CALL6 (cont'd)\n");
 422 
 423   // C(TPR.TRR) > SDW.R3?
 424   if (cpu.TPR.TRR > cpu.SDW->R3) {
 425     DBGAPP ("ACV8\n");
 426     DBGAPP ("doAppendCycleOperandRead(E) ACV8\n");
 427     //Set fault ACV8 = OCB
 428     cpu.acvFaults |= ACV8;
 429     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 430     FMSG (acvFaultsMsg = "acvFaults(E1) C(TPR.TRR) > SDW.R3";)
 431   }
 432 
 433   // C(TPR.TRR) < SDW.R1?
 434   if (cpu.TPR.TRR < cpu.SDW->R1) {
 435     DBGAPP ("ACV9\n");
 436     DBGAPP ("doAppendCycleOperandRead(E) ACV9\n");
 437     // Set fault ACV9 = OCALL
 438     cpu.acvFaults |= ACV9;
 439     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 440     FMSG (acvFaultsMsg = "acvFaults(E1) C(TPR.TRR) < SDW.R1";)
 441   }
 442 
 443   // C(TPR.TRR) > C(PPR.PRR)?
 444   if (cpu.TPR.TRR > cpu.PPR.PRR) {
 445     // C(PPR.PRR) < SDW.R2?
 446     if (cpu.PPR.PRR < cpu.SDW->R2) {
 447       DBGAPP ("ACV10\n");
 448       DBGAPP ("doAppendCycleOperandRead(E) ACV10\n");
 449       // Set fault ACV10 = BOC
 450       cpu.acvFaults |= ACV10;
 451       PNL (L68_ (cpu.apu.state |= apu_FLT;))
 452       FMSG (acvFaultsMsg = "acvFaults(E1) C(TPR.TRR) > C(PPR.PRR) && " "C(PPR.PRR) < SDW.R2";)
 453     }
 454   }
 455 
 456   DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o SDW->R2 %o\n", cpu.TPR.TRR, cpu.SDW->R2);
 457 
 458   // C(TPR.TRR) > SDW.R2?
 459   if (cpu.TPR.TRR > cpu.SDW->R2) {
 460     // SDW.R2 -> C(TPR.TRR)
 461     cpu.TPR.TRR = cpu.SDW->R2;
 462   }
 463 
 464   DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o\n", cpu.TPR.TRR);
 465 
 466   goto G;
 467 
 468 ////////////////////////////////////////
 469 //
 470 // Sheet 6: "F"
 471 //
 472 ////////////////////////////////////////
 473 
 474 F:;
 475   PNL (L68_ (cpu.apu.state |= apu_PIAU;))
 476   DBGAPP ("doAppendCycleOperandRead(F): transfer or instruction fetch\n");
 477 
 478   //
 479   // check ring bracket for instruction fetch
 480   //
 481 
 482   // C(TPR.TRR) < C(SDW .R1)?
 483   // C(TPR.TRR) > C(SDW .R2)?
 484   if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) {
 485     DBGAPP ("ACV1 a/b\n");
 486     DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2);
 487     cpu.acvFaults |= ACV1;
 488     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 489     FMSG (acvFaultsMsg = "acvFaults(F) C(TPR.TRR) < C(SDW .R1)";)
 490   }
 491   // SDW .E set ON?
 492   if (! cpu.SDW->E) {
 493     DBGAPP ("ACV2 c \n");
 494     DBGAPP ("doAppendCycleOperandRead(F) ACV2\n");
 495     cpu.acvFaults |= ACV2;
 496     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 497     FMSG (acvFaultsMsg = "acvFaults(F) SDW .E set OFF";)
 498   }
 499 
 500   // C(PPR.PRR) = C(TPR.TRR)?
 501   if (cpu.PPR.PRR != cpu.TPR.TRR) {
 502     DBGAPP ("ACV12\n");
 503     DBGAPP ("doAppendCycleOperandRead(F) ACV12\n");
 504     //Set fault ACV12 = CRT
 505     cpu.acvFaults |= ACV12;
 506     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 507     FMSG (acvFaultsMsg = "acvFaults(F) C(PPR.PRR) != C(TPR.TRR)";)
 508   }
 509 
 510   goto D;
 511 
 512 ////////////////////////////////////////
 513 //
 514 // Sheet 7: "G"
 515 //
 516 ////////////////////////////////////////
 517 
 518 G:;
 519 
 520   DBGAPP ("doAppendCycleOperandRead(G)\n");
 521 
 522   //C(TPR.CA)0,13 > SDW.BOUND?
 523   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
 524     DBGAPP ("ACV15\n");
 525     DBGAPP ("doAppendCycleOperandRead(G) ACV15\n");
 526     cpu.acvFaults |= ACV15;
 527     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 528     FMSG (acvFaultsMsg = "acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND";)
 529     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o",
 530             cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
 531   }
 532   bound = cpu.SDW->BOUND;
 533   p = cpu.SDW->P;
 534 
 535   if (cpu.acvFaults) {
 536     DBGAPP ("doAppendCycleOperandRead(G) acvFaults\n");
 537     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 538     // Initiate an access violation fault
 539     doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults},
 540             "ACV fault");
 541   }
 542 
 543   // is segment C(TPR.TSR) paged?
 544   if (cpu.SDW->U)
 545     goto H; // Not paged
 546 
 547   // Yes. segment is paged ...
 548   // is PTW for C(TPR.CA) in PTWAM?
 549 
 550   DBGAPP ("doAppendCycleOperandRead(G) CA %06o\n", cpu.TPR.CA);
 551   if (nomatch ||
 552       ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) {
 553     fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA);
 554     if (! cpu.PTW0.DF) {
 555       // initiate a directed fault
 556       doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0},
 557               "PTW0.F == 0");
 558     }
 559     loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
 560   }
 561 
 562   // Prepage mode?
 563   // check for "uninterruptible" EIS instruction
 564   // ISOLTS-878 02: mvn,cmpn,mvne,ad3d; obviously also
 565   // ad2/3d,sb2/3d,mp2/3d,dv2/3d
 566   // DH03 p.8-13: probably also mve,btd,dtb
 567   if (i->opcodeX && ((i->opcode & 0770)== 0200|| (i->opcode & 0770) == 0220
 568       || (i->opcode & 0770)== 020|| (i->opcode & 0770) == 0300)) {
 569     do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA);
 570   }
 571   goto I;
 572 
 573 ////////////////////////////////////////
 574 //
 575 // Sheet 8: "H", "I"
 576 //
 577 ////////////////////////////////////////
 578 
 579 H:;
 580   DBGAPP ("doAppendCycleOperandRead(H): FANP\n");
 581 
 582   paged = false;
 583 
 584   PNL (L68_ (cpu.apu.state |= apu_FANP;))
 585 
 586 
 587 
 588 
 589 
 590 
 591 
 592   set_apu_status (cpup, apuStatus_FANP);
 593 #if defined(HDBG)
 594   hdbgNote ("doAppendCycleOperandRead", "FANP");
 595 #endif /* if defined(HDBG) */
 596   DBGAPP ("doAppendCycleOperandRead(H): SDW->ADDR=%08o CA=%06o \n",
 597           cpu.SDW->ADDR, cpu.TPR.CA);
 598 
 599   pageAddress = (cpu.SDW->ADDR & 077777760);
 600   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
 601   finalAddress &= 0xffffff;
 602   PNL (cpu.APUMemAddr = finalAddress;)
 603 
 604   DBGAPP ("doAppendCycleOperandRead(H:FANP): (%05o:%06o) finalAddress=%08o\n",
 605           cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 606 
 607   goto HI;
 608 
 609 I:;
 610 
 611 // Set PTW.M
 612 
 613   DBGAPP ("doAppendCycleOperandRead(I): FAP\n");
 614 
 615   paged = true;
 616 
 617 #if defined(HDBG)
 618   hdbgNote ("doAppendCycleOperandRead", "FAP");
 619 #endif /* if defined(HDBG) */
 620   // final address paged
 621   set_apu_status (cpup, apuStatus_FAP);
 622   PNL (L68_ (cpu.apu.state |= apu_FAP;))
 623 
 624   word24 y2 = cpu.TPR.CA % 1024;
 625 
 626   pageAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6);
 627   // AL39: The hardware ignores low order bits of the main memory page
 628   // address according to page size
 629   finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2;
 630   finalAddress &= 0xffffff;
 631   PNL (cpu.APUMemAddr = finalAddress;)
 632 
 633 #if defined(L68)
 634   if (cpu.MR_cache.emr && cpu.MR_cache.ihr)
 635     add_APU_history (APUH_FAP);
 636 #endif /* if defined(L68) */
 637   DBGAPP ("doAppendCycleOperandRead(H:FAP): (%05o:%06o) finalAddress=%08o\n",
 638           cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 639 
 640   //goto HI;
 641 
 642 HI:
 643   DBGAPP ("doAppendCycleOperandRead(HI)\n");
 644 
 645 #if defined(TEST_UCACHE)
 646   if (cacheHit) {
 647     bool err = false;
 648     if (cachedAddress != pageAddress) {
 649      sim_printf ("cachedAddress %08o != pageAddress %08o\r\n",
 650              cachedAddress, pageAddress);
 651      err = true;
 652     }
 653     if (cachedR1 != RSDWH_R1) {
 654       sim_printf ("cachedR1 %01o != RSDWH_R1 %01o\r\n",
 655               cachedR1, RSDWH_R1);
 656       err = true;
 657     }
 658     if (cachedBound != bound) {
 659       sim_printf ("cachedBound %01o != bound %01o\r\n",
 660               cachedBound, bound);
 661       err = true;
 662     }
 663     if (cachedPaged != paged) {
 664       sim_printf ("cachedPaged %01o != paged %01o\r\n",
 665               cachedPaged, paged);
 666       err = true;
 667     }
 668     if (err) {
 669 # if defined(HDBG)
 670       HDBGPrint ();
 671 # endif /* if defined(HDBG) */
 672       sim_printf ("oprnd read err  %d %05o:%06o\r\n",
 673               evcnt, cpu.TPR.TSR, cpu.TPR.CA);
 674       exit (1);
 675     }
 676     //sim_printf ("hit  %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
 677 # if defined(HDBG)
 678     hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n",
 679             evcnt, cpu.TPR.TSR, cpu.TPR.CA);
 680 # endif /* if defined(HDBG) */
 681   } else {
 682     //sim_printf ("miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
 683 # if defined(HDBG)
 684     hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n",
 685             evcnt, cpu.TPR.TSR, cpu.TPR.CA);
 686 # endif /* if defined(HDBG) */
 687   }
 688 #endif
 689 
 690   ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged);
 691 #if defined(TEST_UCACHE)
 692 # if defined(HDBG)
 693   hdbgNote ("doAppendCycleOperandRead.h", "cache %d %u %05o:%06o %05o %o %08o %o %o",
 694           evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged);
 695 # endif /* if defined(HDBG) */
 696 #endif /* if defined(TEST_UCACHE) */
 697 evcnt ++;
 698 
 699   // isolts 870
 700   cpu.cu.XSF = 1;
 701   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
 702 
 703   core_readN (cpup, finalAddress, data, nWords, "OPERAND_READ");
 704 
 705   if (i->info->flags & CALL6_INS)
 706     goto N;
 707 
 708   // Transfer or instruction fetch?
 709   if (i->info->flags & TRANSFER_INS)
 710     goto L;
 711 
 712   // APU data movement?
 713   //  handled above
 714   goto Exit;
 715 
 716 ////////////////////////////////////////
 717 //
 718 // Sheet 10: "K", "L", "M", "N"
 719 //
 720 ////////////////////////////////////////
 721 
 722 L:; // Transfer or instruction fetch
 723 
 724   DBGAPP ("doAppendCycleOperandRead(L)\n");
 725 
 726   // Is OPCODE tspn?
 727   if (i->info->flags & TSPN_INS) {
 728     if (i->opcode <= 0273)
 729       n = (i->opcode & 3);
 730     else
 731       n = (i->opcode & 3) + 4;
 732 
 733     // C(PPR.PRR) -> C(PRn .RNR)
 734     // C(PPR.PSR) -> C(PRn .SNR)
 735     // C(PPR.IC) -> C(PRn .WORDNO)
 736     // 000000 -> C(PRn .BITNO)
 737     cpu.PR[n].RNR = cpu.PPR.PRR;
 738 // According the AL39, the PSR is 'undefined' in absolute mode.
 739 // ISOLTS thinks means don't change the operand
 740     if (get_addr_mode (cpup) == APPEND_mode)
 741       cpu.PR[n].SNR = cpu.PPR.PSR;
 742     cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18;
 743     SET_PR_BITNO (n, 0);
 744 #if defined(TESTING)
 745     HDBGRegPRW (n, "app tspn");
 746 #endif /* if defined(TESTING) */
 747   }
 748 
 749 // KL:
 750   DBGAPP ("doAppendCycleOperandRead(KL)\n");
 751 
 752   // C(TPR.TSR) -> C(PPR.PSR)
 753   cpu.PPR.PSR = cpu.TPR.TSR;
 754   // C(TPR.CA) -> C(PPR.IC)
 755   cpu.PPR.IC = cpu.TPR.CA;
 756 
 757   //goto M;
 758 
 759 M: // Set P
 760   DBGAPP ("doAppendCycleOperandRead(M)\n");
 761 
 762   // C(TPR.TRR) = 0?
 763   if (cpu.TPR.TRR == 0) {
 764     // C(SDW.P) -> C(PPR.P)
 765     cpu.PPR.P = p;
 766   } else {
 767     // 0 C(PPR.P)
 768     cpu.PPR.P = 0;
 769   }
 770 
 771   goto Exit;
 772 
 773 N: // CALL6
 774   DBGAPP ("doAppendCycleOperandRead(N)\n");
 775 
 776   // C(TPR.TRR) = C(PPR.PRR)?
 777   if (cpu.TPR.TRR == cpu.PPR.PRR) {
 778     // C(PR6.SNR) -> C(PR7.SNR)
 779     cpu.PR[7].SNR = cpu.PR[6].SNR;
 780     DBGAPP ("doAppendCycleOperandRead(N) PR7.SNR = PR6.SNR %05o\n", cpu.PR[7].SNR);
 781   } else {
 782     // C(DSBR.STACK) || C(TPR.TRR) -> C(PR7.SNR)
 783     cpu.PR[7].SNR = ((word15) (cpu.DSBR.STACK << 3)) | cpu.TPR.TRR;
 784     DBGAPP ("doAppendCycleOperandRead(N) STACK %05o TRR %o\n", cpu.DSBR.STACK, cpu.TPR.TRR);
 785     DBGAPP ("doAppendCycleOperandRead(N) PR7.SNR = STACK||TRR  %05o\n", cpu.PR[7].SNR);
 786   }
 787 
 788   // C(TPR.TRR) -> C(PR7.RNR)
 789   cpu.PR[7].RNR = cpu.TPR.TRR;
 790   // 00...0 -> C(PR7.WORDNO)
 791   cpu.PR[7].WORDNO = 0;
 792   // 000000 -> C(PR7.BITNO)
 793   SET_PR_BITNO (7, 0);
 794 #if defined(TESTING)
 795   HDBGRegPRW (7, "app call6");
 796 #endif /* if defined(TESTING) */
 797   // C(TPR.TRR) -> C(PPR.PRR)
 798   cpu.PPR.PRR = cpu.TPR.TRR;
 799   // C(TPR.TSR) -> C(PPR.PSR)
 800   cpu.PPR.PSR = cpu.TPR.TSR;
 801   // C(TPR.CA) -> C(PPR.IC)
 802   cpu.PPR.IC = cpu.TPR.CA;
 803 
 804   goto M;
 805 
 806 Exit:;
 807 
 808   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
 809   PNL (cpu.APUDataBusAddr = finalAddress;)
 810 
 811   PNL (L68_ (cpu.apu.state |= apu_FA;))
 812 
 813   DBGAPP ("doAppendCycleOperandRead (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
 814   DBGAPP ("doAppendCycleOperandRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
 815 
 816   return finalAddress;    // or 0 or -1???
 817 }
 818 #undef TEST_UCACHE
/* */
root/src/dps8/doAppendCycleOperandRead.h

INCLUDED FROM

DEFINITIONS
