src/dps8/doAppendCycleIndirectWordFetch.h

/* */
This source file includes following definitions.
doAppendCycleIndirectWordFetch
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 501f8fe6-171d-11ee-ab15-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2022-2023 Charles Anthony
   9  * Copyright (c) 2022-2023 Jeffrey H. Johnson
  10  * Copyright (c) 2022-2024 The DPS8M Development Team
  11  *
  12  * This software is made available under the terms of the ICU License.
  13  * See the LICENSE.md file at the top-level directory of this distribution.
  14  *
  15  * ---------------------------------------------------------------------------
  16  */
  17 
  18 //  Indirect word fetch
  19 //
  20 //     A: Get SDW
  21 //         |
  22 //         V
  23 //     B: Check the ring
  24 //         |
  25 //         V
  26 //     G: Check BOUND
  27 //        Paged? No-------------------+
  28 //          Yes                       |
  29 //           |                        |
  30 //           V                        |
  31 //        Get PTW                     |
  32 //           |                        |
  33 //           V                        V
  34 //     I: Compute final address   H: Compute final address
  35 //           |                        |
  36 //           <------------------------+
  37 //           |
  38 //           V
  39 //     HI: Read data
  40 //           |
  41 //           V
  42 //     J: ITS? Yes------------------+
  43 //        ITP? Yes----+             |
  44 //          |         |             |
  45 //          |         V             V
  46 //          |       P: ITP        O: ITS
  47 //          |       Update TRR     Update TRR
  48 //          |         |             |
  49 //          +<--------+-------------+
  50 //          |
  51 //          V
  52 //        Exit: return final address
  53 
  54 word24 doAppendCycleIndirectWordFetch (cpu_state_t * cpup, word36 * data, uint nWords) {
     /*  */
  55   DCDstruct * i = & cpu.currentInstruction;
  56   DBGAPP ("doAppendCycleIndirectWordFetch(Entry) thisCycle=INDIRECT_WORD_FETCH\n");
  57   DBGAPP ("doAppendCycleIndirectWordFetch(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle));
  58   DBGAPP ("doAppendCycleIndirectWordFetch(Entry) CA %06o\n", cpu.TPR.CA);
  59   DBGAPP ("doAppendCycleIndirectWordFetch(Entry) n=%2u\n", nWords);
  60   DBGAPP ("doAppendCycleIndirectWordFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR);
  61   DBGAPP ("doAppendCycleIndirectWordFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
  62 
  63   if (i->b29) {
  64     DBGAPP ("doAppendCycleIndirectWordFetch(Entry) isb29 PRNO %o\n", GET_PRN (IWB_IRODD));
  65   }
  66 
  67   uint this = UC_INDIRECT_WORD_FETCH;
  68 
  69   word24 finalAddress = 0;
  70   word24 pageAddress = 0;
  71   word3 RSDWH_R1 = 0;
  72   word14 bound = 0;
  73   word1 p = 0;
  74   bool paged = false;
  75 
  76 /* Indirect Word Fetch Cache disabled (due to it not working!) */
  77 #undef IDWF_CACHE
  78 //# define IDWF_CACHE 1
  79 #if defined(IDWF_CACHE)
  80 // Is this cycle a candidate for ucache?
  81 
  82   // Prepage mode?
  83   // check for "uninterruptible" EIS instruction
  84   // ISOLTS-878 02: mvn,cmpn,mvne,ad3d; obviously also
  85   // ad2/3d,sb2/3d,mp2/3d,dv2/3d
  86   // DH03 p.8-13: probably also mve,btd,dtb
  87   if (i->opcodeX && ((i->opcode & 0770)== 0200|| (i->opcode & 0770) == 0220
  88       || (i->opcode & 0770)== 020|| (i->opcode & 0770) == 0300)) {
  89     //sim_printf ("skip uninterruptible\r\n");
  90     goto skip_ucache;
  91   }
  92 
  93 // Yes; check the ucache
  94   if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged))
  95     goto miss_ucache;
  96 
  97   if (paged) {
  98     finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK);
  99   } else {
 100     finalAddress = pageAddress + cpu.TPR.CA;
 101   }
 102   cpu.RSDWH_R1 = RSDWH_R1;
 103 
 104   cpu.apu.lastCycle = INDIRECT_WORD_FETCH;
 105   goto HI;
 106 
 107 skip_ucache:;
 108 # if defined(UCACHE_STATS)
 109   cpu.uCache.skips[this] ++;
 110 # endif
 111 
 112 miss_ucache:;
 113 
 114 #endif /* if defined(IDWF_CACHE) */
 115 
 116   bool nomatch = true;
 117   if (cpu.tweaks.enable_wam) {
 118     // AL39: The associative memory is ignored (forced to "no match") during
 119     // address preparation.
 120     // lptp,lptr,lsdp,lsdr,sptp,sptr,ssdp,ssdr
 121     // Unfortunately, ISOLTS doesn't try to execute any of these in append mode.
 122     // XXX should this be only for OPERAND_READ and OPERAND_STORE?
 123     nomatch = ((i->opcode == 0232 || i->opcode == 0254 ||
 124                 i->opcode == 0154 || i->opcode == 0173) &&
 125                 i->opcodeX ) ||
 126                ((i->opcode == 0557 || i->opcode == 0257) &&
 127                 ! i->opcodeX);
 128   }
 129 
 130   processor_cycle_type lastCycle = cpu.apu.lastCycle;
 131   cpu.apu.lastCycle = INDIRECT_WORD_FETCH;
 132 
 133   DBGAPP ("doAppendCycleIndirectWordFetch(Entry) XSF %o\n", cpu.cu.XSF);
 134 
 135   PNL (L68_ (cpu.apu.state = 0;))
 136 
 137   cpu.RSDWH_R1 = 0;
 138 
 139   cpu.acvFaults = 0;
 140 
 141 //#define FMSG(x) x
 142 #define FMSG(x)
 143   FMSG (char * acvFaultsMsg = "<unknown>";)
 144 
 145 ////////////////////////////////////////
 146 //
 147 // Sheet 1: "START APPEND"
 148 //
 149 ////////////////////////////////////////
 150 
 151 // START APPEND
 152   word3 n = 0; // PRn to be saved to TSN_PRNO
 153 
 154 ////////////////////////////////////////
 155 //
 156 // Sheet 2: "A"
 157 //
 158 ////////////////////////////////////////
 159 
 160 //
 161 //  A:
 162 //    Get SDW
 163 
 164   //PNL (cpu.APUMemAddr = address;)
 165   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
 166 
 167   DBGAPP ("doAppendCycleIndirectWordFetch(A)\n");
 168 
 169   // is SDW for C(TPR.TSR) in SDWAM?
 170   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
 171     // No
 172     DBGAPP ("doAppendCycleIndirectWordFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
 173     DBGAPP ("doAppendCycleIndirectWordFetch(A):DSBR.U=%o\n", cpu.DSBR.U);
 174 
 175     if (cpu.DSBR.U == 0) {
 176       fetch_dsptw (cpup, cpu.TPR.TSR);
 177 
 178       if (! cpu.PTW0.DF)
 179         doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleIndirectWordFetch(A): PTW0.F == 0");
 180 
 181       if (! cpu.PTW0.U)
 182           modify_dsptw (cpup, cpu.TPR.TSR);
 183 
 184       fetch_psdw (cpup, cpu.TPR.TSR);
 185     } else
 186       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
 187 
 188     if (cpu.SDW0.DF == 0) {
 189       DBGAPP ("doAppendCycleIndirectWordFetch(A): SDW0.F == 0! " "Initiating directed fault\n");
 190       // initiate a directed fault ...
 191       doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0");
 192     }
 193     // load SDWAM .....
 194     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
 195   }
 196   DBGAPP ("doAppendCycleIndirectWordFetch(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E);
 197 
 198   // Yes...
 199   RSDWH_R1 = cpu.RSDWH_R1 = cpu.SDW->R1;
 200 
 201 ////////////////////////////////////////
 202 //
 203 // Sheet 3: "B"
 204 //
 205 ////////////////////////////////////////
 206 
 207 //
 208 // B: Check the ring
 209 //
 210 
 211   DBGAPP ("doAppendCycleIndirectWordFetch(B)\n");
 212 
 213   // check ring bracket consistency
 214 
 215   //C(SDW.R1) <= C(SDW.R2) <= C(SDW .R3)?
 216   if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) {
 217     // Set fault ACV0 = IRO
 218     cpu.acvFaults |= ACV0;
 219     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 220     FMSG (acvFaultsMsg = "acvFaults(B) C(SDW.R1) <= C(SDW.R2) <= " "C(SDW .R3)";)
 221   }
 222 
 223   // lastCycle == RTCD_OPERAND_FETCH
 224   // if a fault happens between the RTCD_OPERAND_FETCH and the INSTRUCTION_FETCH
 225   // of the next instruction - this happens about 35 time for just booting  and
 226   // shutting down multics -- a stored lastCycle is useless.
 227   // the opcode is preserved across faults and only replaced as the
 228   // INSTRUCTION_FETCH succeeds.
 229   if (lastCycle == RTCD_OPERAND_FETCH)
 230     sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\n", __func__, i->opcode);
 231 
 232   //
 233   // B1: The operand is one of: an instruction, data to be read or data to be
 234   //     written
 235   //
 236 
 237   //
 238   // check read bracket for read access
 239   //
 240 
 241   DBGAPP ("doAppendCycleIndirectWordFetch(B):!STR-OP\n");
 242 
 243   // No
 244   // C(TPR.TRR) > C(SDW .R2)?
 245   if (cpu.TPR.TRR > cpu.SDW->R2) {
 246     DBGAPP ("ACV3\n");
 247     DBGAPP ("doAppendCycleIndirectWordFetch(B) ACV3\n");
 248     //Set fault ACV3 = ORB
 249     cpu.acvFaults |= ACV3;
 250     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 251     FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R2)";)
 252   }
 253 
 254   if (cpu.SDW->R == 0) {
 255     // isolts 870
 256     cpu.TPR.TRR = cpu.PPR.PRR;
 257 
 258     //C(PPR.PSR) = C(TPR.TSR)?
 259     if (cpu.PPR.PSR != cpu.TPR.TSR) {
 260       DBGAPP ("ACV4\n");
 261       DBGAPP ("doAppendCycleIndirectWordFetch(B) ACV4\n");
 262       //Set fault ACV4 = R-OFF
 263       cpu.acvFaults |= ACV4;
 264       PNL (L68_ (cpu.apu.state |= apu_FLT;))
 265       FMSG (acvFaultsMsg = "acvFaults(B) C(PPR.PSR) = C(TPR.TSR)";)
 266     //} else {
 267       // sim_warn ("doAppendCycleIndirectWordFetch(B) SDW->R == 0 && cpu.PPR.PSR == cpu.TPR.TSR: %0#o\n",
 268       //           cpu.PPR.PSR);
 269     }
 270   }
 271 
 272 //  goto G;
 273 
 274 ////////////////////////////////////////
 275 //
 276 // Sheet 7: "G"
 277 //
 278 ////////////////////////////////////////
 279 
 280 //G:;
 281 
 282   DBGAPP ("doAppendCycleIndirectWordFetch(G)\n");
 283 
 284   //C(TPR.CA)0,13 > SDW.BOUND?
 285   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
 286     DBGAPP ("ACV15\n");
 287     DBGAPP ("doAppendCycleIndirectWordFetch(G) ACV15\n");
 288     cpu.acvFaults |= ACV15;
 289     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 290     FMSG (acvFaultsMsg = "acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND";)
 291     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o",
 292             cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
 293   }
 294   bound = cpu.SDW->BOUND;
 295   p = cpu.SDW->P;
 296 
 297   if (cpu.acvFaults) {
 298     DBGAPP ("doAppendCycleIndirectWordFetch(G) acvFaults\n");
 299     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 300     // Initiate an access violation fault
 301     doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault");
 302   }
 303 
 304   // is segment C(TPR.TSR) paged?
 305   if (cpu.SDW->U)
 306     goto H; // Not paged
 307 
 308   // Yes. segment is paged ...
 309   // is PTW for C(TPR.CA) in PTWAM?
 310 
 311   DBGAPP ("doAppendCycleIndirectWordFetch(G) CA %06o\n", cpu.TPR.CA);
 312   if (nomatch ||
 313       ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) {
 314     fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA);
 315     if (! cpu.PTW0.DF) {
 316       // initiate a directed fault
 317       doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0");
 318     }
 319     loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
 320   }
 321 
 322   // Prepage mode?
 323   // check for "uninterruptible" EIS instruction
 324   // ISOLTS-878 02: mvn,cmpn,mvne,ad3d; obviously also
 325   // ad2/3d,sb2/3d,mp2/3d,dv2/3d
 326   // DH03 p.8-13: probably also mve,btd,dtb
 327   if (i->opcodeX && ((i->opcode & 0770)== 0200|| (i->opcode & 0770) == 0220
 328       || (i->opcode & 0770)== 020|| (i->opcode & 0770) == 0300)) {
 329     do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA);
 330   }
 331   goto I;
 332 
 333 ////////////////////////////////////////
 334 //
 335 // Sheet 8: "H", "I"
 336 //
 337 ////////////////////////////////////////
 338 
 339 H:;
 340   DBGAPP ("doAppendCycleIndirectWordFetch(H): FANP\n");
 341 
 342   paged = false;
 343 
 344   PNL (L68_ (cpu.apu.state |= apu_FANP;))
 345 
 346 
 347 
 348 
 349 
 350 
 351 
 352 
 353   set_apu_status (cpup, apuStatus_FANP);
 354 
 355   DBGAPP ("doAppendCycleIndirectWordFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
 356 
 357   pageAddress = (cpu.SDW->ADDR & 077777760);
 358   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
 359   finalAddress &= 0xffffff;
 360   PNL (cpu.APUMemAddr = finalAddress;)
 361 
 362   DBGAPP ("doAppendCycleIndirectWordFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 363 
 364   goto HI;
 365 
 366 I:;
 367 
 368 // Set PTW.M
 369 
 370   DBGAPP ("doAppendCycleIndirectWordFetch(I): FAP\n");
 371 
 372   paged = true;
 373 
 374   // final address paged
 375   set_apu_status (cpup, apuStatus_FAP);
 376   PNL (L68_ (cpu.apu.state |= apu_FAP;))
 377 
 378   word24 y2 = cpu.TPR.CA % 1024;
 379 
 380   pageAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6);
 381   // AL39: The hardware ignores low order bits of the main memory page
 382   // address according to page size
 383   finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2;
 384   finalAddress &= 0xffffff;
 385   PNL (cpu.APUMemAddr = finalAddress;)
 386 
 387 #if defined(L68)
 388   if (cpu.MR_cache.emr && cpu.MR_cache.ihr)
 389     add_APU_history (APUH_FAP);
 390 #endif /* if defined(L68) */
 391   DBGAPP ("doAppendCycleIndirectWordFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 392 
 393   // goto HI;
 394 
 395 HI:
 396   DBGAPP ("doAppendCycleIndirectWordFetch(HI)\n");
 397 
 398   ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged);
 399 
 400   // isolts 870
 401   cpu.cu.XSF = 1;
 402   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
 403 
 404   core_readN (cpup, finalAddress, data, nWords, "INDIRECT_WORD_FETCH");
 405 
 406 ////////////////////////////////////////
 407 //
 408 // Sheet 9: "J"
 409 //
 410 ////////////////////////////////////////
 411 
 412 // Indirect operand fetch
 413 
 414   DBGAPP ("doAppendCycleIndirectWordFetch(J)\n");
 415 
 416   // ri or ir & TPC.CA even?
 417   word6 tag = GET_TAG (IWB_IRODD);
 418   if ((GET_TM (tag) == TM_IR || GET_TM (tag) == TM_RI) && (cpu.TPR.CA & 1) == 0) {
 419     if (ISITS (* data))
 420       goto O;
 421     if (ISITP (* data))
 422       goto P;
 423   }
 424 
 425   goto Exit;
 426 
 427 ////////////////////////////////////////
 428 //
 429 // Sheet 11: "O", "P"
 430 //
 431 ////////////////////////////////////////
 432 
 433 O:; // ITS, RTCD
 434   DBGAPP ("doAppendCycleIndirectWordFetch(O)\n");
 435   word3 its_RNR = GET_ITS_RN (data);
 436   DBGAPP ("doAppendCycleIndirectWordFetch(O) TRR %o RSDWH.R1 %o ITS.RNR %o\n",
 437           cpu.TPR.TRR, cpu.RSDWH_R1, its_RNR);
 438 
 439   // Maximum of
 440   //  C(Y)18,20;  C(TPR.TRR); C(SDW.R1) -> C(TPR.TRR)
 441   cpu.TPR.TRR = max3 (its_RNR, cpu.TPR.TRR, cpu.RSDWH_R1);
 442   DBGAPP ("doAppendCycleIndirectWordFetch(O) Set TRR to %o\n", cpu.TPR.TRR);
 443 
 444   goto Exit;
 445 
 446 P:; // ITP
 447 
 448   DBGAPP ("doAppendCycleIndirectWordFetch(P)\n");
 449 
 450   n = GET_ITP_PRNUM (data);
 451   DBGAPP ("doAppendCycleIndirectWordFetch(P) TRR %o RSDWH.R1 %o PR[n].RNR %o\n",
 452           cpu.TPR.TRR, cpu.RSDWH_R1, cpu.PR[n].RNR);
 453 
 454   // Maximum of
 455   // cpu.PR[n].RNR;  C(TPR.TRR); C(SDW.R1) -> C(TPR.TRR)
 456   cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.TPR.TRR, cpu.RSDWH_R1);
 457   DBGAPP ("doAppendCycleIndirectWordFetch(P) Set TRR to %o\n", cpu.TPR.TRR);
 458 
 459   goto Exit;
 460 
 461 Exit:;
 462 
 463   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
 464   PNL (cpu.APUDataBusAddr = finalAddress;)
 465 
 466   PNL (L68_ (cpu.apu.state |= apu_FA;))
 467 
 468   DBGAPP ("doAppendCycleIndirectWordFetch (Exit) PRR %o PSR %05o P %o IC %06o\n",
 469           cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
 470   DBGAPP ("doAppendCycleIndirectWordFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n",
 471           cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
 472 
 473   return finalAddress;
 474 }
/* */
root/src/dps8/doAppendCycleIndirectWordFetch.h

INCLUDED FROM

DEFINITIONS
