src/dps8/doAppendCycleOperandStore.h

/* */
This source file includes following definitions.
doAppendCycleOperandStore
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 2b0da7ec-171d-11ee-a633-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2022-2023 Charles Anthony
   9  * Copyright (c) 2022-2023 Jeffrey H. Johnson
  10  * Copyright (c) 2022-2024 The DPS8M Development Team
  11  *
  12  * This software is made available under the terms of the ICU License.
  13  * See the LICENSE.md file at the top-level directory of this distribution.
  14  *
  15  * ---------------------------------------------------------------------------
  16  */
  17 
  18 word24 doAppendCycleOperandStore (cpu_state_t * cpup, word36 * data, uint nWords) {
     /*  */
  19   DCDstruct * i = & cpu.currentInstruction;
  20   DBGAPP ("doAppendCycleOperandStore(Entry) thisCycle=OPERAND_STORE\n");
  21   DBGAPP ("doAppendCycleOperandStore(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle));
  22   DBGAPP ("doAppendCycleOperandStore(Entry) CA %06o\n", cpu.TPR.CA);
  23   DBGAPP ("doAppendCycleOperandStore(Entry) n=%2u\n", nWords);
  24   DBGAPP ("doAppendCycleOperandStore(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR);
  25   DBGAPP ("doAppendCycleOperandStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
  26 
  27   if (i->b29) {
  28     DBGAPP ("doAppendCycleOperandStore(Entry) isb29 PRNO %o\n", GET_PRN (IWB_IRODD));
  29   }
  30 
  31   bool nomatch = true;
  32   if (cpu.tweaks.enable_wam) {
  33     // AL39: The associative memory is ignored (forced to "no match") during
  34     // address preparation.
  35     // lptp,lptr,lsdp,lsdr,sptp,sptr,ssdp,ssdr
  36     // Unfortunately, ISOLTS doesn't try to execute any of these in append mode.
  37     // XXX should this be only for OPERAND_READ and OPERAND_STORE?
  38     nomatch = ((i->opcode == 0232 || i->opcode == 0254 ||
  39                 i->opcode == 0154 || i->opcode == 0173) &&
  40                 i->opcodeX ) ||
  41                ((i->opcode == 0557 || i->opcode == 0257) &&
  42                 ! i->opcodeX);
  43   }
  44 
  45   processor_cycle_type lastCycle = cpu.apu.lastCycle;
  46   cpu.apu.lastCycle = OPERAND_STORE;
  47 
  48   DBGAPP ("doAppendCycleOperandStore(Entry) XSF %o\n", cpu.cu.XSF);
  49 
  50   PNL (L68_ (cpu.apu.state = 0;))
  51 
  52   cpu.RSDWH_R1 = 0;
  53 
  54   cpu.acvFaults = 0;
  55 
  56 //#define FMSG(x) x
  57 #define FMSG(x)
  58   FMSG (char * acvFaultsMsg = "<unknown>";)
  59 
  60   word24 finalAddress = (word24) -1;  // not everything requires a final address
  61 
  62 ////////////////////////////////////////
  63 //
  64 // Sheet 2: "A"
  65 //
  66 ////////////////////////////////////////
  67 
  68 //
  69 //  A:
  70 //    Get SDW
  71 
  72   //PNL (cpu.APUMemAddr = address;)
  73   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
  74 
  75   DBGAPP ("doAppendCycleOperandStore(A)\n");
  76 
  77   // is SDW for C(TPR.TSR) in SDWAM?
  78   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
  79     // No
  80     DBGAPP ("doAppendCycleOperandStore(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
  81 
  82     DBGAPP ("doAppendCycleOperandStore(A):DSBR.U=%o\n", cpu.DSBR.U);
  83 
  84     if (cpu.DSBR.U == 0) {
  85       fetch_dsptw (cpup, cpu.TPR.TSR);
  86 
  87       if (! cpu.PTW0.DF)
  88         doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleOperandStore(A): PTW0.F == 0");
  89 
  90       if (! cpu.PTW0.U)
  91         modify_dsptw (cpup, cpu.TPR.TSR);
  92 
  93       fetch_psdw (cpup, cpu.TPR.TSR);
  94     } else
  95       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
  96 
  97     if (cpu.SDW0.DF == 0) {
  98       DBGAPP ("doAppendCycleOperandStore(A): SDW0.F == 0! " "Initiating directed fault\n");
  99       // initiate a directed fault ...
 100       doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0");
 101     }
 102     // load SDWAM .....
 103     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
 104   }
 105   DBGAPP ("doAppendCycleOperandStore(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E);
 106 
 107   // Yes...
 108   cpu.RSDWH_R1 = cpu.SDW->R1;
 109 
 110 ////////////////////////////////////////
 111 //
 112 // Sheet 3: "B"
 113 //
 114 ////////////////////////////////////////
 115 
 116 //
 117 // B: Check the ring
 118 //
 119 
 120   DBGAPP ("doAppendCycleOperandStore(B)\n");
 121 
 122   // check ring bracket consistency
 123 
 124   //C(SDW.R1) <= C(SDW.R2) <= C(SDW .R3)?
 125   if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) {
 126     // Set fault ACV0 = IRO
 127     cpu.acvFaults |= ACV0;
 128     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 129     FMSG (acvFaultsMsg = "acvFaults(B) C(SDW.R1) <= C(SDW.R2) <= " "C(SDW .R3)";)
 130   }
 131 
 132   if (lastCycle == RTCD_OPERAND_FETCH)
 133     sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\n", __func__, i->opcode);
 134 
 135   //
 136   // B1: The operand is one of: an instruction, data to be read or data to be
 137   //     written
 138   //
 139 
 140   //
 141   // check write bracket for write access
 142   //
 143   DBGAPP ("doAppendCycleOperandStore(B):STR-OP\n");
 144 
 145   // isolts 870
 146   if (cpu.TPR.TSR == cpu.PPR.PSR)
 147     cpu.TPR.TRR = cpu.PPR.PRR;
 148 
 149   // C(TPR.TRR) > C(SDW .R1)? Note typo in AL39, R2 should be R1
 150   if (cpu.TPR.TRR > cpu.SDW->R1) {
 151     DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1);
 152     //Set fault ACV5 = OWB
 153     cpu.acvFaults |= ACV5;
 154     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 155     FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R1)";)
 156   }
 157 
 158   if (! cpu.SDW->W) {
 159     // isolts 870
 160     cpu.TPR.TRR = cpu.PPR.PRR;
 161 
 162     DBGAPP ("ACV6\n");
 163     // Set fault ACV6 = W-OFF
 164     cpu.acvFaults |= ACV6;
 165     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 166     FMSG (acvFaultsMsg = "acvFaults(B) ACV6 = W-OFF";)
 167   }
 168 
 169   goto G;
 170 
 171 ////////////////////////////////////////
 172 //
 173 // Sheet 7: "G"
 174 //
 175 ////////////////////////////////////////
 176 
 177 G:;
 178 
 179   DBGAPP ("doAppendCycleOperandStore(G)\n");
 180 
 181   //C(TPR.CA)0,13 > SDW.BOUND?
 182   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
 183     DBGAPP ("ACV15\n");
 184     DBGAPP ("doAppendCycleOperandStore(G) ACV15\n");
 185     cpu.acvFaults |= ACV15;
 186     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 187     FMSG (acvFaultsMsg = "acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND";)
 188     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o",
 189             cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
 190   }
 191 
 192   if (cpu.acvFaults) {
 193     DBGAPP ("doAppendCycleOperandStore(G) acvFaults\n");
 194     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 195     // Initiate an access violation fault
 196     doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault");
 197   }
 198 
 199   // is segment C(TPR.TSR) paged?
 200   if (cpu.SDW->U)
 201     goto H; // Not paged
 202 
 203   // Yes. segment is paged ...
 204   // is PTW for C(TPR.CA) in PTWAM?
 205 
 206   DBGAPP ("doAppendCycleOperandStore(G) CA %06o\n", cpu.TPR.CA);
 207   if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) {
 208     fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA);
 209     if (! cpu.PTW0.DF) {
 210       // initiate a directed fault
 211       doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0");
 212     }
 213     loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
 214   }
 215 
 216   // Prepage mode?
 217   // check for "uninterruptible" EIS instruction
 218   // ISOLTS-878 02: mvn,cmpn,mvne,ad3d; obviously also
 219   // ad2/3d,sb2/3d,mp2/3d,dv2/3d
 220   // DH03 p.8-13: probably also mve,btd,dtb
 221   if (i->opcodeX && ((i->opcode & 0770)== 0200|| (i->opcode & 0770) == 0220
 222       || (i->opcode & 0770)== 020|| (i->opcode & 0770) == 0300)) {
 223     do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA);
 224   }
 225   goto I;
 226 
 227 ////////////////////////////////////////
 228 //
 229 // Sheet 8: "H", "I"
 230 //
 231 ////////////////////////////////////////
 232 
 233 H:;
 234   DBGAPP ("doAppendCycleOperandStore(H): FANP\n");
 235 
 236   PNL (L68_ (cpu.apu.state |= apu_FANP;))
 237 
 238 
 239 
 240 
 241 
 242 
 243 
 244   set_apu_status (cpup, apuStatus_FANP);
 245 
 246   DBGAPP ("doAppendCycleOperandStore(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
 247 
 248   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
 249   finalAddress &= 0xffffff;
 250   PNL (cpu.APUMemAddr = finalAddress;)
 251 
 252   DBGAPP ("doAppendCycleOperandStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 253 
 254   goto HI;
 255 
 256 I:;
 257 
 258 // Set PTW.M
 259 
 260   DBGAPP ("doAppendCycleOperandStore(I): FAP\n");
 261   if (cpu.PTW->M == 0)  // is this the right way to do this?
 262    modify_ptw (cpup, cpu.SDW, cpu.TPR.CA);
 263 
 264   // final address paged
 265   set_apu_status (cpup, apuStatus_FAP);
 266   PNL (L68_ (cpu.apu.state |= apu_FAP;))
 267 
 268   word24 y2 = cpu.TPR.CA % 1024;
 269 
 270   // AL39: The hardware ignores low order bits of the main memory page
 271   // address according to page size
 272   finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2;
 273   finalAddress &= 0xffffff;
 274   PNL (cpu.APUMemAddr = finalAddress;)
 275 
 276 #if defined(L68)
 277   if (cpu.MR_cache.emr && cpu.MR_cache.ihr)
 278     add_APU_history (APUH_FAP);
 279 #endif /* if defined(L68) */
 280   DBGAPP ("doAppendCycleOperandStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 281 
 282   goto HI;
 283 
 284 HI:
 285   DBGAPP ("doAppendCycleOperandStore(HI)\n");
 286 
 287   // isolts 870
 288   cpu.cu.XSF = 1;
 289   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
 290 
 291   if (cpu.useZone)
 292     core_write_zone (cpup, finalAddress, * data, "OPERAND_STORE");
 293   else
 294     core_writeN (cpup, finalAddress, data, nWords, "OPERAND_STORE");
 295 
 296 //Exit:;
 297 
 298   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
 299   PNL (cpu.APUDataBusAddr = finalAddress;)
 300 
 301   PNL (L68_ (cpu.apu.state |= apu_FA;))
 302 
 303   DBGAPP ("doAppendCycleOperandStore (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
 304   DBGAPP ("doAppendCycleOperandStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
 305 
 306   return finalAddress;
 307 }
/* */
root/src/dps8/doAppendCycleOperandStore.h

INCLUDED FROM

DEFINITIONS
