src/dps8/doAppendCycleAPUDataRMW.h

/* */
This source file includes following definitions.
doAppendCycleAPUDataRMW
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 8a44969e-171d-11ee-a0d2-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2022-2023 Charles Anthony
   9  * Copyright (c) 2022-2023 Jeffrey H. Johnson
  10  * Copyright (c) 2022-2025 The DPS8M Development Team
  11  *
  12  * This software is made available under the terms of the ICU License.
  13  * See the LICENSE.md file at the top-level directory of this distribution.
  14  *
  15  * ---------------------------------------------------------------------------
  16  */
  17 
  18 word24 doAppendCycleAPUDataRMW (cpu_state_t * cpup, word36 * data, uint nWords) {
     /*  */
  19   DCDstruct * i = & cpu.currentInstruction;
  20   DBGAPP ("doAppendCycleAPUDataRMW(Entry) thisCycle=APU_DATA_RMW\r\n");
  21   DBGAPP ("doAppendCycleAPUDataRMW(Entry) lastCycle=%s\r\n", str_pct (cpu.apu.lastCycle));
  22   DBGAPP ("doAppendCycleAPUDataRMW(Entry) CA %06o\r\n", cpu.TPR.CA);
  23   DBGAPP ("doAppendCycleAPUDataRMW(Entry) n=%2u\r\n", nWords);
  24   DBGAPP ("doAppendCycleAPUDataRMW(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR);
  25   DBGAPP ("doAppendCycleAPUDataRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\r\n", cpu.TPR.TRR, cpu.TPR.TSR);
  26 
  27   if (i->b29) {
  28     DBGAPP ("doAppendCycleAPUDataRMW(Entry) isb29 PRNO %o\r\n", GET_PRN (IWB_IRODD));
  29   }
  30 
  31   bool nomatch = true;
  32   if (cpu.tweaks.enable_wam) {
  33     // AL39: The associative memory is ignored (forced to "no match") during
  34     // address preparation.
  35     // lptp,lptr,lsdp,lsdr,sptp,sptr,ssdp,ssdr
  36     // Unfortunately, ISOLTS doesn't try to execute any of these in append mode.
  37     // XXX should this be only for OPERAND_READ and OPERAND_STORE?
  38     nomatch = ((i->opcode == 0232 || i->opcode == 0254 ||
  39                 i->opcode == 0154 || i->opcode == 0173) && i->opcodeX ) ||
  40               ((i->opcode == 0557 || i->opcode == 0257) && ! i->opcodeX);
  41   }
  42 
  43   processor_cycle_type lastCycle = cpu.apu.lastCycle;
  44   cpu.apu.lastCycle = APU_DATA_RMW;
  45 
  46   DBGAPP ("doAppendCycleAPUDataRMW(Entry) XSF %o\r\n", cpu.cu.XSF);
  47 
  48   PNL (L68_ (cpu.apu.state = 0;))
  49 
  50   cpu.RSDWH_R1 = 0;
  51 
  52   cpu.acvFaults = 0;
  53 
  54 //#define FMSG(x) x
  55 #define FMSG(x)
  56   FMSG (char * acvFaultsMsg = "<unknown>";)
  57 
  58   word24 finalAddress = (word24) -1;  // not everything requires a final
  59                                       // address
  60 
  61 ////////////////////////////////////////
  62 //
  63 // Sheet 2: "A"
  64 //
  65 ////////////////////////////////////////
  66 
  67 //
  68 //  A:
  69 //    Get SDW
  70 
  71   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
  72 
  73   DBGAPP ("doAppendCycleAPUDataRMW(A)\r\n");
  74 
  75   // is SDW for C(TPR.TSR) in SDWAM?
  76   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
  77     // No
  78     DBGAPP ("doAppendCycleAPUDataRMW(A):SDW for segment %05o not in SDWAM\r\n", cpu.TPR.TSR);
  79 
  80     DBGAPP ("doAppendCycleAPUDataRMW(A):DSBR.U=%o\r\n", cpu.DSBR.U);
  81 
  82     if (cpu.DSBR.U == 0) {
  83       fetch_dsptw (cpup, cpu.TPR.TSR);
  84 
  85       if (! cpu.PTW0.DF)
  86         doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleAPUDataRMW(A): PTW0.F == 0");
  87 
  88       if (! cpu.PTW0.U)
  89         modify_dsptw (cpup, cpu.TPR.TSR);
  90 
  91       fetch_psdw (cpup, cpu.TPR.TSR);
  92     } else
  93       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
  94 
  95     if (cpu.SDW0.DF == 0) {
  96       DBGAPP ("doAppendCycleAPUDataRMW(A): SDW0.F == 0! " "Initiating directed fault\r\n");
  97       // initiate a directed fault ...
  98       doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0");
  99     }
 100     // load SDWAM .....
 101     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
 102   }
 103   DBGAPP ("doAppendCycleAPUDataRMW(A) R1 %o R2 %o R3 %o E %o\r\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E);
 104 
 105   // Yes...
 106   cpu.RSDWH_R1 = cpu.SDW->R1;
 107 
 108 ////////////////////////////////////////
 109 //
 110 // Sheet 3: "B"
 111 //
 112 ////////////////////////////////////////
 113 
 114 //
 115 // B: Check the ring
 116 //
 117 
 118   DBGAPP ("doAppendCycleAPUDataRMW(B)\r\n");
 119 
 120   // check ring bracket consistency
 121 
 122   //C(SDW.R1) <= C(SDW.R2) <= C(SDW .R3)?
 123   if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) {
 124     // Set fault ACV0 = IRO
 125     cpu.acvFaults |= ACV0;
 126     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 127     FMSG (acvFaultsMsg = "acvFaults(B) C(SDW.R1) <= C(SDW.R2) <= " "C(SDW .R3)";)
 128   }
 129 
 130   // lastCycle == RTCD_OPERAND_FETCH
 131   // if a fault happens between the RTCD_OPERAND_FETCH and the INSTRUCTION_FETCH
 132   // of the next instruction - this happens about 35 time for just booting  and
 133   // shutting down multics -- a stored lastCycle is useless.
 134   // the opcode is preserved across faults and only replaced as the
 135   // INSTRUCTION_FETCH succeeds.
 136   if (lastCycle == RTCD_OPERAND_FETCH)
 137     sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\r\n", __func__, i->opcode);
 138 
 139   //
 140   // B1: The operand is one of: an instruction, data to be read or data to be
 141   //     written
 142   //
 143 
 144   //
 145   // check read bracket for read access
 146   //
 147 
 148   DBGAPP ("doAppendCycleAPUDataRMW(B):!STR-OP\r\n");
 149 
 150   // No
 151   // C(TPR.TRR) > C(SDW .R2)?
 152   if (cpu.TPR.TRR > cpu.SDW->R2) {
 153     DBGAPP ("ACV3\r\n");
 154     DBGAPP ("doAppendCycleAPUDataRMW(B) ACV3\r\n");
 155     //Set fault ACV3 = ORB
 156     cpu.acvFaults |= ACV3;
 157     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 158     FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R2)";)
 159   }
 160 
 161   if (cpu.SDW->R == 0) {
 162     // isolts 870
 163     cpu.TPR.TRR = cpu.PPR.PRR;
 164 
 165     //C(PPR.PSR) = C(TPR.TSR)?
 166     if (cpu.PPR.PSR != cpu.TPR.TSR) {
 167       DBGAPP ("ACV4\r\n");
 168       DBGAPP ("doAppendCycleAPUDataRMW(B) ACV4\r\n");
 169       //Set fault ACV4 = R-OFF
 170       cpu.acvFaults |= ACV4;
 171       PNL (L68_ (cpu.apu.state |= apu_FLT;))
 172       FMSG (acvFaultsMsg = "acvFaults(B) C(PPR.PSR) = C(TPR.TSR)";)
 173     //} else {
 174       // sim_warn ("doAppendCycleAPUDataRMW(B) SDW->R == 0 && cpu.PPR.PSR == cpu.TPR.TSR: %0#o\r\n", cpu.PPR.PSR);
 175     }
 176   }
 177 
 178   //
 179   // check write bracket for write access
 180   //
 181   DBGAPP ("doAppendCycleAPUDataRMW(B):STR-OP\r\n");
 182 
 183   // isolts 870
 184   if (cpu.TPR.TSR == cpu.PPR.PSR)
 185     cpu.TPR.TRR = cpu.PPR.PRR;
 186 
 187   // C(TPR.TRR) > C(SDW .R1)? Note typo in AL39, R2 should be R1
 188   if (cpu.TPR.TRR > cpu.SDW->R1) {
 189     DBGAPP ("ACV5 TRR %o R1 %o\r\n", cpu.TPR.TRR, cpu.SDW->R1);
 190     //Set fault ACV5 = OWB
 191     cpu.acvFaults |= ACV5;
 192     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 193     FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R1)";)
 194   }
 195 
 196   if (! cpu.SDW->W) {
 197     // isolts 870
 198     cpu.TPR.TRR = cpu.PPR.PRR;
 199 
 200     DBGAPP ("ACV6\r\n");
 201     // Set fault ACV6 = W-OFF
 202     cpu.acvFaults |= ACV6;
 203     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 204     FMSG (acvFaultsMsg = "acvFaults(B) ACV6 = W-OFF";)
 205   }
 206 
 207   goto G;
 208 
 209 ////////////////////////////////////////
 210 //
 211 // Sheet 7: "G"
 212 //
 213 ////////////////////////////////////////
 214 
 215 G:;
 216 
 217   DBGAPP ("doAppendCycleAPUDataRMW(G)\r\n");
 218 
 219   //C(TPR.CA)0,13 > SDW.BOUND?
 220   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
 221     DBGAPP ("ACV15\r\n");
 222     DBGAPP ("doAppendCycleAPUDataRMW(G) ACV15\r\n");
 223     cpu.acvFaults |= ACV15;
 224     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 225     FMSG (acvFaultsMsg = "acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND";)
 226     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\r\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o",
 227             cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
 228   }
 229 
 230   if (cpu.acvFaults) {
 231     DBGAPP ("doAppendCycleAPUDataRMW(G) acvFaults\r\n");
 232     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 233     // Initiate an access violation fault
 234     doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault");
 235   }
 236 
 237   // is segment C(TPR.TSR) paged?
 238   if (cpu.SDW->U)
 239     goto H; // Not paged
 240 
 241   // Yes. segment is paged ...
 242   // is PTW for C(TPR.CA) in PTWAM?
 243 
 244   DBGAPP ("doAppendCycleAPUDataRMW(G) CA %06o\r\n", cpu.TPR.CA);
 245   if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) {
 246     fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA);
 247     if (! cpu.PTW0.DF) {
 248       // initiate a directed fault
 249       doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0");
 250     }
 251     loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
 252   }
 253 
 254   // Prepage mode?
 255   // check for "uninterruptible" EIS instruction
 256   // ISOLTS-878 02: mvn,cmpn,mvne,ad3d; obviously also
 257   // ad2/3d,sb2/3d,mp2/3d,dv2/3d
 258   // DH03 p.8-13: probably also mve,btd,dtb
 259   if (i->opcodeX && ((i->opcode & 0770)== 0200 || (i->opcode & 0770) == 0220 || \
 260                      (i->opcode & 0770)== 020  || (i->opcode & 0770) == 0300)) {
 261     do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA);
 262   }
 263   goto I;
 264 
 265 ////////////////////////////////////////
 266 //
 267 // Sheet 8: "H", "I"
 268 //
 269 ////////////////////////////////////////
 270 
 271 H:;
 272   DBGAPP ("doAppendCycleAPUDataRMW(H): FANP\r\n");
 273 
 274   PNL (L68_ (cpu.apu.state |= apu_FANP;))
 275 
 276 
 277 
 278 
 279 
 280 
 281 
 282 
 283 
 284   set_apu_status (cpup, apuStatus_FANP);
 285 
 286   DBGAPP ("doAppendCycleAPUDataRMW(H): SDW->ADDR=%08o CA=%06o\r\n", cpu.SDW->ADDR, cpu.TPR.CA);
 287 
 288   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
 289   finalAddress &= 0xffffff;
 290   PNL (cpu.APUMemAddr = finalAddress;)
 291 
 292   DBGAPP ("doAppendCycleAPUDataRMW(H:FANP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 293 
 294   goto HI;
 295 
 296 I:;
 297 
 298 // Set PTW.M
 299 
 300   DBGAPP ("doAppendCycleAPUDataRMW(I): FAP\r\n");
 301   if (cpu.PTW->M == 0) // is this the right way to do this?
 302      modify_ptw (cpup, cpu.SDW, cpu.TPR.CA);
 303 
 304   // final address paged
 305   set_apu_status (cpup, apuStatus_FAP);
 306   PNL (L68_ (cpu.apu.state |= apu_FAP;))
 307 
 308   word24 y2 = cpu.TPR.CA % 1024;
 309 
 310   // AL39: The hardware ignores low order bits of the main memory page
 311   // address according to page size
 312   finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2;
 313   finalAddress &= 0xffffff;
 314   PNL (cpu.APUMemAddr = finalAddress;)
 315 
 316   L68_ (
 317   if (cpu.MR_cache.emr && cpu.MR_cache.ihr)
 318     add_l68_APU_history (cpup, APUH_FAP);
 319   )
 320 
 321   DBGAPP ("doAppendCycleAPUDataRMW(H:FAP): (%05o:%06o) finalAddress=%08o\r\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 322 
 323   goto HI;
 324 
 325 HI:
 326   DBGAPP ("doAppendCycleAPUDataRMW(HI)\r\n");
 327 
 328   // isolts 870
 329   cpu.cu.XSF = 1;
 330   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\r\n");
 331 
 332   if (nWords == 1) {
 333     core_read_lock (cpup, finalAddress, data, "APU_DATA_RMW");
 334   } else {
 335     sim_warn("doAppendCycleAPUDataRMW: RMW nWords %d != 1\r\n", nWords);
 336     core_readN (cpup, finalAddress, data, nWords, "APU_DATA_RMW");
 337   }
 338 
 339 //Exit:;
 340 
 341   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
 342   PNL (cpu.APUDataBusAddr = finalAddress;)
 343 
 344   PNL (L68_ (cpu.apu.state |= apu_FA;))
 345 
 346   DBGAPP ("doAppendCycleAPUDataRMW (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
 347   DBGAPP ("doAppendCycleAPUDataRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\r\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
 348 
 349   return finalAddress;    // or 0 or -1???
 350 }
/* */
root/src/dps8/doAppendCycleAPUDataRMW.h

INCLUDED FROM

DEFINITIONS
