src/dps8/doAppendCycleAPUDataRead.h

/* */
This source file includes following definitions.
doAppendCycleAPUDataRead
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 90fcb7d2-171d-11ee-a18f-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2022-2023 Charles Anthony
   9  * Copyright (c) 2022-2023 Jeffrey H. Johnson
  10  * Copyright (c) 2022-2024 The DPS8M Development Team
  11  *
  12  * This software is made available under the terms of the ICU License.
  13  * See the LICENSE.md file at the top-level directory of this distribution.
  14  *
  15  * ---------------------------------------------------------------------------
  16  */
  17 
  18 word24 doAppendCycleAPUDataRead (cpu_state_t * cpup, word36 * data, uint nWords) {
     /*  */
  19   DCDstruct * i = & cpu.currentInstruction;
  20   DBGAPP ("doAppendCycleAPUDataRead(Entry) thisCycle=APU_DATA_READ\n");
  21   DBGAPP ("doAppendCycleAPUDataRead(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle));
  22   DBGAPP ("doAppendCycleAPUDataRead(Entry) CA %06o\n", cpu.TPR.CA);
  23   DBGAPP ("doAppendCycleAPUDataRead(Entry) n=%2u\n", nWords);
  24   DBGAPP ("doAppendCycleAPUDataRead(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR);
  25   DBGAPP ("doAppendCycleAPUDataRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
  26 
  27   if (i->b29) {
  28     DBGAPP ("doAppendCycleAPUDataRead(Entry) isb29 PRNO %o\n", GET_PRN (IWB_IRODD));
  29   }
  30 
  31   bool nomatch = true;
  32   if (cpu.tweaks.enable_wam) {
  33     // AL39: The associative memory is ignored (forced to "no match") during
  34     // address preparation.
  35     // lptp,lptr,lsdp,lsdr,sptp,sptr,ssdp,ssdr
  36     // Unfortunately, ISOLTS doesn't try to execute any of these in append mode.
  37     // XXX should this be only for OPERAND_READ and OPERAND_STORE?
  38     nomatch = ((i->opcode == 0232 || i->opcode == 0254 ||
  39                 i->opcode == 0154 || i->opcode == 0173) &&
  40                 i->opcodeX ) ||
  41               ((i->opcode == 0557 || i->opcode == 0257) &&
  42                 ! i->opcodeX);
  43   }
  44 
  45   processor_cycle_type lastCycle = cpu.apu.lastCycle;
  46   cpu.apu.lastCycle = APU_DATA_READ;
  47 
  48   DBGAPP ("doAppendCycleAPUDataRead(Entry) XSF %o\n", cpu.cu.XSF);
  49 
  50   PNL (L68_ (cpu.apu.state = 0;))
  51 
  52   cpu.RSDWH_R1 = 0;
  53 
  54   cpu.acvFaults = 0;
  55 
  56 //#define FMSG(x) x
  57 #define FMSG(x)
  58   FMSG (char * acvFaultsMsg = "<unknown>";)
  59 
  60   word24 finalAddress = (word24) -1;  // not everything requires a final
  61                                         // address
  62 
  63 ////////////////////////////////////////
  64 //
  65 // Sheet 2: "A"
  66 //
  67 ////////////////////////////////////////
  68 
  69 //
  70 //  A:
  71 //    Get SDW
  72 
  73   //PNL (cpu.APUMemAddr = address;)
  74   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
  75 
  76   DBGAPP ("doAppendCycleAPUDataRead(A)\n");
  77 
  78     // is SDW for C(TPR.TSR) in SDWAM?
  79   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
  80     // No
  81     DBGAPP ("doAppendCycleAPUDataRead(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
  82 
  83     DBGAPP ("doAppendCycleAPUDataRead(A):DSBR.U=%o\n", cpu.DSBR.U);
  84 
  85     if (cpu.DSBR.U == 0) {
  86       fetch_dsptw (cpup, cpu.TPR.TSR);
  87 
  88       if (! cpu.PTW0.DF)
  89         doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleAPUDataRead(A): PTW0.F == 0");
  90 
  91       if (! cpu.PTW0.U)
  92         modify_dsptw (cpup, cpu.TPR.TSR);
  93 
  94       fetch_psdw (cpup, cpu.TPR.TSR);
  95     } else
  96       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
  97 
  98     if (cpu.SDW0.DF == 0) {
  99       DBGAPP ("doAppendCycleAPUDataRead(A): SDW0.F == 0! " "Initiating directed fault\n");
 100       // initiate a directed fault ...
 101       doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0");
 102     }
 103     // load SDWAM .....
 104     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
 105   }
 106   DBGAPP ("doAppendCycleAPUDataRead(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E);
 107 
 108   // Yes...
 109   cpu.RSDWH_R1 = cpu.SDW->R1;
 110 
 111 ////////////////////////////////////////
 112 //
 113 // Sheet 3: "B"
 114 //
 115 ////////////////////////////////////////
 116 
 117 //
 118 // B: Check the ring
 119 //
 120 
 121   DBGAPP ("doAppendCycleAPUDataRead(B)\n");
 122 
 123   // check ring bracket consistency
 124 
 125   //C(SDW.R1) <= C(SDW.R2) <= C(SDW .R3)?
 126   if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) {
 127     // Set fault ACV0 = IRO
 128     cpu.acvFaults |= ACV0;
 129     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 130     FMSG (acvFaultsMsg = "acvFaults(B) C(SDW.R1) <= C(SDW.R2) <= " "C(SDW .R3)";)
 131   }
 132 
 133   if (lastCycle == RTCD_OPERAND_FETCH)
 134     sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\n", __func__, i->opcode);
 135 
 136   //
 137   // B1: The operand is one of: an instruction, data to be read or data to be
 138   //     written
 139   //
 140 
 141   //
 142   // check read bracket for read access
 143   //
 144 
 145   DBGAPP ("doAppendCycleAPUDataRead(B):!STR-OP\n");
 146 
 147   // No
 148   // C(TPR.TRR) > C(SDW .R2)?
 149   if (cpu.TPR.TRR > cpu.SDW->R2) {
 150     DBGAPP ("ACV3\n");
 151     DBGAPP ("doAppendCycleAPUDataRead(B) ACV3\n");
 152     //Set fault ACV3 = ORB
 153     cpu.acvFaults |= ACV3;
 154     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 155     FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R2)";)
 156   }
 157 
 158   if (cpu.SDW->R == 0) {
 159     // isolts 870
 160     cpu.TPR.TRR = cpu.PPR.PRR;
 161 
 162     //C(PPR.PSR) = C(TPR.TSR)?
 163     if (cpu.PPR.PSR != cpu.TPR.TSR) {
 164       DBGAPP ("ACV4\n");
 165       DBGAPP ("doAppendCycleAPUDataRead(B) ACV4\n");
 166       //Set fault ACV4 = R-OFF
 167       cpu.acvFaults |= ACV4;
 168       PNL (L68_ (cpu.apu.state |= apu_FLT;))
 169       FMSG (acvFaultsMsg = "acvFaults(B) C(PPR.PSR) = C(TPR.TSR)";)
 170     //} else {
 171       // sim_warn ("doAppendCycleAPUDataRead(B) SDW->R == 0 && cpu.PPR.PSR == cpu.TPR.TSR: %0#o\n", cpu.PPR.PSR);
 172     }
 173   }
 174 
 175 ////////////////////////////////////////
 176 //
 177 // Sheet 7: "G"
 178 //
 179 ////////////////////////////////////////
 180 
 181   DBGAPP ("doAppendCycleAPUDataRead(G)\n");
 182 
 183   //C(TPR.CA)0,13 > SDW.BOUND?
 184   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
 185     DBGAPP ("ACV15\n");
 186     DBGAPP ("doAppendCycleAPUDataRead(G) ACV15\n");
 187     cpu.acvFaults |= ACV15;
 188     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 189     FMSG (acvFaultsMsg = "acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND";)
 190     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o",
 191             cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
 192   }
 193 
 194   if (cpu.acvFaults) {
 195     DBGAPP ("doAppendCycleAPUDataRead(G) acvFaults\n");
 196     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 197     // Initiate an access violation fault
 198     doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault");
 199   }
 200 
 201   // is segment C(TPR.TSR) paged?
 202   if (cpu.SDW->U)
 203     goto H; // Not paged
 204 
 205   // Yes. segment is paged ...
 206   // is PTW for C(TPR.CA) in PTWAM?
 207 
 208   DBGAPP ("doAppendCycleAPUDataRead(G) CA %06o\n", cpu.TPR.CA);
 209   if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) {
 210     fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA);
 211     if (! cpu.PTW0.DF)
 212       // initiate a directed fault
 213       doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0");
 214     loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
 215   }
 216 
 217   // Prepage mode?
 218   // check for "uninterruptible" EIS instruction
 219   // ISOLTS-878 02: mvn,cmpn,mvne,ad3d; obviously also
 220   // ad2/3d,sb2/3d,mp2/3d,dv2/3d
 221   // DH03 p.8-13: probably also mve,btd,dtb
 222   if (i->opcodeX && ((i->opcode & 0770)== 0200 || (i->opcode & 0770) == 0220 || \
 223                      (i->opcode & 0770)== 020  || (i->opcode & 0770) == 0300)) {
 224     do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA);
 225   }
 226   goto I;
 227 
 228 ////////////////////////////////////////
 229 //
 230 // Sheet 8: "H", "I"
 231 //
 232 ////////////////////////////////////////
 233 
 234 H:;
 235   DBGAPP ("doAppendCycleAPUDataRead(H): FANP\n");
 236 
 237   PNL (L68_ (cpu.apu.state |= apu_FANP;))
 238 
 239 
 240 
 241 
 242 
 243 
 244 
 245 
 246   set_apu_status (cpup, apuStatus_FANP);
 247 
 248   DBGAPP ("doAppendCycleAPUDataRead(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
 249 
 250   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
 251   finalAddress &= 0xffffff;
 252   PNL (cpu.APUMemAddr = finalAddress;)
 253 
 254   DBGAPP ("doAppendCycleAPUDataRead(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 255 
 256   goto HI;
 257 
 258 I:;
 259 
 260 // Set PTW.M
 261 
 262   DBGAPP ("doAppendCycleAPUDataRead(I): FAP\n");
 263 
 264     // final address paged
 265   set_apu_status (cpup, apuStatus_FAP);
 266   PNL (L68_ (cpu.apu.state |= apu_FAP;))
 267 
 268   word24 y2 = cpu.TPR.CA % 1024;
 269 
 270   // AL39: The hardware ignores low order bits of the main memory page
 271   // address according to page size
 272   finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2;
 273   finalAddress &= 0xffffff;
 274   PNL (cpu.APUMemAddr = finalAddress;)
 275 
 276 #if defined(L68)
 277   if (cpu.MR_cache.emr && cpu.MR_cache.ihr)
 278     add_APU_history (APUH_FAP);
 279 #endif /* if defined(L68) */
 280   DBGAPP ("doAppendCycleAPUDataRead(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 281 
 282 HI:
 283   DBGAPP ("doAppendCycleAPUDataRead(HI)\n");
 284 
 285   // isolts 870
 286   cpu.cu.XSF = 1;
 287   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
 288 
 289   core_readN (cpup, finalAddress, data, nWords, "APU_DATA_READ");
 290 
 291 //Exit:;
 292 
 293   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
 294   PNL (cpu.APUDataBusAddr = finalAddress;)
 295 
 296   PNL (L68_ (cpu.apu.state |= apu_FA;))
 297 
 298   DBGAPP ("doAppendCycleAPUDataRead (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
 299   DBGAPP ("doAppendCycleAPUDataRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
 300 
 301   return finalAddress;    // or 0 or -1???
 302 }
/* */
root/src/dps8/doAppendCycleAPUDataRead.h

INCLUDED FROM

DEFINITIONS
