src/dps8/dps8

/* */
This source file includes following definitions.
iom_core_read
iom_core_read2
iom_core_write
iom_core_write2
iom_core_read_lock
iom_core_write_unlock
iom_action
iom_show_mbx
iom_show_units
iom_set_units
iom_show_config
iom_set_config
iom_reset_unit
iom_unit_reset_idx
iom_reset
init_memory_iom
boot_svc
iom_boot
mbxLoc
status_service
build_AUXPTW_address
build_DDSPTW_address
fetch_DDSPTW
build_IDSPTW_address
fetch_IDSPTW
build_LPWPTW_address
fetch_LPWPTW
iom_direct_data_service
iom_indirect_data_service
update_chan_mode
write_LPW
dumpDCW
dumpLPW
fetch_and_parse_LPW
unpack_DCW
pack_DCW
pack_LPW
fetch_and_parse_PCW
fetch_and_parse_DCW
send_general_interrupt
iom_fault
iom_list_service
doPayloadChannel
doConnectChan
send_marker_interrupt
send_special_interrupt
send_terminate_interrupt
iom_interrupt
chan_thread_main
iom_thread_main
iom_init
do_boot
iomProcess
iomChar
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * SPDX-License-Identifier: Multics
   5  * scspell-id: 89f10936-f62e-11ec-b310-80ee73e9b8e7
   6  *
   7  * ---------------------------------------------------------------------------
   8  *
   9  * Copyright (c) 2007-2013 Michael Mondy
  10  * Copyright (c) 2012-2016 Harry Reed
  11  * Copyright (c) 2013-2022 Charles Anthony
  12  * Copyright (c) 2021-2023 The DPS8M Development Team
  13  *
  14  * This software is made available under the terms of the ICU License.
  15  * See the LICENSE.md file at the top-level directory of this distribution.
  16  *
  17  * ---------------------------------------------------------------------------
  18  *
  19  * This source file may contain code comments that adapt, include, and/or
  20  * incorporate Multics program code and/or documentation distributed under
  21  * the Multics License.  In the event of any discrepancy between code
  22  * comments herein and the original Multics materials, the original Multics
  23  * materials should be considered authoritative unless otherwise noted.
  24  * For more details and historical background, see the LICENSE.md file at
  25  * the top-level directory of this distribution.
  26  *
  27  * ---------------------------------------------------------------------------
  28  */
  29 
  30 //
  31 // IOM rework # 7
  32 //
  33 
  34 // Implementation notes:
  35 //
  36 // The IOM can be configured to operate in GCOS, Extended GCOS, and Paged modes.
  37 // Only the Paged mode is supported.
  38 //
  39 // Backup list service not implemented
  40 // Wraparound channel not implemented
  41 // Snapshot channel not implemented
  42 // Scratchpad Access channel not implemented
  43 
  44 // Direct data service
  45 
  46 // Pg: B20 "Address Extension bits will be used for core selection when the
  47 //          "the IOM is [...] in Paged mode for a non-paged channel.
  48 
  49 // Definitions:
  50 //  unit number -- ambiguous: May indicate either the Multics
  51 //                 designation for IOMA, IOMB, etc. or the scp
  52 //                 UNIT table offset.
  53 //    unit_idx --  always refers to the scp unit table offset.
  54 //
  55 //
  56 
  57 // Functional layout:
  58 
  59 // CPU emulator:
  60 //   CIOC command -> SCU cable routing to IOM emulator "iom_connect"
  61 //
  62 // IOM emulator:
  63 //   iom_connect performs the connect channel operations of fetching
  64 //   the PCW, parsing out the channel number and initial DCW.
  65 //
  66 //   The channel number and initial DCW are passed to doPayloadChannel
  67 //
  68 //   Using the cable tables, doPayloadChannel determines the handler and
  69 //   unit_idx for that channel number and calls
  70 //     iom_unit[channel_number].iom_cmd (unit_idx, DCW)
  71 //   It then walks the channel DCW list, passing DCWs to the handler.
  72 //
  73 
  74 //        make_idcw IDCW_name,
  75 //                  Command,
  76 //                  Device,
  77 //                  {record,multirecord,character,nondata},
  78 //                  {proceed,terminate,marker},
  79 //                  [ChanData,]
  80 //                  [Extension,]
  81 //                  [mask,]
  82 //
  83 //   record      0
  84 //   nondata     2
  85 //   multirecord 6
  86 //   character   8
  87 //
  88 //   terminate   0
  89 //   proceed     2
  90 //   marker      3
  91 //
  92 // Observed channel command dialects
  93 //
  94 // IOM boot
  95 // CIOC 0
  96 // Connect channel LPW 000000040000 (case c)
  97 //   DCW pointer 000000
  98 //     RES              0
  99 //     REL              0
 100 //     AE               0
 101 //     NC 21            1
 102 //     TAL 22           0
 103 //     REL              0
 104 //     TALLY         0000
 105 //
 106 // PCW 000000720201 012000000000
 107 //   Chan info     0012
 108 //   Addr ext        00
 109 //   111              7
 110 //   M                0
 111 //   Chan info  22046447
 112 //   Pg Tbl Ptr  000000
 113 //   PTP              0
 114 //   PGE              0
 115 //   AUX              0
 116 //
 117 // MTP Tape channel LPW 000004020002 (case b)
 118 //   DCW pointer 000004
 119 //     RES              0
 120 //     REL              0
 121 //     AE               0
 122 //     NC 21            0
 123 //     TAL 22           1
 124 //     REL              0
 125 //     TALLY         0002
 126 //
 127 // DCW list dump:
 128 //   IDCW 000000720201
 129 //     cmd             00 Request Status
 130 //     dev code        00
 131 //     ctrl             2 (proceed)
 132 //     chancmd          2 (nondata)
 133 //   IDCW 050000700000
 134 //     cmd             05 Rd Bin Rcrd
 135 //     dev code        00
 136 //     ctrl             0 (terminate)
 137 //     chancmd          0 (record)
 138 //   IOTD (0) 000030000000
 139 //     tally       0000
 140 //     addr            30
 141 //     cp               0
 142 //   IOTD (0) 400000000000000000000
 143 //     tally       0000
 144 //     addr            00
 145 //     cp               0
 146 //   IOTD (0) 400000000000000000000
 147 //     tally       0000
 148 //     addr            00
 149 //     cp               0
 150 //
 151 // Tape commands done:
 152 //   Tape Request Status
 153 //   Tape Read Binary Record
 154 //   IOTD (0) 000030000000
 155 //     tally       0000
 156 //     addr            30
 157 //     cp               0
 158 //   Tape IOT Read
 159 //     Tape 0 reads record 1
 160 //   ctrl == 0 in chan 10 (12) DCW
 161 
 162 // Bootload check tape controller firmware loaded test
 163 //
 164 // CIOC 138
 165 // Connect channel LPW 000000040000 (case c)
 166 //   DCW pointer 000000
 167 //     RES              0
 168 //     REL              0
 169 //     AE               0
 170 //     NC 21            1
 171 //     TAL 22           0
 172 //     REL              0
 173 //     TALLY         0000
 174 //
 175 // PCW 000000720201 012000000000
 176 //   Chan info     0012
 177 //   Addr ext        00
 178 //   111              7
 179 //   M                0
 180 //   Chan info    22046447
 181 //   Pg Tbl Ptr  000000
 182 //   PTP              0
 183 //   PGE              0
 184 //   AUX              0
 185 //
 186 // MTP Tape channel LPW 000540007777 (case a)
 187 //   DCW pointer 000540
 188 //     RES              0
 189 //     REL              0
 190 //     AE               0
 191 //     NC 21            0
 192 //     TAL 22           0
 193 //     REL              0
 194 //     TALLY         7777
 195 //
 196 // DCW list dump:
 197 //   IDCW 000000720201
 198 //     cmd             00 Request Status
 199 //     dev code        00
 200 //     ctrl             2 (proceed)
 201 //     chancmd          2 (nondata)
 202 //   IDCW 510000700200
 203 //     cmd             51 Reset Dev Stat/Alert
 204 //     dev code        00
 205 //     ctrl             0 (terminate)
 206 //     chancmd          2 (nondata)
 207 //   IDCW 000000700200
 208 //     cmd             00 Request Status
 209 //     dev code        00
 210 //     ctrl             0 (terminate)
 211 //     chancmd          2 (nondata)
 212 //   IOTD (0) 200000000000
 213 //     tally       0000
 214 //     addr            200000
 215 //     cp               0
 216 //
 217 // Tape commands done:
 218 //   Tape Request Status
 219 //   Tape Reset Device Status
 220 //   ctrl == 0 in chan 10 (12) DCW
 221 
 222 // Bootload tape read
 223 //
 224 // CIOC 7999826
 225 // Connect channel LPW 000000040000 (case c)
 226 //   DCW pointer 000000
 227 //     RES              0
 228 //     REL              0
 229 //     AE               0
 230 //     NC 21            1
 231 //     TAL 22           0
 232 //     REL              0
 233 //     TALLY         0000
 234 //
 235 // PCW 000000720201 012000000000
 236 //   Chan info     0012
 237 //   Addr ext        00
 238 //   111              7
 239 //   M                0
 240 //   Chan info    22046447
 241 //   Pg Tbl Ptr  000000
 242 //   PTP              0
 243 //   PGE              0
 244 //   AUX              0
 245 //
 246 // MTP Tape channel LPW 000621007777 (case a)
 247 //   DCW pointer 000621
 248 //     RES              0
 249 //     REL              0
 250 //     AE               0
 251 //     NC 21            0
 252 //     TAL 22           0
 253 //     REL              0
 254 //     TALLY         7777
 255 //
 256 // DCW list dump:
 257 //   IDCW 000000720201
 258 //     cmd             00 Request Status
 259 //     dev code        00
 260 //     ctrl             2 (proceed)
 261 //     chancmd          2 (nondata)
 262 //   IDCW 050000700000
 263 //     cmd             05 Rd Bin Rcrd
 264 //     dev code        00
 265 //     ctrl             0 (terminate)
 266 //     chancmd          0 (record)
 267 //   IOTD (0) 060001002020
 268 //     tally       2020
 269 //     addr            60001
 270 //     cp               0
 271 //   IOTD (0) 024000000000
 272 //     tally       0000
 273 //     addr            24000
 274 //     cp               0
 275 //
 276 // Tape commands done:
 277 //   Tape Request Status
 278 //   Tape Read Binary Record
 279 //   IOTD (0) 060001002020
 280 //     tally       2020
 281 //     addr            60001
 282 //     cp               0
 283 //   Tape IOT Read
 284 //   ctrl == 0 in chan 10 (12) DCW
 285 
 286 // Bootload searching for console
 287 //
 288 // CIOC 8191828
 289 // Connect channel LPW 037312020000 (case b)
 290 //   DCW pointer 037312
 291 //     RES              0
 292 //     REL              0
 293 //     AE               0
 294 //     NC 21            0
 295 //     TAL 22           1
 296 //     REL              0
 297 //     TALLY         0000
 298 //
 299 // PCW 510000700200 010000000000
 300 //   Chan info     0010
 301 //   Addr ext        00
 302 //   111              7
 303 //   M                0
 304 //   Chan info 22046447
 305 //   Pg Tbl Ptr  000000
 306 //   PTP              0
 307 //   PGE              0
 308 //   AUX              0
 309 //
 310 
 311 // Bootload finding console
 312 //
 313 // CIOC 8324312
 314 // Connect channel LPW 037312020000 (case b)
 315 //   DCW pointer 037312
 316 //     RES              0
 317 //     REL              0
 318 //     AE               0
 319 //     NC 21            0
 320 //     TAL 22           1
 321 //     REL              0
 322 //     TALLY         0000
 323 //
 324 // PCW 510000700200 036000000000
 325 //   Chan info     0036
 326 //   Addr ext        00
 327 //   111              7
 328 //   M                0
 329 //   Chan info 22046447
 330 //   Pg Tbl Ptr  000000
 331 //   PTP              0
 332 //   PGE              0
 333 //   AUX              0
 334 //
 335 // CONSOLE: ALERT
 336 
 337 // Bootload console read ID
 338 //
 339 // Connect channel LPW 037312020000 (case b)
 340 //   DCW pointer 037312
 341 //     RES              0
 342 //     REL              0
 343 //     AE               0
 344 //     NC 21            0
 345 //     TAL 22           1
 346 //     REL              0
 347 //     TALLY         0000
 348 //
 349 // PCW 570000700200 036000000000
 350 //   Chan info     0036
 351 //   Addr ext        00
 352 //   111              7
 353 //   M                0
 354 //   Chan info 22046447
 355 //   Pg Tbl Ptr  000000
 356 //   PTP              0
 357 //   PGE              0
 358 //   AUX              0
 359 //
 360 
 361 // Bootload console write ASCII
 362 //
 363 // Connect channel LPW 037312020000 (case b)
 364 //   DCW pointer 037312
 365 //     RES              0
 366 //     REL              0
 367 //     AE               0
 368 //     NC 21            0
 369 //     TAL 22           1
 370 //     REL              0
 371 //     TALLY         0000
 372 //
 373 // PCW 330000700000 036000000000
 374 //   Chan info     0036
 375 //   Addr ext        00
 376 //   111              7
 377 //   M                0
 378 //   Chan info 22046447
 379 //   Pg Tbl Ptr  000000
 380 //   PTP              0
 381 //   PGE              0
 382 //   AUX              0
 383 //
 384 // IOTD (0) 033624000022
 385 //   tally       0022
 386 //   addr            33624
 387 //   cp               0
 388 // Console channel LPW 033357007777 (case a)
 389 //   DCW pointer 033357
 390 //     RES              0
 391 //     REL              0
 392 //     AE               0
 393 //     NC 21            0
 394 //     TAL 22           0
 395 //     REL              0
 396 //     TALLY         7777
 397 //
 398 // DCW list dump:
 399 //   IDCW 330000700000
 400 //     cmd             33 Write ASCII
 401 //     dev code        00
 402 //     ctrl             0 (terminate)
 403 //     chancmd          0 (record)
 404 //   IOTD (0) 033624000022
 405 //     tally       0022
 406 //     addr            33624
 407 //     cp               0
 408 //   IDCW 510000700000
 409 //     cmd             51 Reset Dev Stat/Alert
 410 //     dev code        00
 411 //     ctrl             0 (terminate)
 412 //     chancmd          0 (record)
 413 
 414 //
 415 //  T&D Read block 3
 416 //    Connect Channel LPW 006312040001 (case c)
 417 //      DCW pointer 006312
 418 //      RES              0
 419 //      REL              0
 420 //      AE               0
 421 //      NC 21            1
 422 //      TAL 22           0
 423 //      REL              0
 424 //      TALLY         0001
 425 //    PCW 050000700001 012000000000
 426 //      Chan info     0500
 427 //      Addr ext        00
 428 //      111              7
 429 //      M                0
 430 //      Chan info    00001
 431 //      Chan            12
 432 //      Pg Tbl Ptr  000000
 433 //      PTP              0
 434 //      PGE              0
 435 //      AUX              0
 436 //    IDCW 050000700001
 437 //      cmd             05 (Read Binary Record)
 438 //      dev             00
 439 //      ctrl             0
 440 //      chancmd          0
 441 //
 442 //    Payload channel
 443 //      IOTD 010000000000
 444 //        tally       0000
 445 //        addr      010000
 446 //
 447 
 448 // Table 3.2.1 Updating of LPW address and tally and indication of PTRO and TRO
 449 //
 450 //  case   LPW 21   LPW 22  TALLY  UPDATE   INDICATE    INDICATE
 451 //         NC       TALLY   VALUE  ADDR &   PTRO TO     TRO
 452 //                                 TALLY    CONN. CH.   FAULT
 453 //    a.     0       0       any    yes       no         no
 454 //    b.     0       1       > 2    yes       no         no
 455 //                            1     yes       yes        no
 456 //                            0     no        no         yes
 457 //    c.     1       x       any    no        yes        no
 458 //
 459 // Case a. is GCOS common Peripheral Interface payloads channels;
 460 // a tally of 0 is not a fault since the tally field will not be
 461 // used for that purpose.
 462 //
 463 // Case b. is the configuration expected of standard operation with real-time
 464 // applications and/or direct data channels.
 465 //
 466 // Case c. will be used normally only with the connect channel servicing CPI
 467 // type payload channels. [CAC: "INDICATE PTRO TO CONN. CH." means that the
 468 // connect channel should not call list service to obtain additional PCW's]
 469 //
 470 // If case a. is used with the connect channels, a "System Fault: Tally
 471 // Control Error, Connect Channel" will be generated. Case c. will be
 472 // used in the bootload program.
 473 
 474 // LPW bits
 475 //
 476 //  0-17  DCW pointer
 477 //  18    RES - Restrict IDCW's [and] changing AE flag
 478 //  19    REL - IOM controlled image of REL bit
 479 //  20    AE - Address extension flag
 480 //  21    NC
 481 //  22    TAL
 482 //  23    REL
 483 //  24-35 TALLY
 484 //
 485 
 486 // LPWX (sometimes called LPWE)
 487 //
 488 //  0-8   Lower bound
 489 //  9-17  Size
 490 //  18-35 Pointer to DCW of most recent instruction
 491 //
 492 
 493 // PCW bits
 494 //
 495 // word 1
 496 //   0-11 Channel information
 497 //  12-17 Address extension
 498 //  18-20 111
 499 //  21    M
 500 //  22-35 Channel Information
 501 //
 502 // word 2
 503 //  36-38 SBZ
 504 //  39-44 Channel Number
 505 //  45-62 Page table ptr
 506 //  63    PTP
 507 //  64    PGE
 508 //  65    AUX
 509 //  66-21 not used
 510 
 511 // IDCW
 512 //
 513 //   0-11 Channel information
 514 //  12-17 Address extension
 515 //  18-20 111
 516 //  21    EC
 517 //  22-35 Channel Information
 518 //
 519 
 520 // TDCW
 521 //
 522 // Paged, PCW 64 = 0
 523 //
 524 //   0-17 DCW pointer
 525 //  18-20 Not 111
 526 //  21    0
 527 //  22    1
 528 //  23    0
 529 //  24-32 SBZ
 530 //  33    EC
 531 //  34    RES
 532 //  35    REL
 533 //
 534 // Paged, PCW 64 = 1
 535 //
 536 //   0-17 DCW pointer
 537 //  18-20 Not 111
 538 //  21    0
 539 //  22    1
 540 //  23    0
 541 //  24-30 SBZ
 542 //  31    SEG
 543 //  32    PDTA
 544 //  33    PDCW
 545 //  34    RES
 546 //  35    REL
 547 //
 548 
 549 #include "dps8.h"
 550 #include "dps8_cpu.h"
 551 #include "dps8_rt.h"
 552 #include "dps8_priv.h"
 553 #include "dps8_sys.h"
 554 #include "dps8_faults.h"
 555 #include "dps8_scu.h"
 556 #include "dps8_iom.h"
 557 #include "dps8_cable.h"
 558 #include "dps8_console.h"
 559 #include "dps8_fnp2.h"
 560 #include "dps8_utils.h"
 561 #if defined(LOCKLESS)
 562 # include "threadz.h"
 563 #endif
 564 
 565 #define DBG_CTR 1
 566 
 567 // Nomenclature
 568 //
 569 //  IDX index   refers to emulator unit
 570 //  NUM         refers to the number that the unit is configured as ("IOMA,
 571 //              IOMB,..."). Encoded in the low to bits of configSwMultiplexBaseAddress
 572 
 573 // Default
 574 #define N_IOM_UNITS 1
 575 
 576 #define IOM_UNIT_IDX(uptr) ((uptr) - iom_unit)
 577 
 578 #define IOM_SYSTEM_FAULT_CHAN 1U
 579 #define IOM_CONNECT_CHAN 2U
 580 #define IOM_SPECIAL_STATUS_CHAN 6U
 581 
 582 iom_chan_data_t iom_chan_data[N_IOM_UNITS_MAX][MAX_CHANNELS];
 583 
 584 typedef enum iom_status_t
 585   {
 586     iomStatNormal         = 0,
 587     iomStatLPWTRO         = 1,
 588     iomStat2TDCW          = 2,
 589     iomStatBoundaryError  = 3,
 590     iomStatAERestricted   = 4,
 591     iomStatIDCWRestricted = 5,
 592     iomStatCPDiscrepancy  = 6,
 593     iomStatParityErr      = 7
 594   } iom_status_t;
 595 
 596 enum config_sw_OS_t
 597   {
 598     CONFIG_SW_STD_GCOS,
 599     CONFIG_SW_EXT_GCOS,
 600     CONFIG_SW_MULTICS  // "Paged"
 601   };
 602 
 603 enum config_sw_model_t
 604   {
 605     CONFIG_SW_MODEL_IOM,
 606     CONFIG_SW_MODEL_IMU
 607   };
 608 
 609 // Boot device: CARD/TAPE;
 610 enum config_sw_bootload_device_e { CONFIG_SW_BLCT_CARD, CONFIG_SW_BLCT_TAPE };
 611 
 612 typedef struct
 613   {
 614     // Configuration switches
 615 
 616     // Interrupt multiplex base address: 12 toggles
 617     word12 configSwIomBaseAddress;
 618 
 619     // Mailbox base aka IOM base address: 9 toggles
 620     // Note: The IOM number is encoded in the lower two bits
 621 
 622     // AM81, pg 60 shows an image of a Level 68 IOM configuration panel
 623     // The switches are arranged and labeled
 624     //
 625     //  12   13   14   15   16   17   18   --   --  --  IOM
 626     //                                                  NUMBER
 627     //   X    X    X    X    X    X    X                X     X
 628     //
 629 
 630     word9 configSwMultiplexBaseAddress;
 631 
 632     enum config_sw_model_t config_sw_model; // IOM or IMU
 633 
 634     // OS: Three position switch: GCOS, EXT GCOS, Multics
 635     enum config_sw_OS_t config_sw_OS; // = CONFIG_SW_MULTICS;
 636 
 637     // Bootload device: Toggle switch CARD/TAPE
 638     enum config_sw_bootload_device_e configSwBootloadCardTape; // = CONFIG_SW_BLCT_TAPE;
 639 
 640     // Bootload tape IOM channel: 6 toggles
 641     word6 configSwBootloadMagtapeChan; // = 0;
 642 
 643     // Bootload cardreader IOM channel: 6 toggles
 644     word6 configSwBootloadCardrdrChan; // = 1;
 645 
 646     // Bootload: pushbutton
 647 
 648     // Sysinit: pushbutton
 649 
 650     // Bootload SCU port: 3 toggle AKA "ZERO BASE S.C. PORT NO"
 651     // "the port number of the SC through which which connects are to
 652     // be sent to the IOM
 653     word3 configSwBootloadPort; // = 0;
 654 
 655     // 8 Ports: CPU/IOM connectivity
 656     // Port configuration: 3 toggles/port
 657     // Which SCU number is this port attached to
 658     uint configSwPortAddress[N_IOM_PORTS]; // = { 0, 1, 2, 3, 4, 5, 6, 7 };
 659 
 660     // Port interlace: 1 toggle/port
 661     uint configSwPortInterface[N_IOM_PORTS]; // = { 0, 0, 0, 0, 0, 0, 0, 0 };
 662 
 663     // Port enable: 1 toggle/port
 664     uint configSwPortEnable[N_IOM_PORTS]; // = { 0, 0, 0, 0, 0, 0, 0, 0 };
 665 
 666     // Port system initialize enable: 1 toggle/port // XXX What is this
 667     uint configSwPortSysinitEnable[N_IOM_PORTS]; // = { 0, 0, 0, 0, 0, 0, 0, 0 };
 668 
 669     // Port half-size: 1 toggle/port // XXX what is this
 670     uint configSwPortHalfsize[N_IOM_PORTS]; // = { 0, 0, 0, 0, 0, 0, 0, 0 };
 671     // Port store size: 1 8 pos. rotary/port
 672     uint configSwPortStoresize[N_IOM_PORTS]; // = { 0, 0, 0, 0, 0, 0, 0, 0 };
 673 
 674     // other switches:
 675     //   alarm disable
 676     //   test/normal
 677     iom_status_t iomStatus;
 678 
 679     uint invokingScuUnitIdx; // the unit number of the SCU that did the connect.
 680 
 681     coreLockState_t  iomCoreLockState;
 682 
 683   } iom_unit_data_t;
 684 
 685 static iom_unit_data_t iom_unit_data[N_IOM_UNITS_MAX];
 686 
 687 typedef enum iomSysFaults_t
 688   {
 689     // List from 4.5.1; descr from AN87, 3-9
 690     iomNoFlt         = 000,
 691     iomIllChanFlt    = 001, // PCW to chan with chan number >= 40
 692                             // or channel without scratchpad installed
 693     iomIllSrvReqFlt  = 002, // A channel requested a service request code
 694                             // of zero, a channel number of zero, or
 695                             // a channel number >= 40
 696     // =003,                // Parity error scratchpad
 697     iomBndryVioFlt   = 003, // pg B36
 698     iom256KFlt       = 004, // 256K overflow -- address decremented to zero,
 699                             // but not tally
 700     iomLPWTRPConnFlt = 005, // tally was zero for an update LPW (LPW bit
 701                             // 21==0) when the LPW was fetched for the
 702                             // connect channel
 703     iomNotPCWFlt     = 006, // DCW for conn channel had bits 18..20 != 111b
 704     iomCP1Flt        = 007, // DCW was TDCW or had bits 18..20 == 111b
 705     // = 010,               // CP/CS-BAD-DATA DCW fetch for a 9 bit channel
 706                             // contained an illegal character position
 707     // = 011,               // NO-MEM-RES No response to an interrupt from
 708                             // a system controller within 16.5 usec.
 709     // = 012,               // PRTY-ERR-MEM Parity error on the read
 710                             // data when accessing a system controller.
 711     iomIllTalCChnFlt = 013, // LPW bits 21-22 == 00 when LPW was fetched
 712                             // for the connect channel
 713     // = 014,               // PTP-Fault: PTP-Flag= zero or PTP address
 714                             // overflow.
 715     iomPTWFlagFault  = 015, // PTW-Flag-Fault: Page Present flag zero, or
 716                             // Write Control Bit 0, or Housekeeping bit set,
 717     // = 016,               // ILL-LPW-STD LPW had bit 20 on in GCOS mode
 718     iomNoPortFault   = 017, // NO-PRT-SEL No port selected during attempt
 719                             // to access memory.
 720   } iomSysFaults_t;
 721 
 722 typedef enum iomFaultServiceRequest
 723   {
 724     // Combined SR/M/D
 725     iomFsrFirstList =  (1 << 2) | 2,
 726     iomFsrList =       (1 << 2) | 0,
 727     iomFsrStatus =     (2 << 2) | 0,
 728     iomFsrIntr =       (3 << 2) | 0,
 729     iomFsrSPIndLoad =  (4 << 2) | 0,
 730     iomFsrDPIndLoad =  (4 << 2) | 1,
 731     iomFsrSPIndStore = (5 << 2) | 0,
 732     iomFsrDPIndStore = (5 << 2) | 1,
 733     iomFsrSPDirLoad =  (6 << 2) | 0,
 734     iomFsrDPDirLoad =  (6 << 2) | 1,
 735     iomFsrSPDirStore = (7 << 2) | 0,
 736     iomFsrDPDirStore = (7 << 2) | 1
 737   } iomFaultServiceRequest;
 738 
 739 #if defined(IO_THREADZ)
 740 __thread uint this_iom_idx;
 741 __thread uint this_chan_num;
 742 #endif
 743 
 744 #if defined(TESTING)
 745 static char * cmdNames [] =
 746   {
 747     "Request Status",        //  0
 748     "",                      //  1
 749     "Rd Ctrlr Mem",          //  2
 750     "Rd 9 Rcrd",             //  3
 751     "",                      //  4
 752     "Rd Bin Rcrd",           //  5
 753     "Initiate Rd Data Xfer", //  6
 754     "",                      //  7
 755     "",                      // 10
 756     "",                      // 11
 757     "",                      // 12
 758     "Wr 9 Rcrd",             // 13
 759     "",                      // 14
 760     "Wr Bin Rcrd",           // 15
 761     "Initiate Wr Data Xfer", // 16
 762     "",                      // 17
 763     "Release Ctlr",          // 20
 764     "",                      // 21
 765     "RdStatReg",             // 22
 766     "",                      // 23
 767     "",                      // 24
 768     "Read",                  // 25
 769     "",                      // 26
 770     "",                      // 27
 771     "Seek 512",              // 30
 772     "",                      // 31
 773     "MTP Wr Mem",            // 32
 774     "Write ASCII",           // 33
 775     "",                      // 34
 776     "",                      // 35
 777     "",                      // 36
 778     "",                      // 37
 779     "Reset Status",          // 40
 780     "Set 6250 CPI",          // 41
 781     "Restore",               // 42
 782     "",                      // 43
 783     "Forward Skip Rcrd",     // 44
 784     "Forward Skip File",     // 45
 785     "Backward Skip Rcrd",    // 46
 786     "Backspace File",        // 47
 787     "Request Status",        // 50
 788     "Reset Dev Stat/Alert",  // 51
 789     "",                      // 52
 790     "",                      // 53
 791     "",                      // 54
 792     "Write EOF",             // 55
 793     "",                      // 56
 794     "Survey Devs/ReadID",    // 57
 795     "Set 800 BPI",           // 60
 796     "Set 556 BPI",           // 61
 797     "",                      // 62
 798     "Set File Permit",       // 63
 799     "Set 200 BPI",           // 64
 800     "Set 1600 CPI",          // 65
 801     "",                      // 66
 802     "",                      // 67
 803     "Rewind",                // 70
 804     "",                      // 71
 805     "Rewind/Unload",         // 72
 806     "",                      // 73
 807     "",                      // 74
 808     "",                      // 75
 809     "",                      // 76
 810     "",                      // 77
 811   };
 812 #endif
 813 
 814 void iom_core_read (UNUSED uint iom_unit_idx, word24 addr, word36 *data, UNUSED const char * ctx)
     /*  */
 815   {
 816 #if defined(LOCKLESS)
 817 # if !defined(SUNLINT)
 818     word36 v;
 819     LOAD_ACQ_CORE_WORD(v, addr);
 820     * data = v & DMASK;
 821 # endif /* if !defined(SUNLINT) */
 822 #else
 823     * data = M[addr] & DMASK;
 824 #endif
 825   }
 826 
 827 void iom_core_read2 (UNUSED uint iom_unit_idx, word24 addr, word36 *even, word36 *odd, UNUSED const char * ctx)
     /*  */
 828   {
 829 #if defined(LOCKLESS)
 830 # if !defined(SUNLINT)
 831     word36 v;
 832     LOAD_ACQ_CORE_WORD(v, addr);
 833     * even = v & DMASK;
 834 # endif /* if !defined(SUNLINT) */
 835     addr++;
 836 # if !defined(SUNLINT)
 837     LOAD_ACQ_CORE_WORD(v, addr);
 838     * odd = v & DMASK;
 839 # endif /* if !defined(SUNLINT) */
 840 #else
 841     * even = M[addr ++] & DMASK;
 842     * odd =  M[addr]    & DMASK;
 843 #endif
 844   }
 845 
 846 void iom_core_write (uint iom_unit_idx, word24 addr, word36 data, UNUSED const char * ctx)
     /*  */
 847   {
 848 #if defined(LOCKLESS)
 849     LOCK_CORE_WORD(addr, & iom_unit_data[iom_unit_idx].iomCoreLockState);
 850 # if !defined(SUNLINT)
 851     STORE_REL_CORE_WORD(addr, data);
 852 # endif /* if !defined(SUNLINT) */
 853 #else
 854     M[addr] = data & DMASK;
 855 #endif
 856   }
 857 
 858 void iom_core_write2 (UNUSED uint iom_unit_idx, word24 addr, word36 even, word36 odd, UNUSED const char * ctx)
     /*  */
 859   {
 860 #if defined(LOCKLESS)
 861     LOCK_CORE_WORD(addr, & iom_unit_data[iom_unit_idx].iomCoreLockState);
 862 # if !defined(SUNLINT)
 863     STORE_REL_CORE_WORD(addr, even);
 864 # endif /* if !defined(SUNLINT) */
 865     addr++;
 866     LOCK_CORE_WORD(addr, & iom_unit_data[iom_unit_idx].iomCoreLockState);
 867 # if !defined(SUNLINT)
 868     STORE_REL_CORE_WORD(addr, odd);
 869 # endif /* if !defined(SUNLINT) */
 870 #else
 871     M[addr ++] = even;
 872     M[addr] =    odd;
 873 #endif
 874   }
 875 
 876 void iom_core_read_lock (UNUSED uint iom_unit_idx, word24 addr, word36 *data, UNUSED const char * ctx)
     /*  */
 877   {
 878 #if defined(LOCKLESS)
 879     LOCK_CORE_WORD(addr, & iom_unit_data[iom_unit_idx].iomCoreLockState);
 880 # if !defined(SUNLINT)
 881     word36 v;
 882     LOAD_ACQ_CORE_WORD(v, addr);
 883     * data = v & DMASK;
 884 # endif /* if !defined(SUNLINT) */
 885 #else
 886     * data = M[addr] & DMASK;
 887 #endif
 888   }
 889 
 890 void iom_core_write_unlock (UNUSED uint iom_unit_idx, word24 addr, word36 data, UNUSED const char * ctx)
     /*  */
 891   {
 892 #if defined(LOCKLESS)
 893 # if !defined(SUNLINT)
 894     STORE_REL_CORE_WORD(addr, data);
 895 # endif /* if !defined(SUNLINT) */
 896 #else
 897     M[addr] = data & DMASK;
 898 #endif
 899   }
 900 
 901 static t_stat iom_action (UNIT *up)
     /*  */
 902   {
 903     // Recover the stash parameters
 904     uint scu_unit_idx = (uint) (up -> u3);
 905     uint iom_unit_idx = (uint) (up -> u4);
 906     iom_interrupt (scu_unit_idx, iom_unit_idx);
 907     return SCPE_OK;
 908   }
 909 
 910 static UNIT iom_unit[N_IOM_UNITS_MAX] = {
 911 #if defined(NO_C_ELLIPSIS)
 912   { UDATA (iom_action, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
 913   { UDATA (iom_action, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
 914   { UDATA (iom_action, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
 915   { UDATA (iom_action, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL }
 916 #else
 917   [0 ... N_IOM_UNITS_MAX - 1] = {
 918     UDATA (iom_action, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL
 919   }
 920 #endif
 921 };
 922 
 923 static t_stat iom_show_mbx (UNUSED FILE * st,
     /*  */
 924                             UNUSED UNIT * uptr, UNUSED int val,
 925                             UNUSED const void * desc)
 926   {
 927     return SCPE_OK;
 928   }
 929 
 930 static t_stat iom_show_units (UNUSED FILE * st, UNUSED UNIT * uptr, UNUSED int val, UNUSED const void * desc)
     /*  */
 931   {
 932     sim_printf ("Number of IOM units in system is %d\r\n", iom_dev.numunits);
 933     return SCPE_OK;
 934   }
 935 
 936 static t_stat iom_set_units (UNUSED UNIT * uptr, UNUSED int value, const char * cptr, UNUSED void * desc)
     /*  */
 937   {
 938     if (! cptr)
 939       return SCPE_ARG;
 940     int n = atoi (cptr);
 941     if (n < 1 || n > N_IOM_UNITS_MAX)
 942       return SCPE_ARG;
 943     // This was true for early Multics releases.
 944     //if (n > 2)
 945       //sim_printf ("Warning: Multics supports 2 IOMs maximum\r\n");
 946     iom_dev.numunits = (unsigned) n;
 947     return SCPE_OK;
 948   }
 949 
 950 static t_stat iom_show_config (UNUSED FILE * st, UNIT * uptr, UNUSED int val,
     /*  */
 951                              UNUSED const void * desc)
 952   {
 953     uint iom_unit_idx = (uint) IOM_UNIT_IDX (uptr);
 954     if (iom_unit_idx >= iom_dev.numunits)
 955       {
 956         sim_printf ("error: Invalid unit number %lu\r\n", (unsigned long) iom_unit_idx);
 957         return SCPE_ARG;
 958       }
 959 
 960     sim_printf ("IOM unit number %lu\r\n", (unsigned long) iom_unit_idx);
 961     iom_unit_data_t * p = iom_unit_data + iom_unit_idx;
 962 
 963     char * os = "<out of range>";
 964     switch (p -> config_sw_OS)
 965       {
 966         case CONFIG_SW_STD_GCOS:
 967           os = "Standard GCOS";
 968           break;
 969         case CONFIG_SW_EXT_GCOS:
 970           os = "Extended GCOS";
 971           break;
 972         case CONFIG_SW_MULTICS:
 973           os = "Multics";
 974           break;
 975       }
 976     char * blct = "<out of range>";
 977     switch (p -> configSwBootloadCardTape)
 978       {
 979         case CONFIG_SW_BLCT_CARD:
 980           blct = "CARD";
 981           break;
 982         case CONFIG_SW_BLCT_TAPE:
 983           blct = "TAPE";
 984           break;
 985       }
 986 
 987     sim_printf ("Allowed Operating System: %s\r\n", os);
 988     sim_printf ("IOM Base Address:         %03o(8)\r\n", p -> configSwIomBaseAddress);
 989     sim_printf ("Multiplex Base Address:   %04o(8)\r\n", p -> configSwMultiplexBaseAddress);
 990     sim_printf ("Bootload Card/Tape:       %s\r\n", blct);
 991     sim_printf ("Bootload Tape Channel:    %02o(8)\r\n", p -> configSwBootloadMagtapeChan);
 992     sim_printf ("Bootload Card Channel:    %02o(8)\r\n", p -> configSwBootloadCardrdrChan);
 993     sim_printf ("Bootload Port:            %02o(8)\r\n", p -> configSwBootloadPort);
 994     sim_printf ("Port Address:            ");
 995     int i;
 996     for (i = 0; i < N_IOM_PORTS; i ++)
 997       sim_printf (" %03o", p -> configSwPortAddress[i]);
 998     sim_printf ("\r\n");
 999     sim_printf ("Port Interlace:          ");
1000     for (i = 0; i < N_IOM_PORTS; i ++)
1001       sim_printf (" %3o", p -> configSwPortInterface[i]);
1002     sim_printf ("\r\n");
1003     sim_printf ("Port Enable:             ");
1004     for (i = 0; i < N_IOM_PORTS; i ++)
1005       sim_printf (" %3o", p -> configSwPortEnable[i]);
1006     sim_printf ("\r\n");
1007     sim_printf ("Port Sysinit Enable:     ");
1008     for (i = 0; i < N_IOM_PORTS; i ++)
1009       sim_printf (" %3o", p -> configSwPortSysinitEnable[i]);
1010     sim_printf ("\r\n");
1011     sim_printf ("Port Halfsize:           ");
1012     for (i = 0; i < N_IOM_PORTS; i ++)
1013       sim_printf (" %3o", p -> configSwPortHalfsize[i]);
1014     sim_printf ("\r\n");
1015     sim_printf ("Port Storesize:          ");
1016     for (i = 0; i < N_IOM_PORTS; i ++)
1017       sim_printf (" %3o", p -> configSwPortStoresize[i]);
1018     sim_printf ("\r\n");
1019 
1020     return SCPE_OK;
1021   }
1022 
1023 //
1024 // set iom0 config=<blah> [;<blah>]
1025 //
1026 //    blah = iom_base=n
1027 //           multiplex_base=n
1028 //           os=gcos | gcosext | multics
1029 //           boot=card | tape
1030 //           tapechan=n
1031 //           cardchan=n
1032 //           scuport=n
1033 //           port=n   // set port number for below commands
1034 //             addr=n
1035 //             interlace=n
1036 //             enable=n
1037 //             initenable=n
1038 //             halfsize=n
1039 //             storesize=n
1040 //          bootskip=n // Hack: forward skip n records after reading boot record
1041 
1042 static config_value_list_t cfg_model_list[] =
1043   {
1044     { "iom", CONFIG_SW_MODEL_IOM },
1045     { "imu", CONFIG_SW_MODEL_IMU }
1046   };
1047 
1048 static config_value_list_t cfg_os_list[] =
1049   {
1050     { "gcos",    CONFIG_SW_STD_GCOS },
1051     { "gcosext", CONFIG_SW_EXT_GCOS },
1052     { "multics", CONFIG_SW_MULTICS  },
1053     { NULL,      0 }
1054   };
1055 
1056 static config_value_list_t cfg_boot_list[] =
1057   {
1058     { "card", CONFIG_SW_BLCT_CARD },
1059     { "tape", CONFIG_SW_BLCT_TAPE },
1060     { NULL,   0 }
1061   };
1062 
1063 static config_value_list_t cfg_base_list[] =
1064   {
1065     { "multics",  014 },
1066     { "multics1", 014 }, // boot iom
1067     { "multics2", 020 },
1068     { "multics3", 024 },
1069     { "multics4", 030 },
1070     { NULL, 0 }
1071   };
1072 
1073 static config_value_list_t cfg_size_list[] =
1074   {
1075     { "32",    0 },
1076     { "64",    1 },
1077     { "128",   2 },
1078     { "256",   3 },
1079     { "512",   4 },
1080     { "1024",  5 },
1081     { "2048",  6 },
1082     { "4096",  7 },
1083     { "32K",   0 },
1084     { "64K",   1 },
1085     { "128K",  2 },
1086     { "256K",  3 },
1087     { "512K",  4 },
1088     { "1024K", 5 },
1089     { "2048K", 6 },
1090     { "4096K", 7 },
1091     { "1M",    5 },
1092     { "2M",    6 },
1093     { "4M",    7 },
1094     { NULL,    0 }
1095   };
1096 
1097 static config_list_t iom_config_list[] =
1098   {
1099     { "model",          1, 0,               cfg_model_list },
1100     { "os",             1, 0,               cfg_os_list    },
1101     { "boot",           1, 0,               cfg_boot_list  },
1102     { "iom_base",       0, 07777,           cfg_base_list  },
1103     { "multiplex_base", 0, 0777,            NULL           },
1104     { "tapechan",       0, 077,             NULL           },
1105     { "cardchan",       0, 077,             NULL           },
1106     { "scuport",        0, 07,              NULL           },
1107     { "port",           0, N_IOM_PORTS - 1, NULL           },
1108     { "addr",           0, 7,               NULL           },
1109     { "interlace",      0, 1,               NULL           },
1110     { "enable",         0, 1,               NULL           },
1111     { "initenable",     0, 1,               NULL           },
1112     { "halfsize",       0, 1,               NULL           },
1113     { "store_size",     0, 7,               cfg_size_list  },
1114     { NULL,             0, 0,               NULL           }
1115   };
1116 
1117 static t_stat iom_set_config (UNIT * uptr, UNUSED int value, const char * cptr, UNUSED void * desc)
     /*  */
1118   {
1119     uint iom_unit_idx = (uint) IOM_UNIT_IDX (uptr);
1120     if (iom_unit_idx >= iom_dev.numunits)
1121       {
1122         sim_printf ("error: %s: Invalid unit number %ld\r\n", __func__, (long) iom_unit_idx);
1123         return SCPE_ARG;
1124       }
1125 
1126     iom_unit_data_t * p = iom_unit_data + iom_unit_idx;
1127 
1128     static uint port_num = 0;
1129 
1130     config_state_t cfg_state = { NULL, NULL };
1131 
1132     for (;;)
1133       {
1134         int64_t v;
1135         int rc = cfg_parse (__func__, cptr, iom_config_list, & cfg_state, & v);
1136 
1137         if (rc == -1) // done
1138           break;
1139 
1140         if (rc == -2) // error
1141           {
1142             cfg_parse_done (& cfg_state);
1143             continue;
1144           }
1145         const char * name = iom_config_list[rc].name;
1146 
1147         if (strcmp (name, "model") == 0)
1148           {
1149             p -> config_sw_model = (enum config_sw_model_t) v;
1150             continue;
1151           }
1152 
1153         if (strcmp (name, "os") == 0)
1154           {
1155             p -> config_sw_OS = (enum config_sw_OS_t) v;
1156             continue;
1157           }
1158 
1159         if (strcmp (name, "boot") == 0)
1160           {
1161             p -> configSwBootloadCardTape = (enum config_sw_bootload_device_e) v;
1162             continue;
1163           }
1164 
1165         if (strcmp (name, "iom_base") == 0)
1166           {
1167             p -> configSwIomBaseAddress = (word12) v;
1168             continue;
1169           }
1170 
1171         if (strcmp (name, "multiplex_base") == 0)
1172           {
1173             // The IOM number is in the low 2 bits
1174             // The address is in the high 7 bits which are mapped
1175             // to bits 12 to 18 of a 24 bit address
1176             //
1177 //  0  1  2  3  4  5  6  7  8
1178 //  x  x  x  x  x  x  x  y  y
1179 //
1180 //  Address
1181 //  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15 16 17 18 29 20 21 22 23 24
1182 //  0  0  0  0  0  0  0  0  0  0  0  0  x  x  x  x  x  x  x  0  0  0  0  0  0
1183 //
1184 // IOM number
1185 //
1186 //  0  1
1187 //  y  y
1188 
1189             p -> configSwMultiplexBaseAddress = (word9) v;
1190             continue;
1191           }
1192 
1193         if (strcmp (name, "tapechan") == 0)
1194           {
1195             p -> configSwBootloadMagtapeChan = (word6) v;
1196             continue;
1197           }
1198 
1199         if (strcmp (name, "cardchan") == 0)
1200           {
1201             p -> configSwBootloadCardrdrChan = (word6) v;
1202             continue;
1203           }
1204 
1205         if (strcmp (name, "scuport") == 0)
1206           {
1207             p -> configSwBootloadPort = (word3) v;
1208             continue;
1209           }
1210 
1211         if (strcmp (name, "port") == 0)
1212           {
1213             port_num = (uint) v;
1214             continue;
1215           }
1216 
1217         if (strcmp (name, "addr") == 0)
1218           {
1219             p -> configSwPortAddress[port_num] = (uint) v;
1220             continue;
1221           }
1222 
1223         if (strcmp (name, "interlace") == 0)
1224           {
1225             p -> configSwPortInterface[port_num] = (uint) v;
1226             continue;
1227           }
1228 
1229         if (strcmp (name, "enable") == 0)
1230           {
1231             p -> configSwPortEnable[port_num] = (uint) v;
1232             continue;
1233           }
1234 
1235         if (strcmp (name, "initenable") == 0)
1236           {
1237             p -> configSwPortSysinitEnable[port_num] = (uint) v;
1238             continue;
1239           }
1240 
1241         if (strcmp (name, "halfsize") == 0)
1242           {
1243             p -> configSwPortHalfsize[port_num] = (uint) v;
1244             continue;
1245           }
1246 
1247         if (strcmp (name, "store_size") == 0)
1248           {
1249             p -> configSwPortStoresize[port_num] = (uint) v;
1250             continue;
1251           }
1252 
1253         sim_printf ("error: %s: Invalid cfg_parse rc <%ld>\r\n", __func__, (long) rc);
1254         cfg_parse_done (& cfg_state);
1255         return SCPE_ARG;
1256       } // process statements
1257     cfg_parse_done (& cfg_state);
1258     return SCPE_OK;
1259   }
1260 
1261 static t_stat iom_reset_unit (UNIT * uptr, UNUSED int32 value, UNUSED const char * cptr,
     /*  */
1262                        UNUSED void * desc)
1263   {
1264     uint iom_unit_idx = (uint) (uptr - iom_unit);
1265     iom_unit_reset_idx (iom_unit_idx);
1266     return SCPE_OK;
1267   }
1268 
1269 static MTAB iom_mod[] =
1270   {
1271     {
1272        MTAB_XTD | MTAB_VUN | \
1273        MTAB_NMO | MTAB_NC,       /* Mask               */
1274       0,                         /* Match              */
1275       "MBX",                     /* Print string       */
1276       NULL,                      /* Match string       */
1277       NULL,                      /* Validation routine */
1278       iom_show_mbx,              /* Display routine    */
1279       NULL,                      /* Value descriptor   */
1280       NULL                       /* Help string        */
1281     },
1282     {
1283       MTAB_XTD | MTAB_VUN | \
1284       MTAB_NMO | MTAB_VALR,      /* Mask               */
1285       0,                         /* Match              */
1286       "CONFIG",                  /* Print string       */
1287       "CONFIG",                  /* Match string       */
1288       iom_set_config,            /* Validation routine */
1289       iom_show_config,           /* Display routine    */
1290       NULL,                      /* Value descriptor   */
1291       NULL                       /* Help string        */
1292     },
1293     {
1294       MTAB_XTD | MTAB_VUN | \
1295       MTAB_NMO | MTAB_VALR,      /* Mask               */
1296       0,                         /* Match              */
1297       (char *) "RESET",          /* Print string       */
1298       (char *) "RESET",          /* Match string       */
1299       iom_reset_unit,            /* Validation routine */
1300       NULL,                      /* Display routine    */
1301       (char *) "reset IOM unit", /* Value descriptor   */
1302       NULL                       /* Help               */
1303     },
1304     {
1305       MTAB_XTD | MTAB_VDV | \
1306       MTAB_NMO | MTAB_VALR,                 /* Mask               */
1307       0,                                    /* Match              */
1308       "NUNITS",                             /* Print string       */
1309       "NUNITS",                             /* Match string       */
1310       iom_set_units,                        /* Validation routine */
1311       iom_show_units,                       /* Display routine    */
1312       "Number of IOM units in the system",  /* Value descriptor   */
1313       NULL                                  /* Help string        */
1314     },
1315     {
1316       0, 0, NULL, NULL, 0, 0, NULL, NULL
1317     }
1318   };
1319 
1320 static DEBTAB iom_dt[] =
1321   {
1322     { "NOTIFY", DBG_NOTIFY, NULL },
1323     { "INFO",   DBG_INFO,   NULL },
1324     { "ERR",    DBG_ERR,    NULL },
1325     { "WARN",   DBG_WARN,   NULL },
1326     { "DEBUG",  DBG_DEBUG,  NULL },
1327     { "TRACE",  DBG_TRACE,  NULL },
1328     { "ALL",    DBG_ALL,    NULL }, // Don't move as it messes up DBG message
1329     { NULL,     0,          NULL }
1330   };
1331 
1332 //
1333 // iom_unit_reset_idx ()
1334 //
1335 //  Reset -- Reset to initial state -- clear all device flags and cancel any
1336 //  any outstanding timing operations. Used by RESET, RUN, and BOOT commands
1337 //
1338 //  Note that all reset()s run after once-only init().
1339 //
1340 //
1341 
1342 t_stat iom_unit_reset_idx (UNUSED uint iom_unit_idx)
     /*  */
1343   {
1344     return SCPE_OK;
1345   }
1346 
1347 static t_stat iom_reset (UNUSED DEVICE * dptr)
     /*  */
1348   {
1349     //sim_debug (DBG_INFO, & iom_dev, "%s: running.\r\n", __func__);
1350 
1351     for (uint iom_unit_idx = 0; iom_unit_idx < iom_dev.numunits; iom_unit_idx ++)
1352       {
1353         iom_unit_reset_idx (iom_unit_idx);
1354       }
1355     return SCPE_OK;
1356   }
1357 
1358 static t_stat boot_svc (UNIT * unitp);
1359 static UNIT boot_channel_unit[N_IOM_UNITS_MAX] = {
1360 #if defined(NO_C_ELLIPSIS)
1361   { UDATA (& boot_svc, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
1362   { UDATA (& boot_svc, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
1363   { UDATA (& boot_svc, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
1364   { UDATA (& boot_svc, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL }
1365 #else
1366   [0 ... N_IOM_UNITS_MAX - 1] = {
1367     UDATA (& boot_svc, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL
1368   }
1369 #endif
1370 };
1371 
1372 /*
1373  * init_memory_iom ()
1374  *
1375  * Load a few words into memory.   Simulates pressing the BOOTLOAD button
1376  * on an IOM or equivalent.
1377  *
1378  * All values are from bootload_tape_label.alm.  See the comments at the
1379  * top of that file.  See also doc #43A239854.
1380  *
1381  * NOTE: The values used here are for an IOM, not an IOX.
1382  * See init_memory_iox () below.
1383  *
1384  */
1385 
1386 static void init_memory_iom (uint iom_unit_idx)
     /*  */
1387   {
1388     // The presence of a 0 in the top six bits of word 0 denote an IOM boot
1389     // from an IOX boot
1390 
1391     // " The channel number ("Chan#") is set by the switches on the IOM to be
1392     // " the channel for the tape subsystem holding the bootload tape. The
1393     // " drive number for the bootload tape is set by switches on the tape
1394     // " MPC itself.
1395 
1396     //sim_debug (DBG_INFO, & iom_dev,
1397       //"%s: Performing load of eleven words from IOM %c bootchannel to memory.\r\n",
1398       //__func__, iomChar (iom_unit_idx));
1399 
1400     word12 base = iom_unit_data[iom_unit_idx].configSwIomBaseAddress;
1401 
1402     // bootload_io.alm insists that pi_base match
1403     // template_slt_$iom_mailbox_absloc
1404 
1405     //uint pi_base = iom_unit_data[iom_unit_idx].configSwMultiplexBaseAddress & ~3;
1406     word36 pi_base = (((word36)  iom_unit_data[iom_unit_idx].configSwMultiplexBaseAddress)  << 3) |
1407                      (((word36) (iom_unit_data[iom_unit_idx].configSwIomBaseAddress & 07700U)) << 6) ;
1408     word3 iom_num = ((word36) iom_unit_data[iom_unit_idx].configSwMultiplexBaseAddress) & 3;
1409     word36 cmd = 5;       // 6 bits; 05 for tape, 01 for cards
1410     word36 dev = 0;       // 6 bits: drive number
1411 
1412     // is-IMU flag
1413     word36 imu = iom_unit_data[iom_unit_idx].config_sw_model == CONFIG_SW_MODEL_IMU ? 1 : 0;       // 1 bit
1414 
1415     // Description of the bootload channel from 43A239854
1416     //    Legend
1417     //    BB - Bootload channel #
1418     //    C - Cmd (1 or 5)
1419     //    N - IOM #
1420     //    P - Port #
1421     //    XXXX00 - Base Addr -- 01400
1422     //    XXYYYY0 Program Interrupt Base
1423 
1424     enum config_sw_bootload_device_e bootdev = iom_unit_data[iom_unit_idx].configSwBootloadCardTape;
1425 
1426     word6 bootchan;
1427     if (bootdev == CONFIG_SW_BLCT_CARD)
1428       bootchan = iom_unit_data[iom_unit_idx].configSwBootloadCardrdrChan;
1429     else // CONFIG_SW_BLCT_TAPE
1430       bootchan = iom_unit_data[iom_unit_idx].configSwBootloadMagtapeChan;
1431 
1432     // 1
1433     // system fault vector; DIS 0 instruction (imu bit not mentioned by
1434     // 43A239854)
1435 
1436     word36 dis0 = 0616200;
1437 
1438     M[010 + 2 * iom_num + 0] = (imu << 34) | dis0;
1439 
1440     // Simulator specific hack; the simulator flags memory words as
1441     // being "uninitialized"; because the fault pair is fetched as a
1442     // pair, the odd word's uninitialized state may generate a
1443     // run-time warning, even though it is not executed.
1444     //
1445     // By zeroing it here, we clear the flag and avoid the message
1446     // Since the memory will have already been set to zero by
1447     // the "Initialize and clear", this will have no affect
1448     // on the boot operation.
1449 
1450     M[010 + 2 * iom_num + 1] = 0;
1451 
1452     // 2
1453     // terminate interrupt vector (overwritten by bootload)
1454 
1455     M[030 + 2 * iom_num] = dis0;
1456 
1457     // 3
1458     // tally word for sys fault status
1459 
1460     // XXX CAC: Clang -Wsign-conversion claims 'base<<6' is int
1461     word24 base_addr =  (word24) base << 6; // 01400
1462     M[base_addr + 7] = ((word36) base_addr << 18) | 02000002;
1463 
1464     // 4
1465     // Fault channel DCW
1466 
1467     // bootload_tape_label.alm says 04000, 43A239854 says 040000.  Since
1468     // 43A239854 says "no change", 40000 is correct; 4000 would be a
1469     // large tally
1470 
1471     // Connect channel LPW; points to PCW at 000000
1472     M[base_addr + 010] = 040000;
1473 
1474     // 5
1475     // Boot device LPW; points to IDCW at 000003
1476 
1477     word24 mbx = base_addr + 4u * bootchan;
1478     M[mbx]     = 03020003;
1479 
1480     // 6
1481     // Second IDCW: IOTD to loc 30 (startup fault vector)
1482 
1483     M[4] = 030 << 18;
1484 
1485     // 7
1486     // Default SCW points at unused first mailbox.
1487 
1488     // T&D tape overwrites this before the first status is saved, though.
1489     // CAC: But the status is never saved, only a $CON occurs, never
1490     // a status service
1491 
1492     // SCW
1493 
1494     M[mbx + 2] = ((word36)base_addr << 18);
1495 
1496     // 8
1497     // 1st word of bootload channel PCW
1498 
1499     M[0] = 0720201;
1500 
1501     // 9
1502     // 2nd word of PCW pair
1503 
1504     // SCU port
1505     word3 port = iom_unit_data[iom_unit_idx].configSwBootloadPort; // 3 bits;
1506 
1507     // Why does bootload_tape_label.alm claim that a port number belongs in
1508     // the low bits of the 2nd word of the PCW?  The lower 27 bits of the
1509     // odd word of a PCW should be all zero.
1510 
1511     //[CAC] Later, bootload_tape_label.alm does:
1512     //
1513     //     cioc    bootload_info+1 " port # stuck in PCW
1514     //     lda     0,x5            " check for status
1515     //
1516     // So this is a bootloader kludge to pass the bootload SCU number
1517     //
1518 
1519     //[CAC] From Rev01.AN70.archive:
1520     //  In BOS compatibility mode, the BOS BOOT command simulates the IOM,
1521     //  leaving the same information.  However, it also leaves a config deck
1522     //  and flagbox (although bce has its own flagbox) in the usual locations.
1523     //  This allows Bootload Multics to return to BOS if there is a BOS to
1524     //  return to.  The presence of BOS is indicated by the tape drive number
1525     //  being non-zero in the idcw in the "IOM" provided information.  (This is
1526     //  normally zero until firmware is loaded into the bootload tape MPC.)
1527 
1528     M[1] = ((word36) (bootchan) << 27) | port;
1529 
1530     // 10
1531     // word after PCW (used by program)
1532 
1533     M[2] = ((word36) base_addr << 18) | (pi_base) | iom_num;
1534 
1535     // 11
1536     // IDCW for read binary
1537 
1538     M[3] = (cmd << 30) | (dev << 24) | 0700000;
1539   }
1540 
1541 static t_stat boot_svc (UNIT * unitp)
     /*  */
1542   {
1543     uint iom_unit_idx = (uint) (unitp - boot_channel_unit);
1544     // the docs say press sysinit, then boot; we don't have an
1545     // explicit "sysinit", so we treat "reset iom" as sysinit.
1546     // The docs don't say what the behavior is if you don't press
1547     // sysinit first so we won't worry about it.
1548 
1549     //sim_debug (DBG_DEBUG, & iom_dev, "%s: starting on IOM %c\r\n",
1550     //__func__, iomChar (iom_unit_idx));
1551 
1552     // This is needed to reset the interrupt mask registers; Multics tampers
1553     // with runtime values, and mucks up rebooting on multi-CPU systems.
1554     //scu_reset (NULL);
1555     for (int port_num = 0; port_num < N_SCU_PORTS; port_num ++)
1556       {
1557         if (! cables->iom_to_scu[iom_unit_idx][port_num].in_use)
1558           continue;
1559         uint scu_unit_idx = cables->iom_to_scu[iom_unit_idx][port_num].scu_unit_idx;
1560         scu_unit_reset ((int) scu_unit_idx);
1561       }
1562 
1563     // initialize memory with boot program
1564     init_memory_iom (iom_unit_idx);
1565 
1566     // Start the remote console listener
1567     startRemoteConsole ();
1568 
1569     // Start the FNP dialup listener
1570     startFNPListener ();
1571 
1572     // simulate $CON
1573     // XXX Making the assumption that low memory is connected to port 0, ..., high to 3
1574     if (! cables->iom_to_scu[iom_unit_idx][0].in_use)
1575       {
1576         sim_warn ("boot iom can't find a SCU\r\n");
1577         return SCPE_ARG;
1578       }
1579     uint scu_unit_idx = cables->iom_to_scu[iom_unit_idx][0].scu_unit_idx;
1580     iom_interrupt (scu_unit_idx, iom_unit_idx);
1581 
1582     //sim_debug (DBG_DEBUG, &iom_dev, "%s finished\r\n", __func__);
1583 
1584     // returning OK from the BOOT command causes the CPU start
1585     return SCPE_OK;
1586   }
1587 
1588 static t_stat iom_boot (int unitNum, UNUSED DEVICE * dptr)
     /*  */
1589   {
1590     if (unitNum < 0 || unitNum >= (int) iom_dev.numunits)
1591       {
1592         sim_printf ("%s: Invalid unit number %d\r\n", __func__, unitNum);
1593         return SCPE_ARG;
1594       }
1595     //uint iom_unit_idx = (uint) unitNum;
1596     boot_svc (& boot_channel_unit[unitNum]);
1597     return SCPE_OK;
1598   }
1599 
1600 DEVICE iom_dev =
1601   {
1602     "IOM",        /* name                */
1603     iom_unit,     /* units               */
1604     NULL,         /* registers           */
1605     iom_mod,      /* modifiers           */
1606     N_IOM_UNITS,  /* #units              */
1607     10,           /* address radix       */
1608     8,            /* address width       */
1609     1,            /* address increment   */
1610     8,            /* data radix          */
1611     8,            /* data width          */
1612     NULL,         /* examine routine     */
1613     NULL,         /* deposit routine     */
1614     iom_reset,    /* reset routine       */
1615     iom_boot,     /* boot routine        */
1616     NULL,         /* attach routine      */
1617     NULL,         /* detach routine      */
1618     NULL,         /* context             */
1619     DEV_DEBUG,    /* flags               */
1620     0,            /* debug control flags */
1621     iom_dt,       /* debug flag names    */
1622     NULL,         /* memory size change  */
1623     NULL,         /* logical name        */
1624     NULL,         /* help                */
1625     NULL,         /* attach help         */
1626     NULL,         /* help context        */
1627     NULL,         /* description         */
1628     NULL          /* end                 */
1629   };
1630 
1631 static uint mbxLoc (uint iom_unit_idx, uint chan)
     /*  */
1632   {
1633 // IDX is correct here as computation is based on physical unit
1634 // configuration switches
1635     word12 base      = iom_unit_data[iom_unit_idx].configSwIomBaseAddress;
1636     word24 base_addr = ((word24) base) << 6; // 01400
1637     word24 mbx       = base_addr + 4 * chan;
1638     //sim_debug (DBG_DEBUG, & iom_dev, "%s: IOM %c, chan %d is %012o\r\n",
1639       //__func__, iomChar (iom_unit_idx), chan, mbx);
1640     return mbx;
1641   }
1642 
1643 /*
1644  * status_service ()
1645  *
1646  * Write status info into a status mailbox.
1647  *
1648  * BUG: Only partially implemented.
1649  * WARNING: The diag tape will crash because we don't write a non-zero
1650  * value to the low 4 bits of the first status word.  See comments
1651  * at the top of mt.c. [CAC] Not true. The IIOC writes those bits to
1652  * tell the bootloader code whether the boot came from an IOM or IIOC.
1653  * The connect channel does not write status bits. The diag tape crash
1654  * was due so some other issue.
1655  *
1656  */
1657 
1658 // According to gtss_io_status_words.incl.pl1
1659 //
1660 //,     3 WORD1
1661 //,       4 Termination_indicator         bit(01)unal
1662 //,       4 Power_bit                     bit(01)unal
1663 //,       4 Major_status                  bit(04)unal
1664 //,       4 Substatus                     bit(06)unal
1665 //,       4 PSI_channel_odd_even_ind      bit(01)unal
1666 //,       4 Marker_bit_interrupt          bit(01)unal
1667 //,       4 Reserved                      bit(01)unal
1668 //,       4 Lost_interrupt_bit            bit(01)unal
1669 //,       4 Initiate_interrupt_ind        bit(01)unal
1670 //,       4 Abort_indicator               bit(01)unal
1671 //,       4 IOM_status                    bit(06)unal
1672 //,       4 Address_extension_bits        bit(06)unal
1673 //,       4 Record_count_residue          bit(06)unal
1674 //
1675 //,      3 WORD2
1676 //,       4 Data_address_residue          bit(18)unal
1677 //,       4 Character_count               bit(03)unal
1678 //,       4 Read_Write_control_bit        bit(01)unal
1679 //,       4 Action_code                   bit(02)unal
1680 //,       4 Word_count_residue            bit(12)unal
1681 
1682 // iom_stat.incl.pl1
1683 //
1684 // (2 t bit (1),             /* set to "1"b by IOM                         */
1685 //  2 power bit (1),         /* non-zero if peripheral absent or power off */
1686 //  2 major bit (4),         /* major status                               */
1687 //  2 sub bit (6),           /* substatus                                  */
1688 //  2 eo bit (1),            /* even/odd bit                               */
1689 //  2 marker bit (1),        /* non-zero if marker status                  */
1690 //  2 soft bit (2),          /* software status                            */
1691 //  2 initiate bit (1),      /* initiate bit                               */
1692 //  2 abort bit (1),         /* software abort bit                         */
1693 //  2 channel_stat bit (3),  /* IOM channel status                         */
1694 //  2 central_stat bit (3),  /* IOM central status                         */
1695 //  2 mbz bit (6),
1696 //  2 rcount bit (6),        /* record count residue                       */
1697 //
1698 //  2 address bit (18),      /* DCW address residue                        */
1699 //  2 char_pos bit (3),      /* character position residue                 */
1700 //  2 r bit (1),             /* non-zero if reading                        */
1701 //  2 type bit (2),          /* type of last DCW                           */
1702 //  2 tally bit (12)) unal;  /* DCW tally residue                          */
1703 
1704 // Searching the Multics source indicates that
1705 //   eo is  used by tape
1706 //   marker is used by tape and printer
1707 //   soft is set by tolts as /* set "timeout" */'
1708 //   soft is reported by tape, but not used.
1709 //   initiate is used by tape and printer
1710 //   abort is reported by tape, but not used
1711 //   char_pos is used by tape, console
1712 
1713 // pg B26: "The DCW residues stored in the status in page mode will
1714 // represent the next absolute address (bits 6-23) of data prior to
1715 // the application of the Page Table Word"
1716 
1717 static int status_service (uint iom_unit_idx, uint chan, bool marker)
     /*  */
1718   {
1719 #if defined(TESTING)
1720     cpu_state_t * cpup = _cpup;
1721 #endif
1722     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
1723     // See page 33 and AN87 for format of y-pair of status info
1724 
1725     // BUG: much of the following is not tracked
1726 
1727     word36 word1, word2;
1728     word1 = 0;
1729     putbits36_12 (& word1, 0, p -> stati);
1730     // isOdd can be set to zero; see
1731     //   https://ringzero.wikidot.com/wiki:cac-2015-10-22
1732     //putbits36_1 (& word1, 12, p -> isOdd ? 0 : 1);
1733     putbits36_1 (& word1, 13, marker ? 1 : 0);
1734     putbits36_2 (& word1, 14, 0); // software status
1735     putbits36_1 (& word1, 16, p -> initiate ? 1 : 0);
1736     putbits36_1 (& word1, 17, 0); // software abort bit
1737     putbits36_3 (& word1, 18, (word3) p -> chanStatus);
1738     //putbits36_3 (& word1, 21, iom_unit_data[iom_unit_idx].iomStatus);
1739     putbits36_3 (& word1, 21, 0);
1740 
1741 
1742 
1743 
1744     putbits36_6 (& word1, 30, p -> recordResidue);
1745 
1746     word2 = 0;
1747 
1748 
1749 
1750 
1751 
1752     putbits36_3  (& word2, 18, p -> charPos);
1753     putbits36_1  (& word2, 21, p -> isRead ? 1 : 0);
1754     putbits36_12 (& word2, 24, p -> tallyResidue);
1755 
1756     // BUG: need to write to mailbox queue
1757 
1758     // T&D tape does *not* expect us to cache original SCW, it expects us to
1759     // use the SCW loaded from tape.
1760 
1761     uint chanloc   = mbxLoc (iom_unit_idx, chan);
1762     word24 scwAddr = chanloc + IOM_MBX_SCW;
1763     word36 scw;
1764     iom_core_read_lock (iom_unit_idx, scwAddr, & scw, __func__);
1765     word18 addr    = getbits36_18 (scw, 0);   // absolute
1766     uint lq        = getbits36_2 (scw, 18);
1767     uint tally     = getbits36_12 (scw, 24);
1768 
1769     sim_debug (DBG_DEBUG, & iom_dev, "%s: Status: 0%012"PRIo64" 0%012"PRIo64"\r\n",
1770                __func__, word1, word2);
1771     if (lq == 3)
1772       {
1773         sim_debug (DBG_WARN, &iom_dev,
1774                    "%s: SCW for channel %d has illegal LQ\r\n",
1775                    __func__, chan);
1776         lq = 0;
1777       }
1778     iom_core_write2 (iom_unit_idx, addr, word1, word2, __func__);
1779 
1780     // XXX: PVS-Studio believes that tally is always == 0!?
1781     if (tally > 0 || (tally == 0 && lq != 0)) //-V560
1782       {
1783         switch (lq)
1784           {
1785             case 0:
1786               // list
1787               if (tally != 0)
1788                 {
1789                   tally --;
1790                   addr += 2;
1791                 }
1792               break;
1793 
1794             case 1:
1795               // 4 entry (8 word) queue
1796               if (tally % 8 == 1 /* || tally % 8 == -1 */)
1797                 addr -= 8;
1798               else
1799                 addr += 2;
1800               tally --;
1801               break;
1802 
1803             case 2:
1804               // 16 entry (32 word) queue
1805               if (tally % 32 == 1 /* || tally % 32 == -1 */)
1806                 addr -= 32;
1807               else
1808                 addr += 2;
1809               tally --;
1810               break;
1811           }
1812 
1813        // tally is 12 bit math
1814        if (tally & ~07777U)
1815           {
1816             sim_debug (DBG_WARN, & iom_dev,
1817                        "%s: Tally SCW address 0%o under/over flow\r\n",
1818                        __func__, tally);
1819             tally &= 07777;
1820           }
1821 
1822         putbits36_12 (& scw, 24, (word12) tally);
1823         putbits36_18 (& scw, 0, addr);
1824       }
1825 
1826     iom_core_write_unlock (iom_unit_idx, scwAddr, scw, __func__);
1827 
1828     // BUG: update SCW in core
1829     return 0;
1830   }
1831 
1832 static word24 UNUSED build_AUXPTW_address (uint iom_unit_idx, int chan)
     /*  */
1833   {
1834 //    0      5 6            16 17  18              21  22  23
1835 //   ---------------------------------------------------------
1836 //   | Zeroes | IOM Base Address  |                          |
1837 //   ---------------------------------------------------------
1838 //                         |    Channel Number       | 1 | 1 |
1839 //                         -----------------------------------
1840 // XXX Assuming 16 and 17 are or'ed. Pg B4 doesn't specify
1841 
1842     word12 IOMBaseAddress  = iom_unit_data[iom_unit_idx].configSwIomBaseAddress;
1843     word24 addr            = (((word24) IOMBaseAddress) & MASK12) << 6;
1844     addr                  |= ((uint) chan & MASK6) << 2;
1845     addr                  |= 03;
1846     return addr;
1847   }
1848 
1849 static word24 build_DDSPTW_address (word18 PCW_PAGE_TABLE_PTR, word8 pageNumber)
     /*  */
1850   {
1851 //    0      5 6        15  16  17  18                       23
1852 //   ----------------------------------------------------------
1853 //   | Page Table Pointer | 0 | 0 |                           |
1854 //   ----------------------------------------------------------
1855 // or
1856 //                        -------------------------------------
1857 //                        |  Direct chan addr 6-13            |
1858 //                        -------------------------------------
1859     if (PCW_PAGE_TABLE_PTR & 3)
1860       sim_warn ("%s: pcw_ptp %#o page_no  %#o\r\n", __func__, PCW_PAGE_TABLE_PTR, pageNumber);
1861     word24 addr = (((word24) PCW_PAGE_TABLE_PTR) & MASK18) << 6;
1862     addr |= pageNumber;
1863     return addr;
1864   }
1865 
1866 // Fetch Direct Data Service Page Table Word
1867 
1868 static void fetch_DDSPTW (uint iom_unit_idx, int chan, word18 addr)
     /*  */
1869   {
1870     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
1871     word24 pgte         = build_DDSPTW_address (p -> PCW_PAGE_TABLE_PTR,
1872                                       (addr >> 10) & MASK8);
1873     iom_core_read (iom_unit_idx, pgte, (word36 *) & p -> PTW_DCW, __func__);
1874     if ((p -> PTW_DCW & 0740000777747) != 04llu)
1875       sim_warn ("%s: chan %ld addr %#llo pgte %08llo ptw %012llo\r\n",
1876                 __func__, (long)chan, (unsigned long long)addr,
1877                 (unsigned long long)pgte, (unsigned long long)p -> PTW_DCW);
1878   }
1879 
1880 static word24 build_IDSPTW_address (word18 PCW_PAGE_TABLE_PTR, word1 seg, word8 pageNumber)
     /*  */
1881   {
1882 //    0      5 6        15  16  17  18                       23
1883 //   ----------------------------------------------------------
1884 //   | Page Table Pointer         |                           |
1885 //   ----------------------------------------------------------
1886 // plus
1887 //                    ----
1888 //                    | S |
1889 //                    | E |
1890 //                    | G |
1891 //                    -----
1892 // plus
1893 //                        -------------------------------------
1894 //                        |         DCW 0-7                   |
1895 //                        -------------------------------------
1896 
1897     word24 addr  = (((word24) PCW_PAGE_TABLE_PTR) & MASK18) << 6;
1898     addr        += (((word24) seg) & 01) << 8;
1899     addr        += pageNumber;
1900     return addr;
1901   }
1902 
1903 // Fetch Indirect Data Service Page Table Word
1904 
1905 static void fetch_IDSPTW (uint iom_unit_idx, int chan, word18 addr)
     /*  */
1906   {
1907     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
1908     word24 pgte         = build_IDSPTW_address (p -> PCW_PAGE_TABLE_PTR,
1909                                       p -> SEG,
1910                                       (addr >> 10) & MASK8);
1911     iom_core_read (iom_unit_idx, pgte, (word36 *) & p -> PTW_DCW, __func__);
1912     if ((p -> PTW_DCW & 0740000777747) != 04llu)
1913       sim_warn ("%s: chan %d addr %#o ptw %012llo\r\n",
1914                 __func__, chan, addr, (unsigned long long)p -> PTW_DCW);
1915   }
1916 
1917 static word24 build_LPWPTW_address (word18 PCW_PAGE_TABLE_PTR, word1 seg, word8 pageNumber)
     /*  */
1918   {
1919 //    0      5 6        15  16  17  18                       23
1920 //   ----------------------------------------------------------
1921 //   | Page Table Pointer         |                           |
1922 //   ----------------------------------------------------------
1923 // plus
1924 //                    ----
1925 //                    | S |
1926 //                    | E |
1927 //                    | G |
1928 //                    -----
1929 // plus
1930 //                        -------------------------------------
1931 //                        |         LPW 0-7                   |
1932 //                        -------------------------------------
1933 
1934     word24 addr  = (((word24) PCW_PAGE_TABLE_PTR) & MASK18) << 6;
1935     addr        += (((word24) seg) & 01) << 8;
1936     addr        += pageNumber;
1937     return addr;
1938   }
1939 
1940 static void fetch_LPWPTW (uint iom_unit_idx, uint chan)
     /*  */
1941   {
1942     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
1943     word24 addr         = build_LPWPTW_address (p -> PCW_PAGE_TABLE_PTR,
1944                                       p -> SEG,
1945                                       (p -> LPW_DCW_PTR >> 10) & MASK8);
1946     iom_core_read (iom_unit_idx, addr, (word36 *) & p -> PTW_LPW, __func__);
1947     if ((p -> PTW_LPW & 0740000777747) != 04llu)
1948       sim_warn ("%s: chan %d addr %#o ptw %012llo\r\n",
1949                 __func__, chan, addr, (unsigned long long)p -> PTW_LPW);
1950   }
1951 
1952 // 'write' means peripheral write; i.e. the peripheral is writing to core after
1953 // reading media.
1954 
1955 void iom_direct_data_service (uint iom_unit_idx, uint chan, word24 daddr, word36 * data,
     /*  */
1956                               iom_direct_data_service_op op)
1957   {
1958     // The direct data service consists of one core storage cycle (Read Clear, Read
1959     // Restore or Clear Write, Double or Single Precision) using an absolute
1960     // 24-bit address supplied by the channel. This service is used by
1961     // "peripherals" capable of providing addresses from an external source,
1962     // such as the 355 Direct Interface Adapter.
1963 
1964     // The PCW received for the channel contains a Page Table Pointer
1965     // which is used as an absolute address pointing to the Page Table which
1966     // has been set up by software for the Direct Channel. All addresses
1967     // for the Direct Channel will be accessed using this Page Table if paging
1968     // has been requested in the PCW.
1969 
1970     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
1971 
1972     if (p -> masked)
1973       return;
1974 
1975     if (p -> PCW_63_PTP && p -> PCW_64_PGE)
1976       {
1977         fetch_DDSPTW (iom_unit_idx, (int) chan, daddr);
1978         daddr = ((uint) getbits36_14 (p -> PTW_DCW, 4) << 10) | (daddr & MASK10);
1979       }
1980 
1981     if (op == direct_store)
1982       iom_core_write (iom_unit_idx, daddr, * data, __func__);
1983     else if (op == direct_load)
1984       iom_core_read (iom_unit_idx, daddr, data, __func__);
1985     else if (op == direct_read_clear)
1986       {
1987         iom_core_read_lock (iom_unit_idx, daddr, data, __func__);
1988         iom_core_write_unlock (iom_unit_idx, daddr, 0, __func__);
1989       }
1990   }
1991 
1992 // 'tally' is the transfer size request by Multics.
1993 // For write, '*cnt' is the number of words in 'data'.
1994 // For read, '*cnt' will be set to the number of words transferred.
1995 // Caller responsibility to allocate 'data' large enough to accommodate
1996 // 'tally' words.
1997 void iom_indirect_data_service (uint iom_unit_idx, uint chan, word36 * data, uint * cnt, bool write) {
     /*  */
1998   iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
1999 
2000   if (p->masked)
2001     return;
2002 
2003   // tape_ioi_io.pl1  "If the initiate bit is set in the status, no data was
2004   //                   transferred (no tape movement occurred)."
2005   p->initiate = false;
2006 
2007   uint tally = p->DDCW_TALLY;
2008   uint daddr = p->DDCW_ADDR;
2009   if (tally == 0) {
2010     tally = 4096;
2011   }
2012   p->tallyResidue = (word12) tally;
2013 
2014   if (write) {
2015     uint c = * cnt;
2016     while (p->tallyResidue) {
2017       if (c == 0)
2018         break; // read buffer exhausted; returns w/tallyResidue != 0
2019 
2020       if (! IS_IONTP (p)) {
2021         if (p->PCW_63_PTP && p->PCW_64_PGE) {
2022           fetch_IDSPTW (iom_unit_idx, (int) chan, daddr);
2023           word24 addr = ((word24) (getbits36_14 (p -> PTW_DCW, 4) << 10)) | (daddr & MASK10);
2024           iom_core_write (iom_unit_idx, addr, * data, __func__);
2025         } else {
2026           if (daddr > MASK18) { // 256K overflow
2027             sim_warn ("%s 256K ovf\r\n", __func__); // XXX
2028             daddr &= MASK18;
2029           }
2030 
2031           // If PTP is not set, we are in cm1e or cm2e. Both are 'EXT DCW', so
2032           // we can elide the mode check here.
2033           uint daddr2 = daddr | (uint) p->ADDR_EXT << 18;
2034           iom_core_write (iom_unit_idx, daddr2, * data, __func__);
2035         }
2036       }
2037       daddr ++;
2038       data ++;
2039       p->tallyResidue --;
2040       c --;
2041     }
2042   } else { // read
2043     uint c = 0;
2044     while (p -> tallyResidue) {
2045       if (IS_IONTP (p)) {
2046         * data = 0;
2047       } else {
2048         if (p -> PCW_63_PTP  && p -> PCW_64_PGE) {
2049           fetch_IDSPTW (iom_unit_idx, (int) chan, daddr);
2050           word24 addr = ((word24) (getbits36_14 (p -> PTW_DCW, 4) << 10)) | (daddr & MASK10);
2051           iom_core_read (iom_unit_idx, addr, data, __func__);
2052         } else {
2053           // XXX assuming DCW_ABS
2054           if (daddr > MASK18) { // 256K overflow
2055             sim_warn ("%s 256K ovf\r\n", __func__); // XXX
2056             daddr &= MASK18;
2057           }
2058 
2059           // If PTP is not set, we are in cm1e or cm2e. Both are 'EXT DCW', so
2060           // we can elide the mode check here.
2061           uint daddr2 = daddr | (uint) p -> ADDR_EXT << 18;
2062           iom_core_read (iom_unit_idx, daddr2, data, __func__);
2063         }
2064       }
2065       daddr ++;
2066       p->tallyResidue --;
2067       data ++;
2068       c ++;
2069     }
2070     * cnt = c;
2071   }
2072 }
2073 
2074 static void update_chan_mode (uint iom_unit_idx, uint chan, bool tdcw)
     /*  */
2075   {
2076     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
2077     if (chan == IOM_CONNECT_CHAN)
2078       {
2079         p -> chanMode = cm1;
2080         return;
2081       }
2082 
2083     if (! tdcw)
2084       {
2085         if (p -> PCW_64_PGE == 0)
2086           {
2087             if (p -> LPW_20_AE == 0)
2088               {
2089                     p -> chanMode = cm1e;  // AE 0
2090               }
2091             else
2092               {
2093                     p -> chanMode = cm2e;  // AE 1
2094               }
2095 
2096           }
2097         else
2098           {
2099             if (p -> LPW_20_AE == 0)
2100               {
2101                 if (p -> LPW_23_REL == 0)
2102                   {
2103                     p -> chanMode = cm1;  // AE 0, REL 0
2104                   }
2105                 else
2106                   {
2107                     p -> chanMode = cm3a;  // AE 0, REL 1
2108                   }
2109 
2110               }
2111             else  // AE 1
2112               {
2113                 if (p -> LPW_23_REL == 0)
2114                   {
2115                     p -> chanMode = cm3b;  // AE 1, REL 0
2116                   }
2117                 else
2118                   {
2119                     p -> chanMode = cm4;  // AE 1, REL 1
2120                   }
2121 
2122               }
2123           }
2124       }
2125     else // tdcw
2126       {
2127         switch (p -> chanMode)
2128           {
2129             case cm1:
2130               if (p -> TDCW_32_PDTA)
2131                 {
2132                   p -> chanMode = cm2;
2133                   break;
2134                 }
2135               if (p -> TDCW_33_PDCW)
2136                 if (p -> TDCW_35_REL)
2137                   p -> chanMode = cm4; // 33, 35
2138                 else
2139                   p -> chanMode = cm3b; // 33, !35
2140               else
2141                 if (p -> TDCW_35_REL)
2142                   p -> chanMode = cm3a; // !33, 35
2143                 else
2144                   p -> chanMode = cm2; // !33, !35
2145               break;
2146 
2147             case cm2:
2148               if (p -> TDCW_33_PDCW)
2149                 if (p -> TDCW_35_REL)
2150                   p -> chanMode = cm4; // 33, 35
2151                 else
2152                   p -> chanMode = cm3b; // 33, !35
2153               else
2154                 if (p -> TDCW_35_REL)
2155                   p -> chanMode = cm3a; // !33, 35
2156                 else
2157                   p -> chanMode = cm2; // !33, !35
2158               break;
2159 
2160             case cm3a:
2161               if (p -> TDCW_33_PDCW)
2162                 p -> chanMode = cm4;
2163               break;
2164 
2165             case cm3b:
2166               if (p -> TDCW_35_REL)
2167                 p -> chanMode = cm4;
2168               break;
2169 
2170             case cm4:
2171               p -> chanMode = cm5;
2172               break;
2173 
2174             case cm5:
2175               break;
2176 
2177             case cm1e:
2178               {
2179                 if (p -> chanMode == cm1e && p -> TDCW_33_EC)
2180                   p -> chanMode = cm2e;
2181               }
2182               break;
2183 
2184             case cm2e:
2185               break;
2186           } // switch
2187       } // tdcw
2188   }
2189 
2190 static void write_LPW (uint iom_unit_idx, uint chan)
     /*  */
2191   {
2192     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
2193 
2194     uint chanLoc = mbxLoc (iom_unit_idx, chan);
2195     iom_core_write (iom_unit_idx, chanLoc + IOM_MBX_LPW, p -> LPW, __func__);
2196     //sim_debug (DBG_DEBUG, & iom_dev,
2197                //"%s: chan %d lpw %012"PRIo64"\r\n",
2198                //__func__, chan, p -> LPW);
2199     if (chan != IOM_CONNECT_CHAN)
2200       {
2201         iom_core_write (iom_unit_idx, chanLoc + IOM_MBX_LPWX, p -> LPWX, __func__);
2202       }
2203   }
2204 
2205 #if defined(TESTING)
2206 void dumpDCW (word36 DCW, word1 LPW_23_REL) {
     /*  */
2207   static char * charCtrls[4] =
2208     { "terminate", "undefined", "proceed", "marker" };
2209   static char * chanCmds[16] =
2210     { "record",    "undefined", "nondata",     "undefined",
2211       "undefined", "undefined", "multirecord", "undefined",
2212       "character", "undefined", "undefined",   "undefined",
2213       "undefined", "undefined", "undefined",   "undefined"
2214     };
2215   word3 DCW_18_20_CP =      getbits36_3 (DCW, 18);
2216 
2217   if (DCW_18_20_CP == 07) { // IDCW
2218     word6 IDCW_DEV_CMD  =     getbits36_6 (DCW,  0);
2219     word6 IDCW_DEV_CODE =     getbits36_6 (DCW,  6);
2220  /* word6 IDCW_AE =           getbits36_6 (DCW,  12);
2221   * word1 IDCW_EC;
2222   * if (LPW_23_REL)
2223   *   IDCW_EC = 0;
2224   * else
2225   *   IDCW_EC =               getbits36_1 (DCW, 21); */
2226     word2 IDCW_CHAN_CTRL =    getbits36_2 (DCW, 22);
2227     word6 IDCW_CHAN_CMD  =    getbits36_6 (DCW, 24);
2228     word6 IDCW_COUNT     =    getbits36_6 (DCW, 30);
2229     sim_printf ("//   IDCW %012llo\r\n", DCW);
2230     sim_printf ("//     cmd             %02o %s\r\n", IDCW_DEV_CMD, cmdNames[IDCW_DEV_CMD]);
2231     sim_printf ("//     dev code        %02o\r\n", IDCW_DEV_CODE);
2232     sim_printf ("//     ctrl             %o (%s)\r\n", IDCW_CHAN_CTRL, charCtrls[IDCW_CHAN_CTRL]);
2233     sim_printf ("//     chancmd          %o (%s)\r\n", IDCW_CHAN_CMD, IDCW_CHAN_CMD < 16 ? chanCmds[IDCW_CHAN_CMD] : "unknown");
2234     sim_printf ("//     count            %o\r\n", IDCW_COUNT);
2235   } else { // TDCW or DDCW
2236     word18 TDCW_DATA_ADDRESS = getbits36_18 (DCW,  0);
2237     word1  TDCW_31_SEG       = getbits36_1  (DCW, 31);
2238     word1  TDCW_32_PDTA      = getbits36_1  (DCW, 32);
2239     word1  TDCW_33_PDCW      = getbits36_1  (DCW, 33);
2240     word1  TDCW_33_EC        = getbits36_1  (DCW, 33);
2241     word1  TDCW_34_RES       = getbits36_1  (DCW, 34);
2242     word1  TDCW_35_REL       = getbits36_1  (DCW, 35);
2243 
2244     word12 DDCW_TALLY        = getbits36_12 (DCW, 24);
2245     word18 DDCW_ADDR         = getbits36_18 (DCW,  0);
2246     word2  DDCW_22_23_TYPE   = getbits36_2  (DCW, 22);
2247     static char * types[4]   = { "IOTD", "IOTP", "TDCW", "IONTP" };
2248     if (DDCW_22_23_TYPE == 2) {
2249       sim_printf ("//   TDCW (2) %012llo\r\n", DCW);
2250       sim_printf ("//     dcw ptr   %06o\r\n", TDCW_DATA_ADDRESS);
2251       sim_printf ("//     seg            %o\r\n", TDCW_31_SEG);
2252       sim_printf ("//     pdta           %o\r\n", TDCW_32_PDTA);
2253       sim_printf ("//     pdcw           %o\r\n", TDCW_33_PDCW);
2254       sim_printf ("//     ec             %o\r\n", TDCW_33_EC);
2255       sim_printf ("//     res            %o\r\n", TDCW_34_RES);
2256       sim_printf ("//     rel            %o\r\n", TDCW_35_REL);
2257     } else {
2258       sim_printf ("//   %s (%o) %012llo\r\n", types[DDCW_22_23_TYPE], DDCW_22_23_TYPE, DCW);
2259       sim_printf ("//     tally       %04o\r\n", DDCW_TALLY);
2260       sim_printf ("//     addr            %02o\r\n", DDCW_ADDR);
2261       sim_printf ("//     cp               %o\r\n", getbits36_3 (DCW, 18));
2262     }
2263   }
2264 }
2265 
2266 static void dumpLPW (uint iom_unit_idx, uint chan) {
     /*  */
2267   iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
2268   char updateCase;
2269   if (p->LPW_21_NC)
2270     updateCase = 'c';
2271   else if (p->LPW_22_TAL)
2272     updateCase = 'b';
2273   else
2274     updateCase = 'a';
2275   static char * chanName[64] = {
2276         "0.",           //  0.   0
2277         "1.",           //  1.   1
2278         "Connect",      //  2.   2
2279         "3.",           //  3.   3
2280         "4.",           //  4.   4
2281         "5.",           //  5.   5
2282         "6.",           //  6.   6
2283         "7.",           //  7.   7
2284         "8.",           //  8.  10
2285         "9.",           //  9.  11
2286         "MTP Tape",     // 10.  12
2287         "IPC Disk",     // 11.  13
2288         "MPC Disk",     // 12.  14
2289         "Card reader",  // 13.  15
2290         "Card punch",   // 14.  16
2291         "Printer",      // 15.  17
2292         "FNP",          // 16.  20
2293         "FNP",          // 17.  21
2294         "FNP",          // 18.  22
2295         "FNP",          // 19.  23
2296         "FNP",          // 20.  24
2297         "FNP",          // 21.  25
2298         "FNP",          // 22.  26
2299         "FNP",          // 23.  27
2300         "24.",          // 24.  30
2301         "25.",          // 25.  31
2302         "ABSI",         // 26.  32
2303         "27.",          // 27.  33
2304         "28.",          // 28.  34
2305         "29.",          // 29.  35
2306         "Console",      // 30.  36
2307         "31.",          // 31.  37
2308         "Socket",       // 32.  40
2309         "Socket",       // 33.  41
2310         "Socket",       // 34.  42
2311         "Socket",       // 35.  43
2312         "Socket",       // 36.  44
2313         "Socket",       // 37.  45
2314         "Socket",       // 38.  46
2315         "39.",
2316         "40.",
2317         "41.",
2318         "42.",
2319         "43.",
2320         "44.",
2321         "45.",
2322         "46.",
2323         "47.",
2324         "48.",
2325         "49.",
2326         "50.",
2327         "51.",
2328         "52.",
2329         "53.",
2330         "54.",
2331         "55.",
2332         "56.",
2333         "57.",
2334         "58.",
2335         "59.",
2336         "60.",
2337         "61.",
2338         "62.",
2339         "63."
2340   };
2341   sim_printf ("// %s channel LPW %012llo (case %c)\r\n", chanName[chan], p->LPW, updateCase);
2342   sim_printf ("//   DCW pointer %06o\r\n",      p->LPW_DCW_PTR);
2343   sim_printf ("//     RES              %o\r\n", p->LPW_18_RES);
2344   sim_printf ("//     REL              %o\r\n", p->LPW_19_REL);
2345   sim_printf ("//     AE               %o\r\n", p->LPW_20_AE);
2346   sim_printf ("//     NC 21            %o\r\n", p->LPW_21_NC);
2347   sim_printf ("//     TAL 22           %o\r\n", p->LPW_22_TAL);
2348   sim_printf ("//     REL              %o\r\n", p->LPW_23_REL);
2349   sim_printf ("//     TALLY         %04o\r\n",  p->LPW_TALLY);
2350   sim_printf ("// \r\n");
2351 }
2352 #endif
2353 
2354 static void fetch_and_parse_LPW (uint iom_unit_idx, uint chan)
     /*  */
2355   {
2356 #if defined(TESTING)
2357     cpu_state_t * cpup = _cpup;
2358 #endif
2359     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
2360     uint chanLoc        = mbxLoc (iom_unit_idx, chan);
2361 
2362     iom_core_read (iom_unit_idx, chanLoc + IOM_MBX_LPW, (word36 *) & p -> LPW, __func__);
2363     sim_debug (DBG_DEBUG, & iom_dev,
2364                "%s: lpw %08o %012"PRIo64"\r\n", __func__, chanLoc + IOM_MBX_LPW, p->LPW);
2365 
2366     p -> LPW_DCW_PTR = getbits36_18 (p -> LPW,  0);
2367     p -> LPW_18_RES  = getbits36_1  (p -> LPW, 18);
2368     p -> LPW_19_REL  = getbits36_1  (p -> LPW, 19);
2369     p -> LPW_20_AE   = getbits36_1  (p -> LPW, 20);
2370     p -> LPW_21_NC   = getbits36_1  (p -> LPW, 21);
2371     p -> LPW_22_TAL  = getbits36_1  (p -> LPW, 22);
2372     p -> LPW_23_REL  = getbits36_1  (p -> LPW, 23);
2373     p -> LPW_TALLY   = getbits36_12 (p -> LPW, 24);
2374 
2375     if (chan == IOM_CONNECT_CHAN)
2376       {
2377         p -> LPWX = 0;
2378         p -> LPWX_BOUND = 0;
2379         p -> LPWX_SIZE = 0;
2380       }
2381     else
2382       {
2383         iom_core_read (iom_unit_idx, chanLoc + IOM_MBX_LPWX, (word36 *) & p -> LPWX, __func__);
2384         p -> LPWX_BOUND = getbits36_18 (p -> LPWX, 0);
2385         p -> LPWX_SIZE  = getbits36_18 (p -> LPWX, 18);
2386       }
2387     update_chan_mode (iom_unit_idx, chan, false);
2388   }
2389 
2390 static void unpack_DCW (uint iom_unit_idx, uint chan)
     /*  */
2391   {
2392 #if defined(TESTING)
2393     cpu_state_t * cpup = _cpup;
2394 #endif
2395     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
2396     p -> DCW_18_20_CP =      getbits36_3 (p -> DCW, 18);
2397 
2398     if (IS_IDCW (p)) // IDCW
2399       {
2400         p -> IDCW_DEV_CMD   = getbits36_6 (p -> DCW, 0);
2401         p -> IDCW_DEV_CODE  = getbits36_6 (p -> DCW, 6);
2402         p -> IDCW_AE        = getbits36_6 (p -> DCW, 12);
2403         if (p -> LPW_23_REL)
2404           p -> IDCW_EC      = 0;
2405         else
2406           p -> IDCW_EC      = getbits36_1 (p -> DCW, 21);
2407         if (p -> IDCW_EC)
2408           p -> SEG          = 1; // pat. step 45
2409         p -> IDCW_CHAN_CTRL = getbits36_2 (p -> DCW, 22);
2410         p -> IDCW_CHAN_CMD  = getbits36_6 (p -> DCW, 24);
2411         p -> IDCW_COUNT     = getbits36_6 (p -> DCW, 30);
2412         p->recordResidue = p->IDCW_COUNT;
2413 #if defined(TESTING)
2414         sim_debug (DBG_DEBUG, & iom_dev,
2415                    "%s: IDCW %012llo cmd %02o (%s) dev %02o ctrl %o chancmd %o\r\n",
2416                    __func__, p->DCW, p->IDCW_DEV_CMD, cmdNames[p->IDCW_DEV_CMD],
2417                    p->IDCW_DEV_CODE, p->IDCW_CHAN_CTRL, p->IDCW_CHAN_CMD);
2418 #endif
2419       }
2420     else // TDCW or DDCW
2421       {
2422         p -> TDCW_DATA_ADDRESS = getbits36_18 (p -> DCW,  0);
2423         p -> TDCW_31_SEG       = getbits36_1  (p -> DCW, 31);
2424         p -> TDCW_32_PDTA      = getbits36_1  (p -> DCW, 32);
2425         p -> TDCW_33_PDCW      = getbits36_1  (p -> DCW, 33);
2426         p -> TDCW_33_EC        = getbits36_1  (p -> DCW, 33);
2427         p -> TDCW_34_RES       = getbits36_1  (p -> DCW, 34);
2428         p -> TDCW_35_REL       = getbits36_1  (p -> DCW, 35);
2429         p -> DDCW_TALLY        = getbits36_12 (p -> DCW, 24);
2430         p -> DDCW_ADDR         = getbits36_18 (p -> DCW,  0);
2431         p -> DDCW_22_23_TYPE   = getbits36_2  (p -> DCW, 22);
2432         sim_debug (DBG_DEBUG, & iom_dev,
2433                    "%s: TDCW/DDCW %012llo tally %04o addr %06o type %o\r\n",
2434                    __func__, p->DCW, p->DDCW_TALLY, p->DDCW_ADDR, p->DDCW_22_23_TYPE);
2435 // POLTS_TESTING
2436 
2437 
2438 
2439 
2440 
2441 
2442 
2443 
2444 
2445 
2446 
2447 
2448 
2449 
2450 
2451 
2452 
2453 
2454 
2455 
2456       }
2457   }
2458 
2459 static void pack_DCW (uint iom_unit_idx, uint chan)
     /*  */
2460   {
2461     // DCW_18_20_CP is the only field ever changed.
2462     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
2463     putbits36_3 ((word36 *) & p -> DCW, 18, p -> DCW_18_20_CP);
2464   }
2465 
2466 static void pack_LPW (uint iom_unit_idx, uint chan)
     /*  */
2467   {
2468     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
2469     putbits36_18 ((word36 *) & p-> LPW,   0, p -> LPW_DCW_PTR);
2470     putbits36_1  ((word36 *) & p-> LPW,  18, p -> LPW_18_RES);
2471     putbits36_1  ((word36 *) & p-> LPW,  19, p -> LPW_19_REL);
2472     putbits36_1  ((word36 *) & p-> LPW,  20, p -> LPW_20_AE);
2473     putbits36_1  ((word36 *) & p-> LPW,  21, p -> LPW_21_NC);
2474     putbits36_1  ((word36 *) & p-> LPW,  22, p -> LPW_22_TAL);
2475     putbits36_1  ((word36 *) & p-> LPW,  23, p -> LPW_23_REL);
2476     putbits36_12 ((word36 *) & p-> LPW,  24, p -> LPW_TALLY);
2477     putbits36_18 ((word36 *) & p-> LPWX,  0, p -> LPWX_BOUND);
2478     putbits36_18 ((word36 *) & p-> LPWX, 18, p -> LPWX_SIZE);
2479   }
2480 
2481 static void fetch_and_parse_PCW (uint iom_unit_idx, uint chan)
     /*  */
2482   {
2483     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
2484 
2485     iom_core_read2 (iom_unit_idx, p -> LPW_DCW_PTR, (word36 *) & p -> PCW0, (word36 *) & p -> PCW1, __func__);
2486     p -> PCW_CHAN           = getbits36_6  (p -> PCW1,  3);
2487     p -> PCW_AE             = getbits36_6  (p -> PCW0, 12);
2488     p -> PCW_21_MSK         = getbits36_1  (p -> PCW0, 21);
2489     p -> PCW_PAGE_TABLE_PTR = getbits36_18 (p -> PCW1,  9);
2490     p -> PCW_63_PTP         = getbits36_1  (p -> PCW1, 27);
2491     p -> PCW_64_PGE         = getbits36_1  (p -> PCW1, 28);
2492     p -> PCW_65_AUX         = getbits36_1  (p -> PCW1, 29);
2493     if (p -> PCW_65_AUX)
2494       sim_warn ("PCW_65_AUX\r\n");
2495     p -> DCW = p -> PCW0;
2496     unpack_DCW (iom_unit_idx, chan);
2497   }
2498 
2499 static void fetch_and_parse_DCW (uint iom_unit_idx, uint chan, UNUSED bool read_only)
     /*  */
2500   {
2501 #if defined(TESTING)
2502     cpu_state_t * cpup = _cpup;
2503 #endif
2504     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
2505     word24 addr         = p -> LPW_DCW_PTR & MASK18;
2506 
2507     sim_debug (DBG_DEBUG, & iom_dev, "%s: addr %08o\r\n", __func__, addr);
2508     switch (p -> chanMode)
2509       {
2510         // LPW ABS
2511         case cm1:
2512         case cm1e:
2513           {
2514             iom_core_read (iom_unit_idx, addr, (word36 *) & p -> DCW, __func__);
2515           }
2516           break;
2517 
2518         // LPW EXT
2519         case cm2e:
2520           {
2521             // LPXW_BOUND is mod 2; ie. val is * 2
2522             //addr |= ((word24) p -> LPWX_BOUND << 18);
2523             addr += ((word24) p -> LPWX_BOUND << 1);
2524             iom_core_read (iom_unit_idx, addr, (word36 *) & p -> DCW, __func__);
2525           }
2526           break;
2527 
2528         case cm2:
2529         case cm3b:
2530           {
2531             sim_warn ("fetch_and_parse_DCW LPW paged\r\n");
2532           }
2533           break;
2534 
2535         case cm3a:
2536         case cm4:
2537         case cm5:
2538           {
2539             fetch_LPWPTW (iom_unit_idx, chan);
2540             // Calculate effective address
2541             // PTW 4-17 || LPW 8-17
2542             word24 addr_ = ((word24) (getbits36_14 (p -> PTW_LPW, 4) << 10)) | ((p -> LPW_DCW_PTR) & MASK10);
2543             iom_core_read (iom_unit_idx, addr_, (word36 *) & p -> DCW, __func__);
2544           }
2545           break;
2546       }
2547     unpack_DCW (iom_unit_idx, chan);
2548 
2549     if (IS_IDCW (p))
2550       sim_debug (DBG_DEBUG, & iom_dev,
2551                  "%s: chan %d idcw: dev_cmd %#o dev_code %#o ae %#o ec %d control %#o chan_cmd %#o data %#o\r\n",
2552                  __func__, p -> PCW_CHAN, p -> IDCW_DEV_CMD, p -> IDCW_DEV_CODE, p -> IDCW_AE,
2553                  p -> IDCW_EC, p -> IDCW_CHAN_CTRL, p -> IDCW_CHAN_CMD, p -> IDCW_COUNT);
2554     else
2555       if (p -> DDCW_22_23_TYPE == 02)
2556         sim_debug (DBG_DEBUG, & iom_dev,
2557                    "%s: chan %d tdcw: address %#o seg %d pdta %d pdcw/ec %d res %d rel %d\r\n",
2558                    __func__, p -> PCW_CHAN, p -> TDCW_DATA_ADDRESS, p -> TDCW_31_SEG,
2559                    p -> TDCW_32_PDTA, p -> TDCW_33_PDCW, p -> TDCW_34_RES, p -> TDCW_35_REL);
2560       else
2561         sim_debug (DBG_DEBUG, & iom_dev,
2562                    "%s: chan %d ddcw: address %#o char_pos %#o type %#o tally %#o\r\n",
2563                    __func__, p -> PCW_CHAN, p -> DDCW_ADDR, p -> DCW_18_20_CP,
2564                    p -> DDCW_22_23_TYPE, p -> DDCW_TALLY);
2565   }
2566 
2567 /*
2568  * send_general_interrupt ()
2569  *
2570  * Send an interrupt from the IOM to the CPU.
2571  *
2572  */
2573 
2574 int send_general_interrupt (uint iom_unit_idx, uint chan, enum iomImwPics pic)
     /*  */
2575   {
2576 #if defined(TESTING)
2577     cpu_state_t * cpup = _cpup;
2578 #endif
2579     uint imw_addr;
2580     uint chan_group    = chan < 32 ? 1 : 0;
2581     uint chan_in_group = chan & 037;
2582 
2583     uint iomUnitNum =
2584       iom_unit_data[iom_unit_idx].configSwMultiplexBaseAddress & 3u;
2585     uint interrupt_num = iomUnitNum | (chan_group << 2) | ((uint) pic << 3);
2586     // Section 3.2.7 defines the upper bits of the IMW address as
2587     // being defined by the mailbox base address switches and the
2588     // multiplex base address switches.
2589     // However, AN-70 reports that the IMW starts at 01200.  If AN-70 is
2590     // correct, the bits defined by the mailbox base address switches would
2591     // have to always be zero.  We'll go with AN-70.  This is equivalent to
2592     // using bit value 0010100 for the bits defined by the multiplex base
2593     // address switches and zeros for the bits defined by the mailbox base
2594     // address switches.
2595     //imw_addr += 01200;  // all remaining bits
2596     uint pi_base = iom_unit_data[iom_unit_idx].configSwMultiplexBaseAddress & ~3u;
2597     imw_addr = (pi_base << 3) | interrupt_num;
2598 
2599     sim_debug (DBG_DEBUG, & iom_dev,
2600                "%s: IOM %c, channel %d (%#o), level %d; "
2601                "Interrupt %d (%#o).\r\n",
2602                __func__, iomChar (iom_unit_idx), chan, chan, pic, interrupt_num,
2603                interrupt_num);
2604     word36 imw;
2605     iom_core_read_lock (iom_unit_idx, imw_addr, &imw, __func__);
2606     // The 5 least significant bits of the channel determine a bit to be
2607     // turned on.
2608     //sim_debug (DBG_DEBUG, & iom_dev,
2609                //"%s: IMW at %#o was %012"PRIo64"; setting bit %d\r\n",
2610                //__func__, imw_addr, imw, chan_in_group);
2611     putbits36_1 (& imw, chan_in_group, 1);
2612     iom_core_write_unlock (iom_unit_idx, imw_addr, imw, __func__);
2613     return scu_set_interrupt (iom_unit_data[iom_unit_idx].invokingScuUnitIdx, interrupt_num);
2614   }
2615 
2616 static void iom_fault (uint iom_unit_idx, uint chan, UNUSED const char * who,
     /*  */
2617                       iomFaultServiceRequest req,
2618                       iomSysFaults_t signal)
2619   {
2620 #if defined(TESTING)
2621     cpu_state_t * cpup = _cpup;
2622 #endif
2623     sim_warn ("iom_fault %s\r\n", who);
2624 
2625     // iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
2626     // TODO:
2627     // For a system fault:
2628     // Store the indicated fault into a system fault word (3.2.6) in
2629     // the system fault channel -- use a list service to get a DCW to do so
2630     // For a user fault, use the normal channel status mechanisms
2631 
2632     // sys fault masks channel
2633 
2634     // signal gets put in bits 30..35, but we need fault code for 26..29
2635 
2636     // BUG: mostly unimplemented
2637 
2638     // User Faults: Pg 78: "A user fault is an abnormal conditions that can
2639     // be caused by a user program operating in the slave mode in the
2640     // processor."
2641     //  and
2642     // "User faults can be detected by the IOM Central of by a channel. If
2643     // a user fault is detected by the IOM Central, the fault is indicated to
2644     // the channel, and the channel is responsible for reporting the user
2645     // fault as status is its regular status queue.
2646 
2647     // This code only handles system faults
2648     //
2649 
2650     sim_debug (DBG_DEBUG, & iom_dev,
2651                "%s: chan %d %s req %#o signal %#o\r\n",
2652                __func__, chan, who, req, signal);
2653 
2654     word36 faultWord = 0;
2655     putbits36_9 (& faultWord, 9, (word9) chan);
2656     putbits36_5 (& faultWord, 18, (word5) req);
2657     // IAC, bits 26..29
2658     putbits36_6 (& faultWord, 30, (word6) signal);
2659 
2660     uint chanloc = mbxLoc (iom_unit_idx, IOM_SYSTEM_FAULT_CHAN);
2661 
2662     word36 lpw;
2663     iom_core_read (iom_unit_idx, chanloc + IOM_MBX_LPW, & lpw, __func__);
2664 
2665     word36 scw;
2666     iom_core_read (iom_unit_idx, chanloc + IOM_MBX_SCW, & scw, __func__);
2667 
2668     word36 dcw;
2669     iom_core_read_lock (iom_unit_idx, chanloc + IOM_MBX_DCW, & dcw, __func__);
2670 
2671     //sim_debug (DBG_DEBUG, & iom_dev,
2672                //"%s: lpw %012"PRIo64" scw %012"PRIo64" dcw %012"PRIo64"\r\n",
2673                //__func__, lpw, scw, dcw);
2674 
2675     iom_core_write (iom_unit_idx, (dcw >> 18) & MASK18, faultWord, __func__);
2676 
2677     uint tally = dcw & MASK12;
2678     if (tally > 1)
2679       {
2680         dcw -= 01llu;        //-V536  // tally --
2681         dcw += 01000000llu;  //-V536  // addr ++
2682       }
2683     else
2684       dcw = scw; // reset to beginning of queue
2685     iom_core_write_unlock (iom_unit_idx, chanloc + IOM_MBX_DCW, dcw, __func__);
2686 
2687     send_general_interrupt (iom_unit_idx, IOM_SYSTEM_FAULT_CHAN, imwSystemFaultPic);
2688   }
2689 
2690 //  0 ok
2691 // -1 fault
2692 // There is a path through the code where no DCW is sent (IDCW && LPW_18_RES)
2693 // Does the -1 return cover that?
2694 
2695 int iom_list_service (uint iom_unit_idx, uint chan,
     /*  */
2696                            bool * ptro, bool * sendp, bool * uffp)
2697   {
2698     iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][chan];
2699 
2700 // initialize
2701 
2702     bool isConnChan = chan == IOM_CONNECT_CHAN;
2703     * ptro          = false; // assume not PTRO
2704     bool uff        = false; // user fault flag
2705     bool send       = false;
2706 
2707 // Figure 4.3.1
2708 
2709 // START
2710 
2711     // FIRST SERVICE?
2712 
2713     if (p -> lsFirst)
2714       {
2715         // PULL LPW AND LPW EXT. FROM CORE MAILBOX
2716 
2717         fetch_and_parse_LPW (iom_unit_idx, chan);
2718         p -> wasTDCW = false;
2719         p -> SEG     = 0; // pat. FIG. 2, step 44
2720       }
2721     // else lpw and lpwx are in chanData;
2722 
2723     // CONNECT CHANNEL?
2724 
2725     if (isConnChan)
2726       { // connect channel
2727 
2728         // LPW 21 (NC), 22 (TAL) is {00, 01, 1x}?
2729 
2730         if (p -> LPW_21_NC == 0 && p -> LPW_22_TAL == 0)
2731               {
2732                 iom_fault (iom_unit_idx, IOM_CONNECT_CHAN, __func__,
2733                           p -> lsFirst ? iomFsrFirstList : iomFsrList,
2734                           iomIllTalCChnFlt);
2735                 return -1;
2736               }
2737 
2738         if (p -> LPW_21_NC == 0 && p -> LPW_22_TAL == 1)
2739           { // 01
2740 
2741             // TALLY is {0, 1, >1}?
2742 
2743             if (p -> LPW_TALLY == 0)
2744               {
2745                 iom_fault (iom_unit_idx, IOM_CONNECT_CHAN, __func__,
2746                           p -> lsFirst ? iomFsrFirstList : iomFsrList,
2747                           iomIllTalCChnFlt);
2748                 return -1;
2749               }
2750 
2751             if (p -> LPW_TALLY > 1)
2752               { // 00
2753 
2754                 // 256K OVERFLOW?
2755                 if (p -> LPW_20_AE == 0 &&
2756                     (((word36) p -> LPW_DCW_PTR) + ((word36) p -> LPW_TALLY)) >
2757                     01000000llu)
2758                   {
2759                     iom_fault (iom_unit_idx, IOM_CONNECT_CHAN, __func__,
2760                               p -> lsFirst ? iomFsrFirstList : iomFsrList,
2761                               iom256KFlt);
2762                     return -1;
2763                   }
2764               }
2765             else if (p -> LPW_TALLY == 1)
2766               * ptro = true;
2767           }
2768         else // 1x
2769           * ptro = true;
2770 
2771         // PULL PCW FROM CORE
2772 
2773 // B
2774 
2775         fetch_and_parse_PCW (iom_unit_idx, chan); // fills in DCW*
2776 
2777         // PCW 18-20 == 111?
2778         if (IS_NOT_IDCW (p))
2779           {
2780             iom_fault (iom_unit_idx, IOM_CONNECT_CHAN, __func__,
2781                       p -> lsFirst ? iomFsrFirstList : iomFsrList,
2782                       iomNotPCWFlt);
2783             return -1;
2784           }
2785 
2786         // SELECT CHANNEL
2787 
2788         // chan = p -> PCW_CHAN;
2789 
2790 // detect unused slot as fault
2791 // if (no handler in slot)
2792 //  goto FAULT;
2793 
2794        // SEND PCW TO CHANNEL
2795 
2796         // p -> DCW = p -> DCW;
2797         send = true;
2798 
2799         goto D;
2800       }
2801 
2802     // Not connect channel
2803 
2804     // LPW 21 (NC), 22 (TAL) is {00, 01, 1x}?
2805 
2806     if (p -> LPW_21_NC == 0 && p -> LPW_22_TAL == 0)
2807       {
2808         // XXX see pat. 46-51 re: SEG
2809         // 256K OVERFLOW?
2810         if (p -> LPW_20_AE == 0 &&
2811             (((word36) p -> LPW_DCW_PTR) + ((word36) p -> LPW_TALLY)) >
2812             01000000llu)
2813           {
2814             iom_fault (iom_unit_idx, IOM_CONNECT_CHAN, __func__,
2815                       p -> lsFirst ? iomFsrFirstList : iomFsrList,
2816                       iom256KFlt);
2817             return -1;
2818           }
2819        }
2820     else if (p -> LPW_21_NC == 0 && p -> LPW_22_TAL == 1)
2821       { // 01
2822 A:;
2823         // TALLY is {0, 1, >1}?
2824 
2825         if (p -> LPW_TALLY == 0)
2826           {
2827             uff = true;
2828           }
2829         else if (p -> LPW_TALLY > 1)
2830           { // 00
2831 
2832             // XXX see pat. 46-51 re: SEG
2833             // 256K OVERFLOW?
2834             if (p -> LPW_20_AE == 0 &&
2835                 (((word36) p -> LPW_DCW_PTR) + ((word36) p -> LPW_TALLY)) >
2836                 01000000llu)
2837               {
2838                 iom_fault (iom_unit_idx, IOM_CONNECT_CHAN, __func__,
2839                           p -> lsFirst ? iomFsrFirstList : iomFsrList,
2840                           iom256KFlt);
2841                 return -1;
2842               }
2843           }
2844       }
2845 
2846     // LPW 20? -- LPW_20 checked by fetch_and_parse_DCW
2847 
2848     // PULL DCW FROM CORE
2849     fetch_and_parse_DCW (iom_unit_idx, chan, false);
2850 
2851 // C
2852 
2853     // IDCW ?
2854 
2855     if (IS_IDCW (p))
2856       {
2857         // LPW_18_RES?
2858 
2859         if (p -> LPW_18_RES)
2860           {
2861             // SET USER FAULT FLAG
2862             uff = true; // XXX Why? uff isn't not examined later.
2863             // send = false; implicit...
2864           }
2865         else
2866           {
2867             // SEND IDCW TO CHANNEL
2868             // p -> DCW = p -> DCW;
2869             send = true;
2870           }
2871         p -> LPWX_SIZE = p -> LPW_DCW_PTR;
2872         goto D;
2873       }
2874 
2875 // Not IDCW
2876 
2877     if (p -> lsFirst)
2878       p -> LPWX_SIZE = p -> LPW_DCW_PTR;
2879 
2880 // pg B16: "If the IOM is paged [yes] and PCW bit 64 is off, LPW bit 23
2881 //          is ignored by the hardware. If bit 64 is set, LPW bit 23 causes
2882 //          the data to become segmented."
2883 // Handled in fetch_and_parse_LPW
2884 
2885     // LPW 23 REL?
2886 
2887     // TDCW ?
2888 
2889     if (IS_TDCW (p))
2890       {
2891         // SECOND TDCW?
2892         if (p -> wasTDCW)
2893           {
2894             uff = true;
2895             goto uffSet;
2896           }
2897         p -> wasTDCW = true;
2898 
2899         // PUT ADDRESS N LPW
2900 
2901         p -> LPW_DCW_PTR = p -> TDCW_DATA_ADDRESS;
2902         // OR TDCW 33, 34, 35 INTO LPW 20, 18, 23
2903         // XXX is 33 bogus? its semantics change based on PCW 64...
2904         // should be okay; pg B21 says that this is correct; implies that the
2905         // semantics are handled in the LPW code. Check...
2906         p -> LPW_20_AE  |= p -> TDCW_33_EC; // TDCW_33_PDCW
2907         p -> LPW_18_RES |= p -> TDCW_34_RES;
2908         p -> LPW_23_REL |= p -> TDCW_35_REL;
2909 
2910 // Pg B21: (TDCW_31_SEG)
2911 // "SEG = This bit furnishes the 19th address bit (MSD) of a TDCW address
2912 //  used for locating the DCW list in a 512 word page table. It will have
2913 //  meaning only in the TDCW where:
2914 //   (a) the DCW list is already paged and the TDCW calls for the
2915 //       DCW [to be] segmented
2916 //  or
2917 //   (b) the data is already segmented and the TDCW calls for the
2918 //       DCW list to be paged
2919 //  or
2920 //   (c) neither data is segmented nor DCW list is paged and the
2921 //       TDCW calls for both.
2922 //  and
2923 //   (d) an auxiliary PTW in not being used.
2924 
2925 //   (a) the DCW list is already paged   --  LPW PAGED: 3b, 4
2926 //       and the TDCW calls for the
2927 //       DCW [list to be] segmented      --  LPW SEG:       5
2928 
2929 //   (b) the data is already segmented   --  DCW SEG:   3a, 4
2930 //       and the TDCW calls for the
2931 //       DCW list to be paged            --  DCW PAGED:  2, 3b
2932 
2933 //   (c) neither data is segmented       -- DCW !SEG     1, 2, 3b
2934 //       nor DCW list is paged           -- LPW !PAGED   1, 2, 3a
2935 //                                       --              1, 2
2936 //       and the TDCW calls for both.    -- DCW SEG & LPW PAGED
2937 //                                                       4
2938 
2939 //put that weird SEG logic in here
2940 
2941         if (p -> TDCW_31_SEG)
2942           sim_warn ("TDCW_31_SEG\r\n");
2943 
2944         update_chan_mode (iom_unit_idx, chan, true);
2945 
2946         // Decrement tally
2947         p->LPW_TALLY = ((word12) (((word12s) p->LPW_TALLY) - 1)) & MASK12;
2948 
2949         pack_LPW (iom_unit_idx, chan);
2950 
2951         // AC CHANGE ERROR? (LPW 18 == 1 && DCW 33 == 1)
2952 
2953         if (p -> LPW_18_RES && p -> TDCW_33_EC) // same as TDCW_33_PDCW
2954           {
2955             uff = true;
2956             goto uffSet;
2957           }
2958 
2959         goto A;
2960       }
2961 
2962     p -> wasTDCW = false;
2963     // NOT TDCW
2964 
2965     // CP VIOLATION?
2966 
2967     // 43A239854 3.2.3.3 "The byte size, defined by the channel, determines
2968     // what CP values are valid..."
2969 
2970     // If we get here, the DCW is not a IDCW and not a TDCW, therefore
2971     // it must be a DDCW. If the list service knew the sub-word size
2972     // size of the device, it could check the for valid values. Let
2973     // the device handler do that later.
2974 
2975     // if (cp decrepancy)
2976     //   {
2977     //      user_fault_flag = iomCsCpDiscrepancy;
2978     //      goto user_fault;
2979     //   }
2980     // if (cp violation)
2981     //   {
2982     //     uff = true;
2983     //     goto uffSet;
2984     //   }
2985 
2986     // USER FAULT FLAG SET?
2987 
2988     if (uff)
2989       {
2990 uffSet:;
2991         // PUT 7 into DCW 18-20
2992         p -> DCW_18_20_CP = 07u;
2993         pack_DCW (iom_unit_idx, chan);
2994       }
2995 
2996     // WRITE DCW IN [SCRATCH PAD] MAILBOX
2997 
2998     // p -> DVW  = P -> DCW;
2999 
3000     // SEND DCW TO CHANNEL
3001 
3002     // p -> DCW = p -> DCW;
3003     send = true;
3004 
3005     // goto D;
3006 
3007 D:;
3008 
3009     // SEND FLAGS TO CHANNEL
3010 
3011     * uffp  = uff;
3012     * sendp = send;
3013 
3014     // LPW 21 ?
3015 
3016     if (p -> LPW_21_NC == 0) // UPDATE
3017      {
3018        // UPDATE LPW ADDRESS & TALLY
3019        if (isConnChan)
3020          p -> LPW_DCW_PTR = (p -> LPW_DCW_PTR + 2u) & MASK18;
3021        else
3022          p -> LPW_DCW_PTR = (p -> LPW_DCW_PTR + 1u) & MASK18;
3023        // ubsan
3024        p->LPW_TALLY = ((word12) (((word12s) p->LPW_TALLY) - 1)) & MASK12;
3025        pack_LPW (iom_unit_idx, chan);
3026      }
3027 
3028     // IDCW OR FIRST LIST
3029     if (p -> DDCW_22_23_TYPE == 07u || p -> lsFirst)
3030       {
3031         // WRITE LPW & LPW EXT. INTO BOTH SCRATCHPAD AND CORE MAILBOXES
3032         // scratch pad
3033         // p -> lpw = p -> lpw
3034         // core
3035         write_LPW (iom_unit_idx, chan);
3036       }
3037     else
3038       {
3039         if (p -> LPW_21_NC == 0 ||
3040             (IS_TDCW (p)))
3041           {
3042             // WRITE LPW INTO BOTH SCRATCHPAD AND CORE MAILBOXES
3043             // scratch pad
3044             // p -> lpw = p -> lpw
3045             // core
3046             write_LPW (iom_unit_idx, chan);
3047           }
3048       }
3049 
3050     p -> lsFirst = false;
3051     // END
3052 
3053     return 0;
3054   }
3055 
3056 // 0 ok
3057 // -1 uff
3058 static int doPayloadChannel (uint iomUnitIdx, uint chan) {
     /*  */
3059 #if defined(TESTING)
3060   cpu_state_t * cpup = _cpup;
3061   sim_debug (DBG_DEBUG, & iom_dev, "%s: Payload channel %c%02o\r\n", __func__, iomChar (iomUnitIdx), chan);
3062 #endif
3063 // A dubious assumption being made is that the device code will always
3064 // be in bits 6-12 of the DCw. Normally, the controller would
3065 // decipher the device code and route to the device, but we
3066 // have elided the controllers and must do that ourselves.
3067 
3068 // Loop logic
3069 //
3070 //   The DCW list can be terminated two ways; either by having the
3071 //   tally run out, or a IDCW with control set to zero.
3072 //
3073 //   The device handler will absorb DDCWs
3074 //
3075 // loop until:
3076 //
3077 //  listService sets ptro, indicating that no more DCWs are available. or
3078 //     control is 0, indicating last IDCW
3079 
3080   iom_chan_data_t * p = & iom_chan_data[iomUnitIdx][chan];
3081 
3082 #if defined(TESTING)
3083   word36 PCW_DCW        = p->DCW;
3084   word1  PCW_LPW_23_REL = p->LPW_23_REL;
3085 #endif
3086   p -> chanMode   = cm1;
3087   p -> LPW_18_RES = 0;
3088   p -> LPW_20_AE  = 0;
3089   p -> LPW_23_REL = 0;
3090 
3091   unpack_DCW (iomUnitIdx, chan);
3092 
3093   p->isPCW = true;
3094 
3095   // Masked is set in doConnectChannel
3096   //p->masked = !!p->PCW_21_MSK;
3097   struct iom_to_ctlr_s * d = & cables->iom_to_ctlr[iomUnitIdx][chan];
3098 
3099 // A device command of 051 in the PCW is only meaningful to the operator console;
3100 // all other channels should ignore it. We use (somewhat bogusly) a chanType of
3101 // chanTypeCPI to indicate the operator console.
3102   if (d->chan_type != chan_type_CPI && p -> IDCW_DEV_CMD == 051) {
3103     p->stati = 04501;
3104     send_terminate_interrupt (iomUnitIdx, chan);
3105     return 0;
3106   }
3107 
3108   if ((!d->in_use) || (!d->iom_cmd)) {
3109     p -> stati = 06000; // t, power off/missing
3110 #if defined(POLTS_TESTING)
3111 if (chan == 014)      if_sim_debug (DBG_TRACE, & iom_dev) sim_printf \
3112                         ("// terminate 10. ctrl == 0 in chan %d (%o) DCW\r\n", chan, chan);
3113 #endif
3114     goto terminate;
3115   }
3116 
3117 // 3.2.2. "Bits 12-17 [of the PCW] contain the address extension which is maintained by
3118 //         the channel for subsequent use by the IOM in generating a 24-bit
3119 //         address for list of data services for the extended address modes."
3120 // see also 3.2.3.1
3121   p -> ADDR_EXT     = p -> PCW_AE;
3122 
3123   p -> lsFirst      = true;
3124 
3125   p -> tallyResidue = 0;
3126   p -> isRead       = true;
3127   p -> charPos      = 0;
3128 // As far as I can tell, initiate false means that an IOTx succeeded in
3129 // transferring data; assume it didn't since that is the most common
3130 // code path.
3131   p -> initiate     = true;
3132   p -> chanStatus   = chanStatNormal;
3133 
3134 //
3135 // Send the PCW's DCW
3136 //
3137   int rc = d->iom_cmd (iomUnitIdx, chan);
3138 
3139   if (rc < 0) {
3140     p -> dev_code = getbits36_6 (p -> DCW, 6);
3141 #if defined(POLTS_TESTING)
3142 if (chan == 014)      if_sim_debug (DBG_TRACE, & iom_dev) \
3143                         sim_printf ("// terminate 9. ctrl == 0 in chan %d (%o) DCW\r\n", chan, chan);
3144 #endif
3145     goto terminate;
3146   }
3147 
3148   if (IS_IDCW (p) && p->IDCW_CHAN_CTRL == CHAN_CTRL_MARKER) { // IDCW marker bit set
3149     send_marker_interrupt (iomUnitIdx, (int) chan);
3150   }
3151 
3152   if (rc == IOM_CMD_DISCONNECT) {
3153 #if defined(POLTS_TESTING)
3154 if (chan == 014)      if_sim_debug (DBG_TRACE, & iom_dev) sim_printf \
3155                         ("// terminate 8. ctrl == 0 in chan %d (%o) DCW\r\n", chan, chan);
3156 #endif
3157     goto terminate;
3158   }
3159 
3160   if (p->masked) {
3161 #if defined(POLTS_TESTING)
3162 if (chan == 014)      if_sim_debug (DBG_TRACE, & iom_dev) sim_printf \
3163                         ("// terminate 7. ctrl == 0 in chan %d (%o) DCW\r\n", chan, chan);
3164 #endif
3165     goto terminate;
3166   }
3167 
3168   bool ptro, send, uff;
3169   bool terminate = false;
3170   p->isPCW       = false;
3171 
3172 #if defined(TESTING)
3173   bool first = true;
3174 #endif
3175 
3176   (void)terminate;
3177   bool idcw_terminate = p -> IDCW_CHAN_CTRL == CHAN_CTRL_TERMINATE;
3178   do {
3179     int rc2 = iom_list_service (iomUnitIdx, chan, & ptro, & send, & uff);
3180     if (rc2 < 0) {
3181 // XXX set status flags
3182       sim_warn ("%s list service failed\r\n", __func__);
3183       return -1;
3184     }
3185     if (uff) {
3186       // We get a uff if the LPW tally hit 0
3187 #if defined(POLTS_TESTING)
3188 if (chan == 014)      if_sim_debug (DBG_TRACE, & iom_dev) \
3189                         sim_printf ("// terminate 6. ctrl == 0 in chan %d (%o) DCW\r\n", chan, chan);
3190 #endif
3191       goto terminate;
3192     }
3193     // List service failed to get a DCW
3194     if (! send) {
3195       sim_warn ("%s nothing to send\r\n", __func__);
3196       return 1;
3197     }
3198 
3199 #if defined(TESTING)
3200 # if defined(POLTS_TESTING)
3201 if (iomUnitIdx == 1 && chan == 020)
3202 # endif
3203     if_sim_debug (DBG_TRACE, & iom_dev) {
3204       if (first) {
3205         first = false;
3206         dumpLPW (iomUnitIdx, chan);
3207         sim_printf ("// DCW list dump: \r\n");
3208         dumpDCW (PCW_DCW, PCW_LPW_23_REL);
3209         for (int i = 0; i < 8; i ++)
3210           dumpDCW (M[p->LPW_DCW_PTR - 1 + i], p->LPW_23_REL);
3211         sim_printf ("// \r\n");
3212       }
3213     }
3214 #endif
3215 
3216 // 3.2.3.1 "If EC - Bit 21 = 1, The channel will replace the present address
3217 //          extension with the new address extension in bits 12-17. ... In
3218 //          Multics and NSA systems, EC is inhibited from the payload channel
3219 //          if LPW bit 23 = 1.
3220 
3221     if (IS_IDCW (p)) { // IDCW
3222       idcw_terminate = p -> IDCW_CHAN_CTRL == CHAN_CTRL_TERMINATE;
3223       if (p -> LPW_23_REL == 0 && p -> IDCW_EC == 1)
3224         p -> ADDR_EXT = getbits36_6 (p -> DCW, 12);
3225 
3226       p -> tallyResidue = 0;
3227       p -> isRead       = true;
3228       p -> charPos      = 0;
3229       p -> chanStatus   = chanStatNormal;
3230     }
3231 
3232 // Send the DCW list's DCW
3233 
3234     rc2 = d->iom_cmd (iomUnitIdx, chan);
3235 
3236     if (rc2 < 0) {
3237       p -> dev_code = getbits36_6 (p -> DCW, 6);
3238 #if defined(POLTS_TESTING)
3239 if (chan == 014)      if_sim_debug (DBG_TRACE, & iom_dev) \
3240                         sim_printf ("// terminate 5. ctrl == 0 in chan %d (%o) DCW\r\n", chan, chan);
3241 #endif
3242       goto terminate;
3243     }
3244 
3245     if (rc2 == IOM_CMD_DISCONNECT) {
3246       terminate = true;
3247 #if defined(POLTS_TESTING)
3248 if (chan == 014)      if_sim_debug (DBG_TRACE, & iom_dev) sim_printf \
3249                         ("// terminate 4. ctrl == 0 in chan %d (%o) DCW\r\n", chan, chan);
3250 #endif
3251     }
3252 
3253     if (rc2 == IOM_CMD_PENDING) // handler still processing command, don't set
3254       goto pending;             // terminate interrupt.
3255 
3256     // If IDCW and terminate and nondata
3257     if (IS_IDCW (p) && p->IDCW_CHAN_CTRL == CHAN_CTRL_TERMINATE && p->IDCW_CHAN_CMD == CHAN_CMD_NONDATA) {
3258 #if defined(POLTS_TESTING)
3259 if (chan == 014)      if_sim_debug (DBG_TRACE, & iom_dev) \
3260                         sim_printf ("// terminate 1. ctrl == 0 in chan %d (%o) DCW\r\n", chan, chan);
3261 #endif
3262       goto terminate;
3263     }
3264     // If IOTD and last IDCW was terminate
3265     if (IS_IOTD (p) && idcw_terminate && rc2 != IOM_CMD_RESIDUE) {
3266 #if defined(POLTS_TESTING)
3267 //if (iomUnitIdx == 1 && chan == 020)      if_sim_debug (DBG_TRACE, & iom_dev)
3268 //                                           sim_printf ("// ctrl == 0 in chan %d (%o) IOTP\r\n", chan, chan);
3269 if (chan == 014)      if_sim_debug (DBG_TRACE, & iom_dev) \
3270                         sim_printf ("// terminate 2. ctrl == 0 in chan %d (%o) DCW\r\n", chan, chan);
3271 #endif
3272       goto terminate;
3273     }
3274 
3275     // IOM_CMD_RESIDUE: Continue pushing DCWS until the record residue is 0
3276 
3277     if (IS_NOT_IDCW (p) && rc2 == IOM_CMD_RESIDUE) {
3278       if (p->recordResidue)
3279         p->recordResidue --;
3280       if (p->recordResidue == 0)
3281         goto terminate;
3282     }
3283   } while (! terminate);
3284 
3285 terminate:;
3286 #if defined(POLTS_TESTING)
3287 if (iomUnitIdx == 1 && chan == 020) sim_printf ("stati %04o\r\n", p->stati);
3288 #endif
3289   send_terminate_interrupt (iomUnitIdx, chan);
3290   return 0;
3291 
3292 pending:;
3293   return 0;
3294 }
3295 
3296 // doConnectChan ()
3297 //
3298 // Process the "connect channel".  This is what the IOM does when it
3299 // receives a $CON signal.
3300 //
3301 // Only called by iom_interrupt ()
3302 //
3303 // The connect channel requests one or more "list services" and processes the
3304 // resulting PCW control words.
3305 //
3306 
3307 static int doConnectChan (uint iom_unit_idx) {
     /*  */
3308   // ... the connect channel obtains a list service from the IOM Central.
3309   // During this service the IOM Central will do a double precision read
3310   // from the core, under the control of the LPW for the connect channel.
3311   //
3312   // If the IOM Central does not indicate a PTRO during the list service,
3313   // the connect channel obtains another list service.
3314   //
3315   // The connect channel does not interrupt or store status.
3316   //
3317   // The DCW and SCW mailboxes for the connect channel are not used by
3318   // the IOM.
3319 #if defined(TESTING)
3320   cpu_state_t * cpup = _cpup;
3321 #endif
3322   sim_debug (DBG_DEBUG, & iom_dev, "%s: Connect channel\r\n", __func__);
3323   iom_chan_data_t * p = & iom_chan_data[iom_unit_idx][IOM_CONNECT_CHAN];
3324   p -> lsFirst = true;
3325 #if defined(TESTING) && defined(POLTS_TESTING)
3326   bool first = true;
3327 #endif
3328   bool ptro, send, uff;
3329   do {
3330     // Fetch the next PCW
3331     int rc = iom_list_service (iom_unit_idx, IOM_CONNECT_CHAN, & ptro, & send, & uff);
3332     if (rc < 0) {
3333       sim_warn ("connect channel connect failed\r\n");
3334       return -1;
3335     }
3336     if (uff) {
3337       sim_warn ("connect channel ignoring uff\r\n"); // XXX
3338     }
3339     if (! send) {
3340       sim_warn ("connect channel nothing to send\r\n");
3341     } else {
3342 #if defined(xTESTING)
3343       if_sim_debug (DBG_TRACE, & iom_dev) {
3344         if (first) {
3345           first = false;
3346           sim_printf ("// CIOC %lld\r\n", cpu.cycleCnt);
3347           dumpLPW (iom_unit_idx, IOM_CONNECT_CHAN);
3348           sim_printf ("// PCW %012llo %012llo\r\n",    p->PCW0, p->PCW1);
3349           sim_printf ("//   Chan info     %04o\r\n",   p->PCW_CHAN);
3350           sim_printf ("//   Addr ext        %02o\r\n", p->PCW_AE);
3351           sim_printf ("//   111              %o\r\n",  getbits36_3 (p->PCW0, 18));
3352           sim_printf ("//   M                %o\r\n",  p->PCW_21_MSK);
3353           sim_printf ("//   Chan info %08o\r\n",       getbits36_14 (p->PCW0, 22));
3354           sim_printf ("//   Pg Tbl Ptr  %06o\r\n",     p->PCW_PAGE_TABLE_PTR);
3355           sim_printf ("//   PTP              %o\r\n",  p->PCW_63_PTP);
3356           sim_printf ("//   PGE              %o\r\n",  p->PCW_64_PGE);
3357           sim_printf ("//   AUX              %o\r\n",  p->PCW_65_AUX);
3358           sim_printf ("//\r\n");
3359         }
3360       }
3361 #endif
3362       // Copy the PCW's DCW to the payload channel
3363       iom_chan_data_t * q = & iom_chan_data[iom_unit_idx][p -> PCW_CHAN];
3364 
3365       q -> PCW0               = p -> PCW0;
3366       q -> PCW1               = p -> PCW1;
3367       q -> PCW_CHAN           = p -> PCW_CHAN;
3368       q -> PCW_AE             = p -> PCW_AE;
3369       q -> PCW_PAGE_TABLE_PTR = p -> PCW_PAGE_TABLE_PTR;
3370       q -> PCW_63_PTP         = p -> PCW_63_PTP;
3371       q -> PCW_64_PGE         = p -> PCW_64_PGE;
3372       q -> PCW_65_AUX         = p -> PCW_65_AUX;
3373       q -> PCW_21_MSK         = p -> PCW_21_MSK;
3374       q -> DCW                = p -> DCW;
3375 
3376       sim_debug (DBG_DEBUG, & iom_dev, "%s: PCW %012llo %012llo chan %02o\r\n", __func__, q->PCW0, q->PCW1, q->PCW_CHAN);
3377 
3378       q -> masked = p -> PCW_21_MSK;
3379       if (q -> masked) {
3380         if (q -> in_use)
3381           sim_warn ("%s: chan %d masked while in use\r\n", __func__, p -> PCW_CHAN);
3382         q -> in_use = false;
3383         q -> start  = false;
3384       } else {
3385         if (q -> in_use)
3386           sim_warn ("%s: chan %d connect while in use\r\n", __func__, p -> PCW_CHAN);
3387         q -> in_use = true;
3388         q -> start  = true;
3389 #if defined(IO_THREADZ)
3390         setChnConnect (iom_unit_idx, p -> PCW_CHAN);
3391 #else
3392 # if !defined(IO_ASYNC_PAYLOAD_CHAN) && !defined(IO_ASYNC_PAYLOAD_CHAN_THREAD)
3393         doPayloadChannel (iom_unit_idx, p -> PCW_CHAN);
3394 # endif
3395 # if defined(IO_ASYNC_PAYLOAD_CHAN_THREAD)
3396         pthread_cond_signal (& iomCond);
3397 # endif
3398 #endif
3399       }
3400     }
3401   } while (! ptro);
3402   return 0; // XXX
3403 }
3404 
3405 /*
3406  * send_marker_interrupt ()
3407  *
3408  * Send a "marker" interrupt to the CPU.
3409  *
3410  * Channels send marker interrupts to indicate normal completion of
3411  * a PCW or IDCW if the control field of the PCW/IDCW has a value
3412  * of three.
3413  */
3414 
3415 int send_marker_interrupt (uint iom_unit_idx, int chan)
     /*  */
3416   {
3417     if (iom_chan_data [iom_unit_idx] [chan] . masked)
3418       return(0);
3419     status_service (iom_unit_idx, (uint) chan, true);
3420     return send_general_interrupt (iom_unit_idx, (uint) chan, imwMarkerPic);
3421   }
3422 
3423 /*
3424  * send_special_interrupt ()
3425  *
3426  * Send a "special" interrupt to the CPU.
3427  *
3428  */
3429 
3430 int send_special_interrupt (uint iom_unit_idx, uint chan, uint devCode,
     /*  */
3431                             word8 status0, word8 status1)
3432   {
3433 //if (iom_unit_idx == 0 && chan == 013) sim_printf ("spec int %03o %013o\r\n", status0, status1);
3434     uint chanloc = mbxLoc (iom_unit_idx, IOM_SPECIAL_STATUS_CHAN);
3435 
3436     if (iom_chan_data [iom_unit_idx] [chan] . masked)
3437       return(0);
3438 
3439 #if defined(LOCKLESS)
3440     lock_iom();
3441 #endif
3442 
3443 // Multics uses an 12(8) word circular queue, managed by clever manipulation
3444 // of the LPW and DCW.
3445 // Rather then goes through the mechanics of parsing the LPW and DCW,
3446 // we will just assume that everything is set up the way we expect,
3447 // and update the circular queue.
3448     word36 lpw;
3449     iom_core_read (iom_unit_idx, chanloc + IOM_MBX_LPW, & lpw, __func__);
3450 
3451     word36 scw;
3452     iom_core_read (iom_unit_idx, chanloc + IOM_MBX_SCW, & scw, __func__);
3453 
3454     word36 dcw;
3455     iom_core_read_lock (iom_unit_idx, chanloc + IOM_MBX_DCW, & dcw, __func__);
3456 
3457     word36 status  = 0400000000000ull;
3458     status        |= (((word36) chan)    & MASK6) << 27;
3459     status        |= (((word36) devCode) & MASK8) << 18;
3460     status        |= (((word36) status0) & MASK8) <<  9;
3461     status        |= (((word36) status1) & MASK8) <<  0;
3462     iom_core_write (iom_unit_idx, (dcw >> 18) & MASK18, status, __func__);
3463 
3464     uint tally = dcw & MASK12;
3465     if (tally > 1)
3466       {
3467         dcw -= 01llu;  // tally --
3468         dcw += 01000000llu; // addr ++
3469       }
3470     else
3471       dcw = scw; // reset to beginning of queue
3472     iom_core_write_unlock (iom_unit_idx, chanloc + IOM_MBX_DCW, dcw, __func__);
3473 
3474 #if defined(LOCKLESS)
3475     unlock_iom();
3476 #endif
3477 
3478     send_general_interrupt (iom_unit_idx, IOM_SPECIAL_STATUS_CHAN, imwSpecialPic);
3479     return 0;
3480   }
3481 
3482 /*
3483  * send_terminate_interrupt ()
3484  *
3485  * Send a "terminate" interrupt to the CPU.
3486  *
3487  * Channels send a terminate interrupt after doing a status service.
3488  *
3489  */
3490 
3491 int send_terminate_interrupt (uint iom_unit_idx, uint chan)
     /*  */
3492   {
3493     if (iom_chan_data [iom_unit_idx] [chan] . masked)
3494       return 0;
3495     status_service (iom_unit_idx, chan, false);
3496     if (iom_chan_data [iom_unit_idx] [chan] . in_use == false)
3497       sim_warn ("%s: chan %d not in use\r\n", __func__, chan);
3498     iom_chan_data [iom_unit_idx] [chan] . in_use = false;
3499     send_general_interrupt (iom_unit_idx, chan, imwTerminatePic);
3500     return 0;
3501   }
3502 
3503 void iom_interrupt (uint scu_unit_idx, uint iom_unit_idx)
     /*  */
3504   {
3505     cpu_state_t * cpup = _cpup;
3506     sim_debug (DBG_DEBUG, & iom_dev,
3507                "%s: IOM %c starting. [%"PRId64"] %05o:%08o\r\n",
3508                __func__, iomChar (iom_unit_idx), cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC);
3509 
3510     iom_unit_data[iom_unit_idx].invokingScuUnitIdx = scu_unit_idx;
3511 
3512 #if defined(IO_THREADZ)
3513     setIOMInterrupt (iom_unit_idx);
3514     iomDoneWait (iom_unit_idx);
3515 #else
3516     int ret = doConnectChan (iom_unit_idx);
3517 
3518     sim_debug (DBG_DEBUG, & iom_dev,
3519                "%s: IOM %c finished; doConnectChan returned %d.\r\n",
3520                __func__, iomChar (iom_unit_idx), ret);
3521 #endif
3522     // XXX doConnectChan return value ignored
3523   }
3524 
3525 #if defined(IO_THREADZ)
3526 void * chan_thread_main (void * arg)
     /*  */
3527   {
3528     uint myid     = (uint) * (int *) arg;
3529     this_iom_idx  = (uint) myid / MAX_CHANNELS;
3530     this_chan_num = (uint) myid % MAX_CHANNELS;
3531 
3532 // Set CPU context to allow sim_debug to work
3533 
3534     set_cpu_idx (0);
3535 
3536     sim_msg ("\rIOM %c Channel %u thread created\r\n", this_iom_idx + 'a', this_chan_num);
3537 # if defined(TESTING)
3538     printPtid(pthread_self());
3539 # endif /* if defined(TESTING) */
3540     if (realtime_ok) {
3541       set_realtime_priority (pthread_self(), realtime_max_priority() - 1);
3542       check_realtime_priority (pthread_self(), realtime_max_priority() - 1);
3543     } else {
3544 # if !defined(__QNX__)
3545       (void)sim_os_set_thread_priority (PRIORITY_ABOVE_NORMAL);
3546 # endif
3547     }
3548 
3549     setSignals ();
3550     while (1)
3551       {
3552 //sim_printf("IOM %c Channel %u thread waiting\r\n", this_iom_idx + 'a', this_chan_num);
3553         chnConnectWait ();
3554 //sim_printf("IOM %c Channel %u thread running\r\n", this_iom_idx + 'a', this_chan_num);
3555         doPayloadChannel (this_iom_idx, this_chan_num);
3556         chnConnectDone ();
3557       }
3558   }
3559 
3560 void * iom_thread_main (void * arg)
     /*  */
3561   {
3562     int myid = * (int *) arg;
3563     this_iom_idx = (uint) myid;
3564 
3565 // Set CPU context to allow sim_debug to work
3566 
3567     set_cpu_idx (0);
3568 
3569     sim_printf("IOM %c thread created\r\n", 'a' + myid);
3570 
3571     setSignals ();
3572     while (1)
3573       {
3574 //sim_printf("IOM %c thread waiting\r\n", 'a' + myid);
3575         iomInterruptWait ();
3576 //sim_printf("IOM %c thread running\r\n", 'a' + myid);
3577         int ret = doConnectChan (this_iom_idx);
3578 
3579         sim_debug (DBG_DEBUG, & iom_dev,
3580                    "%s: IOM %c finished; doConnectChan returned %d.\r\n",
3581                    __func__, iomChar (myid), ret);
3582         iomInterruptDone ();
3583       }
3584   }
3585 #endif
3586 
3587 /*
3588  * iom_init ()
3589  *
3590  *  Once-only initialization
3591  */
3592 
3593 void iom_init (void)
     /*  */
3594   {
3595     //sim_debug (DBG_INFO, & iom_dev, "%s: running.\r\n", __func__);
3596   }
3597 
3598 #if defined(PANEL68)
3599 void do_boot (void)
     /*  */
3600   {
3601     boot_svc (& boot_channel_unit[0]);
3602   }
3603 #endif
3604 
3605 #if defined(IO_ASYNC_PAYLOAD_CHAN) || defined(IO_ASYNC_PAYLOAD_CHAN_THREAD)
3606 void iomProcess (void)
     /*  */
3607   {
3608     for (uint i = 0; i < N_IOM_UNITS_MAX; i++)
3609       for (uint j = 0; j < MAX_CHANNELS; j++)
3610         {
3611           iom_chan_data_t * p = &iom_chan_data [i] [j];
3612           if (p -> start)
3613             {
3614               p -> start = false;
3615               doPayloadChannel (i, j);
3616             }
3617         }
3618   }
3619 #endif
3620 
3621 char iomChar (uint iomUnitIdx)
     /*  */
3622   {
3623     return (iom_unit_data[iomUnitIdx].configSwMultiplexBaseAddress & 3) + 'A';
3624   }
3625
/* */
root/src/dps8/dps8_iom.c

DEFINITIONS
