root/src/dps8/ucache.c

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DEFINITIONS

This source file includes following definitions.
  1. ucInvalidate
  2. ucacheStats
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 70f11728-171b-11ee-ac22-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2022 Charles Anthony
   9  * Copyright (c) 2022-2024 The DPS8M Development Team
  10  *
  11  * This software is made available under the terms of the ICU License.
  12  * See the LICENSE.md file at the top-level directory of this distribution.
  13  *
  14  * ---------------------------------------------------------------------------
  15  */
  16 
  17 #include <string.h>
  18 
  19 #include "dps8.h"
  20 #include "dps8_cpu.h"
  21 
  22 void ucInvalidate (cpu_state_t * cpup) {
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  23   (void)memset (cpu.uCache.caches, 0, sizeof (cpu.uCache.caches));
  24 }
  25 
  26 void ucCacheSave \
  27          (cpu_state_t * cpup, uint ucNum, word15 segno, word18 offset, word14 bound,
  28           word1 p, word24 address, word3 r1, bool paged) {
  29   if (segno >= UC_CACHE_SZ) {
  30     return;
  31   }
  32   ucache_t * ep;
  33   ep          = & cpu.uCache.caches[ucNum][segno];
  34   ep->valid   = true;
  35   ep->segno   = segno;
  36   ep->offset  = offset;
  37   ep->bound   = bound;
  38   ep->address = address;
  39   ep->r1      = r1;
  40   ep->p       = p;
  41   ep->paged   = paged;
  42 #if defined(HDBG)
  43   hdbgNote ("ucache", "save %u %05o:%06o %05o %o %08o %o %o",
  44             ucNum, segno, offset, bound, p, address, r1, paged);
  45 #endif
  46 }
  47 
  48 bool ucCacheCheck \
  49          (cpu_state_t * cpup, uint ucNum, word15 segno, word18 offset, word14 * bound,
  50           word1 * p, word24 * address, word3 * r1, bool * paged) {
  51   if (segno >= UC_CACHE_SZ) {
  52 #if defined(UCACHE_STATS)
  53     cpu.uCache.segnoSkips ++;
  54 #endif
  55     return false;
  56   }
  57   ucache_t * ep;
  58   ep = & cpu.uCache.caches[ucNum][segno];
  59   // Is cache entry valid?
  60   if (! ep->valid) {
  61 #if defined(HDBG)
  62     hdbgNote ("ucache", "check not valid");
  63 #endif
  64     goto miss;
  65   }
  66 
  67 
  68 
  69 
  70 
  71 
  72 
  73 
  74 
  75   // Same page?
  76   if (ep->paged && ((ep->offset & PG18MASK) != (offset & PG18MASK))) {
  77 #if defined(HDBG)
  78     hdbgNote ("ucache", "pgno %o != %o\r\n", (ep->offset & PG18MASK), (offset & PG18MASK));
  79 #endif
  80     goto miss;
  81   }
  82   // In bounds?
  83   if (((offset >> 4) & 037777) > ep->bound) {
  84     //sim_printf ("bound %o != %o\r\n", ((offset >> 4) & 037777), ep->bound);
  85 #if defined(HDBG)
  86     hdbgNote ("ucache", "bound %o != %o\r\n", ((offset >> 4) & 037777), ep->bound);
  87 #endif
  88     goto miss;
  89   }
  90 #if defined(HDBG)
  91   hdbgNote ("ucache", "hit %u %05o:%06o %05o %o %08o %o %o",
  92             ucNum, segno, offset, ep->bound, ep->p, ep->address, ep->r1, ep->paged);
  93 #endif
  94   * bound = ep->bound;
  95 
  96 
  97 
  98 
  99 
 100 
 101 
 102 
 103 
 104 
 105 
 106 
 107 
 108 
 109   * address = ep->address;
 110 
 111   * r1      = ep->r1;
 112   * p       = ep->p;
 113   * paged   = ep->paged;
 114 #if defined(UCACHE_STATS)
 115   cpu.uCache.hits[ucNum] ++;
 116 #endif
 117   return true;
 118 miss:;
 119 #if defined(UCACHE_STATS)
 120   cpu.uCache.misses[ucNum] ++;
 121 #endif
 122   return false;
 123 }
 124 
 125 #if defined(UCACHE_STATS)
 126 void ucacheStats (int cpuNo) {
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 127   (void)fflush(stdout);
 128   (void)fflush(stderr);
 129   sim_msg ("\r\n|   CPU %c Micro-cache Statistics  |", 'A' + cpuNo);
 130   sim_msg ("\r\n+---------------------------------+\r\n");
 131 # define pct(a, b) ((b) ? (a) * 100.0 / ((a) + (b)) : 0)
 132 # define args(a, b, c) a, b, c, pct (a, (b + c))
 133 # define stats(n) args ( (long long unsigned)cpus[cpuNo].uCache.hits  [n], \
 134                          (long long unsigned)cpus[cpuNo].uCache.misses[n], \
 135                          (long long unsigned)cpus[cpuNo].uCache.skips [n] )
 136   (void)fflush(stdout);
 137   (void)fflush(stderr);
 138 # if defined(WIN_STDIO)
 139   sim_msg ("\r|  Instruction Fetch:             |\r\n|    Hits        %15llu  |"
 140            "\r\n|    Misses      %15llu  |\r\n|    Skipped     %15llu  |"
 141            "\r\n|    Effectiveness   %10.2f%%  |\r\n",
 142            stats (UC_INSTRUCTION_FETCH));
 143   (void)fflush(stdout);
 144   (void)fflush(stderr);
 145   sim_msg ("\r+---------------------------------+\r\n");
 146   sim_msg ("\r|  Operand Read:                  |\r\n|    Hits        %15llu  |"
 147            "\r\n|    Misses      %15llu  |\r\n|    Skipped     %15llu  |"
 148            "\r\n|    Effectiveness   %10.2f%%  |\r\n",
 149            stats (UC_OPERAND_READ));
 150   (void)fflush(stdout);
 151   (void)fflush(stderr);
 152 #  if defined(IDWF_CACHE)
 153   sim_msg ("\r+---------------------------------+\r\n");
 154   sim_msg ("\r|  Indirect Word Fetch:           |\r\n|    Hits        %15llu  |"
 155            "\r\n|    Misses      %15llu  |\r\n|    Skipped     %15llu  |"
 156            "\r\n|    Effectiveness   %10.2f%%  |\r\n",
 157            stats (UC_INDIRECT_WORD_FETCH));
 158   (void)fflush(stdout);
 159   (void)fflush(stderr);
 160 #  endif
 161   sim_msg ("\r+---------------------------------+\r\n");
 162   sim_msg ("\r|  Cache Bypasses:                |\r\n");
 163   sim_msg ("\r|    RALR        %15llu  |\r\n",
 164            (long long unsigned)cpus[cpuNo].uCache.ralrSkips);
 165   sim_msg ("\r|    CALL6       %15llu  |\r\n",
 166            (long long unsigned)cpus[cpuNo].uCache.call6Skips);
 167   sim_msg ("\r|    Segno       %15llu  |\r\n",
 168            (long long unsigned)cpus[cpuNo].uCache.segnoSkips);
 169   (void)fflush(stdout);
 170   (void)fflush(stderr);
 171 # else
 172   sim_msg ("\r|  Instruction Fetch:             |\r\n|    Hits        %'15llu  |"
 173            "\r\n|    Misses      %'15llu  |\r\n|    Skipped     %'15llu  |"
 174            "\r\n|    Effectiveness   %'10.2f%%  |\r\n",
 175            stats (UC_INSTRUCTION_FETCH));
 176   (void)fflush(stdout);
 177   (void)fflush(stderr);
 178   sim_msg ("\r+---------------------------------+\r\n");
 179   sim_msg ("\r|  Operand Read:                  |\r\n|    Hits        %'15llu  |"
 180            "\r\n|    Misses      %'15llu  |\r\n|    Skipped     %'15llu  |"
 181            "\r\n|    Effectiveness   %'10.2f%%  |\r\n",
 182            stats (UC_OPERAND_READ));
 183   (void)fflush(stdout);
 184   (void)fflush(stderr);
 185 #  if defined(IDWF_CACHE)
 186   sim_msg ("\r+---------------------------------+\r\n");
 187   sim_msg ("\r|  Indirect Word Fetch:           |\r\n|    Hits        %'15llu  |"
 188            "\r\n|    Misses      %'15llu  |\r\n|    Skipped     %'15llu  |"
 189            "\r\n|    Effectiveness   %'10.2f%%  |\r\n",
 190            stats (UC_INDIRECT_WORD_FETCH));
 191   (void)fflush(stdout);
 192   (void)fflush(stderr);
 193 #  endif
 194   sim_msg ("\r+---------------------------------+\r\n");
 195   sim_msg ("\r|  Cache Bypasses:                |\r\n");
 196   sim_msg ("\r|    RALR        %'15llu  |\r\n",
 197            (long long unsigned)cpus[cpuNo].uCache.ralrSkips);
 198   sim_msg ("\r|    CALL6       %'15llu  |\r\n",
 199            (long long unsigned)cpus[cpuNo].uCache.call6Skips);
 200   sim_msg ("\r|    Segno       %'15llu  |\r\n",
 201            (long long unsigned)cpus[cpuNo].uCache.segnoSkips);
 202   (void)fflush(stdout);
 203   (void)fflush(stderr);
 204 # endif
 205   sim_msg ("\r+---------------------------------+\r\n");
 206   (void)fflush(stdout);
 207   (void)fflush(stderr);
 208 # undef pct
 209 # undef args
 210 # undef stats
 211 }
 212 #endif
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