IC 281 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 347 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 300 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 303 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 473 src/dps8/doAppendCycleIndirectWordFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 646 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.IC = cpu.TPR.CA; IC 669 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 354 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 747 src/dps8/doAppendCycleOperandRead.h cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; IC 760 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; IC 807 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; IC 818 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 308 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 368 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.IC = cpu.TPR.CA; IC 392 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 84 src/dps8/dps8_addrmods.c return cpu.PPR.IC; IC 2079 src/dps8/dps8_append.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; IC 2128 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; IC 2182 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; IC 2228 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 988 src/dps8/dps8_console.c cpus[i].PPR.IC, IC 980 src/dps8/dps8_cpu.c cpu.PPR.IC = 0; IC 2057 src/dps8/dps8_cpu.c { ORDATA (IC, dummy_IC, VASIZE), 0, 0, 0 }, IC 2059 src/dps8/dps8_cpu.c { ORDATA (IC, cpus[0].PPR.IC, VASIZE), 0, 0, 0 }, IC 2176 src/dps8/dps8_cpu.c sim_brk_test ((cpu.PPR.IC & 0777777) | IC 2513 src/dps8/dps8_cpu.c cpu.PPR.IC = cpu.lufXferIC; IC 2683 src/dps8/dps8_cpu.c cpus [0].PPR.IC = dummy_IC; IC 3047 src/dps8/dps8_cpu.c get_BAR_address (cpup, cpu.PPR.IC); IC 3068 src/dps8/dps8_cpu.c fetchInstruction (cpup, cpu.PPR.IC); IC 3096 src/dps8/dps8_cpu.c (cpu.PPR.IC & 1) == 0 && IC 3113 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 1) IC 3289 src/dps8/dps8_cpu.c fetchInstruction (cpup, cpu.PPR.IC); IC 3442 src/dps8/dps8_cpu.c stall_points[i].offset && stall_points[i].offset == cpu.PPR.IC) IC 3460 src/dps8/dps8_cpu.c cpu.lufExecIC = cpu.PPR.IC; IC 3739 src/dps8/dps8_cpu.c (cpu.cu.rd && (cpu.PPR.IC & 1)) || IC 3744 src/dps8/dps8_cpu.c -- cpu.PPR.IC; IC 3769 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3770 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3817 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3819 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3842 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 0 && IC 3846 src/dps8/dps8_cpu.c (cpu.PPR.IC & ~3u) != (cpu.last_write & ~3u)) IC 3848 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3855 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3857 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3872 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3873 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 4119 src/dps8/dps8_cpu.c dummy_IC = cpu.PPR.IC; IC 4337 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); IC 4344 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, addr, IC 4379 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 4424 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 4447 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 4463 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 4507 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 4546 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); IC 4553 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 4564 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 4583 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); IC 4590 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 4601 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 4643 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 4666 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 5203 src/dps8/dps8_cpu.c putbits36_18 (& w1, 54 - 36, cpu.PPR.IC); IC 102 src/dps8/dps8_cpu.h word18 IC; // The word offset from the origin of the procedure segment IC 1042 src/dps8/dps8_cpu.h #define USE_IRODD (cpu.cu.rd && ((cpu. PPR.IC & 1) != 0)) IC 1723 src/dps8/dps8_cpu.h word18 IC; IC 347 src/dps8/dps8_eis.c return cpu.PPR.IC; IC 444 src/dps8/dps8_eis.c return cpu.PPR.IC; IC 519 src/dps8/dps8_eis.c return cpu.PPR.IC; IC 388 src/dps8/dps8_faults.c sim_printf (" TRO PSR:IC %05o:%06o\r\n", cpu.PPR.PSR, cpu.PPR.IC); IC 393 src/dps8/dps8_faults.c sim_printf (" ACV %012llo PSR:IC %05o:%06o\r\n", subFault.bits, cpu.PPR.PSR, cpu.PPR.IC); IC 426 src/dps8/dps8_faults.c fault_ic = cpu . PPR.IC; IC 542 src/dps8/dps8_faults.c (cpu.PPR.IC & 1) && cpu.l68PairValid && IC 596 src/dps8/dps8_faults.c cpu.PPR.IC = (cpu.PPR.IC - 1) & MASK18; IC 796 src/dps8/dps8_faults.c cpu.PPR.IC); IC 954 src/dps8/dps8_faults.c cpu.PPR.IC); IC 135 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) IC 210 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 281 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 352 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 422 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 494 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 564 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { IC 1154 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) IC 1279 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) IC 319 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; IC 325 src/dps8/dps8_ins.c cpu.PPR.IC = cpu.TPR.CA; IC 330 src/dps8/dps8_ins.c __func__, cpu.PPR.PSR, cpu.PPR.IC); IC 331 src/dps8/dps8_ins.c if (cpu.PPR.IC & 1) IC 450 src/dps8/dps8_ins.c putbits36_18 (& words[4], 0, cpu.PPR.IC); IC 503 src/dps8/dps8_ins.c putbits36_1 (& words[5], 25, cpu.cu.xdo && (! cpu.cu.xde || (cpu.PPR.IC & 1))); IC 627 src/dps8/dps8_ins.c cpu.cu_data.IC = cpu.PPR.IC; IC 737 src/dps8/dps8_ins.c cpu.PPR.IC = getbits36_18 (words[4], 0); IC 1187 src/dps8/dps8_ins.c if (cpu.cu.rd && ((cpu.PPR.IC & 1) != 0)) IC 1223 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) // Even IC 1260 src/dps8/dps8_ins.c char * where = lookup_address (cpu.PPR.PSR, cpu.PPR.IC, & compname, IC 1270 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); IC 1274 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o %s\r\n", cpu.PPR.IC, where); IC 1283 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); IC 1288 src/dps8/dps8_ins.c cpu.PPR.PSR, cpu.PPR.IC, where); IC 1302 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1319 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1341 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1359 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1411 src/dps8/dps8_ins.c trk (cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IWB_IRODD); IC 1575 src/dps8/dps8_ins.c if (!cpu.cu.xde && cpu.cu.xdo /* odd instr being executed */ && !(cpu.PPR.IC & 1)) IC 1582 src/dps8/dps8_ins.c if (opcode == 0560 && !opcodeX && cpu.cu.xde && !(cpu.PPR.IC & 1)) IC 1783 src/dps8/dps8_ins.c if (n_dbgevents && (dbgevt = (dbgevent_lookup (cpu.PPR.PSR, cpu.PPR.IC))) >= 0) { IC 1876 src/dps8/dps8_ins.c cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], IC 1888 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); IC 1970 src/dps8/dps8_ins.c word18 saveIC = cpu.PPR.IC; IC 1972 src/dps8/dps8_ins.c ReadInstructionFetch (cpup, cpu.PPR.IC + 1 + n, & cpu.currentEISinstruction.op[n]); IC 1973 src/dps8/dps8_ins.c cpu.PPR.IC = saveIC; IC 2140 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); IC 2382 src/dps8/dps8_ins.c cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 3061 src/dps8/dps8_ins.c word18 ret = (cpu.PPR.IC + 1) & MASK18; IC 4002 src/dps8/dps8_ins.c SETHI (cpu.CY, (cpu.PPR.IC + 1) & MASK18); IC 4015 src/dps8/dps8_ins.c cpu.CY = ((word36) ((cpu.PPR.IC + 2) & MASK18)) << 18; IC 4086 src/dps8/dps8_ins.c putbits36_18 (& cpu.Ypair[1], 0, cpu.PPR.IC + 2); IC 4096 src/dps8/dps8_ins.c putbits36_18 (& cpu.Ypair[1], 0, cpu.cu_data.IC + 2); IC 6617 src/dps8/dps8_ins.c cpu.PPR.IC = GETHI (cpu.CY); IC 7404 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) IC 7730 src/dps8/dps8_ins.c sim_printf (" ldt %d PSR:IC %05o:%06o\r\n", cpu.rTR, cpu.PPR.PSR, cpu.PPR.IC); IC 7781 src/dps8/dps8_ins.c sim_printf (" RALR set to %o PSR:IC %05o:%06o\r\n", cpu.rRALR, cpu.PPR.PSR, cpu.PPR.IC); IC 8887 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 034 && cpu.PPR.IC == 03535) { IC 8921 src/dps8/dps8_ins.c " no events in queue\r\n", cpu.PPR.IC); IC 8938 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 0430 && cpu.PPR.IC == 012) IC 8978 src/dps8/dps8_ins.c (cpu.PPR.PSR !=0 || cpu.PPR.IC != 0)) { IC 8980 src/dps8/dps8_ins.c sim_printf ("CPU%c DIS %o:%o gives up master\r\n", cpu.cpuIdx + 'A', cpu.PPR.PSR, cpu.PPR.IC); IC 10096 src/dps8/dps8_ins.c (cpu.Yblock8[0]>>18)&MASK15, (cpu.Yblock8[4]>>18)&MASK18, cpu.PPR.PSR, cpu.PPR.IC); IC 3757 src/dps8/dps8_iom.c __func__, iomChar (iom_unit_idx), cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC); IC 2771 src/dps8/dps8_sys.c word18 icOffset = cpu.PPR.IC; IC 4103 src/dps8/dps8_sys.c { "cpus[].PPR.IC", SYM_STRUCT_OFFSET, SYM_UINT32_18, offsetof (struct ppr_s, IC) }, IC 179 src/dps8/hdbg.c if (filter && hdbgSegNum > 0 && blacklist[cpu.PPR.IC]) \ IC 202 src/dps8/hdbg.c hevp[p].trace.ic = cpu.PPR.IC; IC 657 src/dps8/panelScraper.c SETL (bank_e, 0+3, cpu.PPR.IC, 18); IC 917 src/dps8/panelScraper.c SETL (bank_g, 0, cpu.PPR.IC, 18); IC 951 src/dps8/panelScraper.c SETL (bank_j, 3, cpu.PPR.IC, 18);