root/src/dps8/dps8_iefp.c

/* */

DEFINITIONS

1. Read
2. ReadAPUDataRead
3. ReadOperandRead
4. ReadOperandRMW
5. ReadAPUDataRMW
6. ReadInstructionFetch
7. ReadIndirectWordFetch
8. Read2
9. Read2OperandRead
10. Read2OperandRMW
11. Read2InstructionFetch
12. Read2RTCDOperandFetch
13. Read2IndirectWordFetch
14. Read8
15. Read16
16. ReadPage
17. Write
18. WriteAPUDataStore
19. WriteOperandStore
20. Write2
21. Write2OperandStore
22. Write1
23. Write8
24. Write16
25. Write32
26. WritePage
27. ReadIndirect

   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * SPDX-License-Identifier: Multics
   5  * scspell-id: 755f1556-f62e-11ec-8184-80ee73e9b8e7
   6  *
   7  * ---------------------------------------------------------------------------
   8  *
   9  * Copyright (c) 2007-2013 Michael Mondy
  10  * Copyright (c) 2012-2016 Harry Reed
  11  * Copyright (c) 2013-2016 Charles Anthony
  12  * Copyright (c) 2015 Eric Swenson
  13  * Copyright (c) 2017 Michal Tomek
  14  * Copyright (c) 2021-2023 The DPS8M Development Team
  15  *
  16  * All rights reserved.
  17  *
  18  * This software is made available under the terms of the ICU
  19  * License, version 1.8.1 or later.  For more details, see the
  20  * LICENSE.md file at the top-level directory of this distribution.
  21  *
  22  * ---------------------------------------------------------------------------
  23  *
  24  * This source file may contain code comments that adapt, include, and/or
  25  * incorporate Multics program code and/or documentation distributed under
  26  * the Multics License.  In the event of any discrepancy between code
  27  * comments herein and the original Multics materials, the original Multics
  28  * materials should be considered authoritative unless otherwise noted.
  29  * For more details and historical background, see the LICENSE.md file at
  30  * the top-level directory of this distribution.
  31  *
  32  * ---------------------------------------------------------------------------
  33  */
  34 
  35 //-V::536
  36 
  37 #include "dps8.h"
  38 #include "dps8_sys.h"
  39 #include "dps8_faults.h"
  40 #include "dps8_scu.h"
  41 #include "dps8_iom.h"
  42 #include "dps8_cable.h"
  43 #include "dps8_cpu.h"
  44 #include "dps8_append.h"
  45 #include "dps8_iefp.h"
  46 #include "dps8_addrmods.h"
  47 #include "dps8_utils.h"
  48 
  49 #define DBG_CTR cpu.cycleCnt
  50 
  51 // new Read/Write stuff ...
  52 
  53 #ifdef OLDAPP
  54 void Read (word18 address, word36 * result, processor_cycle_type cyctyp)
     /*  */
  55   {
  56     cpu.TPR.CA = cpu.iefpFinalAddress = address;
  57     bool isBAR = get_bar_mode ();
  58 
  59     //if (get_went_appending () ||
  60     if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29))
  61       {
  62         goto B29;
  63       }
  64 
  65     switch (get_addr_mode ())
  66       {
  67         case ABSOLUTE_mode:
  68           {
  69             if (isBAR)
  70               {
  71                 set_apu_status (apuStatus_FABS); // XXX maybe...
  72                 cpu.iefpFinalAddress = get_BAR_address (address);
  73                 fauxDoAppendCycle (cyctyp);
  74 # ifdef LOCKLESS
  75                 if (cyctyp == OPERAND_RMW || cyctyp == APU_DATA_RMW)
  76                   core_read_lock (cpu.iefpFinalAddress, result, __func__);
  77                 else
  78                   core_read (cpu.iefpFinalAddress, result, __func__);
  79 # else
  80                 core_read (cpu.iefpFinalAddress, result, __func__);
  81 # endif
  82                 sim_debug (DBG_FINAL, & cpu_dev,
  83                            "Read (Actual) Read:       bar address=%08o  "
  84                            "readData=%012"PRIo64"\n", address, *result);
  85 # ifdef TESTING
  86                 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read ABS BAR");
  87                 HDBGMRead (cpu.iefpFinalAddress, * result, "Read ABS BAR");
  88 # endif
  89                 return;
  90               }
  91             else
  92               {
  93                 set_apu_status (apuStatus_FABS);
  94                 fauxDoAppendCycle (cyctyp);
  95 # ifdef LOCKLESS
  96                 if (cyctyp == OPERAND_RMW || cyctyp == APU_DATA_RMW)
  97                   core_read_lock (address, result, __func__);
  98                 else
  99                   core_read (address, result, __func__);
 100 # else
 101                 core_read (address, result, __func__);
 102 # endif
 103                 sim_debug (DBG_FINAL, & cpu_dev,
 104                            "Read (Actual) Read:       abs address=%08o  "
 105                            "readData=%012"PRIo64"\n", address, *result);
 106 # ifdef TESTING
 107                 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read ABS");
 108                 HDBGMRead (address, * result, "Read ABS");
 109 # endif
 110                 return;
 111               }
 112           }
 113 
 114         case APPEND_mode:
 115           {
 116 B29:;
 117             if (isBAR)
 118               {
 119                 cpu.TPR.CA = get_BAR_address (address);
 120                 cpu.TPR.TSR = cpu.PPR.PSR;
 121                 cpu.TPR.TRR = cpu.PPR.PRR;
 122                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, result, 1);
 123                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 124                            "Read (Actual) Read:  bar iefpFinalAddress=%08o  "
 125                            "readData=%012"PRIo64"\n",
 126                            cpu.iefpFinalAddress, * result);
 127 # ifdef TESTING
 128                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read BAR");
 129                 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read BAR");
 130 # endif
 131 
 132                 return;
 133               }
 134             else
 135               {
 136                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, result, 1);
 137                 // XXX Don't trace Multics idle loop
 138                 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
 139                   {
 140                     sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 141                                "Read (Actual) Read:  iefpFinalAddress=%08o  "
 142                                "readData=%012"PRIo64"\n",
 143                                cpu.iefpFinalAddress, * result);
 144 # ifdef TESTING
 145                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read");
 146                     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read");
 147 # endif
 148                   }
 149               }
 150             return;
 151           }
 152       }
 153     return ;//SCPE_UNK;
 154   }
 155 #endif // OLDAPP
 156 
 157 #ifndef OLDAPP
 158 void ReadAPUDataRead (word18 address, word36 * result) {
     /*  */
 159   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 160   bool isBAR = get_bar_mode ();
 161 
 162   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 163     goto B29;
 164 
 165   switch (get_addr_mode ()) {
 166     case ABSOLUTE_mode: {
 167       if (isBAR) {
 168         set_apu_status (apuStatus_FABS); // XXX maybe...
 169         cpu.iefpFinalAddress = get_BAR_address (address);
 170         fauxDoAppendCycle (APU_DATA_READ);
 171         core_read (cpu.iefpFinalAddress, result, __func__);
 172         sim_debug (DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\n", address, *result);
 173 # ifdef TESTING
 174         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadAPUDataRead ABS BAR");
 175         HDBGMRead (cpu.iefpFinalAddress, * result, "ReadAPUDataRead ABS BAR");
 176 # endif
 177         return;
 178       } else {
 179         set_apu_status (apuStatus_FABS);
 180         fauxDoAppendCycle (APU_DATA_READ);
 181         core_read (address, result, __func__);
 182         sim_debug (DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\n", address, *result);
 183 # ifdef TESTING
 184         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadAPUDataRead ABS");
 185         HDBGMRead (address, * result, "ReadAPUDataRead ABS");
 186 # endif
 187         return;
 188       }
 189     }
 190 
 191     case APPEND_mode: {
 192 B29:;
 193       if (isBAR) {
 194         cpu.TPR.CA = get_BAR_address (address);
 195         cpu.TPR.TSR = cpu.PPR.PSR;
 196         cpu.TPR.TRR = cpu.PPR.PRR;
 197         cpu.iefpFinalAddress = doAppendCycleAPUDataRead (result, 1);
 198         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
 199 # ifdef TESTING
 200         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRead BAR");
 201         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead BAR");
 202 # endif
 203         return;
 204       } else {
 205         cpu.iefpFinalAddress = doAppendCycleAPUDataRead (result, 1);
 206         // XXX Don't trace Multics idle loop
 207         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
 208           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
 209 # ifdef TESTING
 210           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRead");
 211           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead");
 212 # endif
 213         }
 214         return;
 215       }
 216     }
 217   }
 218 }
 219 
 220 void ReadOperandRead (word18 address, word36 * result) {
     /*  */
 221   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 222   bool isBAR = get_bar_mode ();
 223 
 224   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 225     goto B29;
 226 
 227   switch (get_addr_mode ()) {
 228     case ABSOLUTE_mode: {
 229       if (isBAR) {
 230         set_apu_status (apuStatus_FABS); // XXX maybe...
 231         cpu.iefpFinalAddress = get_BAR_address (address);
 232         fauxDoAppendCycle (OPERAND_READ);
 233         core_read (cpu.iefpFinalAddress, result, __func__);
 234         sim_debug (DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\n", address, *result);
 235 # ifdef TESTING
 236         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "readOperandRead ABS BAR");
 237         HDBGMRead (cpu.iefpFinalAddress, * result, "readOperandRead ABS BAR");
 238 # endif
 239         return;
 240       } else {
 241         set_apu_status (apuStatus_FABS);
 242         fauxDoAppendCycle (OPERAND_READ);
 243         core_read (address, result, __func__);
 244         sim_debug (DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\n", address, *result);
 245 # ifdef TESTING
 246         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "readOperandRead ABS");
 247         HDBGMRead (address, * result, "readOperandRead ABS");
 248 # endif
 249         return;
 250       }
 251     }
 252 
 253     case APPEND_mode: {
 254 B29:;
 255       if (isBAR) {
 256         cpu.TPR.CA = get_BAR_address (address);
 257         cpu.TPR.TSR = cpu.PPR.PSR;
 258         cpu.TPR.TRR = cpu.PPR.PRR;
 259         cpu.iefpFinalAddress = doAppendCycleOperandRead (result, 1);
 260         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
 261 # ifdef TESTING
 262         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "readOperandRead BAR");
 263         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead BAR");
 264 # endif
 265 
 266         return;
 267       } else {
 268         cpu.iefpFinalAddress = doAppendCycleOperandRead (result, 1);
 269         // XXX Don't trace Multics idle loop
 270         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
 271           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
 272 # ifdef TESTING
 273           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "readOperandRead");
 274           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead");
 275 # endif
 276         }
 277         return;
 278       }
 279     }
 280   }
 281 }
 282 
 283 # ifdef LOCKLESS
 284 void ReadOperandRMW (word18 address, word36 * result) {
     /*  */
 285   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 286   bool isBAR = get_bar_mode ();
 287 
 288   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 289     goto B29;
 290 
 291   switch (get_addr_mode ()) {
 292     case ABSOLUTE_mode: {
 293       if (isBAR) {
 294         set_apu_status (apuStatus_FABS); // XXX maybe...
 295         cpu.iefpFinalAddress = get_BAR_address (address);
 296         fauxDoAppendCycle (OPERAND_RMW);
 297         core_read_lock (cpu.iefpFinalAddress, result, __func__);
 298         sim_debug (DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\n", address, *result);
 299 #  ifdef TESTING
 300         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadOperandRMW ABS BAR");
 301         HDBGMRead (cpu.iefpFinalAddress, * result, "ReadOperandRMW ABS BAR");
 302 #  endif
 303         return;
 304       } else {
 305         set_apu_status (apuStatus_FABS);
 306         fauxDoAppendCycle (OPERAND_RMW);
 307         core_read_lock (address, result, __func__);
 308         sim_debug (DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\n", address, *result);
 309 #  ifdef TESTING
 310         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadOperandRMW ABS");
 311         HDBGMRead (address, * result, "ReadOperandRMW ABS");
 312 #  endif
 313         return;
 314       }
 315     }
 316 
 317     case APPEND_mode: {
 318 B29:;
 319       if (isBAR) {
 320         cpu.TPR.CA = get_BAR_address (address);
 321         cpu.TPR.TSR = cpu.PPR.PSR;
 322         cpu.TPR.TRR = cpu.PPR.PRR;
 323         cpu.iefpFinalAddress = doAppendCycleOperandRMW (result, 1);
 324         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
 325 #  ifdef TESTING
 326         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadOperandRMW BAR");
 327         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW BAR");
 328 #  endif
 329         return;
 330       } else {
 331         cpu.iefpFinalAddress = doAppendCycleOperandRMW (result, 1);
 332         // XXX Don't trace Multics idle loop
 333         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
 334           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
 335 #  ifdef TESTING
 336           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadOperandRMW");
 337           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW");
 338 #  endif
 339         }
 340         return;
 341       }
 342     }
 343   }
 344 }
 345 
 346 void ReadAPUDataRMW (word18 address, word36 * result) {
     /*  */
 347   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 348   bool isBAR = get_bar_mode ();
 349 
 350   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 351     goto B29;
 352 
 353   switch (get_addr_mode ()) {
 354     case ABSOLUTE_mode: {
 355       if (isBAR) {
 356         set_apu_status (apuStatus_FABS); // XXX maybe...
 357         cpu.iefpFinalAddress = get_BAR_address (address);
 358         fauxDoAppendCycle (APU_DATA_RMW);
 359         core_read_lock (cpu.iefpFinalAddress, result, __func__);
 360         sim_debug (DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\n", address, *result);
 361 #  ifdef TESTING
 362         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadAPUDataRMW ABS BAR");
 363         HDBGMRead (cpu.iefpFinalAddress, * result, "ReadAPUDataRMW ABS BAR");
 364 #  endif
 365         return;
 366       } else {
 367         set_apu_status (apuStatus_FABS);
 368         fauxDoAppendCycle (APU_DATA_RMW);
 369         core_read_lock (address, result, __func__);
 370         sim_debug (DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\n", address, *result);
 371 #  ifdef TESTING
 372         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadAPUDataRMW ABS");
 373         HDBGMRead (address, * result, "ReadAPUDataRMW ABS");
 374 #  endif
 375         return;
 376       }
 377     }
 378 
 379     case APPEND_mode: {
 380 B29:;
 381       if (isBAR) {
 382         cpu.TPR.CA = get_BAR_address (address);
 383         cpu.TPR.TSR = cpu.PPR.PSR;
 384         cpu.TPR.TRR = cpu.PPR.PRR;
 385         cpu.iefpFinalAddress = doAppendCycleAPUDataRMW (result, 1);
 386         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
 387 #  ifdef TESTING
 388         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRMW BAR");
 389         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW BAR");
 390 #  endif
 391         return;
 392       } else {
 393         cpu.iefpFinalAddress = doAppendCycleAPUDataRMW (result, 1);
 394         // XXX Don't trace Multics idle loop
 395         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
 396           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
 397 #  ifdef TESTING
 398           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRMW");
 399           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW");
 400 #  endif
 401         }
 402         return;
 403       }
 404     }
 405   }
 406   return ;//SCPE_UNK;
 407 }
 408 # endif
 409 
 410 void ReadInstructionFetch (word18 address, word36 * result) {
     /*  */
 411   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 412   bool isBAR = get_bar_mode ();
 413 
 414   if (cpu.cu.XSF)
 415     goto B29;
 416 
 417   switch (get_addr_mode ()) {
 418     case ABSOLUTE_mode: {
 419       if (isBAR) {
 420         set_apu_status (apuStatus_FABS); // XXX maybe...
 421         cpu.iefpFinalAddress = get_BAR_address (address);
 422         fauxDoAppendCycle (INSTRUCTION_FETCH);
 423         core_read (cpu.iefpFinalAddress, result, __func__);
 424         sim_debug (DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\n", address, *result);
 425 # ifdef TESTING
 426         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadInstructionFetch ABS BAR");
 427         HDBGMRead (cpu.iefpFinalAddress, * result, "ReadInstructionFetch ABS BAR");
 428 # endif
 429         return;
 430       } else {
 431         set_apu_status (apuStatus_FABS);
 432         fauxDoAppendCycle (INSTRUCTION_FETCH);
 433         core_read (address, result, __func__);
 434         sim_debug (DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\n", address, *result);
 435 # ifdef TESTING
 436         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadInstructionFetch ABS");
 437         HDBGMRead (address, * result, "ReadInstructionFetch ABS");
 438 # endif
 439         return;
 440       }
 441     }
 442 
 443     case APPEND_mode: {
 444 B29:;
 445       if (isBAR) {
 446         cpu.TPR.CA = get_BAR_address (address);
 447         cpu.TPR.TSR = cpu.PPR.PSR;
 448         cpu.TPR.TRR = cpu.PPR.PRR;
 449         cpu.iefpFinalAddress = doAppendCycleInstructionFetch (result, 1);
 450         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
 451 # ifdef TESTING
 452         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadInstructionFetch BAR");
 453         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch BAR");
 454 # endif
 455         return;
 456       } else {
 457         cpu.iefpFinalAddress = doAppendCycleInstructionFetch (result, 1);
 458         // XXX Don't trace Multics idle loop
 459         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
 460           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
 461 # ifdef TESTING
 462           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadInstructionFetch");
 463           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch");
 464 # endif
 465         }
 466         return;
 467       }
 468     }
 469   }
 470 }
 471 
 472 void ReadIndirectWordFetch (word18 address, word36 * result) {
     /*  */
 473   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 474   bool isBAR = get_bar_mode ();
 475 
 476   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 477     goto B29;
 478 
 479   switch (get_addr_mode ()) {
 480     case ABSOLUTE_mode: {
 481       if (isBAR) {
 482         set_apu_status (apuStatus_FABS); // XXX maybe...
 483         cpu.iefpFinalAddress = get_BAR_address (address);
 484         fauxDoAppendCycle (INDIRECT_WORD_FETCH);
 485         core_read (cpu.iefpFinalAddress, result, __func__);
 486         sim_debug (DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\n", address, *result);
 487 # ifdef TESTING
 488         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadIndirectWordFetch ABS BAR");
 489         HDBGMRead (cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch ABS BAR");
 490 # endif
 491         return;
 492       } else {
 493         set_apu_status (apuStatus_FABS);
 494         fauxDoAppendCycle (INDIRECT_WORD_FETCH);
 495         core_read (address, result, __func__);
 496         sim_debug (DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\n", address, *result);
 497 # ifdef TESTING
 498         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadIndirectWordFetch ABS");
 499         HDBGMRead (address, * result, "ReadIndirectWordFetch ABS");
 500 # endif
 501         return;
 502       }
 503   }
 504 
 505   case APPEND_mode: {
 506 B29:;
 507       if (isBAR) {
 508         cpu.TPR.CA = get_BAR_address (address);
 509         cpu.TPR.TSR = cpu.PPR.PSR;
 510         cpu.TPR.TRR = cpu.PPR.PRR;
 511         cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (result, 1);
 512         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
 513 # ifdef TESTING
 514         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch BAR");
 515         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch BAR");
 516 # endif
 517         return;
 518       } else {
 519         cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (result, 1);
 520         // XXX Don't trace Multics idle loop
 521         if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) {
 522           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
 523 # ifdef TESTING
 524             HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch");
 525             HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch");
 526 # endif
 527           }
 528           return;
 529         }
 530     }
 531   }
 532 }
 533 #endif // !OLDAPP
 534 
 535 #ifdef OLDAPP
 536 void Read2 (word18 address, word36 * result, processor_cycle_type cyctyp) {
     /*  */
 537   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 538 
 539   bool isBAR = get_bar_mode ();
 540 
 541   if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29) || cyctyp == RTCD_OPERAND_FETCH) // ISOLTS-886
 542          // Another option would be to set_went_appending in ReadRTCDOp
 543     goto B29;
 544 
 545   switch (get_addr_mode ()) {
 546     case ABSOLUTE_mode: {
 547       if (isBAR) {
 548         set_apu_status (apuStatus_FABS); // XXX maybe...
 549         cpu.iefpFinalAddress = get_BAR_address (address);
 550 
 551         fauxDoAppendCycle (cyctyp);
 552         core_read2 (cpu.iefpFinalAddress, result + 0, result + 1, __func__);
 553         if_sim_debug (DBG_FINAL, & cpu_dev) {
 554             for (uint i = 0; i < 2; i ++)
 555               sim_debug (DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
 556         }
 557 # ifdef TESTING
 558         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2 ABBR");
 559         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2 ABBR evn");
 560         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2 ABBR odd");
 561 # endif
 562         return;
 563       } else {
 564         set_apu_status (apuStatus_FABS);
 565         fauxDoAppendCycle (cyctyp);
 566         core_read2 (address, result + 0, result + 1, __func__);
 567         if_sim_debug (DBG_FINAL, & cpu_dev) {
 568           for (uint i = 0; i < 2; i ++)
 569             sim_debug (DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
 570         }
 571 # ifdef TESTING
 572         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2 AB");
 573         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2 AB evn");
 574         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2 AB odd");
 575 # endif
 576         return;
 577       }
 578     }
 579 
 580     case APPEND_mode: {
 581 B29:;
 582       if (isBAR) {
 583         cpu.TPR.CA = get_BAR_address (address);
 584         cpu.TPR.TSR = cpu.PPR.PSR;
 585         cpu.TPR.TRR = cpu.PPR.PRR;
 586         cpu.iefpFinalAddress = do_append_cycle (cyctyp, result, 2);
 587         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 588           for (uint i = 0; i < 2; i ++)
 589            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 590         }
 591 # ifdef TESTING
 592         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR");
 593         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn");
 594         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd");
 595 # endif
 596         return;
 597       } else {
 598         cpu.iefpFinalAddress = do_append_cycle (cyctyp, result, 2);
 599         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 600           for (uint i = 0; i < 2; i ++)
 601             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 602         }
 603         if_sim_debug (DBG_FINAL, & cpu_dev) {
 604           if (cyctyp == OPERAND_READ) {
 605             for (uint i = 0; i < 2; i ++)
 606               sim_debug (DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 607           }
 608         }
 609 # ifdef TESTING
 610         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2");
 611         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn");
 612         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd");
 613 # endif
 614       }
 615       return;
 616     }
 617   }
 618 }
 619 #endif // OLDAPP
 620 
 621 #ifndef OLDAPP
 622 void Read2OperandRead (word18 address, word36 * result) {
     /*  */
 623   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 624 
 625   bool isBAR = get_bar_mode ();
 626 
 627   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 628     goto B29;
 629 
 630   switch (get_addr_mode ()) {
 631     case ABSOLUTE_mode: {
 632       if (isBAR) {
 633         set_apu_status (apuStatus_FABS); // XXX maybe...
 634         cpu.iefpFinalAddress = get_BAR_address (address);
 635 
 636         fauxDoAppendCycle (OPERAND_READ);
 637         core_read2 (cpu.iefpFinalAddress, result + 0, result + 1, __func__);
 638         if_sim_debug (DBG_FINAL, & cpu_dev) {
 639             for (uint i = 0; i < 2; i ++)
 640               sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
 641         }
 642 # ifdef TESTING
 643         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2OperandRead ABBR");
 644         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRead ABBR evn");
 645         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRead ABBR odd");
 646 # endif
 647         return;
 648       } else {
 649         set_apu_status (apuStatus_FABS);
 650         fauxDoAppendCycle (OPERAND_READ);
 651         core_read2 (address, result + 0, result + 1, __func__);
 652         if_sim_debug (DBG_FINAL, & cpu_dev) {
 653           for (uint i = 0; i < 2; i ++)
 654             sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
 655         }
 656 # ifdef TESTING
 657         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2OperandRead AB");
 658         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRead AB evn");
 659         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRead AB odd");
 660 # endif
 661         return;
 662       }
 663     }
 664 
 665     case APPEND_mode: {
 666 B29:;
 667       if (isBAR) {
 668         cpu.TPR.CA = get_BAR_address (address);
 669         cpu.TPR.TSR = cpu.PPR.PSR;
 670         cpu.TPR.TRR = cpu.PPR.PRR;
 671         cpu.iefpFinalAddress = doAppendCycleOperandRead (result, 2);
 672         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 673           for (uint i = 0; i < 2; i ++)
 674            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 675         }
 676 # ifdef TESTING
 677         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRead BR");
 678         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead BR evn");
 679         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead BR odd");
 680 # endif
 681         return;
 682       } else {
 683         cpu.iefpFinalAddress = doAppendCycleOperandRead (result, 2);
 684         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 685           for (uint i = 0; i < 2; i ++)
 686             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 687         }
 688         if_sim_debug (DBG_FINAL, & cpu_dev) {
 689           for (uint i = 0; i < 2; i ++)
 690             sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 691         }
 692 # ifdef TESTING
 693         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRead");
 694         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead evn");
 695         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead odd");
 696 # endif
 697         return;
 698       }
 699     }
 700   }
 701 }
 702 
 703 # ifdef LOCKLESS
 704 void Read2OperandRMW (word18 address, word36 * result) {
     /*  */
 705   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 706 
 707   bool isBAR = get_bar_mode ();
 708 
 709   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 710     goto B29;
 711 
 712   switch (get_addr_mode ()) {
 713     case ABSOLUTE_mode: {
 714       if (isBAR) {
 715         set_apu_status (apuStatus_FABS); // XXX maybe...
 716         cpu.iefpFinalAddress = get_BAR_address (address);
 717 
 718         fauxDoAppendCycle (OPERAND_RMW);
 719         core_read2 (cpu.iefpFinalAddress, result + 0, result + 1, __func__);
 720         if_sim_debug (DBG_FINAL, & cpu_dev) {
 721             for (uint i = 0; i < 2; i ++)
 722               sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
 723         }
 724 #  ifdef TESTING
 725         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2OperandRMW ABBR");
 726         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRMW ABBR evn");
 727         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRMW ABBR odd");
 728 #  endif
 729         return;
 730       } else {
 731         set_apu_status (apuStatus_FABS);
 732         fauxDoAppendCycle (OPERAND_RMW);
 733         core_read2 (address, result + 0, result + 1, __func__);
 734         if_sim_debug (DBG_FINAL, & cpu_dev) {
 735           for (uint i = 0; i < 2; i ++)
 736             sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
 737         }
 738 #  ifdef TESTING
 739         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2OperandRMW AB");
 740         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRMW AB evn");
 741         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRMW AB odd");
 742 #  endif
 743         return;
 744       }
 745     }
 746 
 747     case APPEND_mode: {
 748 B29:;
 749       if (isBAR) {
 750         cpu.TPR.CA = get_BAR_address (address);
 751         cpu.TPR.TSR = cpu.PPR.PSR;
 752         cpu.TPR.TRR = cpu.PPR.PRR;
 753         cpu.iefpFinalAddress = doAppendCycleOperandRMW (result, 2);
 754         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 755           for (uint i = 0; i < 2; i ++)
 756            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 757         }
 758 #  ifdef TESTING
 759         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRMW BR");
 760         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW BR evn");
 761         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW BR odd");
 762 #  endif
 763         return;
 764       } else {
 765         cpu.iefpFinalAddress = doAppendCycleOperandRMW (result, 2);
 766         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 767           for (uint i = 0; i < 2; i ++)
 768             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 769         }
 770 #  ifdef TESTING
 771         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRMW");
 772         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW evn");
 773         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW odd");
 774 #  endif
 775         return;
 776       }
 777     }
 778   }
 779 }
 780 # endif
 781 
 782 void Read2InstructionFetch (word18 address, word36 * result) {
     /*  */
 783   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 784 
 785   bool isBAR = get_bar_mode ();
 786 
 787   if (cpu.cu.XSF)
 788     goto B29;
 789 
 790   switch (get_addr_mode ()) {
 791     case ABSOLUTE_mode: {
 792       if (isBAR) {
 793         set_apu_status (apuStatus_FABS); // XXX maybe...
 794         cpu.iefpFinalAddress = get_BAR_address (address);
 795 
 796         fauxDoAppendCycle (INSTRUCTION_FETCH);
 797         core_read2 (cpu.iefpFinalAddress, result + 0, result + 1, __func__);
 798         if_sim_debug (DBG_FINAL, & cpu_dev) {
 799             for (uint i = 0; i < 2; i ++)
 800               sim_debug (DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
 801         }
 802 # ifdef TESTING
 803         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2InstructionFetch ABBR");
 804         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2InstructionFetch ABBR evn");
 805         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2InstructionFetch ABBR odd");
 806 # endif
 807         return;
 808       } else {
 809         set_apu_status (apuStatus_FABS);
 810         fauxDoAppendCycle (INSTRUCTION_FETCH);
 811         core_read2 (address, result + 0, result + 1, __func__);
 812         if_sim_debug (DBG_FINAL, & cpu_dev) {
 813           for (uint i = 0; i < 2; i ++)
 814             sim_debug (DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
 815         }
 816 # ifdef TESTING
 817         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2InstructionFetch AB");
 818         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2InstructionFetch AB evn");
 819         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2InstructionFetch AB odd");
 820 # endif
 821         return;
 822       }
 823     }
 824 
 825     case APPEND_mode: {
 826 B29:;
 827       if (isBAR) {
 828         cpu.TPR.CA = get_BAR_address (address);
 829         cpu.TPR.TSR = cpu.PPR.PSR;
 830         cpu.TPR.TRR = cpu.PPR.PRR;
 831         cpu.iefpFinalAddress = doAppendCycleInstructionFetch (result, 2);
 832         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 833           for (uint i = 0; i < 2; i ++)
 834            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 835         }
 836 # ifdef TESTING
 837         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2InstructionFetch BR");
 838         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch BR evn");
 839         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch BR odd");
 840 # endif
 841         return;
 842       } else {
 843         cpu.iefpFinalAddress = doAppendCycleInstructionFetch (result, 2);
 844         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 845           for (uint i = 0; i < 2; i ++)
 846             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 847         }
 848 # ifdef TESTING
 849         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2InstructionFetch");
 850         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch evn");
 851         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch odd");
 852 # endif
 853         return;
 854       }
 855     }
 856   }
 857 }
 858 
 859 void Read2RTCDOperandFetch (word18 address, word36 * result) {
     /*  */
 860   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 861 
 862   bool isBAR = get_bar_mode ();
 863 
 864   if (isBAR) {
 865     cpu.TPR.CA = get_BAR_address (address);
 866     cpu.TPR.TSR = cpu.PPR.PSR;
 867     cpu.TPR.TRR = cpu.PPR.PRR;
 868     cpu.iefpFinalAddress = doAppendCycleRTCDOperandFetch (result, 2);
 869     if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 870       for (uint i = 0; i < 2; i ++)
 871        sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 872     }
 873 # ifdef TESTING
 874     HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR");
 875     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn");
 876     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd");
 877 # endif
 878     return;
 879   } else {
 880     cpu.iefpFinalAddress = doAppendCycleRTCDOperandFetch (result, 2);
 881     if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 882       for (uint i = 0; i < 2; i ++)
 883         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 884     }
 885 # ifdef TESTING
 886     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2");
 887     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn");
 888     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd");
 889 # endif
 890     return;
 891   }
 892 }
 893 
 894 void Read2IndirectWordFetch (word18 address, word36 * result) {
     /*  */
 895   cpu.TPR.CA = cpu.iefpFinalAddress = address;
 896 
 897   bool isBAR = get_bar_mode ();
 898 
 899   if (cpu.cu.XSF || cpu.currentInstruction.b29)
 900     goto B29;
 901 
 902   switch (get_addr_mode ()) {
 903     case ABSOLUTE_mode: {
 904       if (isBAR) {
 905         set_apu_status (apuStatus_FABS); // XXX maybe...
 906         cpu.iefpFinalAddress = get_BAR_address (address);
 907 
 908         fauxDoAppendCycle (INDIRECT_WORD_FETCH);
 909         core_read2 (cpu.iefpFinalAddress, result + 0, result + 1, __func__);
 910         if_sim_debug (DBG_FINAL, & cpu_dev) {
 911             for (uint i = 0; i < 2; i ++)
 912               sim_debug (DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
 913         }
 914 # ifdef TESTING
 915         HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2IndirectWordFetch ABBR");
 916         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch ABBR evn");
 917         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2IndirectWordFetch ABBR odd");
 918 # endif
 919         return;
 920       } else {
 921         set_apu_status (apuStatus_FABS);
 922         fauxDoAppendCycle (INDIRECT_WORD_FETCH);
 923         core_read2 (address, result + 0, result + 1, __func__);
 924         if_sim_debug (DBG_FINAL, & cpu_dev) {
 925           for (uint i = 0; i < 2; i ++)
 926             sim_debug (DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
 927         }
 928 # ifdef TESTING
 929         HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2IndirectWordFetch AB");
 930         HDBGMRead (cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch AB evn");
 931         HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2IndirectWordFetch AB odd");
 932 # endif
 933         return;
 934       }
 935     }
 936 
 937     case APPEND_mode: {
 938 B29:;
 939       if (isBAR) {
 940         cpu.TPR.CA = get_BAR_address (address);
 941         cpu.TPR.TSR = cpu.PPR.PSR;
 942         cpu.TPR.TRR = cpu.PPR.PRR;
 943         cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (result, 2);
 944         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 945           for (uint i = 0; i < 2; i ++)
 946            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 947         }
 948 # ifdef TESTING
 949         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch BR");
 950         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch BR evn");
 951         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch BR odd");
 952 # endif
 953         return;
 954       } else {
 955         cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (result, 2);
 956         if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) {
 957           for (uint i = 0; i < 2; i ++)
 958             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
 959         }
 960 # ifdef TESTING
 961         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch");
 962         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch evn");
 963         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch odd");
 964         return;
 965 # endif
 966       }
 967     }
 968   }
 969 }
 970 #endif // !OLDAPP
 971 
 972 void Read8 (word18 address, word36 * result, bool isAR)
     /*  */
 973   {
 974     cpu.TPR.CA = cpu.iefpFinalAddress = address;
 975 
 976     bool isBAR = get_bar_mode ();
 977 
 978     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
 979       {
 980         goto B29;
 981       }
 982 
 983     switch (get_addr_mode ())
 984       {
 985         case ABSOLUTE_mode:
 986           {
 987             if (isBAR)
 988               {
 989                 set_apu_status (apuStatus_FABS); // XXX maybe...
 990                 cpu.iefpFinalAddress = get_BAR_address (address);
 991 
 992                 fauxDoAppendCycle (APU_DATA_READ);
 993                 core_readN (cpu.iefpFinalAddress, result, 8, __func__);
 994                 if_sim_debug (DBG_FINAL, & cpu_dev)
 995                   {
 996                     for (uint i = 0; i < 8; i ++)
 997                       sim_debug (DBG_FINAL, & cpu_dev,
 998                                  "Read8 (Actual) Read:       bar address=%08o"
 999                                  "  readData=%012"PRIo64"\n",
1000                                  address + i, result [i]);
1001                   }
1002 #ifdef TESTING
1003                 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read8 ABBR");
1004                 for (uint i = 0; i < 8; i ++)
1005                   HDBGMRead (cpu.iefpFinalAddress + i, result [i], "Read8 ABBR");
1006 #endif
1007                 return;
1008               }
1009             else
1010               {
1011                 set_apu_status (apuStatus_FABS);
1012                 fauxDoAppendCycle (APU_DATA_READ);
1013                 core_readN (address, result, 8, __func__);
1014                 if_sim_debug (DBG_FINAL, & cpu_dev)
1015                   {
1016                     for (uint i = 0; i < 8; i ++)
1017                       sim_debug (DBG_FINAL, & cpu_dev,
1018                                  "Read8 (Actual) Read:       abs address=%08o"
1019                                  "  readData=%012"PRIo64"\n",
1020                                  address + i, result [i]);
1021                   }
1022 #ifdef TESTING
1023                 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read8 ABS");
1024                 for (uint i = 0; i < 8; i ++)
1025                   HDBGMRead (address + i, result [i], "Read8 ABS");
1026 #endif
1027                 return;
1028               }
1029           }
1030 
1031         case APPEND_mode:
1032           {
1033 B29:;
1034             if (isBAR)
1035               {
1036                 cpu.TPR.CA = get_BAR_address (address);
1037                 cpu.TPR.TSR = cpu.PPR.PSR;
1038                 cpu.TPR.TRR = cpu.PPR.PRR;
1039                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_READ, result, 8);
1040                 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (result, 8);
1041                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1042                   {
1043                     for (uint i = 0; i < 8; i ++)
1044                      sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1045                                 "Read8 (Actual) Read:  bar iefpFinalAddress="
1046                                 "%08o  readData=%012"PRIo64"\n",
1047                                 cpu.iefpFinalAddress + i, result [i]);
1048                   }
1049 #ifdef TESTING
1050                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read8 BAR");
1051                 for (uint i = 0; i < 8; i ++)
1052                   HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result[i], "Read8 BAR");
1053 #endif
1054                 return;
1055               }
1056             else
1057               {
1058                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_READ, result, 8);
1059                 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (result, 8);
1060                 // XXX Don't trace Multics idle loop
1061                 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
1062                   {
1063                     if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1064                       {
1065                         for (uint i = 0; i < 8; i ++)
1066                           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1067                                      "Read8 (Actual) Read:  iefpFinalAddress="
1068                                      "%08o  readData=%012"PRIo64"\n",
1069                                      cpu.iefpFinalAddress + i, result [i]);
1070                       }
1071 #ifdef TESTING
1072                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read8");
1073                     for (uint i = 0; i < 8; i ++)
1074                       HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "Read8");
1075 #endif
1076                   }
1077                 return;
1078               }
1079           }
1080       }
1081   }
1082 
1083 void Read16 (word18 address, word36 * result)
     /*  */
1084   {
1085     address &= paragraphMask; // Round to 8 word boundary
1086     Read8 (address, result, cpu.currentInstruction.b29);
1087     Read8 (address + 8, result + 8, cpu.currentInstruction.b29);
1088     return;
1089   }
1090 
1091 void ReadPage (word18 address, word36 * result, bool isAR)
     /*  */
1092   {
1093     if ((address & PGMK) != 0)
1094       {
1095         sim_warn ("ReadPage not on boundary %06o\n", address);
1096       }
1097     address &= (word18) ~PGMK; // Round to page boundary
1098     cpu.TPR.CA = cpu.iefpFinalAddress = address;
1099 
1100     bool isBAR = get_bar_mode ();
1101 
1102     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
1103       {
1104         goto B29;
1105       }
1106 
1107     switch (get_addr_mode ())
1108       {
1109         case ABSOLUTE_mode:
1110           {
1111             if (isBAR)
1112               {
1113                 set_apu_status (apuStatus_FABS); // XXX maybe...
1114                 cpu.iefpFinalAddress = get_BAR_address (address);
1115 
1116                 fauxDoAppendCycle (APU_DATA_READ);
1117                 core_readN (cpu.iefpFinalAddress, result, PGSZ, __func__);
1118                 if_sim_debug (DBG_FINAL, & cpu_dev)
1119                   {
1120                     for (uint i = 0; i < PGSZ; i ++)
1121                       sim_debug (DBG_FINAL, & cpu_dev,
1122                                  "ReadPage (Actual) Read:       bar address="
1123                                  "%08o  readData=%012"PRIo64"\n",
1124                                   address + i, result [i]);
1125                   }
1126 #ifdef TESTING
1127                 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadPage AB");
1128                 for (uint i = 0; i < PGSZ; i ++)
1129                   HDBGMRead (cpu.iefpFinalAddress + i, result [i], "ReadPage AB");
1130 #endif
1131                 return;
1132               }
1133             else
1134               {
1135                 set_apu_status (apuStatus_FABS);
1136                 fauxDoAppendCycle (APU_DATA_READ);
1137                 core_readN (address, result, PGSZ, __func__);
1138                 if_sim_debug (DBG_FINAL, & cpu_dev)
1139                   {
1140                     for (uint i = 0; i < PGSZ; i ++)
1141                       sim_debug (DBG_FINAL, & cpu_dev,
1142                                  "ReadPage (Actual) Read:       abs address="
1143                                  "%08o  readData=%012"PRIo64"\n",
1144                                  address + i, result [i]);
1145                   }
1146 #ifdef TESTING
1147                 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadPage ABS");
1148                 for (uint i = 0; i < PGSZ; i ++)
1149                   HDBGMRead (address + i, result [i], "ReadPage ABS");
1150 #endif
1151                 return;
1152               }
1153           }
1154 
1155         case APPEND_mode:
1156           {
1157 B29:;
1158             if (isBAR)
1159               {
1160                 cpu.TPR.CA = get_BAR_address (address);
1161                 cpu.TPR.TSR = cpu.PPR.PSR;
1162                 cpu.TPR.TRR = cpu.PPR.PRR;
1163                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_READ, result, PGSZ);
1164                 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (result, PGSZ);
1165                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1166                   {
1167                     for (uint i = 0; i < PGSZ; i ++)
1168                      sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1169                                 "ReadPage (Actual) Read:  bar iefpFinalAddress="
1170                                 "%08o  readData=%012"PRIo64"\n",
1171                                 cpu.iefpFinalAddress + i, result [i]);
1172                   }
1173 #ifdef TESTING
1174                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadPage B");
1175                 for (uint i = 0; i < PGSZ; i ++)
1176                   HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage B");
1177 #endif
1178 
1179                 return;
1180               }
1181             else
1182               {
1183                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_READ, result, PGSZ);
1184                 cpu.iefpFinalAddress = doAppendCycleAPUDataRead (result, PGSZ);
1185                 // XXX Don't trace Multics idle loop
1186                 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
1187                   {
1188                     if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1189                       {
1190                         for (uint i = 0; i < PGSZ; i ++)
1191                           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1192                                      "ReadPage (Actual) Read:  iefpFinalAddress"
1193                                      "=%08o  readData=%012"PRIo64"\n",
1194                                      cpu.iefpFinalAddress + i, result [i]);
1195                       }
1196 #ifdef TESTING
1197                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadPage");
1198                     for (uint i = 0; i < PGSZ; i ++)
1199                       HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage");
1200 #endif
1201                   }
1202                 return;
1203               }
1204           }
1205       }
1206   }
1207 
1208 #ifdef OLDAPP
1209 void Write (word18 address, word36 data, processor_cycle_type cyctyp) {
     /*  */
1210   cpu.TPR.CA = cpu.iefpFinalAddress = address;
1211 
1212   bool isBAR = get_bar_mode ();
1213 
1214   if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29))
1215     goto B29;
1216 
1217   switch (get_addr_mode ()) {
1218     case ABSOLUTE_mode: {
1219       if (isBAR) {
1220         cpu.iefpFinalAddress = get_BAR_address (address);
1221         set_apu_status (apuStatus_FABS); // XXX maybe...
1222         fauxDoAppendCycle (cyctyp);
1223         if (cyctyp == OPERAND_STORE && cpu.useZone)
1224           core_write_zone (cpu.iefpFinalAddress, data, __func__);
1225         else
1226           core_write (cpu.iefpFinalAddress, data, __func__);
1227         sim_debug (DBG_FINAL, & cpu_dev, "Write(Actual) Write:      bar address=%08o writeData=%012"PRIo64"\n", address, data);
1228 # ifdef TESTING
1229         HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write ABBR");
1230         HDBGMWrite (cpu.iefpFinalAddress, data, "Write ABBR");
1231 # endif
1232         return;
1233       } else {
1234         set_apu_status (apuStatus_FABS);
1235         fauxDoAppendCycle (cyctyp);
1236         if (cyctyp == OPERAND_STORE && cpu.useZone)
1237           core_write_zone (address, data, __func__);
1238         else
1239           core_write (address, data, __func__);
1240         sim_debug (DBG_FINAL, & cpu_dev, "Write(Actual) Write:      abs address=%08o writeData=%012"PRIo64"\n", address, data);
1241 # ifdef TESTING
1242         HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write AB");
1243         HDBGMWrite (address, data, "Write AB");
1244 # endif
1245         return;
1246       }
1247     }
1248 
1249     case APPEND_mode: {
1250 B29:
1251       if (isBAR) {
1252         cpu.TPR.CA = get_BAR_address (address);
1253         cpu.TPR.TSR = cpu.PPR.PSR;
1254         cpu.TPR.TRR = cpu.PPR.PRR;
1255         cpu.iefpFinalAddress = do_append_cycle (cyctyp, & data, 1);
1256         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data);
1257 # ifdef TESTING
1258         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write BR");
1259         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write BR");
1260 # endif
1261         return;
1262       } else {
1263         cpu.iefpFinalAddress = do_append_cycle (cyctyp, & data, 1);
1264         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data);
1265 # ifdef TESTING
1266         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write");
1267         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write");
1268 # endif
1269         return;
1270       }
1271     }
1272   }
1273 }
1274 #endif // OLDAPP
1275 
1276 #ifndef OLDAPP
1277 void WriteAPUDataStore (word18 address, word36 data) {
     /*  */
1278   cpu.TPR.CA = cpu.iefpFinalAddress = address;
1279 
1280   bool isBAR = get_bar_mode ();
1281 
1282   if (cpu.cu.XSF || cpu.currentInstruction.b29)
1283     goto B29;
1284 
1285   switch (get_addr_mode ()) {
1286     case ABSOLUTE_mode: {
1287       if (isBAR) {
1288         cpu.iefpFinalAddress = get_BAR_address (address);
1289         set_apu_status (apuStatus_FABS); // XXX maybe...
1290         fauxDoAppendCycle (APU_DATA_STORE);
1291         core_write (cpu.iefpFinalAddress, data, __func__);
1292         sim_debug (DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write:      bar address=%08o writeData=%012"PRIo64"\n", address, data);
1293 # ifdef TESTING
1294         HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "WriteAPUDataStore ABBR");
1295         HDBGMWrite (cpu.iefpFinalAddress, data, "WriteAPUDataStore ABBR");
1296 # endif
1297         return;
1298       } else {
1299         set_apu_status (apuStatus_FABS);
1300         fauxDoAppendCycle (APU_DATA_STORE);
1301         core_write (address, data, __func__);
1302         sim_debug (DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write:      abs address=%08o writeData=%012"PRIo64"\n", address, data);
1303 # ifdef TESTING
1304         HDBGIEFP (hdbgIEFP_abs_write, 0, address, "WriteAPUDataStore AB");
1305         HDBGMWrite (address, data, "WriteAPUDataStore AB");
1306 # endif
1307         return;
1308       }
1309     }
1310 
1311     case APPEND_mode: {
1312 B29:
1313       if (isBAR) {
1314         cpu.TPR.CA = get_BAR_address (address);
1315         cpu.TPR.TSR = cpu.PPR.PSR;
1316         cpu.TPR.TRR = cpu.PPR.PRR;
1317         cpu.iefpFinalAddress = doAppendCycleAPUDataStore (& data, 1);
1318         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data);
1319 # ifdef TESTING
1320         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteAPUDataStore BR");
1321         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore BR");
1322 # endif
1323         return;
1324       } else {
1325         cpu.iefpFinalAddress = doAppendCycleAPUDataStore (& data, 1);
1326         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data);
1327 # ifdef TESTING
1328         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteAPUDataStore");
1329         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore");
1330 # endif
1331         return;
1332       }
1333     }
1334   }
1335 }
1336 
1337 void WriteOperandStore (word18 address, word36 data) {
     /*  */
1338   cpu.TPR.CA = cpu.iefpFinalAddress = address;
1339 
1340   bool isBAR = get_bar_mode ();
1341 
1342   if (cpu.cu.XSF || cpu.currentInstruction.b29)
1343     goto B29;
1344 
1345   switch (get_addr_mode ()) {
1346     case ABSOLUTE_mode: {
1347       if (isBAR) {
1348         cpu.iefpFinalAddress = get_BAR_address (address);
1349         set_apu_status (apuStatus_FABS); // XXX maybe...
1350         fauxDoAppendCycle (OPERAND_STORE);
1351         if (cpu.useZone)
1352           core_write_zone (cpu.iefpFinalAddress, data, __func__);
1353         else
1354           core_write (cpu.iefpFinalAddress, data, __func__);
1355         sim_debug (DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write:      bar address=%08o writeData=%012"PRIo64"\n", address, data);
1356 # ifdef TESTING
1357         HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "WriteOperandStore ABBR");
1358         HDBGMWrite (cpu.iefpFinalAddress, data, "WriteOperandStore ABBR");
1359 # endif
1360         return;
1361       } else {
1362         set_apu_status (apuStatus_FABS);
1363         fauxDoAppendCycle (OPERAND_STORE);
1364         if (cpu.useZone)
1365           core_write_zone (address, data, __func__);
1366         else
1367           core_write (address, data, __func__);
1368         sim_debug (DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write:      abs address=%08o writeData=%012"PRIo64"\n", address, data);
1369 # ifdef TESTING
1370         HDBGIEFP (hdbgIEFP_abs_write, 0, address, "WriteOperandStore AB");
1371         HDBGMWrite (address, data, "WriteOperandStore AB");
1372 # endif
1373         return;
1374       }
1375     }
1376 
1377     case APPEND_mode: {
1378 B29:
1379       if (isBAR) {
1380         cpu.TPR.CA = get_BAR_address (address);
1381         cpu.TPR.TSR = cpu.PPR.PSR;
1382         cpu.TPR.TRR = cpu.PPR.PRR;
1383         cpu.iefpFinalAddress = doAppendCycleOperandStore (& data, 1);
1384         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data);
1385 # ifdef TESTING
1386         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteOperandStore BR");
1387         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore BR");
1388 # endif
1389         return;
1390       } else {
1391         cpu.iefpFinalAddress = doAppendCycleOperandStore (& data, 1);
1392         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data);
1393 # ifdef TESTING
1394         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteOperandStore");
1395         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore");
1396 # endif
1397         return;
1398       }
1399     }
1400   }
1401 }
1402 #endif // !OLDAPP
1403 
1404 #ifdef OLDAPP
1405 void Write2 (word18 address, word36 * data, processor_cycle_type cyctyp)
     /*  */
1406   {
1407     cpu.TPR.CA = cpu.iefpFinalAddress = address;
1408     bool isBAR = get_bar_mode ();
1409 
1410     if (cpu.cu.XSF /*get_went_appending ()*/ || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29))
1411       goto B29;
1412 
1413     switch (get_addr_mode ())
1414       {
1415         case ABSOLUTE_mode:
1416           {
1417             if (isBAR)
1418               {
1419                 cpu.iefpFinalAddress = get_BAR_address (address);
1420                 set_apu_status (apuStatus_FABS); // XXX maybe...
1421                 fauxDoAppendCycle (cyctyp);
1422                 core_write2 (cpu.iefpFinalAddress, data [0], data [1],
1423                               __func__);
1424 # ifdef TESTING
1425                 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write2 ABBR");
1426                 HDBGMWrite (cpu.iefpFinalAddress, data [0], "Write2 ABBR evn");
1427                 HDBGMWrite (cpu.iefpFinalAddress+1, data [1], "Write2 ABBR odd");
1428 # endif
1429                 sim_debug (DBG_FINAL, & cpu_dev,
1430                            "Write2 (Actual) Write:      bar address=%08o "
1431                            "writeData=%012"PRIo64" %012"PRIo64"\n",
1432                            address, data [0], data [1]);
1433                 return;
1434               }
1435             else
1436               {
1437                 set_apu_status (apuStatus_FABS);
1438                 fauxDoAppendCycle (cyctyp);
1439                 core_write2 (address, data [0], data [1], __func__);
1440                 sim_debug (DBG_FINAL, & cpu_dev,
1441                            "Write2 (Actual) Write:      abs address=%08o "
1442                            "writeData=%012"PRIo64" %012"PRIo64"\n",
1443                            address, data [0], data [1]);
1444 # ifdef TESTING
1445                 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write2 AB");
1446                 HDBGMWrite (address, data [0], "Write2 AB evn");
1447                 HDBGMWrite (address+1, data [1], "Write2 AB odd");
1448 # endif
1449                 return;
1450               }
1451           }
1452 
1453         case APPEND_mode:
1454           {
1455 B29:
1456             if (isBAR)
1457               {
1458                 cpu.TPR.CA = get_BAR_address (address);
1459                 cpu.TPR.TSR = cpu.PPR.PSR;
1460                 cpu.TPR.TRR = cpu.PPR.PRR;
1461                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, data, 2);
1462                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1463                            "Write2 (Actual) Write: bar iefpFinalAddress=%08o "
1464                            "writeData=%012"PRIo64" %012"PRIo64"\n",
1465                            address, data [0], data [1]);
1466 # ifdef TESTING
1467                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2 BR");
1468                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 BR evn");
1469                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 BR odd");
1470 # endif
1471                 return;
1472               }
1473             else
1474               {
1475                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, data, 2);
1476                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1477                            "Write2 (Actual) Write: iefpFinalAddress=%08o "
1478                            "writeData=%012"PRIo64" %012"PRIo64"\n",
1479                            address, data [0], data [1]);
1480 # ifdef TESTING
1481                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2");
1482                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 evn");
1483                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 odd");
1484 # endif
1485                 return;
1486               }
1487           }
1488       }
1489   }
1490 #endif // OLDAPP
1491 
1492 #ifndef OLDAPP
1493 void Write2OperandStore (word18 address, word36 * data) {
     /*  */
1494   cpu.TPR.CA = cpu.iefpFinalAddress = address;
1495   bool isBAR = get_bar_mode ();
1496 
1497   if (cpu.cu.XSF || cpu.currentInstruction.b29)
1498     goto B29;
1499 
1500   switch (get_addr_mode ()) {
1501     case ABSOLUTE_mode: {
1502       if (isBAR) {
1503         cpu.iefpFinalAddress = get_BAR_address (address);
1504         set_apu_status (apuStatus_FABS); // XXX maybe...
1505         fauxDoAppendCycle (OPERAND_STORE);
1506         core_write2 (cpu.iefpFinalAddress, data [0], data [1], __func__);
1507 # ifdef TESTING
1508         HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write2OperandStore ABBR");
1509         HDBGMWrite (cpu.iefpFinalAddress, data [0], "Write2OperandStore ABBR evn");
1510         HDBGMWrite (cpu.iefpFinalAddress+1, data [1], "Write2OperandStore ABBR odd");
1511 # endif
1512         sim_debug (DBG_FINAL, & cpu_dev, "Write2OperandStore (Actual) Write:      bar address=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n", address, data [0], data [1]);
1513         return;
1514       } else {
1515         set_apu_status (apuStatus_FABS);
1516         fauxDoAppendCycle (OPERAND_STORE);
1517         core_write2 (address, data [0], data [1], __func__);
1518         sim_debug (DBG_FINAL, & cpu_dev, "Write2OperandStore (Actual) Write:      abs address=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n", address, data [0], data [1]);
1519 # ifdef TESTING
1520         HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write2OperandStore AB");
1521         HDBGMWrite (address, data [0], "Write2OperandStore AB evn");
1522         HDBGMWrite (address+1, data [1], "Write2OperandStore AB odd");
1523 # endif
1524         return;
1525       }
1526     }
1527 
1528     case APPEND_mode: {
1529 B29:
1530       if (isBAR) {
1531         cpu.TPR.CA = get_BAR_address (address);
1532         cpu.TPR.TSR = cpu.PPR.PSR;
1533         cpu.TPR.TRR = cpu.PPR.PRR;
1534         cpu.iefpFinalAddress = doAppendCycleOperandStore (data, 2);
1535         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write2OperandStore (Actual) Write: bar iefpFinalAddress=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n", address, data [0], data [1]);
1536 # ifdef TESTING
1537         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2OperandStore BR");
1538         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore BR evn");
1539         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore BR odd");
1540 # endif
1541         return;
1542       } else {
1543         cpu.iefpFinalAddress = doAppendCycleOperandStore (data, 2);
1544         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write2OperandStore (Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n", address, data [0], data [1]);
1545 # ifdef TESTING
1546         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2OperandStore");
1547         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore evn");
1548         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore odd");
1549 # endif
1550         return;
1551       }
1552     }
1553   }
1554 }
1555 #endif // !OLDAPP
1556 
1557 void Write1 (word18 address, word36 data, bool isAR)
     /*  */
1558   {
1559     cpu.TPR.CA = cpu.iefpFinalAddress = address;
1560     bool isBAR = get_bar_mode ();
1561     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
1562       goto B29;
1563     switch (get_addr_mode ())
1564       {
1565         case ABSOLUTE_mode:
1566           {
1567             if (isBAR)
1568              {
1569                 cpu.iefpFinalAddress = get_BAR_address (address);
1570                 set_apu_status (apuStatus_FABS); // XXX maybe...
1571                 fauxDoAppendCycle (APU_DATA_STORE);
1572                 core_write (cpu.iefpFinalAddress, data, __func__);
1573                 sim_debug (DBG_FINAL, & cpu_dev,
1574                            "Write1(Actual) Write:      bar address=%08o "
1575                            "writeData=%012"PRIo64"\n",
1576                            address, data);
1577 #ifdef TESTING
1578                 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write1 ABBR");
1579                 HDBGMWrite (cpu.iefpFinalAddress, data, "Write1 ABBR");
1580 #endif
1581                 return;
1582               }
1583             else
1584               {
1585                 set_apu_status (apuStatus_FABS);
1586                 fauxDoAppendCycle (APU_DATA_STORE);
1587                 core_write (address, data, __func__);
1588                 sim_debug (DBG_FINAL, & cpu_dev,
1589                            "Write1(Actual) Write:      abs address=%08o "
1590                            "writeData=%012"PRIo64"\n",
1591                            address, data);
1592 #ifdef TESTING
1593                 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write1 AB");
1594                 HDBGMWrite (address, data, "Write1 AB");
1595 #endif
1596                 return;
1597               }
1598           }
1599 
1600         case APPEND_mode:
1601           {
1602 B29:
1603             if (isBAR)
1604               {
1605                 cpu.TPR.CA = get_BAR_address (address);
1606                 cpu.TPR.TSR = cpu.PPR.PSR;
1607                 cpu.TPR.TRR = cpu.PPR.PRR;
1608                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, & data, 1);
1609                 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (& data, 1);
1610                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1611                            "Write8(Actual) Write: bar iefpFinalAddress="
1612                            "%08o writeData=%012"PRIo64"\n",
1613                            cpu.iefpFinalAddress, data);
1614 #ifdef TESTING
1615                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write1 BR");
1616                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1 BR");
1617 #endif
1618                 return;
1619               }
1620             else
1621               {
1622                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, & data, 1);
1623                 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (& data, 1);
1624                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1625                            "Write(Actual) Write: iefpFinalAddress=%08o "
1626                            "writeData=%012"PRIo64"\n",
1627                            cpu.iefpFinalAddress, data);
1628 #ifdef TESTING
1629                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write1");
1630                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1");
1631 #endif
1632                 return;
1633               }
1634           }
1635       }
1636   }
1637 
1638 void Write8 (word18 address, word36 * data, bool isAR)
     /*  */
1639   {
1640     address &= paragraphMask; // Round to 8 word boundarryt
1641     cpu.TPR.CA = cpu.iefpFinalAddress = address;
1642 
1643     bool isBAR = get_bar_mode ();
1644 
1645     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
1646       goto B29;
1647 
1648     switch (get_addr_mode ())
1649      {
1650         case ABSOLUTE_mode:
1651           {
1652             if (isBAR)
1653              {
1654                 cpu.iefpFinalAddress = get_BAR_address (address);
1655                 set_apu_status (apuStatus_FABS); // XXX maybe...
1656                 fauxDoAppendCycle (APU_DATA_STORE);
1657                 core_writeN (cpu.iefpFinalAddress, data, 8, __func__);
1658                 if_sim_debug (DBG_FINAL, & cpu_dev)
1659                   {
1660                     for (uint i = 0; i < 8; i ++)
1661                       sim_debug (DBG_FINAL, & cpu_dev,
1662                                  "Write8(Actual) Write:      bar address=%08o "
1663                                  "writeData=%012"PRIo64"\n",
1664                                  address + i, data [i]);
1665                   }
1666 #ifdef TESTING
1667                 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write8 ABBR");
1668                 for (uint i = 0; i < 8; i ++)
1669                   HDBGMWrite (cpu.iefpFinalAddress + i, data [i], "Write8 ABBR");
1670 #endif
1671                 return;
1672               }
1673             else
1674               {
1675                 set_apu_status (apuStatus_FABS);
1676                 fauxDoAppendCycle (APU_DATA_STORE);
1677                 core_writeN (address, data, 8, __func__);
1678                 if_sim_debug (DBG_FINAL, & cpu_dev)
1679                   {
1680                     for (uint i = 0; i < 8; i ++)
1681                       sim_debug (DBG_FINAL, & cpu_dev,
1682                                  "Write8(Actual) Write:      abs address=%08o "
1683                                  "writeData=%012"PRIo64"\n",
1684                                   address + i, data [i]);
1685                   }
1686 #ifdef TESTING
1687                 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write8 AB");
1688                 for (uint i = 0; i < 8; i ++)
1689                   HDBGMWrite (address + i, data [i], "Write8 AB");
1690 #endif
1691                 return;
1692               }
1693           }
1694 
1695         case APPEND_mode:
1696           {
1697 B29:
1698             if (isBAR)
1699               {
1700                 cpu.TPR.CA = get_BAR_address (address);
1701                 cpu.TPR.TSR = cpu.PPR.PSR;
1702                 cpu.TPR.TRR = cpu.PPR.PRR;
1703                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, data, 8);
1704                 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (data, 8);
1705                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1706                   {
1707                     for (uint i = 0; i < 8; i ++)
1708                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1709                                  "Write8(Actual) Write: bar iefpFinalAddress="
1710                                  "%08o writeData=%012"PRIo64"\n",
1711                                  cpu.iefpFinalAddress + i, data [i]);
1712                   }
1713 #ifdef TESTING
1714                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write8 BR");
1715                 for (uint i = 0; i < 8; i ++)
1716                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8 BR");
1717 #endif
1718 
1719                 return;
1720               }
1721             else
1722               {
1723                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, data, 8);
1724                 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (data, 8);
1725                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1726                   {
1727                     for (uint i = 0; i < 8; i ++)
1728                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1729                                  "Write8(Actual) Write: iefpFinalAddress=%08o "
1730                                  "writeData=%012"PRIo64"\n",
1731                                  cpu.iefpFinalAddress + i, data [i]);
1732                   }
1733 #ifdef TESTING
1734                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write8");
1735                 for (uint i = 0; i < 8; i ++)
1736                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8");
1737 #endif
1738 
1739                 return;
1740               }
1741           }
1742       }
1743   }
1744 
1745 void Write16 (word18 address, word36 * data)
     /*  */
1746   {
1747     address &= paragraphMask; // Round to 8 word boundary
1748     Write8 (address, data, cpu.currentInstruction.b29);
1749     Write8 (address + 8, data + 8, cpu.currentInstruction.b29);
1750   }
1751 
1752 void Write32 (word18 address, word36 * data)
     /*  */
1753   {
1754 //#define paragraphMask 077777770
1755     //address &= paragraphMask; // Round to 8 word boundary
1756     address &= 077777740; // Round to 32 word boundary
1757     Write8 (address, data, cpu.currentInstruction.b29);
1758     Write8 (address + 8, data + 8, cpu.currentInstruction.b29);
1759     Write8 (address + 16, data + 16, cpu.currentInstruction.b29);
1760     Write8 (address + 24, data + 24, cpu.currentInstruction.b29);
1761   }
1762 
1763 void WritePage (word18 address, word36 * data, bool isAR)
     /*  */
1764   {
1765     if ((address & PGMK) != 0)
1766       {
1767         sim_warn ("WritePage not on boundary %06o\n", address);
1768       }
1769     address &= (word18) ~PGMK; // Round to page boundary
1770     cpu.TPR.CA = cpu.iefpFinalAddress = address;
1771 
1772     bool isBAR = get_bar_mode ();
1773 
1774     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
1775       goto B29;
1776 
1777     switch (get_addr_mode ())
1778      {
1779         case ABSOLUTE_mode:
1780           {
1781             if (isBAR)
1782              {
1783                 cpu.iefpFinalAddress = get_BAR_address (address);
1784                 set_apu_status (apuStatus_FABS); // XXX maybe...
1785                 fauxDoAppendCycle (APU_DATA_STORE);
1786                 core_writeN (cpu.iefpFinalAddress, data, PGSZ, __func__);
1787                 if_sim_debug (DBG_FINAL, & cpu_dev)
1788                   {
1789                     for (uint i = 0; i < PGSZ; i ++)
1790                       sim_debug (DBG_FINAL, & cpu_dev,
1791                                  "WritePage(Actual) Write:      bar address="
1792                                  "%08o writeData=%012"PRIo64"\n",
1793                                  address + i, data [i]);
1794                   }
1795 #ifdef TESTING
1796                 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "WritePage ABBR");
1797                 for (uint i = 0; i < PGSZ; i ++)
1798                   HDBGMWrite (cpu.iefpFinalAddress + i, data [i], "WritePage ABBR");
1799 #endif
1800                 return;
1801               }
1802             else
1803               {
1804                 set_apu_status (apuStatus_FABS);
1805                 fauxDoAppendCycle (APU_DATA_STORE);
1806                 core_writeN (address, data, PGSZ, __func__);
1807                 if_sim_debug (DBG_FINAL, & cpu_dev)
1808                   {
1809                     for (uint i = 0; i < PGSZ; i ++)
1810                       sim_debug (DBG_FINAL, & cpu_dev,
1811                                  "WritePage(Actual) Write:      abs address="
1812                                  "%08o writeData=%012"PRIo64"\n",
1813                                  address + i, data [i]);
1814                   }
1815 #ifdef TESTING
1816                 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "WritePage AB");
1817                 for (uint i = 0; i < PGSZ; i ++)
1818                   HDBGMWrite (address + i, data [i], "WritePage AB");
1819 #endif
1820                 return;
1821               }
1822           }
1823 
1824         case APPEND_mode:
1825           {
1826 B29:
1827             if (isBAR)
1828               {
1829                 cpu.TPR.CA = get_BAR_address (address);
1830                 cpu.TPR.TSR = cpu.PPR.PSR;
1831                 cpu.TPR.TRR = cpu.PPR.PRR;
1832                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, data, PGSZ);
1833                 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (data, PGSZ);
1834                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1835                   {
1836                     for (uint i = 0; i < PGSZ; i ++)
1837                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1838                                  "WritePage(Actual) Write: bar "
1839                                  "iefpFinalAddress=%08o writeData=%012"PRIo64
1840                                  "\n",
1841                                  cpu.iefpFinalAddress + i, data [i]);
1842                   }
1843 #ifdef TESTING
1844                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WritePage BR");
1845                 for (uint i = 0; i < PGSZ; i ++)
1846                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage BR");
1847 #endif
1848                 return;
1849               }
1850             else
1851               {
1852                 //cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, data, PGSZ);
1853                 cpu.iefpFinalAddress = doAppendCycleAPUDataStore (data, PGSZ);
1854                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
1855                   {
1856                     for (uint i = 0; i < PGSZ; i ++)
1857                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1858                                  "WritePage(Actual) Write: iefpFinalAddress="
1859                                  "%08o writeData=%012"PRIo64"\n",
1860                                  cpu.iefpFinalAddress + i, data [i]);
1861                   }
1862 #ifdef TESTING
1863                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WritePage");
1864                 for (uint i = 0; i < PGSZ; i ++)
1865                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage");
1866 #endif
1867 
1868                 return;
1869               }
1870           }
1871       }
1872   }
1873 
1874 void ReadIndirect (void)
     /*  */
1875   {
1876     if (cpu.TPR.CA & 1) // is odd?
1877       {
1878         ReadIndirectWordFetch (cpu.TPR.CA, cpu.itxPair);
1879         cpu.itxPair[1] = MASK36; // fill with ones for debugging
1880       }
1881     else
1882       {
1883         Read2IndirectWordFetch (cpu.TPR.CA, cpu.itxPair);
1884       }
1885   }