src/dps8/doAppendCycleABSA.h

/* */
This source file includes following definitions.
doAppendCycleABSA
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: b05ae630-171d-11ee-b5d9-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2022-2023 Charles Anthony
   9  * Copyright (c) 2022-2023 Jeffrey H. Johnson <trnsz@pobox.com>
  10  * Copyright (c) 2023-2023 The DPS8M Development Team
  11  *
  12  * All rights reserved.
  13  *
  14  * This software is made available under the terms of the ICU
  15  * License, version 1.8.1 or later.  For more details, see the
  16  * LICENSE.md file at the top-level directory of this distribution.
  17  *
  18  * ---------------------------------------------------------------------------
  19  */
  20 
  21 #undef thisCycle
  22 #define thisCycle ABSA_CYCLE
  23 word24 doAppendCycleABSA (word36 * data, uint nWords) {
     /*  */
  24   DCDstruct * i = & cpu.currentInstruction;
  25   DBGAPP ("doAppendCycleABSA(Entry) thisCycle=ABSA_CYCLE\n");
  26   DBGAPP ("doAppendCycleABSA(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle));
  27   DBGAPP ("doAppendCycleABSA(Entry) CA %06o\n", cpu.TPR.CA);
  28   DBGAPP ("doAppendCycleABSA(Entry) n=%2u\n", nWords);
  29   DBGAPP ("doAppendCycleABSA(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR);
  30   DBGAPP ("doAppendCycleABSA(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
  31 
  32   if (i->b29) {
  33     DBGAPP ("doAppendCycleABSA(Entry) isb29 PRNO %o\n", GET_PRN (IWB_IRODD));
  34   }
  35 
  36   bool nomatch = true;
  37   if (cpu.tweaks.enable_wam) {
  38     // AL39: The associative memory is ignored (forced to "no match") during
  39     // address preparation.
  40     // lptp,lptr,lsdp,lsdr,sptp,sptr,ssdp,ssdr
  41     // Unfortunately, ISOLTS doesn't try to execute any of these in append mode.
  42     // XXX should this be only for OPERAND_READ and OPERAND_STORE?
  43     nomatch = ((i->opcode == 0232 || i->opcode == 0254 ||
  44                 i->opcode == 0154 || i->opcode == 0173) &&
  45                 i->opcodeX ) ||
  46               ((i->opcode == 0557 || i->opcode == 0257) &&
  47                 ! i->opcodeX);
  48   }
  49 
  50   processor_cycle_type lastCycle = cpu.apu.lastCycle;
  51   cpu.apu.lastCycle = ABSA_CYCLE;
  52 
  53   DBGAPP ("doAppendCycleABSA(Entry) XSF %o\n", cpu.cu.XSF);
  54 
  55   PNL (L68_ (cpu.apu.state = 0;))
  56 
  57   cpu.RSDWH_R1 = 0;
  58 
  59   cpu.acvFaults = 0;
  60 
  61 //#define FMSG(x) x
  62 #define FMSG(x)
  63   FMSG (char * acvFaultsMsg = "<unknown>";)
  64 
  65   word24 finalAddress = (word24) -1;  // not everything requires a final
  66                                       // address
  67 
  68 //
  69 //  A:
  70 //    Get SDW
  71 
  72   PNL (cpu.APUMemAddr = cpu.TPR.CA;)
  73 
  74   DBGAPP ("doAppendCycleABSA(A)\n");
  75 
  76   // is SDW for C(TPR.TSR) in SDWAM?
  77   if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) {
  78     // No
  79     DBGAPP ("doAppendCycleABSA(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
  80 
  81     DBGAPP ("doAppendCycleABSA(A):DSBR.U=%o\n", cpu.DSBR.U);
  82 
  83     if (cpu.DSBR.U == 0) {
  84       fetch_dsptw (cpu.TPR.TSR);
  85 
  86       if (! cpu.PTW0.DF)
  87         doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleABSA(A): PTW0.F == 0");
  88 
  89       if (! cpu.PTW0.U)
  90         modify_dsptw (cpu.TPR.TSR);
  91 
  92       fetch_psdw (cpu.TPR.TSR);
  93     } else
  94       fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
  95 
  96     // load SDWAM .....
  97     load_sdwam (cpu.TPR.TSR, nomatch);
  98   }
  99   DBGAPP ("doAppendCycleABSA(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E);
 100 
 101   // Yes...
 102   cpu.RSDWH_R1 = cpu.SDW->R1;
 103 
 104 ////////////////////////////////////////
 105 //
 106 // Sheet 3: "B"
 107 //
 108 ////////////////////////////////////////
 109 
 110 //
 111 // B: Check the ring
 112 //
 113 
 114   DBGAPP ("doAppendCycleABSA(B)\n");
 115 
 116   // check ring bracket consistency
 117 
 118   //C(SDW.R1) <= C(SDW.R2) <= C(SDW .R3)?
 119   if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) {
 120     // Set fault ACV0 = IRO
 121     cpu.acvFaults |= ACV0;
 122     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 123     FMSG (acvFaultsMsg = "acvFaults(B) C(SDW.R1) <= C(SDW.R2) <= " "C(SDW .R3)";)
 124   }
 125 
 126   // lastCycle == RTCD_OPERAND_FETCH
 127   // if a fault happens between the RTCD_OPERAND_FETCH and the INSTRUCTION_FETCH
 128   // of the next instruction - this happens about 35 time for just booting  and
 129   // shutting down multics -- a stored lastCycle is useless.
 130   // the opcode is preserved across faults and only replaced as the
 131   // INSTRUCTION_FETCH succeeds.
 132   if (lastCycle == RTCD_OPERAND_FETCH)
 133     sim_warn ("%s: lastCycle == RTCD_OPERAND_FETCH opcode %0#o\n", __func__, i->opcode);
 134 
 135   //
 136   // check read bracket for read access
 137   //
 138 
 139   DBGAPP ("doAppendCycleABSA(B):!STR-OP\n");
 140 
 141   // No
 142   // C(TPR.TRR) > C(SDW .R2)?
 143   if (cpu.TPR.TRR > cpu.SDW->R2) {
 144     DBGAPP ("ACV3\n");
 145     DBGAPP ("doAppendCycleABSA(B) ACV3\n");
 146     //Set fault ACV3 = ORB
 147     cpu.acvFaults |= ACV3;
 148     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 149     FMSG (acvFaultsMsg = "acvFaults(B) C(TPR.TRR) > C(SDW .R2)";)
 150   }
 151 
 152   if (cpu.SDW->R == 0) {
 153     // isolts 870
 154     cpu.TPR.TRR = cpu.PPR.PRR;
 155 
 156     //C(PPR.PSR) = C(TPR.TSR)?
 157     if (cpu.PPR.PSR != cpu.TPR.TSR) {
 158       DBGAPP ("ACV4\n");
 159       DBGAPP ("doAppendCycleABSA(B) ACV4\n");
 160       //Set fault ACV4 = R-OFF
 161       cpu.acvFaults |= ACV4;
 162       PNL (L68_ (cpu.apu.state |= apu_FLT;))
 163       FMSG (acvFaultsMsg = "acvFaults(B) C(PPR.PSR) = C(TPR.TSR)";)
 164     //} else {
 165       // sim_warn ("doAppendCycleABSA(B) SDW->R == 0 && cpu.PPR.PSR == cpu.TPR.TSR: %0#o\n", cpu.PPR.PSR);
 166     }
 167   }
 168 
 169 ////////////////////////////////////////
 170 //
 171 // Sheet 7: "G"
 172 //
 173 ////////////////////////////////////////
 174 
 175   DBGAPP ("doAppendCycleABSA(G)\n");
 176 
 177   //C(TPR.CA)0,13 > SDW.BOUND?
 178   if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) {
 179     DBGAPP ("ACV15\n");
 180     DBGAPP ("doAppendCycleABSA(G) ACV15\n");
 181     cpu.acvFaults |= ACV15;
 182     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 183     FMSG (acvFaultsMsg = "acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND";)
 184     DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n"
 185             "   CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o",
 186             cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND);
 187   }
 188 
 189   if (cpu.acvFaults) {
 190     DBGAPP ("doAppendCycleABSA(G) acvFaults\n");
 191     PNL (L68_ (cpu.apu.state |= apu_FLT;))
 192     // Initiate an access violation fault
 193     doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault");
 194   }
 195 
 196   // is segment C(TPR.TSR) paged?
 197   if (cpu.SDW->U)
 198     goto H; // Not paged
 199 
 200   // Yes. segment is paged ...
 201   // is PTW for C(TPR.CA) in PTWAM?
 202 
 203   DBGAPP ("doAppendCycleABSA(G) CA %06o\n", cpu.TPR.CA);
 204   if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { //TPR.CA))
 205     fetch_ptw (cpu.SDW, cpu.TPR.CA);
 206     loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM
 207   }
 208 
 209   // Prepage mode?
 210   // check for "uninterruptible" EIS instruction
 211   // ISOLTS-878 02: mvn,cmpn,mvne,ad3d; obviously also
 212   // ad2/3d,sb2/3d,mp2/3d,dv2/3d
 213   // DH03 p.8-13: probably also mve,btd,dtb
 214   if (i->opcodeX && ((i->opcode & 0770)== 0200|| (i->opcode & 0770) == 0220 || (i->opcode & 0770)== 020|| (i->opcode & 0770) == 0300)) {
 215     do_ptw2 (cpu.SDW, cpu.TPR.CA);
 216   }
 217   goto I;
 218 
 219 ////////////////////////////////////////
 220 //
 221 // Sheet 8: "H", "I"
 222 //
 223 ////////////////////////////////////////
 224 
 225 H:;
 226   DBGAPP ("doAppendCycleABSA(H): FANP\n");
 227 
 228   PNL (L68_ (cpu.apu.state |= apu_FANP;))
 229 
 230 
 231 
 232 
 233 
 234 
 235 
 236   set_apu_status (apuStatus_FANP);
 237 
 238   DBGAPP ("doAppendCycleABSA(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA);
 239 
 240   finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA;
 241   finalAddress &= 0xffffff;
 242   PNL (cpu.APUMemAddr = finalAddress;)
 243 
 244   DBGAPP ("doAppendCycleABSA(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 245 
 246   goto HI;
 247 
 248 I:;
 249 
 250   // final address paged
 251   set_apu_status (apuStatus_FAP);
 252   PNL (L68_ (cpu.apu.state |= apu_FAP;))
 253 
 254   word24 y2 = cpu.TPR.CA % 1024;
 255 
 256   // AL39: The hardware ignores low order bits of the main memory page
 257   // address according to page size
 258   finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2;
 259   finalAddress &= 0xffffff;
 260   PNL (cpu.APUMemAddr = finalAddress;)
 261 
 262 #ifdef L68
 263   if (cpu.MR_cache.emr && cpu.MR_cache.ihr)
 264     add_APU_history (APUH_FAP);
 265 #endif
 266   DBGAPP ("doAppendCycleABSA(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
 267 
 268   goto HI;
 269 
 270 HI:
 271   DBGAPP ("doAppendCycleABSA(HI)\n");
 272 
 273   goto Exit;
 274 
 275 Exit:;
 276 
 277   PNL (cpu.APUDataBusOffset = cpu.TPR.CA;)
 278   PNL (cpu.APUDataBusAddr = finalAddress;)
 279 
 280   PNL (L68_ (cpu.apu.state |= apu_FA;))
 281 
 282   DBGAPP ("doAppendCycleABSA (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
 283   DBGAPP ("doAppendCycleABSA (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
 284 
 285   return finalAddress;    // or 0 or -1???
 286 }
/* */
root/src/dps8/doAppendCycleABSA.h

INCLUDED FROM

DEFINITIONS
