This source file includes following definitions.
- print_default_base_system_script
- do_ini_line
- set_default_base_system
- boot_skip
- do_execute_fault
- do_restart
- set_sys_polling_interval
- set_sys_slow_polling_interval
- set_sys_poll_check_rate
- dps_debug_mme_cntdwn
- dps_debug_skip
- dps_debug_start
- dps_debug_stop
- dps_debug_break
- dps_debug_segno
- dps_debug_ringno
- dps_debug_bar
- abs_addr_n
- abs_addr
- lookup_book_segment
- add_book_segment
- add_book_component
- lookup_system_book_address
- lookup_address
- lookup_system_book_name
- list_source
- stack_trace
- list_source_at
- load_system_book
- add_system_book_entry
- lookup_system_book
- fetchSDW
- virtAddrN
- virt_address
- set_search_path
- brkbrk
- sbreak
- dfx1entry
- dfx1exit
- dv2scale
- dfx2entry
- mdfx3entry
- smfx1entry
- search_memory
- set_dbg_cpu_mask
- scraper
- clear_yield
- yield
- set_luf
- dbgevent_compar
- dbgevent_lookup
- set_dbgevent
- rewind_media
- load_media
- ready_media
- trkw
- trkr
- usr1_signal_handler
- systabInit
- hash32s
- dps8_init
- dps8_exit
- getAddress
- parse_addr
- fprint_addr
- fprint_sym
- parse_sym
- sys_show_config
- sys_set_break
- sys_show_break
- sys_set_config
- sys_reset
- dps8_init_strip
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32 #include <stdio.h>
33 #if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW64) && !defined(CROSS_MINGW32)
34 # include <signal.h>
35 # include <sys/mman.h>
36 #endif
37 #include <time.h>
38 #include <stdint.h>
39 #include <unistd.h>
40 #include <ctype.h>
41
42 #if defined(__APPLE__)
43 # include <pthread.h>
44 #endif
45
46 #include "dps8.h"
47 #include "dps8_sys.h"
48 #include "dps8_sir.h"
49 #include "dps8_iom.h"
50 #include "dps8_console.h"
51 #include "dps8_cable.h"
52 #include "dps8_cpu.h"
53 #include "dps8_faults.h"
54 #include "dps8_scu.h"
55 #include "dps8_state.h"
56 #include "dps8_ins.h"
57 #include "dps8_math.h"
58 #include "dps8_mt.h"
59 #include "dps8_socket_dev.h"
60 #include "dps8_disk.h"
61 #include "dps8_append.h"
62 #include "dps8_fnp2.h"
63 #include "dps8_crdrdr.h"
64 #include "dps8_crdpun.h"
65 #include "dps8_prt.h"
66 #include "dps8_urp.h"
67 #include "dps8_absi.h"
68 #include "dps8_mgp.h"
69 #include "dps8_utils.h"
70 #include "dps8_memalign.h"
71 #include "shm.h"
72 #include "ver.h"
73
74 #include "../simh/sim_os_mem.h"
75
76 #if defined(THREADZ) || defined(LOCKLESS)
77 # include "threadz.h"
78 #endif
79
80 #include "panelScraper.h"
81
82 #include "segldr.h"
83
84 #if defined(NO_LOCALE)
85 # define xstrerror_l strerror
86 #endif
87
88 #define DBG_CTR cpu.cycleCnt
89
90 #define ASSUME0 0
91
92 #if defined(FREE)
93 # undef FREE
94 #endif
95 #define FREE(p) do \
96 { \
97 free((p)); \
98 (p) = NULL; \
99 } while(0)
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108 struct system_state_s * system_state;
109
110 volAtomic word36 * M = NULL;
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116 const char* appname = "dps8";
117 char sim_name[] = "DPS8/M";
118 int32 sim_emax = 4;
119 static void dps8_init(void);
120 static void dps8_exit (void);
121 void (*sim_vm_init) (void) = & dps8_init;
122 void (*sim_vm_exit) (void) = & dps8_exit;
123
124 #if defined(TESTING)
125 static t_addr parse_addr(DEVICE *dptr, const char *cptr, const char **optr);
126 static void fprint_addr(FILE *stream, DEVICE *dptr, t_addr addr);
127 #endif
128
129 int32 luf_flag = 1;
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142 #if !defined(PERF_STRIP)
143 static char * default_base_system_script [] =
144 {
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223 "CABLE_RIPOUT",
224
225 "SET CPU NUNITS=6",
226 "SET IOM NUNITS=2",
227
228 "SET TAPE NUNITS=17",
229 "SET MTP NUNITS=1",
230
231
232
233
234 "SET IPC NUNITS=2",
235 "SET MSP NUNITS=2",
236 "SET DISK NUNITS=26",
237 "SET SCU NUNITS=4",
238 "SET OPC NUNITS=2",
239 "SET FNP NUNITS=8",
240 "SET URP NUNITS=10",
241 "SET RDR NUNITS=3",
242 "SET PUN NUNITS=3",
243 "SET PRT NUNITS=4",
244 # if defined (WITH_ABSI_DEV)
245 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW64) && !defined(CROSS_MINGW32)
246 "SET ABSI NUNITS=1",
247 # endif
248 # endif
249
250 # if defined(WITH_MGP_DEV)
251 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW64) && !defined(CROSS_MINGW32)
252 "SET MGP NUNITS=2",
253 # endif
254 # endif
255
256 # if defined(WITH_SOCKET_DEV)
257 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW64) && !defined(CROSS_MINGW32)
258 "SET SKC NUNITS=64",
259 # endif
260 # endif
261
262
263
264 "SET CPU0 CONFIG=FAULTBASE=Multics",
265
266 "SET CPU0 CONFIG=NUM=0",
267
268
269 "SET CPU0 CONFIG=DATA=024000717200",
270 "SET CPU0 CONFIG=ADDRESS=000000000000",
271
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287
288 "SET CPU0 CONFIG=PORT=A",
289 "SET CPU0 CONFIG=ASSIGNMENT=0",
290 "SET CPU0 CONFIG=INTERLACE=0",
291 "SET CPU0 CONFIG=ENABLE=1",
292 "SET CPU0 CONFIG=INIT_ENABLE=1",
293 "SET CPU0 CONFIG=STORE_SIZE=4M",
294
295 "SET CPU0 CONFIG=PORT=B",
296 "SET CPU0 CONFIG=ASSIGNMENT=1",
297 "SET CPU0 CONFIG=INTERLACE=0",
298 "SET CPU0 CONFIG=ENABLE=1",
299 "SET CPU0 CONFIG=INIT_ENABLE=1",
300 "SET CPU0 CONFIG=STORE_SIZE=4M",
301
302 "SET CPU0 CONFIG=PORT=C",
303 "SET CPU0 CONFIG=ASSIGNMENT=2",
304 "SET CPU0 CONFIG=INTERLACE=0",
305 "SET CPU0 CONFIG=ENABLE=1",
306 "SET CPU0 CONFIG=INIT_ENABLE=1",
307 "SET CPU0 CONFIG=STORE_SIZE=4M",
308
309 "SET CPU0 CONFIG=PORT=D",
310 "SET CPU0 CONFIG=ASSIGNMENT=3",
311 "SET CPU0 CONFIG=INTERLACE=0",
312 "SET CPU0 CONFIG=ENABLE=1",
313 "SET CPU0 CONFIG=INIT_ENABLE=1",
314 "SET CPU0 CONFIG=STORE_SIZE=4M",
315
316
317 "SET CPU0 CONFIG=MODE=Multics",
318
319 "SET CPU0 CONFIG=ENABLE_CACHE=enable",
320 "SET CPU0 CONFIG=SDWAM=enable",
321 "SET CPU0 CONFIG=PTWAM=enable",
322
323
324 "SET CPU0 CONFIG=SPEED=0",
325
326 "SET CPU0 CONFIG=DIS_ENABLE=enable",
327 "SET CPU0 CONFIG=STEADY_CLOCK=disable",
328 "SET CPU0 CONFIG=HALT_ON_UNIMPLEMENTED=disable",
329 "SET CPU0 CONFIG=ENABLE_WAM=disable",
330 "SET CPU0 CONFIG=REPORT_FAULTS=disable",
331 "SET CPU0 CONFIG=TRO_ENABLE=enable",
332 "SET CPU0 CONFIG=DRL_FATAL=disable",
333 "SET CPU0 CONFIG=USEMAP=disable",
334 "SET CPU0 CONFIG=PROM_INSTALLED=enable",
335 "SET CPU0 CONFIG=HEX_MODE_INSTALLED=disable",
336 "SET CPU0 CONFIG=CACHE_INSTALLED=enable",
337 "SET CPU0 CONFIG=CLOCK_SLAVE_INSTALLED=enable",
338
339
340
341 "SET CPU1 CONFIG=FAULTBASE=Multics",
342
343 "SET CPU1 CONFIG=NUM=1",
344
345
346 "SET CPU1 CONFIG=DATA=024000717200",
347 "SET CPU1 CONFIG=ADDRESS=000000000000",
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365 "SET CPU1 CONFIG=PORT=A",
366 "SET CPU1 CONFIG=ASSIGNMENT=0",
367 "SET CPU1 CONFIG=INTERLACE=0",
368 "SET CPU1 CONFIG=ENABLE=1",
369 "SET CPU1 CONFIG=INIT_ENABLE=1",
370 "SET CPU1 CONFIG=STORE_SIZE=4M",
371
372 "SET CPU1 CONFIG=PORT=B",
373 "SET CPU1 CONFIG=ASSIGNMENT=1",
374 "SET CPU1 CONFIG=INTERLACE=0",
375 "SET CPU1 CONFIG=ENABLE=1",
376 "SET CPU1 CONFIG=INIT_ENABLE=1",
377 "SET CPU1 CONFIG=STORE_SIZE=4M",
378
379 "SET CPU1 CONFIG=PORT=C",
380 "SET CPU1 CONFIG=ASSIGNMENT=2",
381 "SET CPU1 CONFIG=INTERLACE=0",
382 "SET CPU1 CONFIG=ENABLE=1",
383 "SET CPU1 CONFIG=INIT_ENABLE=1",
384 "SET CPU1 CONFIG=STORE_SIZE=4M",
385
386 "SET CPU1 CONFIG=PORT=D",
387 "SET CPU1 CONFIG=ASSIGNMENT=3",
388 "SET CPU1 CONFIG=INTERLACE=0",
389 "SET CPU1 CONFIG=ENABLE=1",
390 "SET CPU1 CONFIG=INIT_ENABLE=1",
391 "SET CPU1 CONFIG=STORE_SIZE=4M",
392
393
394 "SET CPU1 CONFIG=MODE=Multics",
395
396 "SET CPU1 CONFIG=ENABLE_CACHE=enable",
397 "SET CPU1 CONFIG=SDWAM=enable",
398 "SET CPU1 CONFIG=PTWAM=enable",
399
400
401 "SET CPU1 CONFIG=SPEED=0",
402
403 "SET CPU1 CONFIG=DIS_ENABLE=enable",
404 "SET CPU1 CONFIG=STEADY_CLOCK=disable",
405 "SET CPU1 CONFIG=HALT_ON_UNIMPLEMENTED=disable",
406 "SET CPU1 CONFIG=ENABLE_WAM=disable",
407 "SET CPU1 CONFIG=REPORT_FAULTS=disable",
408 "SET CPU1 CONFIG=TRO_ENABLE=enable",
409 "SET CPU1 CONFIG=DRL_FATAL=disable",
410 "SET CPU1 CONFIG=USEMAP=disable",
411 "SET CPU1 CONFIG=PROM_INSTALLED=enable",
412 "SET CPU1 CONFIG=HEX_MODE_INSTALLED=disable",
413 "SET CPU1 CONFIG=CACHE_INSTALLED=enable",
414 "SET CPU1 CONFIG=CLOCK_SLAVE_INSTALLED=enable",
415
416
417
418 "SET CPU2 CONFIG=FAULTBASE=Multics",
419
420 "SET CPU2 CONFIG=NUM=2",
421
422
423 "SET CPU2 CONFIG=DATA=024000717200",
424 "SET CPU2 CONFIG=ADDRESS=000000000000",
425
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442 "SET CPU2 CONFIG=PORT=A",
443 "SET CPU2 CONFIG=ASSIGNMENT=0",
444 "SET CPU2 CONFIG=INTERLACE=0",
445 "SET CPU2 CONFIG=ENABLE=1",
446 "SET CPU2 CONFIG=INIT_ENABLE=1",
447 "SET CPU2 CONFIG=STORE_SIZE=4M",
448
449 "SET CPU2 CONFIG=PORT=B",
450 "SET CPU2 CONFIG=ASSIGNMENT=1",
451 "SET CPU2 CONFIG=INTERLACE=0",
452 "SET CPU2 CONFIG=ENABLE=1",
453 "SET CPU2 CONFIG=INIT_ENABLE=1",
454 "SET CPU2 CONFIG=STORE_SIZE=4M",
455
456 "SET CPU2 CONFIG=PORT=C",
457 "SET CPU2 CONFIG=ASSIGNMENT=2",
458 "SET CPU2 CONFIG=INTERLACE=0",
459 "SET CPU2 CONFIG=ENABLE=1",
460 "SET CPU2 CONFIG=INIT_ENABLE=1",
461 "SET CPU2 CONFIG=STORE_SIZE=4M",
462
463 "SET CPU2 CONFIG=PORT=D",
464 "SET CPU2 CONFIG=ASSIGNMENT=3",
465 "SET CPU2 CONFIG=INTERLACE=0",
466 "SET CPU2 CONFIG=ENABLE=1",
467 "SET CPU2 CONFIG=INIT_ENABLE=1",
468 "SET CPU2 CONFIG=STORE_SIZE=4M",
469
470
471 "SET CPU2 CONFIG=MODE=Multics",
472
473 "SET CPU2 CONFIG=ENABLE_CACHE=enable",
474 "SET CPU2 CONFIG=SDWAM=enable",
475 "SET CPU2 CONFIG=PTWAM=enable",
476
477
478 "SET CPU2 CONFIG=SPEED=0",
479
480 "SET CPU2 CONFIG=DIS_ENABLE=enable",
481 "SET CPU2 CONFIG=STEADY_CLOCK=disable",
482 "SET CPU2 CONFIG=HALT_ON_UNIMPLEMENTED=disable",
483 "SET CPU2 CONFIG=ENABLE_WAM=disable",
484 "SET CPU2 CONFIG=REPORT_FAULTS=disable",
485 "SET CPU2 CONFIG=TRO_ENABLE=enable",
486 "SET CPU2 CONFIG=DRL_FATAL=disable",
487 "SET CPU2 CONFIG=USEMAP=disable",
488 "SET CPU2 CONFIG=PROM_INSTALLED=enable",
489 "SET CPU2 CONFIG=HEX_MODE_INSTALLED=disable",
490 "SET CPU2 CONFIG=CACHE_INSTALLED=enable",
491 "SET CPU2 CONFIG=CLOCK_SLAVE_INSTALLED=enable",
492
493
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495 "SET CPU3 CONFIG=FAULTBASE=Multics",
496
497 "SET CPU3 CONFIG=NUM=3",
498
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500 "SET CPU3 CONFIG=DATA=024000717200",
501 "SET CPU3 CONFIG=ADDRESS=000000000000",
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519 "SET CPU3 CONFIG=PORT=A",
520 "SET CPU3 CONFIG=ASSIGNMENT=0",
521 "SET CPU3 CONFIG=INTERLACE=0",
522 "SET CPU3 CONFIG=ENABLE=1",
523 "SET CPU3 CONFIG=INIT_ENABLE=1",
524 "SET CPU3 CONFIG=STORE_SIZE=4M",
525
526 "SET CPU3 CONFIG=PORT=B",
527 "SET CPU3 CONFIG=ASSIGNMENT=1",
528 "SET CPU3 CONFIG=INTERLACE=0",
529 "SET CPU3 CONFIG=ENABLE=1",
530 "SET CPU3 CONFIG=INIT_ENABLE=1",
531 "SET CPU3 CONFIG=STORE_SIZE=4M",
532
533 "SET CPU3 CONFIG=PORT=C",
534 "SET CPU3 CONFIG=ASSIGNMENT=2",
535 "SET CPU3 CONFIG=INTERLACE=0",
536 "SET CPU3 CONFIG=ENABLE=1",
537 "SET CPU3 CONFIG=INIT_ENABLE=1",
538 "SET CPU3 CONFIG=STORE_SIZE=4M",
539
540 "SET CPU3 CONFIG=PORT=D",
541 "SET CPU3 CONFIG=ASSIGNMENT=3",
542 "SET CPU3 CONFIG=INTERLACE=0",
543 "SET CPU3 CONFIG=ENABLE=1",
544 "SET CPU3 CONFIG=INIT_ENABLE=1",
545 "SET CPU3 CONFIG=STORE_SIZE=4M",
546
547
548 "SET CPU3 CONFIG=MODE=Multics",
549
550 "SET CPU3 CONFIG=ENABLE_CACHE=enable",
551 "SET CPU3 CONFIG=SDWAM=enable",
552 "SET CPU3 CONFIG=PTWAM=enable",
553
554
555 "SET CPU3 CONFIG=SPEED=0",
556
557 "SET CPU3 CONFIG=DIS_ENABLE=enable",
558 "SET CPU3 CONFIG=STEADY_CLOCK=disable",
559 "SET CPU3 CONFIG=HALT_ON_UNIMPLEMENTED=disable",
560 "SET CPU3 CONFIG=ENABLE_WAM=disable",
561 "SET CPU3 CONFIG=REPORT_FAULTS=disable",
562 "SET CPU3 CONFIG=TRO_ENABLE=enable",
563 "SET CPU3 CONFIG=DRL_FATAL=disable",
564 "SET CPU3 CONFIG=USEMAP=disable",
565 "SET CPU3 CONFIG=PROM_INSTALLED=enable",
566 "SET CPU3 CONFIG=HEX_MODE_INSTALLED=disable",
567 "SET CPU3 CONFIG=CACHE_INSTALLED=enable",
568 "SET CPU3 CONFIG=CLOCK_SLAVE_INSTALLED=enable",
569
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572 "SET CPU4 CONFIG=FAULTBASE=Multics",
573
574 "SET CPU4 CONFIG=NUM=4",
575
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577 "SET CPU4 CONFIG=DATA=024000717200",
578 "SET CPU4 CONFIG=ADDRESS=000000000000",
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596 "SET CPU4 CONFIG=PORT=A",
597 "SET CPU4 CONFIG=ASSIGNMENT=0",
598 "SET CPU4 CONFIG=INTERLACE=0",
599 "SET CPU4 CONFIG=ENABLE=1",
600 "SET CPU4 CONFIG=INIT_ENABLE=1",
601 "SET CPU4 CONFIG=STORE_SIZE=4M",
602
603 "SET CPU4 CONFIG=PORT=B",
604 "SET CPU4 CONFIG=ASSIGNMENT=1",
605 "SET CPU4 CONFIG=INTERLACE=0",
606 "SET CPU4 CONFIG=ENABLE=1",
607 "SET CPU4 CONFIG=INIT_ENABLE=1",
608 "SET CPU4 CONFIG=STORE_SIZE=4M",
609
610 "SET CPU4 CONFIG=PORT=C",
611 "SET CPU4 CONFIG=ASSIGNMENT=2",
612 "SET CPU4 CONFIG=INTERLACE=0",
613 "SET CPU4 CONFIG=ENABLE=1",
614 "SET CPU4 CONFIG=INIT_ENABLE=1",
615 "SET CPU4 CONFIG=STORE_SIZE=4M",
616
617 "SET CPU4 CONFIG=PORT=D",
618 "SET CPU4 CONFIG=ASSIGNMENT=3",
619 "SET CPU4 CONFIG=INTERLACE=0",
620 "SET CPU4 CONFIG=ENABLE=1",
621 "SET CPU4 CONFIG=INIT_ENABLE=1",
622 "SET CPU4 CONFIG=STORE_SIZE=4M",
623
624
625 "SET CPU4 CONFIG=MODE=Multics",
626
627 "SET CPU4 CONFIG=ENABLE_CACHE=enable",
628 "SET CPU4 CONFIG=SDWAM=enable",
629 "SET CPU4 CONFIG=PTWAM=enable",
630
631
632 "SET CPU4 CONFIG=SPEED=0",
633
634 "SET CPU4 CONFIG=DIS_ENABLE=enable",
635 "SET CPU4 CONFIG=STEADY_CLOCK=disable",
636 "SET CPU4 CONFIG=HALT_ON_UNIMPLEMENTED=disable",
637 "SET CPU4 CONFIG=ENABLE_WAM=disable",
638 "SET CPU4 CONFIG=REPORT_FAULTS=disable",
639 "SET CPU4 CONFIG=TRO_ENABLE=enable",
640 "SET CPU4 CONFIG=DRL_FATAL=disable",
641 "SET CPU4 CONFIG=USEMAP=disable",
642 "SET CPU4 CONFIG=PROM_INSTALLED=enable",
643 "SET CPU4 CONFIG=HEX_MODE_INSTALLED=disable",
644 "SET CPU4 CONFIG=CACHE_INSTALLED=enable",
645 "SET CPU4 CONFIG=CLOCK_SLAVE_INSTALLED=enable",
646
647
648
649 "SET CPU5 CONFIG=FAULTBASE=Multics",
650
651 "SET CPU5 CONFIG=NUM=5",
652
653
654 "SET CPU5 CONFIG=DATA=024000717200",
655 "SET CPU5 CONFIG=ADDRESS=000000000000",
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673 "SET CPU5 CONFIG=PORT=A",
674 "SET CPU5 CONFIG=ASSIGNMENT=0",
675 "SET CPU5 CONFIG=INTERLACE=0",
676 "SET CPU5 CONFIG=ENABLE=1",
677 "SET CPU5 CONFIG=INIT_ENABLE=1",
678 "SET CPU5 CONFIG=STORE_SIZE=4M",
679
680 "SET CPU5 CONFIG=PORT=B",
681 "SET CPU5 CONFIG=ASSIGNMENT=1",
682 "SET CPU5 CONFIG=INTERLACE=0",
683 "SET CPU5 CONFIG=ENABLE=1",
684 "SET CPU5 CONFIG=INIT_ENABLE=1",
685 "SET CPU5 CONFIG=STORE_SIZE=4M",
686
687 "SET CPU5 CONFIG=PORT=C",
688 "SET CPU5 CONFIG=ASSIGNMENT=2",
689 "SET CPU5 CONFIG=INTERLACE=0",
690 "SET CPU5 CONFIG=ENABLE=1",
691 "SET CPU5 CONFIG=INIT_ENABLE=1",
692 "SET CPU5 CONFIG=STORE_SIZE=4M",
693
694 "SET CPU5 CONFIG=PORT=D",
695 "SET CPU5 CONFIG=ASSIGNMENT=3",
696 "SET CPU5 CONFIG=INTERLACE=0",
697 "SET CPU5 CONFIG=ENABLE=1",
698 "SET CPU5 CONFIG=INIT_ENABLE=1",
699 "SET CPU5 CONFIG=STORE_SIZE=4M",
700
701
702 "SET CPU5 CONFIG=MODE=Multics",
703
704 "SET CPU5 CONFIG=ENABLE_CACHE=enable",
705 "SET CPU5 CONFIG=SDWAM=enable",
706 "SET CPU5 CONFIG=PTWAM=enable",
707
708
709 "SET CPU5 CONFIG=SPEED=0",
710
711 "SET CPU5 CONFIG=DIS_ENABLE=enable",
712 "SET CPU5 CONFIG=STEADY_CLOCK=disable",
713 "SET CPU5 CONFIG=HALT_ON_UNIMPLEMENTED=disable",
714 "SET CPU5 CONFIG=ENABLE_WAM=disable",
715 "SET CPU5 CONFIG=REPORT_FAULTS=disable",
716 "SET CPU5 CONFIG=TRO_ENABLE=enable",
717 "SET CPU5 CONFIG=DRL_FATAL=disable",
718 "SET CPU5 CONFIG=USEMAP=disable",
719 "SET CPU5 CONFIG=PROM_INSTALLED=enable",
720 "SET CPU5 CONFIG=HEX_MODE_INSTALLED=disable",
721 "SET CPU5 CONFIG=CACHE_INSTALLED=enable",
722 "SET CPU5 CONFIG=CLOCK_SLAVE_INSTALLED=enable",
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887 "SET IOM0 CONFIG=IOM_BASE=Multics",
888 "SET IOM0 CONFIG=MULTIPLEX_BASE=0120",
889 "SET IOM0 CONFIG=OS=Multics",
890 "SET IOM0 CONFIG=BOOT=tape",
891 "SET IOM0 CONFIG=TAPECHAN=012",
892 "SET IOM0 CONFIG=CARDCHAN=011",
893 "SET IOM0 CONFIG=SCUPORT=0",
894
895 "SET IOM0 CONFIG=PORT=0",
896 "SET IOM0 CONFIG=ADDR=0",
897 "SET IOM0 CONFIG=INTERLACE=0",
898 "SET IOM0 CONFIG=ENABLE=1",
899 "SET IOM0 CONFIG=INITENABLE=0",
900 "SET IOM0 CONFIG=HALFSIZE=0",
901 "SET IOM0 CONFIG=STORE_SIZE=4M",
902
903 "SET IOM0 CONFIG=PORT=1",
904 "SET IOM0 CONFIG=ADDR=1",
905 "SET IOM0 CONFIG=INTERLACE=0",
906 "SET IOM0 CONFIG=ENABLE=1",
907 "SET IOM0 CONFIG=INITENABLE=0",
908 "SET IOM0 CONFIG=HALFSIZE=0",
909 "SET IOM0 CONFIG=STORE_SIZE=4M",
910
911 "SET IOM0 CONFIG=PORT=2",
912 "SET IOM0 CONFIG=ADDR=2",
913 "SET IOM0 CONFIG=INTERLACE=0",
914 "SET IOM0 CONFIG=ENABLE=1",
915 "SET IOM0 CONFIG=INITENABLE=0",
916 "SET IOM0 CONFIG=HALFSIZE=0",
917 "SET IOM0 CONFIG=STORE_SIZE=4M",
918
919 "SET IOM0 CONFIG=PORT=3",
920 "SET IOM0 CONFIG=ADDR=3",
921 "SET IOM0 CONFIG=INTERLACE=0",
922 "SET IOM0 CONFIG=ENABLE=1",
923 "SET IOM0 CONFIG=INITENABLE=0",
924 "SET IOM0 CONFIG=HALFSIZE=0",
925 "SET IOM0 CONFIG=STORE_SIZE=4M",
926
927 "SET IOM0 CONFIG=PORT=4",
928 "SET IOM0 CONFIG=ENABLE=0",
929
930 "SET IOM0 CONFIG=PORT=5",
931 "SET IOM0 CONFIG=ENABLE=0",
932
933 "SET IOM0 CONFIG=PORT=6",
934 "SET IOM0 CONFIG=ENABLE=0",
935
936 "SET IOM0 CONFIG=PORT=7",
937 "SET IOM0 CONFIG=ENABLE=0",
938
939
940
941 "SET IOM1 CONFIG=IOM_BASE=Multics2",
942 "SET IOM1 CONFIG=MULTIPLEX_BASE=0121",
943 "SET IOM1 CONFIG=OS=Multics",
944 "SET IOM1 CONFIG=BOOT=tape",
945 "SET IOM1 CONFIG=TAPECHAN=012",
946 "SET IOM1 CONFIG=CARDCHAN=011",
947 "SET IOM1 CONFIG=SCUPORT=0",
948
949 "SET IOM1 CONFIG=PORT=0",
950 "SET IOM1 CONFIG=ADDR=0",
951 "SET IOM1 CONFIG=INTERLACE=0",
952 "SET IOM1 CONFIG=ENABLE=1",
953 "SET IOM1 CONFIG=INITENABLE=0",
954 "SET IOM1 CONFIG=HALFSIZE=0",
955
956 "SET IOM1 CONFIG=PORT=1",
957 "SET IOM1 CONFIG=ADDR=1",
958 "SET IOM1 CONFIG=INTERLACE=0",
959 "SET IOM1 CONFIG=ENABLE=1",
960 "SET IOM1 CONFIG=INITENABLE=0",
961 "SET IOM1 CONFIG=HALFSIZE=0",
962
963 "SET IOM1 CONFIG=PORT=2",
964 "SET IOM1 CONFIG=ENABLE=0",
965 "SET IOM1 CONFIG=PORT=3",
966 "SET IOM1 CONFIG=ENABLE=0",
967 "SET IOM1 CONFIG=PORT=4",
968 "SET IOM1 CONFIG=ENABLE=0",
969 "SET IOM1 CONFIG=PORT=5",
970 "SET IOM1 CONFIG=ENABLE=0",
971 "SET IOM1 CONFIG=PORT=6",
972 "SET IOM1 CONFIG=ENABLE=0",
973 "SET IOM1 CONFIG=PORT=7",
974 "SET IOM1 CONFIG=ENABLE=0",
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055 "SET SCU0 CONFIG=MODE=program",
1056 "SET SCU0 CONFIG=PORT0=enable",
1057 "SET SCU0 CONFIG=PORT1=enable",
1058 "SET SCU0 CONFIG=PORT2=enable",
1059 "SET SCU0 CONFIG=PORT3=enable",
1060 "SET SCU0 CONFIG=PORT4=enable",
1061 "SET SCU0 CONFIG=PORT5=enable",
1062 "SET SCU0 CONFIG=PORT6=enable",
1063 "SET SCU0 CONFIG=PORT7=enable",
1064 "SET SCU0 CONFIG=MASKA=7",
1065 "SET SCU0 CONFIG=MASKB=off",
1066 "SET SCU0 CONFIG=LWRSTORESIZE=7",
1067 "SET SCU0 CONFIG=CYCLIC=0040",
1068 "SET SCU0 CONFIG=NEA=0200",
1069 "SET SCU0 CONFIG=ONL=014",
1070 "SET SCU0 CONFIG=INT=0",
1071 "SET SCU0 CONFIG=LWR=0",
1072 "SET SCU0 CONFIG=CLOCK_DELTA=0",
1073
1074
1075
1076 "SET SCU1 CONFIG=MODE=program",
1077 "SET SCU1 CONFIG=PORT0=enable",
1078 "SET SCU1 CONFIG=PORT1=enable",
1079 "SET SCU1 CONFIG=PORT2=enable",
1080 "SET SCU1 CONFIG=PORT3=enable",
1081 "SET SCU1 CONFIG=PORT4=enable",
1082 "SET SCU1 CONFIG=PORT5=enable",
1083 "SET SCU1 CONFIG=PORT6=enable",
1084 "SET SCU1 CONFIG=PORT7=enable",
1085 "SET SCU1 CONFIG=MASKA=off",
1086 "SET SCU1 CONFIG=MASKB=off",
1087 "SET SCU1 CONFIG=LWRSTORESIZE=7",
1088 "SET SCU1 CONFIG=CYCLIC=0040",
1089 "SET SCU1 CONFIG=NEA=0200",
1090 "SET SCU1 CONFIG=ONL=014",
1091 "SET SCU1 CONFIG=INT=0",
1092 "SET SCU1 CONFIG=LWR=0",
1093 "SET SCU1 CONFIG=CLOCK_DELTA=0",
1094
1095
1096
1097 "SET SCU2 CONFIG=MODE=program",
1098 "SET SCU2 CONFIG=PORT0=enable",
1099 "SET SCU2 CONFIG=PORT1=enable",
1100 "SET SCU2 CONFIG=PORT2=enable",
1101 "SET SCU2 CONFIG=PORT3=enable",
1102 "SET SCU2 CONFIG=PORT4=enable",
1103 "SET SCU2 CONFIG=PORT5=enable",
1104 "SET SCU2 CONFIG=PORT6=enable",
1105 "SET SCU2 CONFIG=PORT7=enable",
1106 "SET SCU2 CONFIG=MASKA=off",
1107 "SET SCU2 CONFIG=MASKB=off",
1108 "SET SCU2 CONFIG=LWRSTORESIZE=7",
1109 "SET SCU2 CONFIG=CYCLIC=0040",
1110 "SET SCU2 CONFIG=NEA=0200",
1111 "SET SCU2 CONFIG=ONL=014",
1112 "SET SCU2 CONFIG=INT=0",
1113 "SET SCU2 CONFIG=LWR=0",
1114 "SET SCU2 CONFIG=CLOCK_DELTA=0",
1115
1116
1117
1118 "SET SCU3 CONFIG=MODE=program",
1119 "SET SCU3 CONFIG=PORT0=enable",
1120 "SET SCU3 CONFIG=PORT1=enable",
1121 "SET SCU3 CONFIG=PORT2=enable",
1122 "SET SCU3 CONFIG=PORT3=enable",
1123 "SET SCU3 CONFIG=PORT4=enable",
1124 "SET SCU3 CONFIG=PORT5=enable",
1125 "SET SCU3 CONFIG=PORT6=enable",
1126 "SET SCU3 CONFIG=PORT7=enable",
1127 "SET SCU3 CONFIG=MASKA=off",
1128 "SET SCU3 CONFIG=MASKB=off",
1129 "SET SCU3 CONFIG=LWRSTORESIZE=7",
1130 "SET SCU3 CONFIG=CYCLIC=0040",
1131 "SET SCU3 CONFIG=NEA=0200",
1132 "SET SCU3 CONFIG=ONL=014",
1133 "SET SCU3 CONFIG=INT=0",
1134 "SET SCU3 CONFIG=LWR=0",
1135 "SET SCU3 CONFIG=CLOCK_DELTA=0",
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237 "SET FNP0 CONFIG=MAILBOX=03400",
1238 "SET FNP0 IPC_NAME=fnp-a",
1239 "SET FNP1 CONFIG=MAILBOX=03700",
1240 "SET FNP1 IPC_NAME=fnp-b",
1241 "SET FNP2 CONFIG=MAILBOX=04200",
1242 "SET FNP2 IPC_NAME=fnp-c",
1243 "SET FNP3 CONFIG=MAILBOX=04500",
1244 "SET FNP3 IPC_NAME=fnp-d",
1245 "SET FNP4 CONFIG=MAILBOX=05000",
1246 "SET FNP4 IPC_NAME=fnp-e",
1247 "SET FNP5 CONFIG=MAILBOX=05300",
1248 "SET FNP5 IPC_NAME=fnp-f",
1249 "SET FNP6 CONFIG=MAILBOX=05600",
1250 "SET FNP6 IPC_NAME=fnp-g",
1251 "SET FNP7 CONFIG=MAILBOX=06100",
1252 "SET FNP7 IPC_NAME=fnp-h",
1253
1254
1255
1256 "SET MTP0 BOOT_DRIVE=0",
1257 "SET MTP0 NAME=MTP0",
1258
1259 "CABLE IOM0 012 MTP0 0",
1260 "CABLE IOM1 012 MTP0 1",
1261 "CABLE MTP0 1 TAPE1",
1262 "SET TAPE1 NAME=tapa_01",
1263 "CABLE MTP0 2 TAPE2",
1264 "SET TAPE2 NAME=tapa_02",
1265 "CABLE MTP0 3 TAPE3",
1266 "SET TAPE3 NAME=tapa_03",
1267 "CABLE MTP0 4 TAPE4",
1268 "SET TAPE4 NAME=tapa_04",
1269 "CABLE MTP0 5 TAPE5",
1270 "SET TAPE5 NAME=tapa_05",
1271 "CABLE MTP0 6 TAPE6",
1272 "SET TAPE6 NAME=tapa_06",
1273 "CABLE MTP0 7 TAPE7",
1274 "SET TAPE7 NAME=tapa_07",
1275 "CABLE MTP0 8 TAPE8",
1276 "SET TAPE8 NAME=tapa_08",
1277 "CABLE MTP0 9 TAPE9",
1278 "SET TAPE9 NAME=tapa_09",
1279 "CABLE MTP0 10 TAPE10",
1280 "SET TAPE10 NAME=tapa_10",
1281 "CABLE MTP0 11 TAPE11",
1282 "SET TAPE11 NAME=tapa_11",
1283 "CABLE MTP0 12 TAPE12",
1284 "SET TAPE12 NAME=tapa_12",
1285 "CABLE MTP0 13 TAPE13",
1286 "SET TAPE13 NAME=tapa_13",
1287 "CABLE MTP0 14 TAPE14",
1288 "SET TAPE14 NAME=tapa_14",
1289 "CABLE MTP0 15 TAPE15",
1290 "SET TAPE15 NAME=tapa_15",
1291 "CABLE MTP0 16 TAPE16",
1292 "SET TAPE16 NAME=tapa_16",
1293
1294
1295
1296 "SET IPC0 NAME=IPC0",
1297 "CABLE IOM0 013 IPC0 0",
1298 "CABLE IOM1 013 IPC0 1",
1299
1300 "CABLE IPC0 0 DISK0",
1301 "SET DISK0 TYPE=3381",
1302 "SET DISK0 NAME=dska_00",
1303
1304 "cable IPC0 1 DISK1",
1305 "set disk1 type=3381",
1306 "set disk1 name=dska_01",
1307
1308 "CABLE IPC0 2 DISK2",
1309 "SET DISK2 TYPE=3381",
1310 "SET DISK2 NAME=dska_02",
1311
1312 "CABLE IPC0 3 DISK3",
1313 "SET DISK3 TYPE=3381",
1314 "SET DISK3 NAME=dska_03",
1315
1316
1317 "SET MSP0 NAME=MSP0",
1318 "CABLE IOM0 014 MSP0 0",
1319 "CABLE IOM1 014 MSP0 1",
1320
1321
1322 "CABLE MSP0 1 DISK4",
1323 "SET disk4 TYPE=d501",
1324 "SET disk4 NAME=dskb_01",
1325
1326 "CABLE MSP0 2 DISK5",
1327 "SET DISK5 TYPE=d501",
1328 "SET DISK5 NAME=dskb_02",
1329
1330 "CABLE MSP0 3 DISK6",
1331 "SET DISK6 TYPE=d501",
1332 "SET DISK6 NAME=dskb_03",
1333
1334 "CABLE MSP0 4 DISK7",
1335 "SET DISK7 TYPE=d501",
1336 "SET DISK7 NAME=dskb_04",
1337
1338
1339 "CABLE MSP0 5 DISK8",
1340 "SET DISK8 TYPE=d451",
1341 "SET DISK8 NAME=dskb_05",
1342
1343 "CABLE MSP0 6 DISK9",
1344 "SET DISK9 TYPE=d451",
1345 "SET DISK9 NAME=dskb_06",
1346
1347 "CABLE MSP0 7 DISK10",
1348 "SET DISK10 TYPE=d451",
1349 "SET DISK10 NAME=dskb_07",
1350
1351 "CABLE MSP0 8 DISK11",
1352 "SET DISK11 TYPE=d451",
1353 "SET DISK11 NAME=dskb_08",
1354
1355 "CABLE MSP0 9 DISK12",
1356 "SET DISK12 TYPE=d500",
1357 "SET DISK12 NAME=dskb_09",
1358
1359 "CABLE MSP0 10 DISK13",
1360 "SET DISK13 TYPE=d500",
1361 "SET DISK13 NAME=dskb_10",
1362
1363
1364
1365 "CABLE IPC0 4 DISK14",
1366 "SET DISK14 TYPE=3381",
1367 "SET DISK14 NAME=dska_04",
1368
1369 "CABLE IPC0 5 DISK15",
1370 "SET DISK15 TYPE=3381",
1371 "SET DISK15 NAME=dska_05",
1372
1373 "CABLE IPC0 6 DISK16",
1374 "SET DISK16 TYPE=3381",
1375 "SET DISK16 NAME=dska_06",
1376
1377 "CABLE IPC0 7 DISK17",
1378 "SET DISK17 TYPE=3381",
1379 "SET DISK17 NAME=dska_07",
1380
1381 "CABLE IPC0 8 DISK18",
1382 "SET DISK18 TYPE=3381",
1383 "SET DISK18 NAME=dska_08",
1384
1385 "CABLE IPC0 9 DISK19",
1386 "SET DISK19 TYPE=3381",
1387 "SET DISK19 NAME=dska_09",
1388
1389 "CABLE IPC0 10 DISK20",
1390 "SET DISK20 TYPE=3381",
1391 "SET DISK20 NAME=dska_10",
1392
1393 "CABLE IPC0 11 DISK21",
1394 "SET DISK21 TYPE=3381",
1395 "SET DISK21 NAME=dska_11",
1396
1397 "CABLE IPC0 12 DISK22",
1398 "SET DISK22 TYPE=3381",
1399 "SET DISK22 NAME=dska_12",
1400
1401 "CABLE IPC0 13 DISK23",
1402 "SET DISK23 TYPE=3381",
1403 "SET DISK23 NAME=dska_13",
1404
1405 "CABLE IPC0 14 DISK24",
1406 "SET DISK24 TYPE=3381",
1407 "SET DISK24 NAME=dska_14",
1408
1409 "CABLE IPC0 15 DISK25",
1410 "SET DISK25 TYPE=3381",
1411 "SET DISK25 NAME=dska_15",
1412
1413
1414 "CABLE IOMA 036 OPC0",
1415
1416 "CABLE IOMA 053 OPC1",
1417 "SET OPC1 CONFIG=MODEL=m6601",
1418
1419
1420
1421
1422
1423
1424
1425 "CABLE IOMA 020 FNPD",
1426
1427 "CABLE IOMA 021 FNPA",
1428
1429 "CABLE IOMA 022 FNPB",
1430
1431 "CABLE IOMA 023 FNPC",
1432
1433 "CABLE IOMA 024 FNPE",
1434
1435 "CABLE IOMA 025 FNPF",
1436
1437 "CABLE IOMA 026 FNPG",
1438
1439 "CABLE IOMA 027 FNPH",
1440
1441
1442
1443
1444
1445
1446 "CABLE IOM0 015 URP0",
1447 "SET URP0 NAME=urpa",
1448
1449
1450 "CABLE URP0 1 RDR0",
1451 "SET RDR0 NAME=rdra",
1452
1453
1454 "CABLE IOM0 016 URP1",
1455 "SET URP1 NAME=urpb",
1456
1457
1458 "CABLE URP1 1 PUN0",
1459 "SET PUN0 NAME=puna",
1460
1461
1462 "CABLE IOM0 017 URP2",
1463 "SET URP2 NAME=urpc",
1464
1465
1466 "CABLE URP2 1 PRT0",
1467 "SET PRT0 NAME=prta",
1468
1469
1470
1471 "CABLE IOMA 050 URP3",
1472 "SET URP3 NAME=urpd",
1473
1474
1475 "CABLE URP3 1 PRT1",
1476 "SET PRT1 NAME=prtb",
1477
1478
1479
1480 "CABLE IOMA 051 URP4",
1481 "SET URP4 NAME=urpe",
1482
1483
1484 "CABLE URP4 1 PRT2",
1485 "SET PRT2 NAME=prtc",
1486
1487
1488
1489 "CABLE IOMA 052 URP5",
1490 "SET URP5 NAME=urpf",
1491
1492
1493 "CABLE URP5 1 PRT3",
1494 "SET PRT3 NAME=prtd",
1495
1496
1497
1498 "CABLE IOMA 055 URP6",
1499 "SET URP6 NAME=urpg",
1500
1501
1502 "CABLE URP6 1 RDRB",
1503 "SET RDR1 NAME=rdrb",
1504
1505
1506 "CABLE IOMA 056 URP7",
1507 "SET URP7 NAME=urph",
1508
1509
1510 "CABLE URP7 1 RDRC",
1511 "SET RDR2 NAME=rdrc",
1512
1513
1514 "CABLE IOMA 057 URP8",
1515 "SET URP8 NAME=urpi",
1516
1517
1518 "CABLE URP8 1 PUNB",
1519 "SET PUN1 NAME=punb",
1520
1521
1522 "CABLE IOMA 060 URP9",
1523 "SET URP9 NAME=urpj",
1524
1525
1526 "CABLE URP9 1 PUNC",
1527 "SET PUN2 NAME=punc",
1528
1529 # if defined(WITH_SOCKET_DEV)
1530 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW32) && !defined(CROSS_MINGW64)
1531 "CABLE IOMA 040 SKCA",
1532 "CABLE IOMA 041 SKCB",
1533 "CABLE IOMA 042 SKCC",
1534 "CABLE IOMA 043 SKCD",
1535 "CABLE IOMA 044 SKCE",
1536 "CABLE IOMA 045 SKCF",
1537 "CABLE IOMA 046 SKCG",
1538 "CABLE IOMA 047 SKCH",
1539 # endif
1540 # endif
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606 # if defined(WITH_ABSI_DEV)
1607 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW64) && !defined(CROSS_MINGW32)
1608
1609 "CABLE IOM0 032 ABSI0",
1610 # endif
1611 # endif
1612
1613 # if defined(WITH_MGP_DEV)
1614 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW64) && !defined(CROSS_MINGW32)
1615
1616 "CABLE IOM0 033 MGP0",
1617
1618 "CABLE IOM0 034 MGP1",
1619 # endif
1620 # endif
1621
1622
1623 "CABLE SCU0 0 IOM0 0",
1624
1625
1626 "CABLE SCU1 0 IOM0 1",
1627
1628
1629 "CABLE SCU2 0 IOM0 2",
1630
1631
1632 "CABLE SCU3 0 IOM0 3",
1633
1634
1635 "CABLE SCU0 1 IOM1 0",
1636
1637
1638 "CABLE SCU1 1 IOM1 1",
1639
1640
1641 "CABLE SCU2 1 IOM1 2",
1642
1643
1644 "CABLE SCU3 1 IOM1 3",
1645
1646
1647
1648
1649 "CABLE SCU0 7 CPU0 0",
1650
1651
1652 "CABLE SCU0 6 CPU1 0",
1653
1654
1655 "CABLE SCU0 5 CPU2 0",
1656
1657
1658 "CABLE SCU0 4 CPU3 0",
1659
1660
1661 "CABLE SCU0 3 CPU4 0",
1662
1663
1664 "CABLE SCU0 2 CPU5 0",
1665
1666
1667
1668
1669 "CABLE SCU1 7 CPU0 1",
1670
1671
1672 "CABLE SCU1 6 CPU1 1",
1673
1674
1675 "CABLE SCU1 5 CPU2 1",
1676
1677
1678 "CABLE SCU1 4 CPU3 1",
1679
1680
1681 "CABLE SCU1 3 CPU4 1",
1682
1683
1684 "CABLE SCU1 2 CPU5 1",
1685
1686
1687
1688
1689 "CABLE SCU2 7 CPU0 2",
1690
1691
1692 "CABLE SCU2 6 CPU1 2",
1693
1694
1695 "CABLE SCU2 5 CPU2 2",
1696
1697
1698 "CABLE SCU2 4 CPU3 2",
1699
1700
1701 "CABLE SCU2 3 CPU4 2",
1702
1703
1704 "CABLE SCU2 2 CPU5 2",
1705
1706
1707
1708
1709 "CABLE SCU3 7 CPU0 3",
1710
1711
1712 "CABLE SCU3 6 CPU1 3",
1713
1714
1715 "CABLE SCU3 5 CPU2 3",
1716
1717
1718 "CABLE SCU3 4 CPU3 3",
1719
1720
1721 "CABLE SCU3 3 CPU4 3",
1722
1723
1724 "CABLE SCU3 2 CPU5 3",
1725
1726 "SET CPU0 RESET",
1727 "SET SCU0 RESET",
1728 "SET SCU1 RESET",
1729 "SET SCU2 RESET",
1730 "SET SCU3 RESET",
1731 "SET IOM0 RESET",
1732
1733 # if defined(THREADZ) || defined(LOCKLESS)
1734 "SET CPU NUNITS=6",
1735 # else
1736 # if defined(ROUND_ROBIN)
1737 "SET CPU NUNITS=6",
1738 # else
1739 "SET CPU NUNITS=1",
1740 # endif
1741 # endif
1742
1743
1744 "SET SYS CONFIG=CONNECT_TIME=-1",
1745 };
1746
1747 void print_default_base_system_script (void)
1748 {
1749 int n_lines = sizeof (default_base_system_script) / sizeof (char *);
1750 sim_printf ("; DEFAULT_BASE_SYSTEM_SCRIPT (%lu lines follow)\r\n",
1751 (unsigned long)n_lines);
1752 for (int line = 0; line < n_lines; line ++)
1753 sim_printf ("%s\r\n", default_base_system_script[line]);
1754 }
1755
1756
1757
1758 static void do_ini_line (char * text)
1759 {
1760
1761 char gbuf[257];
1762 const char * cptr = get_glyph (text, gbuf, 0);
1763 CTAB *cmdp;
1764 if ((cmdp = find_cmd (gbuf)))
1765 {
1766 t_stat stat = cmdp->action (cmdp->arg, cptr);
1767 if (stat != SCPE_OK)
1768 sim_warn ("%s: %s\r\n", sim_error_text (SCPE_UNK), text);
1769 }
1770 else
1771 sim_warn ("%s: %s\r\n", sim_error_text (SCPE_UNK), text);
1772 }
1773
1774
1775
1776
1777 static t_stat set_default_base_system (UNUSED int32 arg, UNUSED const char * buf)
1778 {
1779 # if defined(PERF_STRIP)
1780 cpu_dev.numunits = 1;
1781 # else
1782 int n_lines = sizeof (default_base_system_script) / sizeof (char *);
1783 for (int line = 0; line < n_lines; line ++)
1784 do_ini_line (default_base_system_script [line]);
1785 # endif
1786 return SCPE_OK;
1787 }
1788
1789
1790
1791
1792
1793
1794
1795 static t_stat boot_skip (int32 UNUSED arg, UNUSED const char * buf)
1796 {
1797 uint32 skipped;
1798 t_stat rc = sim_tape_sprecsf (& mt_unit[0], 1, & skipped);
1799 if (rc == SCPE_OK)
1800 tape_states[0].rec_num ++;
1801 return rc;
1802 }
1803
1804
1805
1806
1807
1808 static t_stat do_execute_fault (UNUSED int32 arg, UNUSED const char * buf)
1809 {
1810
1811 setG7fault (0, FAULT_EXF);
1812 return SCPE_OK;
1813 }
1814
1815
1816
1817
1818
1819
1820 static t_stat do_restart (UNUSED int32 arg, UNUSED const char * buf)
1821 {
1822 if (sim_is_running)
1823 {
1824 sim_printf ("Don't restart a running system....\r\n");
1825 return SCPE_ARG;
1826 }
1827 int n = 010000;
1828 if (buf)
1829 {
1830 n = (int) strtol (buf, NULL, 0);
1831 }
1832 sim_printf ("Restart entry 0%o\r\n", n);
1833
1834 cpu_state_t * cpup = _cpup;
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848 cpu_reset_unit_idx (0, false);
1849 cpu.restart = true;
1850 cpu.restart_address = (uint) n;
1851
1852 t_stat rc = run_cmd (RU_CONT, "");
1853 return rc;
1854 }
1855
1856 static t_stat set_sys_polling_interval (UNUSED int32 arg, const char * buf)
1857 {
1858 if (! buf)
1859 return SCPE_ARG;
1860 int n = atoi (buf);
1861 if (n < 1 || n > 1000)
1862 {
1863 sim_printf ("POLL %d: must be 1 (1 millisecond) to 1000 (1 second)\r\n", n);
1864 return SCPE_ARG;
1865 }
1866 sim_printf ("Polling set to %d milliseconds\r\n", n);
1867 sys_opts.sys_poll_interval = (uint) n;
1868 return SCPE_OK;
1869 }
1870
1871 static t_stat set_sys_slow_polling_interval (UNUSED int32 arg, const char * buf)
1872 {
1873 if (! buf)
1874 return SCPE_ARG;
1875 int n = atoi (buf);
1876 if (n < 1 || n > 1000)
1877 {
1878 sim_printf ("SLOWPOLL %d: must be 1 (1 slow poll per pol) to 1000 (1 slow poll per 1000 polls)\r\n", n);
1879 return SCPE_ARG;
1880 }
1881 sim_printf ("Slow polling set to %d polls\r\n", n);
1882 sys_opts.sys_slow_poll_interval = (uint) n;
1883 return SCPE_OK;
1884 }
1885
1886 static t_stat set_sys_poll_check_rate (UNUSED int32 arg, const char * buf)
1887 {
1888 if (! buf)
1889 return SCPE_ARG;
1890 int n = atoi (buf);
1891 if (n < 1 || n > 1024*1024)
1892 {
1893 sim_printf ("CHECKPOLL %d: must be 1 (check every cycle) to 1048576 (check every million cycles\r\n", n);
1894 return SCPE_ARG;
1895 }
1896 sim_printf ("Poll check rate set to %d CPU cycles\r\n", n);
1897 sys_opts.sys_poll_check_rate = (uint) n;
1898 return SCPE_OK;
1899 }
1900 #endif
1901
1902
1903
1904
1905
1906 #if defined(TESTING)
1907
1908
1909
1910
1911 uint64 sim_deb_start = 0;
1912
1913 uint64 sim_deb_stop = 0;
1914
1915 uint64 sim_deb_break = 0;
1916
1917 bool sim_deb_segno_on = false;
1918 # if defined(NO_C_ELLIPSIS)
1919 bool sim_deb_segno[DEBUG_SEGNO_LIMIT];
1920 # else
1921 bool sim_deb_segno[DEBUG_SEGNO_LIMIT] = { [0 ... DEBUG_SEGNO_LIMIT - 1] = false };
1922 # endif
1923
1924 uint64 sim_deb_ringno = NO_SUCH_RINGNO;
1925
1926
1927 uint64 sim_deb_skip_limit = 0;
1928
1929
1930 uint64 sim_deb_skip_cnt = 0;
1931
1932
1933 uint64 sim_deb_mme_cntdwn = 0;
1934
1935 uint dbgCPUMask = 0377;
1936
1937
1938 bool sim_deb_bar = false;
1939
1940
1941
1942 static t_stat dps_debug_mme_cntdwn (UNUSED int32 arg, const char * buf)
1943 {
1944 sim_deb_mme_cntdwn = strtoull (buf, NULL, 0);
1945 sim_msg ("Debug MME countdown set to %llu\r\n", (long long unsigned int)sim_deb_mme_cntdwn);
1946 return SCPE_OK;
1947 }
1948
1949 static t_stat dps_debug_skip (UNUSED int32 arg, const char * buf)
1950 {
1951 sim_deb_skip_cnt = 0;
1952 sim_deb_skip_limit = strtoull (buf, NULL, 0);
1953 sim_msg ("Debug skip set to %llu\r\n", (long long unsigned int)sim_deb_skip_limit);
1954 return SCPE_OK;
1955 }
1956
1957 static t_stat dps_debug_start (UNUSED int32 arg, const char * buf)
1958 {
1959 sim_deb_start = strtoull (buf, NULL, 0);
1960 sim_msg ("Debug set to start at cycle: %llu\r\n", (long long unsigned int)sim_deb_start);
1961 return SCPE_OK;
1962 }
1963
1964 static t_stat dps_debug_stop (UNUSED int32 arg, const char * buf)
1965 {
1966 sim_deb_stop = strtoull (buf, NULL, 0);
1967 sim_msg ("Debug set to stop at cycle: %llu\r\n", (long long unsigned int)sim_deb_stop);
1968 return SCPE_OK;
1969 }
1970
1971 static t_stat dps_debug_break (UNUSED int32 arg, const char * buf)
1972 {
1973 sim_deb_break = strtoull (buf, NULL, 0);
1974 if (buf[0] == '+')
1975 sim_deb_break += sim_deb_start;
1976 sim_msg ("Debug set to break at cycle: %llu\r\n", (long long unsigned int)sim_deb_break);
1977 return SCPE_OK;
1978 }
1979
1980 static t_stat dps_debug_segno (int32 arg, const char * buf)
1981 {
1982 if (arg)
1983 {
1984 unsigned long segno = strtoul (buf, NULL, 0);
1985 if (segno >= DEBUG_SEGNO_LIMIT)
1986 {
1987 sim_printf ("out of range; 0 to %u %d.\r\n", DEBUG_SEGNO_LIMIT, DEBUG_SEGNO_LIMIT);
1988 return SCPE_ARG;
1989 }
1990 sim_deb_segno[segno] = true;
1991 sim_deb_segno_on = true;
1992 sim_msg ("Debug set for segno %llo %llu.\r\n",
1993 (long long unsigned int)segno, (long long unsigned int) segno);
1994 }
1995 else
1996 {
1997 (void)memset (sim_deb_segno, 0, sizeof (sim_deb_segno));
1998 sim_deb_segno_on = false;
1999 sim_msg ("Debug set for all segments\r\n");
2000 }
2001 return SCPE_OK;
2002 }
2003
2004 static t_stat dps_debug_ringno (UNUSED int32 arg, const char * buf)
2005 {
2006 sim_deb_ringno = strtoull (buf, NULL, 0);
2007 sim_msg ("Debug set to ringno %llo\r\n", (long long unsigned int)sim_deb_ringno);
2008 return SCPE_OK;
2009 }
2010
2011 static t_stat dps_debug_bar (int32 arg, UNUSED const char * buf)
2012 {
2013 sim_deb_bar = arg;
2014 if (arg)
2015 sim_msg ("Debug set BAR %llo\r\n", (long long unsigned int)sim_deb_ringno);
2016 else
2017 sim_msg ("Debug unset BAR %llo\r\n", (long long unsigned int)sim_deb_ringno);
2018 return SCPE_OK;
2019 }
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233 static t_stat abs_addr_n (int segno, uint offset)
2234 {
2235 word24 res;
2236
2237
2238 if (dbgLookupAddress ((word18) segno, offset, & res, NULL))
2239 return SCPE_ARG;
2240
2241 sim_msg ("Address is %08o\r\n", res);
2242 return SCPE_OK;
2243 }
2244
2245
2246
2247
2248 static t_stat abs_addr (UNUSED int32 arg, const char * buf)
2249 {
2250 uint segno;
2251 uint offset;
2252 if (sscanf (buf, "%o:%o", & segno, & offset) != 2)
2253 return SCPE_ARG;
2254 return abs_addr_n ((int) segno, offset);
2255 }
2256
2257
2258
2259
2260
2261
2262 # define BOOT_SEGMENTS_MAX 1024
2263 # define BOOT_COMPONENTS_MAX 4096
2264 # define BOOK_SEGMENT_NAME_LEN 33
2265
2266 static struct book_segment
2267 {
2268 char * segname;
2269 int segno;
2270 } book_segments[BOOT_SEGMENTS_MAX];
2271
2272 static int n_book_segments = 0;
2273
2274 static struct book_component
2275 {
2276 char * compname;
2277 int book_segment_number;
2278 uint txt_start, txt_length;
2279 int intstat_start, intstat_length, symbol_start, symbol_length;
2280 } book_components[BOOT_COMPONENTS_MAX];
2281
2282 static int n_book_components = 0;
2283
2284 static int lookup_book_segment (char * name)
2285 {
2286 for (int i = 0; i < n_book_segments; i ++)
2287 if (strcmp (name, book_segments[i].segname) == 0)
2288 return i;
2289 return -1;
2290 }
2291
2292 static int add_book_segment (char * name, int segno)
2293 {
2294 int n = lookup_book_segment (name);
2295 if (n >= 0)
2296 return n;
2297 if (n_book_segments >= BOOT_SEGMENTS_MAX)
2298 return -1;
2299 book_segments[n_book_segments].segname = strdup (name);
2300 if (!book_segments[n_book_segments].segname)
2301 {
2302 (void)fprintf (stderr, "\rFATAL: Out of memory! Aborting at %s[%s:%d]\r\n",
2303 __func__, __FILE__, __LINE__);
2304 # if defined(USE_BACKTRACE)
2305 # if defined(SIGUSR2)
2306 (void)raise(SIGUSR2);
2307
2308 # endif
2309 # endif
2310 abort();
2311 }
2312 book_segments[n_book_segments].segno = segno;
2313 n = n_book_segments;
2314 n_book_segments ++;
2315 return n;
2316 }
2317
2318 static int add_book_component (int segnum, char * name, uint txt_start,
2319 uint txt_length, int intstat_start,
2320 int intstat_length, int symbol_start,
2321 int symbol_length)
2322 {
2323 if (n_book_components >= BOOT_COMPONENTS_MAX)
2324 return -1;
2325 book_components[n_book_components].compname = strdup (name);
2326 if (!book_components[n_book_components].compname)
2327 {
2328 (void)fprintf (stderr, "\rFATAL: Out of memory! Aborting at %s[%s:%d]\r\n",
2329 __func__, __FILE__, __LINE__);
2330 # if defined(USE_BACKTRACE)
2331 # if defined(SIGUSR2)
2332 (void)raise(SIGUSR2);
2333
2334 # endif
2335 # endif
2336 abort();
2337 }
2338 book_components[n_book_components].book_segment_number = segnum;
2339 book_components[n_book_components].txt_start = txt_start;
2340 book_components[n_book_components].txt_length = txt_length;
2341 book_components[n_book_components].intstat_start = intstat_start;
2342 book_components[n_book_components].intstat_length = intstat_length;
2343 book_components[n_book_components].symbol_start = symbol_start;
2344 book_components[n_book_components].symbol_length = symbol_length;
2345 int n = n_book_components;
2346 n_book_components ++;
2347 return n;
2348 }
2349
2350
2351
2352
2353
2354 static char * lookup_system_book_address (word18 segno, word18 offset,
2355 char * * compname, word18 * compoffset)
2356 {
2357 static char buf[129];
2358 int i;
2359
2360 for (i = 0; i < n_book_segments; i ++)
2361 if (book_segments[i].segno == (int) segno)
2362 break;
2363
2364 if (i >= n_book_segments)
2365 return NULL;
2366
2367 int best = -1;
2368 uint bestoffset = 0;
2369
2370 for (int j = 0; j < n_book_components; j ++)
2371 {
2372 if (book_components[j].book_segment_number != i)
2373 continue;
2374 if (book_components[j].txt_start <= offset &&
2375 book_components[j].txt_start + book_components[j].txt_length > offset)
2376 {
2377 (void)sprintf (buf, "%s:%s+0%0o", book_segments[i].segname,
2378 book_components[j].compname,
2379 offset - book_components[j].txt_start);
2380 if (compname)
2381 * compname = book_components[j].compname;
2382 if (compoffset)
2383 * compoffset = offset - book_components[j].txt_start;
2384 return buf;
2385 }
2386 if (book_components[j].txt_start <= offset &&
2387 book_components[j].txt_start > bestoffset)
2388 {
2389 best = j;
2390 bestoffset = book_components[j].txt_start;
2391 }
2392 }
2393
2394 if (best != -1)
2395 {
2396
2397
2398 if (compname)
2399 * compname = book_components[best].compname;
2400 if (compoffset)
2401 * compoffset = offset - book_components[best].txt_start;
2402 (void)sprintf (buf, "%s:%s+0%0o", book_segments[i].segname,
2403 book_components[best].compname,
2404 offset - book_components[best].txt_start);
2405 return buf;
2406 }
2407
2408
2409
2410
2411 if (compname)
2412 * compname = book_segments[i].segname;
2413 if (compoffset)
2414 * compoffset = offset;
2415 (void)sprintf (buf, "%s:+0%0o", book_segments[i].segname,
2416 offset);
2417 return buf;
2418 }
2419
2420
2421
2422
2423 char * lookup_address (word18 segno, word18 offset, char * * compname,
2424 word18 * compoffset)
2425 {
2426 if (compname)
2427 * compname = NULL;
2428 if (compoffset)
2429 * compoffset = 0;
2430
2431
2432
2433
2434
2435
2436
2437
2438 if (segno == 0322)
2439 segno = 0162;
2440 if (segno == 0310)
2441 segno = 041;
2442 if (segno == 0314)
2443 segno = 041;
2444 if (segno == 0313)
2445 segno = 040;
2446 if (segno == 0317)
2447 segno = 0161;
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480 char * ret = lookup_system_book_address (segno, offset, compname, compoffset);
2481 return ret;
2482 }
2483
2484
2485
2486
2487
2488 static int lookup_system_book_name (char * segname, char * compname, long * segno,
2489 long * offset)
2490 {
2491 int i;
2492 for (i = 0; i < n_book_segments; i ++)
2493 if (strcmp (book_segments[i].segname, segname) == 0)
2494 break;
2495 if (i >= n_book_segments)
2496 return -1;
2497
2498 for (int j = 0; j < n_book_components; j ++)
2499 {
2500 if (book_components[j].book_segment_number != i)
2501 continue;
2502 if (strcmp (book_components[j].compname, compname) == 0)
2503 {
2504 * segno = book_segments[i].segno;
2505 * offset = (long) book_components[j].txt_start;
2506 return 0;
2507 }
2508 }
2509
2510 return -1;
2511 }
2512
2513 static char * source_search_path = NULL;
2514
2515
2516
2517
2518
2519
2520 void list_source (char * compname, word18 offset, uint dflag)
2521 {
2522 cpu_state_t * cpup = _cpup;
2523 const int offset_str_len = 10;
2524
2525 char offset_str[17];
2526 (void)sprintf (offset_str, " %06o", offset);
2527
2528 char path[(source_search_path ? strlen (source_search_path) : 1) +
2529 1 +
2530 (compname ? strlen (compname) : 1) +
2531 1 + strlen (".list") + 1];
2532 char * searchp = source_search_path ? source_search_path : ".";
2533
2534 while (* searchp)
2535 {
2536 size_t pathlen = strcspn (searchp, ":");
2537 strncpy (path, searchp, pathlen);
2538 path[pathlen] = '\0';
2539 if (searchp[pathlen] == ':')
2540 searchp += pathlen + 1;
2541 else
2542 searchp += pathlen;
2543
2544 if (compname)
2545 {
2546 strcat (path, "/");
2547 strcat (path, compname);
2548 }
2549 strcat (path, ".list");
2550
2551 FILE * listing = fopen (path, "r");
2552 if (listing)
2553 {
2554 char line[1025];
2555 if (feof (listing))
2556 goto fileDone;
2557 fgets (line, 1024, listing);
2558 if (strncmp (line, "ASSEMBLY LISTING", 16) == 0)
2559 {
2560
2561
2562
2563
2564
2565 while (! feof (listing))
2566 {
2567 fgets (line, 1024, listing);
2568 if (strncmp (line, offset_str, (size_t) offset_str_len) == 0)
2569 {
2570 if (! dflag)
2571 sim_msg ("%s", line);
2572 else
2573 sim_debug (dflag, & cpu_dev, "%s", line);
2574
2575 }
2576 if (strcmp (line, "\fLITERALS\n") == 0)
2577 break;
2578 }
2579 }
2580 else if (strncmp (line, "\tCOMPILATION LISTING", 20) == 0)
2581 {
2582
2583
2584
2585
2586
2587 bool foundTable = false;
2588 while (! feof (listing))
2589 {
2590 fgets (line, 1024, listing);
2591 if (strncmp (line, " LINE LOC", 14) != 0)
2592 continue;
2593 foundTable = true;
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608 int best = -1;
2609 char bestLines[8] = {0, 0, 0, 0, 0, 0, 0};
2610 while (! feof (listing))
2611 {
2612 int loc[7];
2613 char linenos[7][8];
2614 (void)memset (linenos, 0, sizeof (linenos));
2615 fgets (line, 1024, listing);
2616
2617 while (strncmp (line,
2618 " ", 8 + 6 + 3) == 0)
2619 memmove (line, line + 8 + 6 + 3,
2620 strlen (line + 8 + 6 + 3));
2621
2622
2623 int cnt = sscanf (line,
2624
2625 "%8c%o%*3c"
2626 "%8c%o%*3c"
2627 "%8c%o%*3c"
2628 "%8c%o%*3c"
2629 "%8c%o%*3c"
2630 "%8c%o%*3c"
2631 "%8c%o",
2632 (char *) & linenos[0], (uint *) & loc[0],
2633 (char *) & linenos[1], (uint *) & loc[1],
2634 (char *) & linenos[2], (uint *) & loc[2],
2635 (char *) & linenos[3], (uint *) & loc[3],
2636 (char *) & linenos[4], (uint *) & loc[4],
2637 (char *) & linenos[5], (uint *) & loc[5],
2638 (char *) & linenos[6], (uint *) & loc[6]);
2639 if (! (cnt == 2 || cnt == 4 || cnt == 6 ||
2640 cnt == 8 || cnt == 10 || cnt == 12 ||
2641 cnt == 14))
2642 break;
2643 int n;
2644 for (n = 0; n < cnt / 2; n ++)
2645 {
2646 if (loc[n] > best && loc[n] <= (int) offset)
2647 {
2648 best = loc[n];
2649 memcpy (bestLines, linenos[n],
2650 sizeof (bestLines));
2651 }
2652 }
2653 if (best == (int) offset)
2654 break;
2655 }
2656 if (best == -1)
2657 goto fileDone;
2658
2659
2660
2661
2662
2663
2664 char searchPrefix[10];
2665 searchPrefix[0] = ' ';
2666 searchPrefix[1] = bestLines[0];
2667 searchPrefix[2] = bestLines[1];
2668 searchPrefix[3] = ' ';
2669 searchPrefix[4] = bestLines[2];
2670 searchPrefix[5] = bestLines[3];
2671 searchPrefix[6] = bestLines[4];
2672 searchPrefix[7] = bestLines[5];
2673 searchPrefix[8] = bestLines[6];
2674
2675
2676 searchPrefix[9] = '\0';
2677
2678
2679 rewind (listing);
2680 while (! feof (listing))
2681 {
2682 fgets (line, 1024, listing);
2683 if (strncmp (line, "\f\tSOURCE", 8) == 0)
2684 goto fileDone;
2685 char prefix[10];
2686 strncpy (prefix, line, 9);
2687 prefix[9] = '\0';
2688 if (strcmp (prefix, searchPrefix) != 0)
2689 continue;
2690
2691 if (!dflag)
2692 sim_msg ("%s", line);
2693 else
2694 sim_debug (dflag, & cpu_dev, "%s", line);
2695
2696 }
2697 goto fileDone;
2698 }
2699 if (! foundTable)
2700 {
2701
2702 rewind (listing);
2703 while (! feof (listing))
2704 {
2705 fgets (line, 1024, listing);
2706 if (strncmp (line,
2707 offset_str + 4,
2708 offset_str_len - 4) == 0)
2709 {
2710 if (! dflag)
2711 sim_msg ("%s", line);
2712 else
2713 sim_debug (dflag, & cpu_dev, "%s", line);
2714
2715 }
2716
2717
2718 }
2719 }
2720 }
2721
2722 fileDone:
2723 fclose (listing);
2724 }
2725 }
2726 }
2727
2728
2729
2730 static t_stat stack_trace (UNUSED int32 arg, UNUSED const char * buf)
2731 {
2732 cpu_state_t * cpup = _cpup;
2733 char * msg;
2734
2735 word15 icSegno = cpu.PPR.PSR;
2736 word18 icOffset = cpu.PPR.IC;
2737
2738 sim_msg ("Entry ptr %05o:%06o\r\n", icSegno, icOffset);
2739
2740 char * compname;
2741 word18 compoffset;
2742 char * where = lookup_address (icSegno, icOffset,
2743 & compname, & compoffset);
2744 if (where)
2745 {
2746 sim_msg ("%05o:%06o %s\r\n", icSegno, icOffset, where);
2747 list_source (compname, compoffset, 0);
2748 }
2749 sim_msg ("\r\n");
2750
2751
2752
2753
2754
2755
2756
2757
2758 word15 fpSegno = cpu.PR[6].SNR;
2759 word18 fpOffset = cpu.PR[6].WORDNO;
2760
2761 for (uint frameNo = 1; ; frameNo ++)
2762 {
2763 sim_msg ("Frame %d %05o:%06o\r\n",
2764 frameNo, fpSegno, fpOffset);
2765
2766 word24 fp;
2767 if (dbgLookupAddress (fpSegno, fpOffset, & fp, & msg))
2768 {
2769 sim_msg ("can't lookup fp (%05o:%06o) because %s\r\n",
2770 fpSegno, fpOffset, msg);
2771 break;
2772 }
2773
2774 word15 prevfpSegno = (word15) ((M[fp + 16] >> 18) & MASK15);
2775 word18 prevfpOffset = (word18) ((M[fp + 17] >> 18) & MASK18);
2776
2777 sim_msg ("Previous FP %05o:%06o\r\n", prevfpSegno, prevfpOffset);
2778
2779 word15 returnSegno = (word15) ((M[fp + 20] >> 18) & MASK15);
2780 word18 returnOffset = (word18) ((M[fp + 21] >> 18) & MASK18);
2781
2782 sim_msg ("Return ptr %05o:%06o\r\n", returnSegno, returnOffset);
2783
2784 if (returnOffset == 0)
2785 {
2786 if (frameNo == 1)
2787 {
2788
2789 sim_msg ("guessing X7 has a return address....\r\n");
2790 where = lookup_address (icSegno, cpu.rX[7] - 1,
2791 & compname, & compoffset);
2792 if (where)
2793 {
2794 sim_msg ("%05o:%06o %s\r\n", icSegno, cpu.rX[7] - 1, where);
2795 list_source (compname, compoffset, 0);
2796 }
2797 }
2798 }
2799 else
2800 {
2801 where = lookup_address (returnSegno, returnOffset - 1,
2802 & compname, & compoffset);
2803 if (where)
2804 {
2805 sim_msg ("%05o:%06o %s\r\n",
2806 returnSegno, returnOffset - 1, where);
2807 list_source (compname, compoffset, 0);
2808 }
2809 }
2810
2811 word15 entrySegno = (word15) ((M[fp + 22] >> 18) & MASK15);
2812 word18 entryOffset = (word18) ((M[fp + 23] >> 18) & MASK18);
2813
2814 sim_msg ("Entry ptr %05o:%06o\r\n", entrySegno, entryOffset);
2815
2816 where = lookup_address (entrySegno, entryOffset,
2817 & compname, & compoffset);
2818 if (where)
2819 {
2820 sim_msg ("%05o:%06o %s\r\n", entrySegno, entryOffset, where);
2821 list_source (compname, compoffset, 0);
2822 }
2823
2824 word15 argSegno = (word15) ((M[fp + 26] >> 18) & MASK15);
2825 word18 argOffset = (word18) ((M[fp + 27] >> 18) & MASK18);
2826 sim_msg ("Arg ptr %05o:%06o\r\n", argSegno, argOffset);
2827
2828 word24 ap;
2829 if (dbgLookupAddress (argSegno, argOffset, & ap, & msg))
2830 {
2831 sim_msg ("can't lookup arg ptr (%05o:%06o) because %s\r\n",
2832 argSegno, argOffset, msg);
2833 goto skipArgs;
2834 }
2835
2836 word16 argCount = (word16) ((M[ap + 0] >> 19) & MASK17);
2837 word18 callType = (word18) (M[ap + 0] & MASK18);
2838 word16 descCount = (word16) ((M[ap + 1] >> 19) & MASK17);
2839 sim_msg ("arg_count %d\r\n", argCount);
2840 switch (callType)
2841 {
2842 case 0u:
2843 sim_msg ("call_type Quick internal call\r\n");
2844 break;
2845 case 4u:
2846 sim_msg ("call_type Inter-segment\r\n");
2847 break;
2848 case 8u:
2849 sim_msg ("call_type Environment pointer\r\n");
2850 break;
2851 default:
2852 sim_msg ("call_type Unknown (%o)\r\n", callType);
2853 goto skipArgs;
2854 }
2855 sim_msg ("desc_count %d\r\n", descCount);
2856
2857
2858
2859
2860
2861
2862
2863
2864 {
2865 for (uint argno = 0; argno < argCount; argno ++)
2866 {
2867 uint argnoos = ap + 2 + argno * 2;
2868 word15 argnoSegno = (word15) ((M[argnoos] >> 18) & MASK15);
2869 word18 argnoOffset = (word18) ((M[argnoos + 1] >> 18) & MASK18);
2870 word24 argnop;
2871 if (dbgLookupAddress (argnoSegno, argnoOffset, & argnop, & msg))
2872 {
2873 sim_msg ("can't lookup arg%d ptr (%05o:%06o) because %s\r\n",
2874 argno, argSegno, argOffset, msg);
2875 continue;
2876 }
2877 word36 argv = M[argnop];
2878 sim_msg ("arg%d value %05o:%06o[%08o] "
2879 "%012llo (%llu)\r\n",
2880 argno, argSegno, argOffset, argnop,
2881 (unsigned long long int)argv, (unsigned long long int)argv);
2882 sim_msg ("\r\n");
2883 }
2884 }
2885 skipArgs:;
2886
2887 sim_msg ("End of frame %d\r\n\r\n", frameNo);
2888
2889 if (prevfpSegno == 077777 && prevfpOffset == 1)
2890 break;
2891 fpSegno = prevfpSegno;
2892 fpOffset = prevfpOffset;
2893 }
2894 return SCPE_OK;
2895 }
2896
2897 static t_stat list_source_at (UNUSED int32 arg, UNUSED const char * buf)
2898 {
2899
2900 uint segno;
2901 uint offset;
2902 if (sscanf (buf, "%o:%o", & segno, & offset) != 2)
2903 return SCPE_ARG;
2904 char * compname;
2905 word18 compoffset;
2906 char * where = lookup_address ((word18) segno, offset,
2907 & compname, & compoffset);
2908 if (where)
2909 {
2910 sim_msg ("%05o:%06o %s\r\n", segno, offset, where);
2911 list_source (compname, compoffset, 0);
2912 }
2913 return SCPE_OK;
2914 }
2915
2916 static t_stat load_system_book (UNUSED int32 arg, UNUSED const char * buf)
2917 {
2918
2919 # if !defined(SPEED)
2920
2921 uint c3 = 0244;
2922
2923 # define bufSz 257
2924 char filebuf[bufSz];
2925 int current = -1;
2926
2927 FILE * fp = fopen (buf, "r");
2928 if (! fp)
2929 {
2930 sim_msg ("error opening file %s\r\n", buf);
2931 return SCPE_ARG;
2932 }
2933 for (;;)
2934 {
2935 char * bufp = fgets (filebuf, bufSz, fp);
2936 if (! bufp)
2937 break;
2938
2939 char name[BOOK_SEGMENT_NAME_LEN];
2940 uint segno, p0, p1, p2;
2941
2942
2943 int cnt = sscanf (filebuf, "%32s %o (%o, %o, %o)", name, & segno,
2944 & p0, & p1, & p2);
2945 if (filebuf[0] != '\t' && cnt == 5)
2946 {
2947
2948 int rc = add_book_segment (name, (int) segno);
2949 if (rc < 0)
2950 {
2951 sim_warn ("error adding segment name\r\n");
2952 fclose (fp);
2953 return SCPE_ARG;
2954 }
2955 continue;
2956 }
2957 else
2958 {
2959
2960
2961 cnt = sscanf (filebuf, "%32s (%o, %o, %o)", name,
2962 & p0, & p1, & p2);
2963 if (filebuf[0] != '\t' && cnt == 4)
2964 {
2965 if (strstr (name, "fw.") || strstr (name, ".ec"))
2966 continue;
2967
2968 int rc = add_book_segment (name, (int) (c3 ++));
2969 if (rc < 0)
2970 {
2971 sim_warn ("error adding segment name\r\n");
2972 fclose (fp);
2973 return SCPE_ARG;
2974 }
2975 continue;
2976 }
2977 }
2978 cnt = sscanf (filebuf, "Bindmap for >ldd>h>e>%32s", name);
2979 if (cnt != 1)
2980 cnt = sscanf (filebuf, "Bindmap for >ldd>hard>e>%32s", name);
2981 if (cnt == 1)
2982 {
2983
2984
2985 int rc = lookup_book_segment (name);
2986 if (rc < 0)
2987 {
2988
2989
2990
2991 current = -1;
2992 continue;
2993
2994
2995 }
2996 current = rc;
2997 continue;
2998 }
2999
3000 uint txt_start, txt_length;
3001 int intstat_start, intstat_length, symbol_start, symbol_length;
3002 cnt = sscanf (filebuf, "%32s %o %o %o %o %o %o", name, & txt_start,
3003 & txt_length, & intstat_start, & intstat_length,
3004 & symbol_start, & symbol_length);
3005
3006 if (cnt == 7)
3007 {
3008
3009 if (current >= 0)
3010 {
3011 add_book_component (current, name, txt_start, txt_length,
3012 intstat_start, intstat_length, symbol_start,
3013 symbol_length);
3014 }
3015 continue;
3016 }
3017
3018 cnt = sscanf (filebuf, "%32s %o (%o, %o, %o)", name, & segno,
3019 & p0, & p1, & p2);
3020 if (filebuf[0] == '\t' && cnt == 5)
3021 {
3022
3023 int rc = add_book_segment (name, (int) segno);
3024 if (rc < 0)
3025 {
3026 sim_warn ("error adding segment name\r\n");
3027 fclose (fp);
3028 return SCPE_ARG;
3029 }
3030 continue;
3031 }
3032
3033 }
3034 fclose (fp);
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056 # endif
3057 return SCPE_OK;
3058 }
3059
3060 static t_stat add_system_book_entry (UNUSED int32 arg, const char * buf)
3061 {
3062
3063
3064 char segname[BOOK_SEGMENT_NAME_LEN];
3065 char compname[BOOK_SEGMENT_NAME_LEN];
3066 uint segno;
3067 uint txt_start, txt_len;
3068 uint intstat_start, intstat_length;
3069 uint symbol_start, symbol_length;
3070
3071
3072 if (sscanf (buf, "%32s %32s %o %o %o %o %o %o %o",
3073 segname, compname, & segno,
3074 & txt_start, & txt_len, & intstat_start, & intstat_length,
3075 & symbol_start, & symbol_length) != 9)
3076 return SCPE_ARG;
3077
3078 int idx = add_book_segment (segname, (int) segno);
3079 if (idx < 0)
3080 return SCPE_ARG;
3081
3082 if (add_book_component (idx, compname, txt_start, txt_len, (int) intstat_start,
3083 (int) intstat_length, (int) symbol_start,
3084 (int) symbol_length) < 0)
3085 return SCPE_ARG;
3086
3087 return SCPE_OK;
3088 }
3089
3090
3091
3092
3093
3094
3095
3096 static t_stat lookup_system_book (UNUSED int32 arg, const char * buf)
3097 {
3098 char w1[strlen (buf)];
3099 char w2[strlen (buf)];
3100 char w3[strlen (buf)];
3101 long segno, offset;
3102
3103 size_t colon = strcspn (buf, ":");
3104 if (buf[colon] != ':')
3105 return SCPE_ARG;
3106
3107 strncpy (w1, buf, colon);
3108 w1[colon] = '\0';
3109
3110
3111 size_t plus = strcspn (buf + colon + 1, "+");
3112 if (buf[colon + 1 + plus] == '+')
3113 {
3114 strncpy (w2, buf + colon + 1, plus);
3115 w2[plus] = '\0';
3116 (void)strcpy (w3, buf + colon + 1 + plus + 1);
3117 }
3118 else
3119 {
3120 (void)strcpy (w2, buf + colon + 1);
3121 (void)strcpy (w3, "");
3122 }
3123
3124
3125
3126
3127 char * end1;
3128 segno = strtol (w1, & end1, 8);
3129 char * end2;
3130 offset = strtol (w2, & end2, 8);
3131
3132 if (* end1 == '\0' && * end2 == '\0' && * w3 == '\0')
3133 {
3134
3135 char * ans = lookup_address ((word18) segno, (word18) offset, NULL, NULL);
3136 sim_warn ("%s\r\n", ans ? ans : "not found");
3137 }
3138 else
3139 {
3140 if (* w3)
3141 {
3142 char * end3;
3143 offset = strtol (w3, & end3, 8);
3144 if (* end3 != '\0')
3145 return SCPE_ARG;
3146 }
3147 else
3148 offset = 0;
3149 long comp_offset;
3150 int rc = lookup_system_book_name (w1, w2, & segno, & comp_offset);
3151 if (rc)
3152 {
3153 sim_warn ("not found\r\n");
3154 return SCPE_OK;
3155 }
3156 sim_msg ("0%o:0%o\r\n", (uint) segno, (uint) (comp_offset + offset));
3157 abs_addr_n ((int) segno, (uint) (comp_offset + offset));
3158 }
3159
3160
3161
3162
3163
3164
3165 return SCPE_OK;
3166 }
3167
3168
3169
3170 static sdw0_s *fetchSDW (word15 segno)
3171 {
3172 cpu_state_t * cpup = _cpup;
3173 word36 SDWeven, SDWodd;
3174
3175 core_read2 (cpup, (cpu.DSBR.ADDR + 2u * segno) & PAMASK, & SDWeven, & SDWodd,
3176 __func__);
3177
3178
3179
3180 sdw0_s *SDW = & cpu._s;
3181 (void)memset (SDW, 0, sizeof (cpu._s));
3182
3183 SDW->ADDR = (SDWeven >> 12) & 077777777;
3184 SDW->R1 = (SDWeven >> 9) & 7;
3185 SDW->R2 = (SDWeven >> 6) & 7;
3186 SDW->R3 = (SDWeven >> 3) & 7;
3187 SDW->DF = TSTBIT (SDWeven, 2);
3188 SDW->FC = SDWeven & 3;
3189
3190
3191 SDW->BOUND = (SDWodd >> 21) & 037777;
3192 SDW->R = TSTBIT (SDWodd, 20);
3193 SDW->E = TSTBIT (SDWodd, 19);
3194 SDW->W = TSTBIT (SDWodd, 18);
3195 SDW->P = TSTBIT (SDWodd, 17);
3196 SDW->U = TSTBIT (SDWodd, 16);
3197 SDW->G = TSTBIT (SDWodd, 15);
3198 SDW->C = TSTBIT (SDWodd, 14);
3199 SDW->EB = SDWodd & 037777;
3200
3201 return SDW;
3202 }
3203
3204 static t_stat virtAddrN (uint address)
3205 {
3206 cpu_state_t * cpup = _cpup;
3207 if (cpu.DSBR.U) {
3208 for(word15 segno = 0; 2u * segno < 16u * (cpu.DSBR.BND + 1u); segno += 1)
3209 {
3210 sdw0_s *s = fetchSDW(segno);
3211 if (address >= s -> ADDR && address < s -> ADDR + s -> BOUND * 16u)
3212 sim_msg (" %06o:%06o\r\n", segno, address - s -> ADDR);
3213 }
3214 } else {
3215 for(word15 segno = 0;
3216 2u * segno < 16u * (cpu.DSBR.BND + 1u);
3217 segno += 512u)
3218 {
3219 word24 y1 = (2u * segno) % 1024u;
3220 word24 x1 = (2u * segno - y1) / 1024u;
3221 word36 PTWx1;
3222 core_read (cpup, (cpu.DSBR.ADDR + x1) & PAMASK, & PTWx1, __func__);
3223
3224 ptw_s PTW1;
3225 PTW1.ADDR = GETHI(PTWx1);
3226 PTW1.U = TSTBIT(PTWx1, 9);
3227 PTW1.M = TSTBIT(PTWx1, 6);
3228 PTW1.DF = TSTBIT(PTWx1, 2);
3229 PTW1.FC = PTWx1 & 3;
3230
3231 if (PTW1.DF == 0)
3232 continue;
3233
3234
3235
3236 for (word15 tspt = 0; tspt < 512u; tspt ++)
3237 {
3238 word36 SDWeven, SDWodd;
3239 core_read2(cpup, ((PTW1.ADDR << 6) + tspt * 2u) & PAMASK, & SDWeven,
3240 & SDWodd, __func__);
3241 sdw0_s SDW0;
3242
3243 SDW0.ADDR = (SDWeven >> 12) & PAMASK;
3244 SDW0.R1 = (SDWeven >> 9) & 7u;
3245 SDW0.R2 = (SDWeven >> 6) & 7u;
3246 SDW0.R3 = (SDWeven >> 3) & 7u;
3247 SDW0.DF = TSTBIT(SDWeven, 2);
3248 SDW0.FC = SDWeven & 3u;
3249
3250
3251 SDW0.BOUND = (SDWodd >> 21) & 037777;
3252 SDW0.R = TSTBIT(SDWodd, 20);
3253 SDW0.E = TSTBIT(SDWodd, 19);
3254 SDW0.W = TSTBIT(SDWodd, 18);
3255 SDW0.P = TSTBIT(SDWodd, 17);
3256 SDW0.U = TSTBIT(SDWodd, 16);
3257 SDW0.G = TSTBIT(SDWodd, 15);
3258 SDW0.C = TSTBIT(SDWodd, 14);
3259 SDW0.EB = SDWodd & 037777;
3260
3261 if (SDW0.DF == 0)
3262 continue;
3263
3264
3265
3266
3267
3268
3269 if (SDW0.U == 0)
3270 {
3271 for (word18 offset = 0;
3272 offset < 16u * (SDW0.BOUND + 1u);
3273 offset += 1024)
3274 {
3275 word24 y2 = offset % 1024;
3276 word24 x2 = (offset - y2) / 1024;
3277
3278
3279
3280
3281 word36 PTWx2;
3282 core_read (cpup, (SDW0.ADDR + x2) & PAMASK, & PTWx2, __func__);
3283
3284 ptw_s PTW2;
3285 PTW2.ADDR = GETHI(PTWx2);
3286 PTW2.U = TSTBIT(PTWx2, 9);
3287 PTW2.M = TSTBIT(PTWx2, 6);
3288 PTW2.DF = TSTBIT(PTWx2, 2);
3289 PTW2.FC = PTWx2 & 3;
3290
3291
3292
3293
3294
3295 if (address >= PTW2.ADDR + offset &&
3296 address < PTW2.ADDR + offset + 1024)
3297 sim_msg (" %06o:%06o\r\n", tspt, (address - offset) - PTW2.ADDR);
3298
3299 }
3300 }
3301 else
3302 {
3303 if (address >= SDW0.ADDR &&
3304 address < SDW0.ADDR + SDW0.BOUND * 16u)
3305 sim_msg (" %06o:%06o\r\n", tspt, address - SDW0.ADDR);
3306 }
3307 }
3308 }
3309 }
3310
3311 return SCPE_OK;
3312
3313 }
3314
3315
3316
3317 static t_stat virt_address (UNUSED int32 arg, const char * buf)
3318 {
3319 uint address;
3320 if (sscanf (buf, "%o", & address) != 1)
3321 return SCPE_ARG;
3322 return virtAddrN (address);
3323 }
3324
3325
3326
3327 static t_stat set_search_path (UNUSED int32 arg, UNUSED const char * buf)
3328 {
3329
3330 # if !defined(SPEED)
3331 if (source_search_path)
3332 FREE (source_search_path);
3333 source_search_path = strdup (buf);
3334 if (!source_search_path)
3335 {
3336 (void)fprintf (stderr, "\rFATAL: Out of memory! Aborting at %s[%s:%d]\r\n",
3337 __func__, __FILE__, __LINE__);
3338 # if defined(USE_BACKTRACE)
3339 # if defined(SIGUSR2)
3340 (void)raise(SIGUSR2);
3341
3342 # endif
3343 # endif
3344 abort();
3345 }
3346 # endif
3347 return SCPE_OK;
3348 }
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358 t_stat brkbrk (UNUSED int32 arg, UNUSED const char * buf)
3359 {
3360
3361 return SCPE_OK;
3362 }
3363
3364
3365
3366 static t_stat sbreak (int32 arg, const char * buf)
3367 {
3368
3369 int segno, offset;
3370 int where;
3371 int cnt = sscanf (buf, "%o:%o%n", & segno, & offset, & where);
3372 if (cnt != 2)
3373 {
3374 return SCPE_ARG;
3375 }
3376 char reformatted[strlen (buf) + 20];
3377 (void)sprintf (reformatted, "0%04o%06o%s", segno, offset, buf + where);
3378
3379 t_stat rc = brk_cmd (arg, reformatted);
3380 return rc;
3381 }
3382
3383 # if defined(DVFDBG)
3384 static t_stat dfx1entry (UNUSED int32 arg, UNUSED const char * buf)
3385 {
3386
3387 sim_msg ("dfx1entry\r\n");
3388 sim_msg ("rA %012"PRIo64" (%llu)\r\n", rA, rA);
3389 sim_msg ("rQ %012"PRIo64" (%llu)\r\n", rQ, rQ);
3390
3391
3392 word24 pa;
3393 char * msg;
3394 if (dbgLookupAddress (cpu.PR[6].SNR, 046, & pa, & msg))
3395 {
3396 sim_msg ("text segment number lookup failed because %s\r\n", msg);
3397 }
3398 else
3399 {
3400 sim_msg ("text segno %012"PRIo64" (%llu)\r\n", M[pa], M[pa]);
3401 }
3402 sim_msg ("%05o:%06o\r\n", cpu.PR[2].SNR, cpu.rX[0]);
3403
3404 if (dbgLookupAddress (cpu.PR[2].SNR, cpu.rX[0], & pa, & msg))
3405 {
3406 sim_msg ("return address lookup failed because %s\r\n", msg);
3407 }
3408 else
3409 {
3410 sim_msg ("scale %012"PRIo64" (%llu)\r\n", M[pa], M[pa]);
3411 }
3412 if (dbgLookupAddress (cpu.PR[2].SNR, cpu.PR[2].WORDNO, & pa, & msg))
3413 {
3414 sim_msg ("divisor address lookup failed because %s\r\n", msg);
3415 }
3416 else
3417 {
3418 sim_msg ("divisor %012"PRIo64" (%llu)\r\n", M[pa], M[pa]);
3419 }
3420 return SCPE_OK;
3421 }
3422
3423 static t_stat dfx1exit (UNUSED int32 arg, UNUSED const char * buf)
3424 {
3425 sim_msg ("dfx1exit\r\n");
3426 sim_msg ("rA %012"PRIo64" (%llu)\r\n", rA, rA);
3427 sim_msg ("rQ %012"PRIo64" (%llu)\r\n", rQ, rQ);
3428 return SCPE_OK;
3429 }
3430
3431 static t_stat dv2scale (UNUSED int32 arg, UNUSED const char * buf)
3432 {
3433 sim_msg ("dv2scale\r\n");
3434 sim_msg ("rQ %012"PRIo64" (%llu)\r\n", rQ, rQ);
3435 return SCPE_OK;
3436 }
3437
3438 static t_stat dfx2entry (UNUSED int32 arg, UNUSED const char * buf)
3439 {
3440
3441 sim_msg ("dfx2entry\r\n");
3442 sim_msg ("rA %012"PRIo64" (%llu)\r\n", rA, rA);
3443 sim_msg ("rQ %012"PRIo64" (%llu)\r\n", rQ, rQ);
3444
3445
3446 word24 pa;
3447 char * msg;
3448 if (dbgLookupAddress (cpu.PR[6].SNR, 046, & pa, & msg))
3449 {
3450 sim_msg ("text segment number lookup failed because %s\r\n", msg);
3451 }
3452 else
3453 {
3454 sim_msg ("text segno %012"PRIo64" (%llu)\r\n", M[pa], M[pa]);
3455 }
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482 if (dbgLookupAddress (cpu.PR[2].SNR, cpu.PR[2].WORDNO, & pa, & msg))
3483 {
3484 sim_msg ("divisor address lookup failed because %s\r\n", msg);
3485 }
3486 else
3487 {
3488 sim_msg ("divisor %012"PRIo64" (%llu)\r\n", M[pa], M[pa]);
3489 sim_msg ("divisor %012"PRIo64" (%llu)\r\n", M[pa + 1], M[pa + 1]);
3490 }
3491 return SCPE_OK;
3492 }
3493
3494 static t_stat mdfx3entry (UNUSED int32 arg, UNUSED const char * buf)
3495 {
3496
3497
3498
3499
3500 sim_msg ("mdfx3entry\r\n");
3501
3502 sim_msg ("rQ %012"PRIo64" (%llu)\r\n", rQ, rQ);
3503
3504
3505 word24 pa;
3506 char * msg;
3507 if (dbgLookupAddress (cpu.PR[6].SNR, 046, & pa, & msg))
3508 {
3509 sim_msg ("text segment number lookup failed because %s\r\n", msg);
3510 }
3511 else
3512 {
3513 sim_msg ("text segno %012"PRIo64" (%llu)\r\n", M[pa], M[pa]);
3514 }
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527 if (dbgLookupAddress (cpu.PR[2].SNR, cpu.PR[2].WORDNO, & pa, & msg))
3528 {
3529 sim_msg ("divisor address lookup failed because %s\r\n", msg);
3530 }
3531 else
3532 {
3533 sim_msg ("divisor %012"PRIo64" (%llu)\r\n", M[pa], M[pa]);
3534 }
3535 return SCPE_OK;
3536 }
3537
3538 static t_stat smfx1entry (UNUSED int32 arg, UNUSED const char * buf)
3539 {
3540
3541
3542
3543
3544 sim_msg ("smfx1entry\r\n");
3545
3546 sim_msg ("rQ %012"PRIo64" (%llu)\r\n", rQ, rQ);
3547
3548
3549 word24 pa;
3550 char * msg;
3551 if (dbgLookupAddress (cpu.PR[6].SNR, 046, & pa, & msg))
3552 {
3553 sim_msg ("text segment number lookup failed because %s\r\n", msg);
3554 }
3555 else
3556 {
3557 sim_msg ("text segno %012"PRIo64" (%llu)\r\n", M[pa], M[pa]);
3558 }
3559 sim_msg ("%05o:%06o\r\n", cpu.PR[2].SNR, cpu.rX[0]);
3560
3561 if (dbgLookupAddress (cpu.PR[2].SNR, cpu.rX[0], & pa, & msg))
3562 {
3563 sim_msg ("return address lookup failed because %s\r\n", msg);
3564 }
3565 else
3566 {
3567 sim_msg ("scale %012"PRIo64" (%llu)\r\n", M[pa], M[pa]);
3568 }
3569 if (dbgLookupAddress (cpu.PR[2].SNR, cpu.PR[2].WORDNO, & pa, & msg))
3570 {
3571 sim_msg ("divisor address lookup failed because %s\r\n", msg);
3572 }
3573 else
3574 {
3575 sim_msg ("divisor %012"PRIo64" (%llu)\r\n", M[pa], M[pa]);
3576 }
3577 return SCPE_OK;
3578 }
3579 # endif
3580
3581
3582
3583 static t_stat search_memory (UNUSED int32 arg, const char * buf)
3584 {
3585 word36 value;
3586 if (sscanf (buf, "%llo", & value) != 1)
3587 return SCPE_ARG;
3588
3589 uint i;
3590 for (i = 0; i < MEMSIZE; i ++)
3591 if ((M[i] & DMASK) == value)
3592 sim_msg ("%08o\r\n", i);
3593 return SCPE_OK;
3594 }
3595
3596 static t_stat set_dbg_cpu_mask (int32 UNUSED arg, const char * UNUSED buf)
3597 {
3598 uint msk;
3599 int cnt = sscanf (buf, "%u", & msk);
3600 if (cnt != 1)
3601 {
3602 sim_msg ("Huh?\r\n");
3603 return SCPE_ARG;
3604 }
3605 sim_msg ("mask set to %u\r\n", msk);
3606 dbgCPUMask = msk;
3607 return SCPE_OK;
3608 }
3609
3610 #endif
3611
3612
3613
3614
3615
3616 #if defined(PANEL68)
3617 static t_stat scraper (UNUSED int32 arg, const char * buf)
3618 {
3619 if (strcasecmp (buf, "start") == 0)
3620 return panelScraperStart ();
3621 if (strcasecmp (buf, "stop") == 0)
3622 return panelScraperStop ();
3623 if (strcasecmp (buf, "msg") == 0)
3624 {
3625 return panelScraperMsg (NULL);
3626 }
3627 if (strncasecmp (buf, "msg ", 4) == 0)
3628 {
3629 const char * p = buf + 4;
3630 while (* p == ' ')
3631 p ++;
3632 return panelScraperMsg (p);
3633 }
3634 sim_msg ("err: scraper start|stop|msg\r\n");
3635 return SCPE_ARG;
3636 }
3637 #endif
3638
3639 #if defined(YIELD)
3640 static t_stat clear_yield (int32 flag, UNUSED const char * cptr)
3641 {
3642 return SCPE_OK;
3643 }
3644
3645 static t_stat yield (int32 flag, UNUSED const char * cptr)
3646 {
3647 return SCPE_OK;
3648 }
3649 #endif
3650
3651 #if !defined(PERF_STRIP)
3652 static t_stat set_luf (int32 flag, UNUSED const char * cptr)
3653 {
3654 luf_flag = flag;
3655 return SCPE_OK;
3656 }
3657 #endif
3658
3659 #if defined(DBGEVENT)
3660 uint n_dbgevents;
3661 struct dbgevent_t dbgevents[max_dbgevents];
3662 struct timespec dbgevent_t0;
3663
3664 static int dbgevent_compar (const void * a, const void * b)
3665 {
3666 struct dbgevent_t * ea = (struct dbgevent_t *) a;
3667 struct dbgevent_t * eb = (struct dbgevent_t *) b;
3668 if (ea->segno < eb->segno)
3669 return -1;
3670 if (ea->segno > eb->segno)
3671 return 1;
3672 if (ea->offset < eb->offset)
3673 return -1;
3674 if (ea->offset > eb->offset)
3675 return 1;
3676 return 0;
3677 }
3678
3679 int dbgevent_lookup (word15 segno, word18 offset)
3680 {
3681 struct dbgevent_t key = {segno, offset, false};
3682 struct dbgevent_t * p = (struct dbgevent_t *) bsearch (& key, dbgevents, (size_t) n_dbgevents,
3683 sizeof (struct dbgevent_t), dbgevent_compar);
3684 if (! p)
3685 return -1;
3686 return (int) (p - dbgevents);
3687 }
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699 static t_stat set_dbgevent (int32 arg, const char * buf)
3700 {
3701 if (arg == 0 || arg == 1)
3702 {
3703 if (n_dbgevents >= max_dbgevents)
3704 {
3705 sim_printf ("too many dbgevents %u/%u\r\n", n_dbgevents, max_dbgevents);
3706 return SCPE_ARG;
3707 }
3708 if (strlen (buf) > dbgevent_tagsize - 1)
3709 {
3710 sim_printf ("command too long %lu/%u\r\n", strlen (buf), dbgevent_tagsize -1);
3711 return SCPE_ARG;
3712 }
3713
3714 uint segno;
3715 uint offset;
3716 if (sscanf (buf, "%o:%o", & segno, & offset) != 2)
3717 return SCPE_ARG;
3718 if (segno > MASK15 || offset > MASK18)
3719 return SCPE_ARG;
3720 if (dbgevent_lookup ((word15) segno, (word18) offset) != -1)
3721 {
3722 sim_printf ("not adding duplicate 0%o:0%o\r\n", segno, offset);
3723 return SCPE_ARG;
3724 }
3725 dbgevents[n_dbgevents].segno = (word15) segno;
3726 dbgevents[n_dbgevents].offset = (word18) offset;
3727 dbgevents[n_dbgevents].t0 = arg == 0;
3728 strncpy (dbgevents[n_dbgevents].tag, buf, dbgevent_tagsize - 1);
3729 dbgevents[n_dbgevents].tag[dbgevent_tagsize - 1] = 0;
3730 sim_printf ("%o:%o %u(%d) %s\r\n", dbgevents[n_dbgevents].segno,
3731 dbgevents[n_dbgevents].offset,
3732 dbgevents[n_dbgevents].t0, arg, dbgevents[n_dbgevents].tag);
3733 n_dbgevents ++;
3734 qsort (dbgevents, n_dbgevents, sizeof (struct dbgevent_t), dbgevent_compar);
3735 }
3736 else if (arg == 2)
3737 {
3738 uint segno;
3739 uint offset;
3740 if (sscanf (buf, "%o:%o", & segno, & offset) != 2)
3741 return SCPE_ARG;
3742 int n = dbgevent_lookup ((word15) segno, (word18) offset);
3743 if (n < 0)
3744 {
3745 sim_printf ("0%o:0%o not found\r\n", segno, offset);
3746 return SCPE_ARG;
3747 }
3748 for (int i = n; i < n_dbgevents - 1; i ++)
3749 dbgevents[i] = dbgevents[i + 1];
3750 n_dbgevents --;
3751 }
3752 else if (arg == 3)
3753 {
3754 for (int i = 0; i < n_dbgevents; i ++)
3755 sim_printf (" %s %05o:%06o %s\r\n", dbgevents[i].t0 ? "T0" : " ", dbgevents[i].segno,
3756 dbgevents[i].offset,dbgevents[i].tag);
3757 }
3758 else if (arg == 4)
3759 {
3760 n_dbgevents = 0;
3761 sim_printf ("dbgevents cleared\r\n");
3762 }
3763 else
3764 {
3765 sim_printf ("set_dbgevent bad arg %d\r\n", arg);
3766 return SCPE_ARG;
3767 }
3768 return SCPE_OK;
3769 }
3770 #endif
3771
3772
3773
3774
3775
3776
3777 t_stat rewind_media (int32 arg, const char * buf) {
3778 char name[strlen (buf) + 1];
3779
3780 int rc = sscanf (buf, "%s", name);
3781 if (rc != 1)
3782 return SCPE_ARG;
3783
3784 for (uint i = 0; i < N_MT_UNITS_MAX; i ++) {
3785 if (strcmp (tape_states[i].device_name, name) == 0) {
3786 UNIT * unitp = & mt_unit [i];
3787 return sim_tape_rewind (unitp);
3788 }
3789 }
3790
3791 sim_printf ("Can't find name '%s'\r\n", name);
3792 sim_printf ("REWIND device_name\r\n");
3793 return SCPE_ARG;
3794 }
3795
3796
3797
3798
3799
3800
3801
3802
3803 t_stat load_media (int32 arg, const char * buf)
3804 {
3805
3806
3807
3808 char name[strlen (buf) + 1];
3809 char fname[strlen (buf) + 1];
3810 char perm[strlen (buf) + 1];
3811 bool ro = false;
3812 if (arg)
3813 {
3814 int rc = sscanf (buf, "%s %s %s", name, fname, perm);
3815 if (rc != 3)
3816 return SCPE_ARG;
3817 if (strcasecmp (perm, "rw") == 0)
3818 ro = false;
3819 else if (strcasecmp (perm, "ro") == 0)
3820 ro = true;
3821 else
3822 {
3823 sim_print ("'%s' not 'ro' or 'rw'\r\n", perm);
3824 goto usage;
3825 }
3826 }
3827 else
3828 {
3829 int rc = sscanf (buf, "%s", name);
3830 if (rc != 1)
3831 return SCPE_ARG;
3832 }
3833
3834 for (uint i = 0; i < N_DSK_UNITS_MAX; i ++)
3835 if (strcmp (dsk_states[i].device_name, name) == 0)
3836 {
3837 if (arg)
3838 return loadDisk (i, fname, ro);
3839 return unloadDisk (i);
3840 }
3841
3842 for (uint i = 0; i < N_MT_UNITS_MAX; i ++)
3843 if (strcmp (tape_states[i].device_name, name) == 0)
3844 {
3845 if (arg)
3846 return loadTape (i, fname, ro);
3847 return unloadTape (i);
3848 }
3849
3850 sim_printf ("Can't find name '%s'\r\n", name);
3851 usage:
3852 sim_printf ("[UN]LOAD device_name image_name ro|rw\r\n");
3853 return SCPE_ARG;
3854 }
3855
3856 t_stat ready_media (int32 arg, const char * buf) {
3857 char name[strlen (buf) + 1];
3858 int rc = sscanf (buf, "%s", name);
3859 if (rc != 1)
3860 return SCPE_ARG;
3861
3862 for (uint i = 0; i < N_DSK_UNITS_MAX; i ++) {
3863 if (strcmp (dsk_states[i].device_name, name) == 0) {
3864 return signal_disk_ready (i);
3865 }
3866 }
3867
3868 for (uint i = 0; i < N_MT_UNITS_MAX; i ++) {
3869 if (strcmp (tape_states[i].device_name, name) == 0) {
3870 return signal_tape (i, 0, 020 );
3871 }
3872 }
3873
3874 sim_printf ("Can't find name '%s'\r\n", name);
3875 sim_printf ("[UN]LOAD device_name image_name ro|rw\r\n");
3876 return SCPE_ARG;
3877 }
3878
3879
3880
3881
3882
3883
3884 #if defined(TESTING)
3885 # include "tracker.h"
3886
3887 static t_stat trkw (UNUSED int32 arg, const char * buf)
3888 {
3889 trk_init (true);
3890 return SCPE_OK;
3891 }
3892
3893 static t_stat trkr (UNUSED int32 arg, const char * buf)
3894 {
3895 trk_init (false);
3896 return SCPE_OK;
3897 }
3898 #endif
3899
3900 #if !defined(PERF_STRIP)
3901 static CTAB dps8_cmds[] =
3902 {
3903
3904
3905
3906
3907 {"DEFAULT_BASE_SYSTEM", set_default_base_system, 0, "Set configuration to defaults\r\n", NULL, NULL},
3908
3909 {"CABLE", sys_cable, 0, "String a cable.\r\n", NULL, NULL},
3910 {"UNCABLE", sys_cable, 1, "Unstring a cable.\r\n", NULL, NULL},
3911 {"CABLE_RIPOUT", sys_cable_ripout, 0, "Remove all cables from the configuration.\r\n", NULL, NULL},
3912 {"CABLE_SHOW", sys_cable_show, 0, "Show the current cabling configuration.\r\n", NULL, NULL},
3913
3914 {"FNPSERVERPORT", set_fnp_server_port, 0, "Set the FNP dialin TELNET port number\r\n", NULL, NULL},
3915 {"FNPSERVERADDRESS", set_fnp_server_address, 0, "Set the FNP dialin server binding address\r\n", NULL, NULL},
3916 {"FNPSERVER3270PORT", set_fnp_3270_server_port, 0, "Set the FNP TN3270 dialin port number\r\n", NULL, NULL},
3917
3918
3919
3920
3921
3922 {"SKIPBOOT", boot_skip, 0, "Skip forward on boot tape\r\n", NULL, NULL},
3923 {"FNPSTART", fnp_start, 0, "Directs the simulator to immediately start listening for FNP connections.\r\n",
3924 NULL, NULL},
3925 {"MOUNT", mount_tape, 0, "Mount tape image and signal Multics\r\n", NULL, NULL},
3926 {"LOAD", load_media, 1, "Mount disk or tape image and signal Multics\r\n", NULL, NULL},
3927 {"UNLOAD", load_media, 0, "Unmount disk or tape image and signal Multics\r\n", NULL, NULL},
3928 {"READY", ready_media, 0, "Signal Multics that media is ready\r\n", NULL, NULL},
3929 {"REWIND", rewind_media, 0, "Rewind tape\r\n", NULL, NULL},
3930 {"XF", do_execute_fault, 0, "Execute fault: Press the execute fault button\r\n", NULL, NULL},
3931 {"RESTART", do_restart, 0, "Execute fault: Press the execute fault button\r\n", NULL, NULL},
3932 {"POLL", set_sys_polling_interval, 0, "Set polling interval (in milliseconds)\r\n", NULL, NULL},
3933 {"SLOWPOLL", set_sys_slow_polling_interval, 0, "Set slow polling interval (in polling intervals).\r\n", NULL, NULL},
3934 {"CHECKPOLL", set_sys_poll_check_rate, 0, "Set polling check rate (in polling intervals).\r\n", NULL, NULL},
3935 {"BURST", burst_printer, 0, "Burst process output from printer.\r\n", NULL, NULL},
3936
3937
3938
3939
3940
3941 # if defined(TESTING)
3942 {"TRKW", trkw, 0, "Start tracking to track.dat\r\n", NULL, NULL},
3943 {"TRKR", trkr, 0, "Start comparing with track.dat\r\n", NULL, NULL},
3944 {"DBGMMECNTDWN", dps_debug_mme_cntdwn, 0, "Enable debug after n MMEs\r\n", NULL, NULL},
3945 {"DBGSKIP", dps_debug_skip, 0, "Skip first n TRACE debugs\r\n", NULL, NULL},
3946 {"DBGSTART", dps_debug_start, 0, "Limit debugging to N > Cycle count\r\n", NULL, NULL},
3947 {"DBGSTOP", dps_debug_stop, 0, "Limit debugging to N < Cycle count\r\n", NULL, NULL},
3948 {"DBGBREAK", dps_debug_break, 0, "Break when N >= Cycle count\r\n", NULL, NULL},
3949 {"DBGSEGNO", dps_debug_segno, 1, "Limit debugging to PSR == segno\r\n", NULL, NULL},
3950 {"NODBGSEGNO", dps_debug_segno, 0, "Reset to debugging all segments\r\n", NULL, NULL},
3951 {"DBGRINGNO", dps_debug_ringno, 0, "Limit debugging to PRR == ringno\r\n", NULL, NULL},
3952 {"DBGBAR", dps_debug_bar, 1, "Limit debugging to BAR mode\r\n", NULL, NULL},
3953 {"NODBGBAR", dps_debug_bar, 0, "Limit debugging to BAR mode\r\n", NULL, NULL},
3954 {"HDBG", hdbg_size, 0, "Set history debugger buffer size\r\n", NULL, NULL},
3955 {"HDSEG", hdbgSegmentNumber, 0, "Set history debugger segment number\r\n", NULL, NULL},
3956 {"HDBL", hdbgBlacklist, 0, "Set history debugger blacklist\r\n", NULL, NULL},
3957 {"PHDBG", hdbg_print, 0, "Dump history buffer to 'hdbg0000.list'\r\n", NULL, NULL},
3958 {"HDBG_CPU_MASK", hdbg_cpu_mask, 0, "Set which CPUs to track (by mask)\r\n", NULL, NULL},
3959 {"ABSOLUTE", abs_addr, 0, "Compute the absolute address of segno:offset\r\n", NULL, NULL},
3960 {"STK", stack_trace, 0, "Print a stack trace\r\n", NULL, NULL},
3961 {"LIST", list_source_at, 0, "List source for address / segno:offset\r\n", NULL, NULL},
3962 {"LD_SYSTEM_BOOK", load_system_book, 0, "Load a Multics system book for symbolic debugging\r\n", NULL, NULL},
3963 {"ASBE", add_system_book_entry, 0, "Add an entry to the system book\r\n", NULL, NULL},
3964 {"LOOKUP_SYSTEM_BOOK", lookup_system_book, 0, "Lookup an address or symbol in the Multics system book\r\n", NULL, NULL},
3965 {"LSB", lookup_system_book, 0, "Lookup an address or symbol in the Multics system book\r\n", NULL, NULL},
3966 {"VIRTUAL", virt_address, 0, "Compute the virtual address(es) of segno:offset\r\n", NULL, NULL},
3967 {"SPATH", set_search_path, 0, "Set source code search path\r\n", NULL, NULL},
3968 {"TEST", brkbrk, 0, "GDB test hook\r\n", NULL, NULL},
3969 # if defined(DBGEVENT)
3970 {"DBG0EVENT", set_dbgevent, 0, "Set t0 debug event\r\n", NULL, NULL},
3971 {"DBGEVENT", set_dbgevent, 1, "Set debug event\r\n", NULL, NULL},
3972 {"DBGNOEVENT", set_dbgevent, 2, "Clear debug event\r\n", NULL, NULL},
3973 {"DBGLISTEVENTS", set_dbgevent, 3, "List debug events\r\n", NULL, NULL},
3974 {"DBGCLEAREVENTS", set_dbgevent, 4, "Clear debug events\r\n", NULL, NULL},
3975 # endif
3976 # define SSH_ST 0
3977 # define SSH_SH 1
3978 # define SSH_CL 2
3979 {"SBREAK", sbreak, SSH_ST, "Set a breakpoint with segno:offset syntax\r\n", NULL, NULL},
3980 {"NOSBREAK", sbreak, SSH_CL, "Unset an SBREAK\r\n", NULL, NULL},
3981 # if defined(DVFDBG)
3982
3983 {"DFX1ENTRY", dfx1entry, 0, "\r\n", NULL, NULL},
3984 {"DFX2ENTRY", dfx2entry, 0, "\r\n", NULL, NULL},
3985 {"DFX1EXIT", dfx1exit, 0, "\r\n", NULL, NULL},
3986 {"DV2SCALE", dv2scale, 0, "\r\n", NULL, NULL},
3987 {"MDFX3ENTRY", mdfx3entry, 0, "\r\n", NULL, NULL},
3988 {"SMFX1ENTRY", smfx1entry, 0, "\r\n", NULL, NULL},
3989 # endif
3990 # if !defined(SPEED)
3991 {"WATCH", set_mem_watch, 1, "Watch memory location\r\n", NULL, NULL},
3992 {"NOWATCH", set_mem_watch, 0, "Unwatch memory location\r\n", NULL, NULL},
3993 # endif
3994 {"SEARCHMEMORY", search_memory, 0, "Search memory for value\r\n", NULL, NULL},
3995 {"DBGCPUMASK", set_dbg_cpu_mask, 0, "Set per-CPU debug enable mask\r\n", NULL, NULL},
3996 # endif
3997
3998 {"SEGLDR", segment_loader, 0, "Segment Loader\r\n", NULL, NULL},
3999
4000
4001
4002
4003
4004 # if defined(MATRIX)
4005 {"DISPLAYMATRIX", display_the_matrix, 0, "Display instruction usage counts\r\n", NULL, NULL},
4006 # endif
4007
4008
4009
4010
4011
4012 {"AUTOINPUT", add_opc_autoinput, 0, "Set primary console auto-input\r\n", NULL, NULL},
4013 {"AI", add_opc_autoinput, 0, "Set primary console auto-input\r\n", NULL, NULL},
4014 {"AUTOINPUT2", add_opc_autoinput, 1, "Set secondary console auto-input\r\n", NULL, NULL},
4015 {"AI2", add_opc_autoinput, 1, "Set secondary console auto-input\r\n", NULL, NULL},
4016 {"CLRAUTOINPUT", clear_opc_autoinput, 0, "Clear primary console auto-input\r\n", NULL, NULL},
4017 {"CLRAUTOINPUT2", clear_opc_autoinput, 1, "Clear secondary console auto-input\r\n", NULL, NULL},
4018
4019
4020
4021
4022
4023 # if YIELD
4024 {"CLEAR_YIELD", clear_yield, 1, "Clear yield data points\r\n", NULL, NULL},
4025 {"YIELD", yield, 1, "Define yield data point\r\n", NULL, NULL},
4026 # endif
4027
4028
4029
4030
4031
4032 {"LUF", set_luf, 1, "Enable normal LUF handling\r\n", NULL, NULL},
4033 {"NOLUF", set_luf, 0, "Disable normal LUF handling\r\n", NULL, NULL},
4034
4035
4036
4037
4038
4039 # if defined(PANEL68)
4040 {"SCRAPER", scraper, 0, "Control panel scraper\r\n", NULL, NULL},
4041 # endif
4042 { NULL, NULL, 0, NULL, NULL, NULL}
4043 };
4044
4045 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW64) && !defined(CROSS_MINGW32) && !defined(PERF_STRIP)
4046 static void usr1_signal_handler (UNUSED int sig)
4047 {
4048 sim_msg ("USR1 signal caught; pressing the EXF button\r\n");
4049
4050 setG7fault (ASSUME0, FAULT_EXF);
4051 return;
4052 }
4053 # endif
4054
4055 static struct symbol_s symbols [] = {
4056 { "commit_id", SYM_STATE_OFFSET, SYM_STRING, offsetof (struct system_state_s, commit_id) },
4057 { "M[]", SYM_STATE_OFFSET, SYM_ARRAY, offsetof (struct system_state_s, M) },
4058 { "sizeof(*M)", SYM_STRUCT_SZ, SYM_SZ, sizeof (word36) },
4059
4060 { "cpus[]", SYM_STATE_OFFSET, SYM_ARRAY, offsetof (struct system_state_s, cpus) },
4061 { "sizeof(*cpus)", SYM_STRUCT_SZ, SYM_SZ, sizeof (cpu_state_t) },
4062
4063 { "cpus[].PPR", SYM_STRUCT_OFFSET, SYM_PTR, offsetof (cpu_state_t, PPR) },
4064 { "cpus[].PPR.PRR", SYM_STRUCT_OFFSET, SYM_UINT8_3, offsetof (struct ppr_s, PRR) },
4065 { "cpus[].PPR.PSR", SYM_STRUCT_OFFSET, SYM_UINT16_15, offsetof (struct ppr_s, PSR) },
4066 { "cpus[].PPR.P", SYM_STRUCT_OFFSET, SYM_UINT8_1, offsetof (struct ppr_s, P) },
4067 { "cpus[].PPR.IC", SYM_STRUCT_OFFSET, SYM_UINT32_18, offsetof (struct ppr_s, IC) },
4068
4069 { "cpus[].cu", SYM_STRUCT_OFFSET, SYM_PTR, offsetof (cpu_state_t, cu) },
4070 { "cpus[].cu.IWB", SYM_STRUCT_OFFSET, SYM_UINT64_36, offsetof (ctl_unit_data_t, IWB) },
4071 { "cpus[].cu.IR", SYM_STRUCT_OFFSET, SYM_UINT32_18, offsetof (ctl_unit_data_t, IR) },
4072
4073 { "cpus[].rA", SYM_STRUCT_OFFSET, SYM_UINT64_36, offsetof (cpu_state_t, rA) },
4074
4075 { "cpus[].rQ", SYM_STRUCT_OFFSET, SYM_UINT64_36, offsetof (cpu_state_t, rQ) },
4076
4077 { "cpus[].rE", SYM_STRUCT_OFFSET, SYM_UINT64_36, offsetof (cpu_state_t, rE) },
4078
4079 { "cpus[].rX[]", SYM_STRUCT_OFFSET, SYM_ARRAY, offsetof (cpu_state_t, rX) },
4080 { "sizeof(*rX)", SYM_STRUCT_SZ, SYM_SZ, sizeof (word18) },
4081 { "cpus[].rX", SYM_STRUCT_OFFSET, SYM_UINT32_18, 0 },
4082
4083 { "cpus[].rTR", SYM_STRUCT_OFFSET, SYM_UINT32_27, offsetof (cpu_state_t, rTR) },
4084
4085 { "cpus[].rRALR", SYM_STRUCT_OFFSET, SYM_UINT8_3, offsetof (cpu_state_t, rRALR) },
4086
4087 { "cpus[].PAR[]", SYM_STRUCT_OFFSET, SYM_ARRAY, offsetof (cpu_state_t, PAR) },
4088 { "sizeof(*PAR)", SYM_STRUCT_SZ, SYM_SZ, sizeof (struct par_s) },
4089
4090 { "cpus[].PAR[].SNR", SYM_STRUCT_OFFSET, SYM_UINT16_15, offsetof (struct par_s, SNR) },
4091 { "cpus[].PAR[].RNR", SYM_STRUCT_OFFSET, SYM_UINT8_3, offsetof (struct par_s, RNR) },
4092 { "cpus[].PAR[].PR_BITNO", SYM_STRUCT_OFFSET, SYM_UINT8_6, offsetof (struct par_s, PR_BITNO) },
4093 { "cpus[].PAR[].WORDNO", SYM_STRUCT_OFFSET, SYM_UINT32_18, offsetof (struct par_s, WORDNO) },
4094
4095 { "cpus[].BAR", SYM_STRUCT_OFFSET, SYM_PTR, offsetof (cpu_state_t, BAR) },
4096 { "cpus[].BAR.BASE", SYM_STRUCT_OFFSET, SYM_UINT16_9, offsetof (struct bar_s, BASE) },
4097 { "cpus[].BAR.BOUND", SYM_STRUCT_OFFSET, SYM_UINT16_9, offsetof (struct bar_s, BOUND) },
4098
4099 { "cpus[].TPR", SYM_STRUCT_OFFSET, SYM_PTR, offsetof (cpu_state_t, TPR) },
4100 { "cpus[].TPR.TRR", SYM_STRUCT_OFFSET, SYM_UINT8_3, offsetof (struct tpr_s, TRR) },
4101 { "cpus[].TPR.TSR", SYM_STRUCT_OFFSET, SYM_UINT16_15, offsetof (struct tpr_s, TSR) },
4102 { "cpus[].TPR.TBR", SYM_STRUCT_OFFSET, SYM_UINT8_6, offsetof (struct tpr_s, TBR) },
4103 { "cpus[].TPR.CA", SYM_STRUCT_OFFSET, SYM_UINT32_18, offsetof (struct tpr_s, CA) },
4104
4105 { "cpus[].DSBR", SYM_STRUCT_OFFSET, SYM_PTR, offsetof (cpu_state_t, DSBR) },
4106 { "cpus[].DSBR.ADDR", SYM_STRUCT_OFFSET, SYM_UINT32_24, offsetof (struct dsbr_s, ADDR) },
4107 { "cpus[].DSBR.BND", SYM_STRUCT_OFFSET, SYM_UINT16_14, offsetof (struct dsbr_s, BND) },
4108 { "cpus[].DSBR.U", SYM_STRUCT_OFFSET, SYM_UINT8_1, offsetof (struct dsbr_s, U) },
4109 { "cpus[].DSBR.STACK", SYM_STRUCT_OFFSET, SYM_UINT16_12, offsetof (struct dsbr_s, STACK) },
4110
4111 { "cpus[].faultNumber", SYM_STRUCT_OFFSET, SYM_UINT32, offsetof (cpu_state_t, faultNumber) },
4112 # define SYMTAB_ENUM32(e) { #e, SYM_ENUM, SYM_UINT32, e }
4113 SYMTAB_ENUM32 (FAULT_SDF),
4114 SYMTAB_ENUM32 (FAULT_STR),
4115 SYMTAB_ENUM32 (FAULT_MME),
4116 SYMTAB_ENUM32 (FAULT_F1),
4117 SYMTAB_ENUM32 (FAULT_TRO),
4118 SYMTAB_ENUM32 (FAULT_CMD),
4119 SYMTAB_ENUM32 (FAULT_DRL),
4120 SYMTAB_ENUM32 (FAULT_LUF),
4121 SYMTAB_ENUM32 (FAULT_CON),
4122 SYMTAB_ENUM32 (FAULT_PAR),
4123 SYMTAB_ENUM32 (FAULT_IPR),
4124 SYMTAB_ENUM32 (FAULT_ONC),
4125 SYMTAB_ENUM32 (FAULT_SUF),
4126 SYMTAB_ENUM32 (FAULT_OFL),
4127 SYMTAB_ENUM32 (FAULT_DIV),
4128 SYMTAB_ENUM32 (FAULT_EXF),
4129 SYMTAB_ENUM32 (FAULT_DF0),
4130 SYMTAB_ENUM32 (FAULT_DF1),
4131 SYMTAB_ENUM32 (FAULT_DF2),
4132 SYMTAB_ENUM32 (FAULT_DF3),
4133 SYMTAB_ENUM32 (FAULT_ACV),
4134 SYMTAB_ENUM32 (FAULT_MME2),
4135 SYMTAB_ENUM32 (FAULT_MME3),
4136 SYMTAB_ENUM32 (FAULT_MME4),
4137 SYMTAB_ENUM32 (FAULT_F2),
4138 SYMTAB_ENUM32 (FAULT_F3),
4139 SYMTAB_ENUM32 (FAULT_UN1),
4140 SYMTAB_ENUM32 (FAULT_UN2),
4141 SYMTAB_ENUM32 (FAULT_UN3),
4142 SYMTAB_ENUM32 (FAULT_UN4),
4143 SYMTAB_ENUM32 (FAULT_UN5),
4144 SYMTAB_ENUM32 (FAULT_TRB),
4145
4146 { "", SYM_EMPTY, SYM_UNDEF, 0 },
4147 };
4148
4149 static void systabInit (void) {
4150 strncpy (system_state->symbolTable.symtabHdr, SYMTAB_HDR, sizeof (system_state->symbolTable.symtabHdr));
4151 system_state->symbolTable.symtabVer = SYMTAB_VER;
4152 memcpy (system_state->symbolTable.symbols, symbols, sizeof (symbols));
4153 }
4154 #endif
4155
4156 static inline uint32_t
4157 hash32s(const void *buf, size_t len, uint32_t h)
4158 {
4159 const unsigned char *p = buf;
4160
4161 for (size_t i = 0; i < len; i++)
4162 h = h * 31 + p[i];
4163
4164 h ^= h >> 17;
4165 h *= UINT32_C(0xed5ad4bb);
4166 h ^= h >> 11;
4167 h *= UINT32_C(0xac4c1b51);
4168 h ^= h >> 15;
4169 h *= UINT32_C(0x31848bab);
4170 h ^= h >> 14;
4171
4172 return h;
4173 }
4174
4175
4176
4177 static void dps8_init (void) {
4178 int st1ret;
4179 (void)fflush(stderr);
4180 (void)fflush(stdout);
4181 #if !defined(PERF_STRIP)
4182 if (!sim_quiet) {
4183 # if defined(GENERATED_MAKE_VER_H) && defined(VER_H_GIT_VERSION)
4184 # if defined(VER_H_GIT_PATCH_INT) && defined(VER_H_GIT_PATCH)
4185 # if VER_H_GIT_PATCH_INT < 1
4186 sim_msg ("%s simulator %s (%ld-bit)",
4187 sim_name, VER_H_GIT_VERSION,
4188 (long)(CHAR_BIT*sizeof(void *)));
4189 # else
4190 sim_msg ("%s simulator %s+%s (%ld-bit)",
4191 sim_name, VER_H_GIT_VERSION, VER_H_GIT_PATCH,
4192 (long)(CHAR_BIT*sizeof(void *)));
4193 # endif
4194 # else
4195 sim_msg ("%s simulator %s (%ld-bit)",
4196 sim_name, VER_H_GIT_VERSION,
4197 (long)(CHAR_BIT*sizeof(void *)));
4198 # endif
4199 # endif
4200 # if !defined(VER_H_GIT_VERSION) || !defined(GENERATED_MAKE_VER_H)
4201 sim_msg ("%s simulator (%ld-bit)",
4202 sim_name, (long)(CHAR_BIT*sizeof(void *)));
4203 # endif
4204
4205
4206 # if defined(TESTING)
4207 sim_msg ("\r\n Options: ");
4208 # if !defined(HAVE_DPSOPT)
4209 # define HAVE_DPSOPT 1
4210 # endif
4211 sim_msg ("TESTING");
4212 # endif
4213
4214
4215 # if defined(ISOLTS)
4216 # if defined(HAVE_DPSOPT)
4217 sim_msg (", ");
4218 # else
4219 sim_msg ("\r\n Options: ");
4220 # endif
4221 # if !defined(HAVE_DPSOPT)
4222 # define HAVE_DPSOPT 1
4223 # endif
4224 sim_msg ("ISOLTS");
4225 # endif
4226
4227
4228 # if defined(NEED_128)
4229 # if defined(HAVE_DPSOPT)
4230 sim_msg (", ");
4231 # else
4232 sim_msg ("\r\n Options: ");
4233 # endif
4234 # if !defined(HAVE_DPSOPT)
4235 # define HAVE_DPSOPT 1
4236 # endif
4237 sim_msg ("NEED_128");
4238 # endif
4239
4240
4241 # if defined(WAM)
4242 # if defined(HAVE_DPSOPT)
4243 sim_msg (", ");
4244 # else
4245 sim_msg ("\r\n Options: ");
4246 # endif
4247 # if !defined(HAVE_DPSOPT)
4248 # define HAVE_DPSOPT 1
4249 # endif
4250 sim_msg ("WAM");
4251 # endif
4252
4253
4254 # if defined(ROUND_ROBIN)
4255 # if defined(HAVE_DPSOPT)
4256 sim_msg (", ");
4257 # else
4258 sim_msg ("\r\n Options: ");
4259 # endif
4260 # if !defined(HAVE_DPSOPT)
4261 # define HAVE_DPSOPT 1
4262 # endif
4263 sim_msg ("ROUND_ROBIN");
4264 # endif
4265
4266
4267 # if !defined(LOCKLESS)
4268 # if defined(HAVE_DPSOPT)
4269 sim_msg (", ");
4270 # else
4271 sim_msg ("\r\n Options: ");
4272 # endif
4273 # if !defined(HAVE_DPSOPT)
4274 # define HAVE_DPSOPT 1
4275 # endif
4276 sim_msg ("NO_LOCKLESS");
4277 # endif
4278
4279
4280 # if defined(PANEL68)
4281 # if defined(HAVE_DPSOPT)
4282 sim_msg (", ");
4283 # else
4284 sim_msg ("\r\n Options: ");
4285 # endif
4286 # if !defined(HAVE_DPSOPT)
4287 # define HAVE_DPSOPT 1
4288 # endif
4289 sim_msg ("PANEL68");
4290 # endif
4291
4292
4293 # if defined(WITH_ABSI_DEV)
4294 # if defined(HAVE_DPSOPT)
4295 sim_msg (", ");
4296 # else
4297 sim_msg ("\r\n Options: ");
4298 # endif
4299 # if !defined(HAVE_DPSOPT)
4300 # define HAVE_DPSOPT 1
4301 # endif
4302 sim_msg ("ABSI");
4303 # endif
4304
4305
4306 # if defined(WITH_SOCKET_DEV)
4307 # if defined(HAVE_DPSOPT)
4308 sim_msg (", ");
4309 # else
4310 sim_msg ("\r\n Options: ");
4311 # endif
4312 # if !defined(HAVE_DPSOPT)
4313 # define HAVE_DPSOPT 1
4314 # endif
4315 sim_msg ("SOCKET");
4316 # endif
4317
4318
4319 # if defined(WITH_MGP_DEV)
4320 # if defined(HAVE_DPSOPT)
4321 sim_msg (", ");
4322 # else
4323 sim_msg ("\r\n Options: ");
4324 # endif
4325 # if !defined(HAVE_DPSOPT)
4326 # define HAVE_DPSOPT 1
4327 # endif
4328 sim_msg ("CHAOSNET");
4329 # endif
4330
4331
4332 # if defined(USE_DUMA)
4333 # if defined(HAVE_DPSOPT)
4334 sim_msg (", ");
4335 # else
4336 sim_msg ("\r\n Options: ");
4337 # endif
4338 # if !defined(HAVE_DPSOPT)
4339 # define HAVE_DPSOPT 1
4340 # endif
4341 sim_msg ("DUMA");
4342 # endif
4343
4344 # if defined(GENERATED_MAKE_VER_H) && defined(VER_H_GIT_HASH)
4345 sim_msg ("\r\n Commit: %s", VER_H_GIT_HASH);
4346 # endif
4347 sim_msg ("\r\n\r\n");
4348 (void)fflush(stderr);
4349 (void)fflush(stdout);
4350 }
4351
4352
4353
4354 # if defined(TESTING)
4355
4356 sim_vm_parse_addr = parse_addr;
4357 sim_vm_fprint_addr = fprint_addr;
4358 # endif
4359
4360 sim_vm_cmd = dps8_cmds;
4361
4362
4363 sim_brk_types = sim_brk_dflt = SWMASK ('E');
4364
4365 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW32) && !defined(CROSS_MINGW64)
4366
4367 signal (SIGUSR1, usr1_signal_handler);
4368
4369 signal(SIGPIPE, SIG_IGN);
4370 # endif
4371
4372 #endif
4373
4374 #if defined(__MINGW64__) || defined(__MINGW32__)
4375 # include "bsd_random.h"
4376 # define random bsd_random
4377 # define srandom bsd_srandom
4378 #endif
4379
4380 char rcap = 0;
4381 char rnum = 0;
4382 struct timespec ts;
4383
4384 char rssuffix[24];
4385 (void)memset(rssuffix, 0, 24);
4386
4387 char statenme[32];
4388 (void)memset(statenme, 0, 32);
4389
4390 #if defined(USE_MONOTONIC)
4391 st1ret = clock_gettime(CLOCK_MONOTONIC, &ts);
4392 #else
4393 st1ret = clock_gettime(CLOCK_REALTIME, &ts);
4394 #endif
4395 if (st1ret != 0)
4396 {
4397 (void)fprintf (stderr, "\rFATAL: clock_gettime failure! Aborting at %s[%s:%d]\r\n",
4398 __func__, __FILE__, __LINE__);
4399 #if defined(USE_BACKTRACE)
4400 # if defined(SIGUSR2)
4401 (void)raise(SIGUSR2);
4402
4403 # endif
4404 #endif
4405 abort();
4406 }
4407
4408 uint32_t h = 0;
4409 #if __STDC_VERSION__ < 201112L
4410
4411 void *(*mallocptr)() = malloc;
4412 h = hash32s(&mallocptr, sizeof(mallocptr), h);
4413 #endif
4414 void *ptr = &ptr;
4415 h = hash32s(&ptr, sizeof(ptr), h);
4416 time_t t = time(0);
4417 h = hash32s(&t, sizeof(t), h);
4418 #if !defined(_AIX)
4419 for (int i = 0; i < 1000; i++)
4420 {
4421 unsigned long counter = 0;
4422 clock_t start = clock();
4423 while (clock() == start)
4424 {
4425 counter++;
4426 }
4427 h = hash32s(&start, sizeof(start), h);
4428 h = hash32s(&counter, sizeof(counter), h);
4429 }
4430 #endif
4431 int mypid = (int)_sir_getpid();
4432 h = hash32s(&mypid, sizeof(mypid), h);
4433 char rnd[4];
4434 FILE *f = fopen("/dev/urandom", "rb");
4435 if (f)
4436 {
4437 if (fread(rnd, sizeof(rnd), 1, f))
4438 {
4439 h = hash32s(rnd, sizeof(rnd), h);
4440 }
4441 fclose(f);
4442 }
4443 srandom(h);
4444
4445 for (int i = 1; i < 21; ++i) {
4446 rcap = (int)random() % 2;
4447 rnum = (int)random() % 3;
4448 if (!rnum) rnum = (((int)random() % 10) + 48);
4449 if (!rcap) rcap = 33;
4450 if (rnum >= 48) rssuffix[i-1]=rnum;
4451 else rssuffix[i-1]=(char)(((long)random() % 26) + 64) + rcap;
4452 }
4453
4454 #if defined(__MINGW64__) || \
4455 defined(__MINGW32__) || \
4456 defined(CROSS_MINGW32) || \
4457 defined(CROSS_MINGW64)
4458 system_state = aligned_malloc (sizeof (struct system_state_s));
4459 #else
4460 if (sim_randstate)
4461 (void)sprintf(statenme, "%s.state", rssuffix);
4462 else
4463 (void)sprintf(statenme, "state");
4464 if (!sim_nostate)
4465 system_state = (struct system_state_s *)
4466 create_shm (statenme, sizeof (struct system_state_s));
4467 else
4468 # if !defined(_AIX)
4469 system_state = aligned_malloc (sizeof (struct system_state_s));
4470 # else
4471 system_state = malloc (sizeof (struct system_state_s));
4472 # endif
4473 #endif
4474
4475 if (!system_state) {
4476 int svErrno = errno;
4477 (void)fflush(stderr);
4478 (void)fflush(stdout);
4479 sim_warn ("\rFATAL: %s: aborting at %s[%s:%d]\r\n",
4480 xstrerror_l(svErrno),
4481 __func__, __FILE__, __LINE__);
4482 #if defined(USE_BACKTRACE)
4483 # if defined(SIGUSR2)
4484 (void)raise(SIGUSR2);
4485
4486 # endif
4487 #endif
4488 exit (svErrno);
4489 }
4490 #if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW64) && !defined(CROSS_MINGW32) && !defined(__PASE__)
4491 if (0 == sim_free_memory || sim_free_memory >= 192000000) {
4492 if (mlock(system_state, sizeof(struct system_state_s)) == -1) {
4493 mlock_failure = true;
4494 }
4495 } else {
4496 # if defined(TESTING)
4497 sim_warn ("Low memory - no memory locking attempted.\r\n");
4498 # else
4499 (void)system_state;
4500 # endif
4501 }
4502 #endif
4503
4504 #if !defined(PERF_STRIP)
4505
4506 # if !defined(VER_H_GIT_HASH)
4507 # define VER_H_GIT_HASH "0000000000000000000000000000000000000000"
4508 # endif
4509
4510 (void)fflush(stdout);
4511 (void)fflush(stderr);
4512 if (strlen (system_state->commit_id) == 0) {
4513 if (!sim_quiet && sim_randstate && sim_randompst)
4514 sim_printf ("Initialized new system state file \"dps8m.%s\"\r\n",
4515 statenme);
4516 } else {
4517 if (strcmp (system_state->commit_id, VER_H_GIT_HASH) != 0) {
4518 (void)memset(system_state, 0, sizeof(*system_state));
4519 sim_warn ("NOTE: State hash mismatch; system state reset.\r\n");
4520 }
4521 }
4522 (void)fflush(stderr);
4523 (void)fflush(stdout);
4524
4525 strncpy (system_state->stateHdr, STATE_HDR, sizeof (system_state->stateHdr));
4526 system_state->stateVer = STATE_VER;
4527 strncpy (system_state->commit_id, VER_H_GIT_HASH, sizeof (system_state->commit_id));
4528
4529 systabInit ();
4530
4531
4532 (void)memset (& sys_opts, 0, sizeof (sys_opts));
4533
4534 sys_opts.sys_poll_interval = 10;
4535
4536 sys_opts.sys_slow_poll_interval = 100;
4537
4538 sys_opts.sys_poll_check_rate = 1024;
4539 #endif
4540
4541 #if defined(PERF_STRIP)
4542 cpu_init ();
4543 #else
4544 sysCableInit ();
4545 iom_init ();
4546 disk_init ();
4547 mt_init ();
4548 # if defined(WITH_SOCKET_DEV)
4549 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW64) && !defined(CROSS_MINGW32)
4550 sk_init ();
4551 # endif
4552 # endif
4553 fnpInit ();
4554 console_init ();
4555 scu_init ();
4556 cpu_init ();
4557 rdr_init ();
4558 pun_init ();
4559 prt_init ();
4560 urp_init ();
4561
4562 # if defined(WITH_ABSI_DEV)
4563 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW64) && !defined(CROSS_MINGW32)
4564 absi_init ();
4565 # endif
4566 # endif
4567
4568 # if defined(WITH_MGP_DEV)
4569 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW64) && !defined(CROSS_MINGW32)
4570 mgp_init ();
4571 # endif
4572 # endif
4573
4574 set_default_base_system (0, NULL);
4575 # if defined(PANEL68)
4576 panelScraperInit ();
4577 # endif
4578 #endif
4579 #if defined(THREADZ) || defined(LOCKLESS)
4580 initThreadz ();
4581 #endif
4582 }
4583
4584
4585
4586 static void dps8_exit (void) {
4587 console_exit ();
4588 mt_exit ();
4589 fnpExit ();
4590 }
4591
4592 #if defined(TESTING)
4593 static struct pr_table
4594 {
4595 char * alias;
4596 int n;
4597 } _prtab[] =
4598 {
4599 { "pr0", 0 },
4600 { "pr1", 1 },
4601 { "pr2", 2 },
4602 { "pr3", 3 },
4603 { "pr4", 4 },
4604 { "pr5", 5 },
4605 { "pr6", 6 },
4606 { "pr7", 7 },
4607
4608 { "pr[0]", 0 },
4609 { "pr[1]", 1 },
4610 { "pr[2]", 2 },
4611 { "pr[3]", 3 },
4612 { "pr[4]", 4 },
4613 { "pr[5]", 5 },
4614 { "pr[6]", 6 },
4615 { "pr[7]", 7 },
4616
4617
4618 { "ap", 0 },
4619 { "ab", 1 },
4620 { "bp", 2 },
4621 { "bb", 3 },
4622 { "lp", 4 },
4623 { "lb", 5 },
4624 { "sp", 6 },
4625 { "sb", 7 },
4626 { 0, 0 }
4627 };
4628
4629 static int getAddress(int segno, int offset)
4630 {
4631
4632
4633
4634 sdw0_s *s = fetchSDW ((word15) segno);
4635
4636 return (s->ADDR + (word18) offset) & 0xffffff;
4637 }
4638
4639 static t_addr parse_addr (UNUSED DEVICE * dptr, const char *cptr,
4640 const char **optr)
4641 {
4642 cpu_state_t * cpup = _cpup;
4643
4644 if (strchr(cptr, '|'))
4645 {
4646 static char addspec[256];
4647 (void)strcpy(addspec, cptr);
4648
4649 *strchr(addspec, '|') = ' ';
4650
4651 char seg[256], off[256];
4652 int params = sscanf(addspec, "%s %s", seg, off);
4653 if (params != 2)
4654 {
4655 sim_warn("parse_addr(): illegal number of parameters\r\n");
4656 *optr = cptr;
4657 return 0;
4658 }
4659
4660
4661 char *endp;
4662 word18 PRoffset = 0;
4663 int segno = (int)strtoll(seg, &endp, 8);
4664 if (endp == seg)
4665 {
4666
4667
4668 struct pr_table *prt = _prtab;
4669 while (prt->alias)
4670 {
4671 if (strcasecmp(seg, prt->alias) == 0)
4672 {
4673 segno = cpu.PR[prt->n].SNR;
4674 PRoffset = cpu.PR[prt->n].WORDNO;
4675 break;
4676 }
4677
4678 prt += 1;
4679 }
4680
4681 if (!prt->alias)
4682 {
4683 return 0;
4684 }
4685 }
4686
4687
4688 uint offset = (uint)strtoll(off, &endp, 8);
4689 if (endp == off)
4690 {
4691
4692 return 0;
4693 }
4694
4695
4696
4697
4698
4699 word24 abs_addr = (word24) getAddress(segno, (int) (offset + PRoffset));
4700
4701
4702 *optr = endp;
4703
4704 return abs_addr;
4705 }
4706 else
4707 {
4708
4709 int segno = 0;
4710 word24 offset = 0;
4711 struct pr_table *prt = _prtab;
4712 while (prt->alias)
4713 {
4714 if (strncasecmp(cptr, prt->alias, strlen(prt->alias)) == 0)
4715 {
4716 segno = cpu.PR[prt->n].SNR;
4717 offset = cpu.PR[prt->n].WORDNO;
4718 break;
4719 }
4720
4721 prt += 1;
4722 }
4723 if (prt->alias)
4724 {
4725 word24 abs_addr = (word24) getAddress(segno, (int) offset);
4726 *optr = cptr + strlen(prt->alias);
4727
4728 return abs_addr;
4729 }
4730 }
4731
4732
4733 return (t_addr)strtol(cptr, (char **) optr, 8);
4734 }
4735 #endif
4736
4737 #if defined(TESTING)
4738 static void fprint_addr (FILE * stream, UNUSED DEVICE * dptr, t_addr simh_addr)
4739 {
4740 (void)fprintf(stream, "%06o", simh_addr);
4741 }
4742 #endif
4743
4744
4745
4746
4747
4748
4749
4750 t_stat fprint_sym (UNUSED FILE * ofile, UNUSED t_addr addr,
4751 UNUSED t_value *val, UNUSED UNIT *uptr, int32 UNUSED sw)
4752 {
4753 #if defined(TESTING)
4754
4755
4756
4757
4758
4759 cpu_state_t * cpup = _cpup;
4760
4761 if (!((uint) sw & SWMASK ('M')))
4762 return SCPE_ARG;
4763
4764 if (uptr == &cpu_dev.units[0])
4765 {
4766 word36 word1 = *val;
4767 char buf[256];
4768
4769 char *d = disassemble(buf, word1);
4770
4771 (void)fprintf(ofile, "%s", d);
4772
4773
4774 DCDstruct ci;
4775 DCDstruct * p = & ci;
4776 decode_instruction (cpup, word1, p);
4777
4778
4779 if (p->info->ndes > 1)
4780 {
4781
4782
4783
4784 for(uint n = 0 ; n < p->info->ndes; n += 1)
4785 (void)fprintf(ofile, " %012llo", (unsigned long long int)val[n + 1]);
4786
4787 return (t_stat) -p->info->ndes;
4788 }
4789
4790 return SCPE_OK;
4791
4792
4793
4794 }
4795 #endif
4796 return SCPE_ARG;
4797 }
4798
4799
4800
4801
4802
4803 t_stat parse_sym (UNUSED const char * cptr, UNUSED t_addr addr,
4804 UNUSED UNIT * uptr, UNUSED t_value * val, UNUSED int32 sswitch)
4805 {
4806 return SCPE_ARG;
4807 }
4808
4809 #if defined(THREADZ) || defined(LOCKLESS)
4810 volAtomic bool syncClockMode;
4811 volAtomic uint syncClockModeMasterIdx;
4812 #endif
4813
4814
4815
4816 sysinfo_t sys_opts;
4817
4818 static t_stat sys_show_config (UNUSED FILE * st, UNUSED UNIT * uptr,
4819 UNUSED int val, UNUSED const void * desc)
4820 {
4821 sim_msg ("IOM connect time: %d\r\n", sys_opts.iom_times.connect);
4822 sim_msg ("nosync %d\r\n", sys_opts.nosync);
4823 return SCPE_OK;
4824 }
4825
4826 static config_value_list_t cfg_timing_list[] =
4827 {
4828 { "disable", -1 },
4829 { NULL, 0 }
4830 };
4831
4832 bool breakEnable = false;
4833
4834 static t_stat sys_set_break (UNUSED UNIT * uptr, int32 value,
4835 UNUSED const char * cptr, UNUSED void * desc)
4836 {
4837 breakEnable = !! value;
4838 return SCPE_OK;
4839 }
4840
4841 static t_stat sys_show_break (UNUSED FILE * st, UNUSED UNIT * uptr,
4842 UNUSED int val, UNUSED const void * desc)
4843 {
4844 sim_msg ("BREAK %s\r\n", breakEnable ? "ON" : "OFF" );
4845 return SCPE_OK;
4846 }
4847
4848 static config_value_list_t cfg_on_off [] =
4849 {
4850 { "off", 0 },
4851 { "on", 1 },
4852 { "disable", 0 },
4853 { "enable", 1 },
4854 { NULL, 0 }
4855 };
4856
4857 static config_list_t sys_config_list[] =
4858 {
4859 { "connect_time", -1, 100000, cfg_timing_list },
4860 { "nosync", 0, 1, cfg_on_off },
4861 { "color", 0, 1, cfg_on_off },
4862 { NULL, 0, 0, NULL }
4863 };
4864
4865 static t_stat sys_set_config (UNUSED UNIT * uptr, UNUSED int32 value,
4866 const char * cptr, UNUSED void * desc)
4867 {
4868 config_state_t cfg_state = { NULL, NULL };
4869
4870 for (;;)
4871 {
4872 int64_t v;
4873 int rc = cfg_parse ("sys_set_config", cptr, sys_config_list, & cfg_state,
4874 & v);
4875 if (rc == -1)
4876 {
4877 break;
4878 }
4879 if (rc == -2)
4880 {
4881 cfg_parse_done (& cfg_state);
4882 return SCPE_ARG;
4883 }
4884
4885 const char * p = sys_config_list[rc].name;
4886 if (strcmp (p, "connect_time") == 0)
4887 sys_opts.iom_times.connect = (int) v;
4888 else if (strcmp (p, "color") == 0)
4889 sys_opts.no_color = ! v;
4890 else if (strcmp (p, "nosync") == 0)
4891 sys_opts.nosync = !! v;
4892 else
4893 {
4894 sim_msg ("error: sys_set_config: Invalid cfg_parse rc <%ld>\r\n", (long) rc);
4895 cfg_parse_done (& cfg_state);
4896 return SCPE_ARG;
4897 }
4898 }
4899 cfg_parse_done (& cfg_state);
4900 return SCPE_OK;
4901 }
4902
4903 static MTAB sys_mod[] =
4904 {
4905 {
4906 MTAB_dev_value,
4907 0,
4908 (char *) "CONFIG",
4909 (char *) "CONFIG",
4910 sys_set_config,
4911 sys_show_config,
4912 NULL,
4913 NULL,
4914 },
4915 {
4916 MTAB_dev_novalue,
4917 1,
4918 (char *) "BREAK",
4919 (char *) "BREAK",
4920 sys_set_break,
4921 sys_show_break,
4922 NULL,
4923 NULL,
4924 },
4925 {
4926 MTAB_dev_novalue,
4927 0,
4928 (char *) "NOBREAK",
4929 (char *) "NOBREAK",
4930 sys_set_break,
4931 sys_show_break,
4932 NULL,
4933 NULL,
4934 },
4935 MTAB_eol
4936 };
4937
4938 static t_stat sys_reset (UNUSED DEVICE * dptr)
4939 {
4940 return SCPE_OK;
4941 }
4942
4943 static DEVICE sys_dev = {
4944 "SYS",
4945 NULL,
4946 NULL,
4947 sys_mod,
4948 0,
4949 8,
4950 PASIZE,
4951 1,
4952 8,
4953 36,
4954 NULL,
4955 NULL,
4956 & sys_reset,
4957 NULL,
4958 NULL,
4959 NULL,
4960 NULL,
4961 0,
4962 0,
4963 0,
4964 NULL,
4965 NULL,
4966 NULL,
4967 NULL,
4968 NULL,
4969 NULL,
4970 NULL
4971 };
4972
4973
4974 DEVICE * sim_devices[] =
4975 {
4976 & cpu_dev,
4977 & iom_dev,
4978 & tape_dev,
4979 #if defined(WITH_SOCKET_DEV)
4980 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW32) && !defined(CROSS_MINGW64)
4981 & skc_dev,
4982 # endif
4983 #endif
4984 & mtp_dev,
4985 & fnp_dev,
4986 & dsk_dev,
4987 & ipc_dev,
4988 & msp_dev,
4989 & scu_dev,
4990 & opc_dev,
4991 & sys_dev,
4992 & urp_dev,
4993 & rdr_dev,
4994 & pun_dev,
4995 & prt_dev,
4996
4997 #if defined(WITH_ABSI_DEV)
4998 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW32) && !defined(CROSS_MINGW64)
4999 & absi_dev,
5000 # endif
5001 #endif
5002
5003 #if defined(WITH_MGP_DEV)
5004 # if !defined(__MINGW64__) && !defined(__MINGW32__) && !defined(CROSS_MINGW32) && !defined(CROSS_MINGW64)
5005 & mgp_dev,
5006 # endif
5007 #endif
5008
5009 NULL
5010 };
5011
5012 #if defined(PERF_STRIP)
5013 void dps8_init_strip (void)
5014 {
5015 dps8_init ();
5016 }
5017 #endif
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