root/src/dps8/dps8_cache.h

/* */

INCLUDED FROM

DEFINITIONS

1. cacheStoreNotify
2. cachePurgeAll
3. cache_read_lock
4. cache_write_unlock
5. cache_read
6. cache_read2
7. cache_readN
8. cache_write_zone
9. cache_write
10. cache_writeN
11. cache_write2

   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 384a80e6-df7a-11f1-9a7e-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2026 Charles Anthony
   9  * Copyright (c) 2026 Eric J. Swenson
  10  * Copyright (c) 2021-2026 The DPS8M Development Team
  11  *
  12  * This software is made available under the terms of the ICU License.
  13  * See the LICENSE.md file at the top-level directory of this distribution.
  14  *
  15  * ---------------------------------------------------------------------------
  16  */
  17 
  18 //-V::536
  19 //-V::652
  20 
  21 #if !defined(DPS8_CACHE_H)
  22 # define DPS8_CACHE_H
  23 
  24 // mask off the low 2 bits of a word24 address
  25 # define BLK_ADDR(ADDR) ((ADDR) & (word24) 077777774)
  26 
  27 void cacheReset (cpu_state_t * cpup);
  28 void cacheCpuReset (cpu_state_t * cpup);
  29 bool cacheConfigured (cpu_state_t * cpup);
  30 void cacheConfigChanged (cpu_state_t * cpup, bool was);
  31 void cacheUpdateAnyOn (void);
  32 void cacheClearStarted (cpu_state_t * cpup);
  33 void cacheInvalidate (cpu_state_t * cpup, word24 addr);
  34 void cachePurgeOthers (cpu_state_t * cpup, word24 addr);
  35 void cacheStoreNotifyOn (cpu_state_t * cpup, word24 addr, word36 data);
  36 void cacheStoreBadParity (cpu_state_t * cpup, word24 addr);
  37 void cachePurgeAllOn (word24 addr);
  38 void cacheStats (uint cpuNo);
  39 word36 cacheDirWord (cpu_state_t * cpup, word24 y);
  40 
  41 # if defined(LOCKLESS)
  42 int cache_read_lock_on (cpu_state_t * cpup, word24 addr, word36 *data, const char * ctx);
  43 # endif /* if defined(LOCKLESS) */
  44 int cache_read_on (cpu_state_t * cpup, word24 addr, word36 *data, const char * ctx);
  45 int cache_read2_on (cpu_state_t * cpup, word24 addr, word36 *even, word36 *odd, const char * ctx);
  46 void cache_writeN_on (cpu_state_t * cpup, word24 addr, word36 * data, uint n, const char * ctx);
  47 void cache_readN_on (cpu_state_t * cpup, word24 addr, word36 * data, uint n, const char * ctx);
  48 int cache_write2_on (cpu_state_t * cpup, word24 addr, word36 even, word36 odd, const char * ctx);
  49 
  50 // Is the cache model on in any CPU (enable_cache and enable_wam)?  Kept by
  51 // cacheUpdateAnyOn whenever a CPU's configuration changes and when the
  52 // simulation starts. While it is off (the default, and what Multics runs
  53 // with), the cache layer below goes straight to the core_* routines: the
  54 // memory path costs what it did before the cache model, and stores don't
  55 // look for other CPUs' caches to purge.
  56 # if defined(THREADZ) || defined(LOCKLESS)
  57 extern atomic_bool cacheAnyOn;
  58 #  define CACHE_ANY_ON() UNLIKELY (atomic_load_explicit (& cacheAnyOn, memory_order_relaxed))
  59 # else
  60 extern bool cacheAnyOn;
  61 #  define CACHE_ANY_ON() UNLIKELY (cacheAnyOn)
  62 # endif
  63 
  64 // This CPU stored DATA to real address ADDR: update its own cached copy and
  65 // purge the other CPUs' caches (see cacheStoreNotifyOn)
  66 static inline void cacheStoreNotify (cpu_state_t * cpup, word24 addr, word36 data) {
     /*  */
  67   if (CACHE_ANY_ON ())
  68     cacheStoreNotifyOn (cpup, addr, data);
  69 }
  70 
  71 // A store from outside the CPUs: purge every CPU's cache
  72 static inline void cachePurgeAll (word24 addr) {
     /*  */
  73   if (CACHE_ANY_ON ())
  74     cachePurgeAllOn (addr);
  75 }
  76 
  77 // The CPU's memory accesses. The instruction fetch sets the fetch flag
  78 // (cpu.cacheFetch) only while a cache is on.
  79 
  80 # if defined(LOCKLESS)
  81 static inline int cache_read_lock (cpu_state_t * cpup, word24 addr, word36 *data, const char * ctx) {
     /*  */
  82   if (! CACHE_ANY_ON ()) {
  83     return core_read_lock (cpup, addr, data, ctx);
  84   }
  85   return cache_read_lock_on (cpup, addr, data, ctx);
  86 }
  87 
  88 static inline int cache_write_unlock (cpu_state_t * cpup, word24 addr, word36 data, const char * ctx) {
     /*  */
  89   return core_write_unlock (cpup, addr, data, ctx);
  90 }
  91 # endif /* if defined(LOCKLESS) */
  92 
  93 static inline int cache_read (cpu_state_t * cpup, word24 addr, word36 *data, const char * ctx) {
     /*  */
  94   if (! CACHE_ANY_ON ()) {
  95     return core_read (cpup, addr, data, ctx);
  96   }
  97   return cache_read_on (cpup, addr, data, ctx);
  98 }
  99 
 100 static inline int cache_read2 (cpu_state_t * cpup, word24 addr, word36 *even, word36 *odd, const char * ctx) {
     /*  */
 101   if (! CACHE_ANY_ON ()) {
 102     return core_read2 (cpup, addr, even, odd, ctx);
 103   }
 104   return cache_read2_on (cpup, addr, even, odd, ctx);
 105 }
 106 
 107 static inline void cache_readN (cpu_state_t * cpup, word24 addr, word36 * data, uint n, const char * ctx) {
     /*  */
 108   if (! CACHE_ANY_ON ()) {
 109     core_readN (cpup, addr, data, n, ctx);
 110     return;
 111   }
 112   cache_readN_on (cpup, addr, data, n, ctx);
 113 }
 114 
 115 static inline int cache_write_zone (cpu_state_t * cpup, word24 addr, word36 data, const char * ctx) {
     /*  */
 116   return core_write_zone (cpup, addr, data, NULL, ctx);
 117 }
 118 
 119 static inline int cache_write (cpu_state_t * cpup, word24 addr, word36 data, const char * ctx) {
     /*  */
 120   return core_write (cpup, addr, data, ctx);
 121 }
 122 
 123 static inline void cache_writeN (cpu_state_t * cpup, word24 addr, word36 * data, uint n, const char * ctx) {
     /*  */
 124   if (! CACHE_ANY_ON ()) {
 125     core_writeN (cpup, addr, data, n, ctx);
 126     return;
 127   }
 128   cache_writeN_on (cpup, addr, data, n, ctx);
 129 }
 130 
 131 static inline int cache_write2 (cpu_state_t * cpup, word24 addr, word36 even, word36 odd, const char * ctx) {
     /*  */
 132   if (! CACHE_ANY_ON ())
 133     return core_write2 (cpup, addr, even, odd, ctx);
 134   return cache_write2_on (cpup, addr, even, odd, ctx);
 135 }
 136 
 137 #endif // !defined(DPS8_CACHE_H)

/* */