TPR 24 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) CA %06o\n", cpu.TPR.CA); TPR 27 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TPR 69 src/dps8/doAppendCycleABSA.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) TPR 74 src/dps8/doAppendCycleABSA.h if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) { TPR 76 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TPR 81 src/dps8/doAppendCycleABSA.h fetch_dsptw (cpup, cpu.TPR.TSR); TPR 87 src/dps8/doAppendCycleABSA.h modify_dsptw (cpup, cpu.TPR.TSR); TPR 89 src/dps8/doAppendCycleABSA.h fetch_psdw (cpup, cpu.TPR.TSR); TPR 91 src/dps8/doAppendCycleABSA.h fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table. TPR 94 src/dps8/doAppendCycleABSA.h load_sdwam (cpup, cpu.TPR.TSR, nomatch); TPR 140 src/dps8/doAppendCycleABSA.h if (cpu.TPR.TRR > cpu.SDW->R2) { TPR 151 src/dps8/doAppendCycleABSA.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 154 src/dps8/doAppendCycleABSA.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TPR 175 src/dps8/doAppendCycleABSA.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { TPR 183 src/dps8/doAppendCycleABSA.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); TPR 200 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(G) CA %06o\n", cpu.TPR.CA); TPR 201 src/dps8/doAppendCycleABSA.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { //TPR.CA)) TPR 202 src/dps8/doAppendCycleABSA.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 203 src/dps8/doAppendCycleABSA.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM TPR 213 src/dps8/doAppendCycleABSA.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); TPR 236 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); TPR 238 src/dps8/doAppendCycleABSA.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; TPR 242 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 252 src/dps8/doAppendCycleABSA.h word24 y2 = cpu.TPR.CA % 1024; TPR 264 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 275 src/dps8/doAppendCycleABSA.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) TPR 281 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TPR 22 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) CA %06o\n", cpu.TPR.CA); TPR 25 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TPR 73 src/dps8/doAppendCycleAPUDataRMW.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) TPR 78 src/dps8/doAppendCycleAPUDataRMW.h if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) { TPR 80 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TPR 85 src/dps8/doAppendCycleAPUDataRMW.h fetch_dsptw (cpup, cpu.TPR.TSR); TPR 91 src/dps8/doAppendCycleAPUDataRMW.h modify_dsptw (cpup, cpu.TPR.TSR); TPR 93 src/dps8/doAppendCycleAPUDataRMW.h fetch_psdw (cpup, cpu.TPR.TSR); TPR 95 src/dps8/doAppendCycleAPUDataRMW.h fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table. TPR 103 src/dps8/doAppendCycleAPUDataRMW.h load_sdwam (cpup, cpu.TPR.TSR, nomatch); TPR 154 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TRR > cpu.SDW->R2) { TPR 165 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 168 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TPR 186 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TSR == cpu.PPR.PSR) TPR 187 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 190 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TRR > cpu.SDW->R1) { TPR 191 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1); TPR 200 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 222 src/dps8/doAppendCycleAPUDataRMW.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { TPR 229 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); TPR 246 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(G) CA %06o\n", cpu.TPR.CA); TPR 247 src/dps8/doAppendCycleAPUDataRMW.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { TPR 248 src/dps8/doAppendCycleAPUDataRMW.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 253 src/dps8/doAppendCycleAPUDataRMW.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM TPR 263 src/dps8/doAppendCycleAPUDataRMW.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); TPR 288 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); TPR 290 src/dps8/doAppendCycleAPUDataRMW.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; TPR 294 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 304 src/dps8/doAppendCycleAPUDataRMW.h modify_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 310 src/dps8/doAppendCycleAPUDataRMW.h word24 y2 = cpu.TPR.CA % 1024; TPR 322 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 342 src/dps8/doAppendCycleAPUDataRMW.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) TPR 348 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TPR 22 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) CA %06o\n", cpu.TPR.CA); TPR 25 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TPR 74 src/dps8/doAppendCycleAPUDataRead.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) TPR 79 src/dps8/doAppendCycleAPUDataRead.h if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) { TPR 81 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TPR 86 src/dps8/doAppendCycleAPUDataRead.h fetch_dsptw (cpup, cpu.TPR.TSR); TPR 92 src/dps8/doAppendCycleAPUDataRead.h modify_dsptw (cpup, cpu.TPR.TSR); TPR 94 src/dps8/doAppendCycleAPUDataRead.h fetch_psdw (cpup, cpu.TPR.TSR); TPR 96 src/dps8/doAppendCycleAPUDataRead.h fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table. TPR 104 src/dps8/doAppendCycleAPUDataRead.h load_sdwam (cpup, cpu.TPR.TSR, nomatch); TPR 149 src/dps8/doAppendCycleAPUDataRead.h if (cpu.TPR.TRR > cpu.SDW->R2) { TPR 160 src/dps8/doAppendCycleAPUDataRead.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 163 src/dps8/doAppendCycleAPUDataRead.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TPR 184 src/dps8/doAppendCycleAPUDataRead.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { TPR 191 src/dps8/doAppendCycleAPUDataRead.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); TPR 208 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(G) CA %06o\n", cpu.TPR.CA); TPR 209 src/dps8/doAppendCycleAPUDataRead.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { TPR 210 src/dps8/doAppendCycleAPUDataRead.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 214 src/dps8/doAppendCycleAPUDataRead.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM TPR 224 src/dps8/doAppendCycleAPUDataRead.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); TPR 248 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); TPR 250 src/dps8/doAppendCycleAPUDataRead.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; TPR 254 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 268 src/dps8/doAppendCycleAPUDataRead.h word24 y2 = cpu.TPR.CA % 1024; TPR 280 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 293 src/dps8/doAppendCycleAPUDataRead.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) TPR 299 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TPR 22 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) CA %06o\n", cpu.TPR.CA); TPR 25 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TPR 72 src/dps8/doAppendCycleAPUDataStore.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) TPR 77 src/dps8/doAppendCycleAPUDataStore.h if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) { TPR 79 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TPR 84 src/dps8/doAppendCycleAPUDataStore.h fetch_dsptw (cpup, cpu.TPR.TSR); TPR 90 src/dps8/doAppendCycleAPUDataStore.h modify_dsptw (cpup, cpu.TPR.TSR); TPR 92 src/dps8/doAppendCycleAPUDataStore.h fetch_psdw (cpup, cpu.TPR.TSR); TPR 94 src/dps8/doAppendCycleAPUDataStore.h fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table. TPR 102 src/dps8/doAppendCycleAPUDataStore.h load_sdwam (cpup, cpu.TPR.TSR, nomatch); TPR 151 src/dps8/doAppendCycleAPUDataStore.h if (cpu.TPR.TSR == cpu.PPR.PSR) TPR 152 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 155 src/dps8/doAppendCycleAPUDataStore.h if (cpu.TPR.TRR > cpu.SDW->R1) { TPR 156 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1); TPR 165 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 183 src/dps8/doAppendCycleAPUDataStore.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { TPR 190 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); TPR 207 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(G) CA %06o\n", cpu.TPR.CA); TPR 208 src/dps8/doAppendCycleAPUDataStore.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { TPR 209 src/dps8/doAppendCycleAPUDataStore.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 214 src/dps8/doAppendCycleAPUDataStore.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM TPR 224 src/dps8/doAppendCycleAPUDataStore.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); TPR 248 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); TPR 250 src/dps8/doAppendCycleAPUDataStore.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; TPR 254 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 264 src/dps8/doAppendCycleAPUDataStore.h modify_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 270 src/dps8/doAppendCycleAPUDataStore.h word24 y2 = cpu.TPR.CA % 1024; TPR 282 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 295 src/dps8/doAppendCycleAPUDataStore.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) TPR 301 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TPR 58 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) CA %06o\n", cpu.TPR.CA); TPR 61 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TPR 94 src/dps8/doAppendCycleIndirectWordFetch.h if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) TPR 98 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); TPR 100 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = pageAddress + cpu.TPR.CA; TPR 165 src/dps8/doAppendCycleIndirectWordFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) TPR 170 src/dps8/doAppendCycleIndirectWordFetch.h if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) { TPR 172 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TPR 176 src/dps8/doAppendCycleIndirectWordFetch.h fetch_dsptw (cpup, cpu.TPR.TSR); TPR 182 src/dps8/doAppendCycleIndirectWordFetch.h modify_dsptw (cpup, cpu.TPR.TSR); TPR 184 src/dps8/doAppendCycleIndirectWordFetch.h fetch_psdw (cpup, cpu.TPR.TSR); TPR 186 src/dps8/doAppendCycleIndirectWordFetch.h fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table. TPR 194 src/dps8/doAppendCycleIndirectWordFetch.h load_sdwam (cpup, cpu.TPR.TSR, nomatch); TPR 245 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.TPR.TRR > cpu.SDW->R2) { TPR 256 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 259 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TPR 285 src/dps8/doAppendCycleIndirectWordFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { TPR 292 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); TPR 311 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(G) CA %06o\n", cpu.TPR.CA); TPR 313 src/dps8/doAppendCycleIndirectWordFetch.h ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { TPR 314 src/dps8/doAppendCycleIndirectWordFetch.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 319 src/dps8/doAppendCycleIndirectWordFetch.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM TPR 329 src/dps8/doAppendCycleIndirectWordFetch.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); TPR 355 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); TPR 358 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; TPR 362 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 378 src/dps8/doAppendCycleIndirectWordFetch.h word24 y2 = cpu.TPR.CA % 1024; TPR 391 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 398 src/dps8/doAppendCycleIndirectWordFetch.h ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); TPR 418 src/dps8/doAppendCycleIndirectWordFetch.h if ((GET_TM (tag) == TM_IR || GET_TM (tag) == TM_RI) && (cpu.TPR.CA & 1) == 0) { TPR 437 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR, cpu.RSDWH_R1, its_RNR); TPR 441 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = max3 (its_RNR, cpu.TPR.TRR, cpu.RSDWH_R1); TPR 442 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(O) Set TRR to %o\n", cpu.TPR.TRR); TPR 452 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR, cpu.RSDWH_R1, cpu.PR[n].RNR); TPR 456 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.TPR.TRR, cpu.RSDWH_R1); TPR 457 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(P) Set TRR to %o\n", cpu.TPR.TRR); TPR 463 src/dps8/doAppendCycleIndirectWordFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) TPR 471 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TPR 69 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) CA %06o\n", cpu.TPR.CA); TPR 72 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TPR 148 src/dps8/doAppendCycleInstructionFetch.h ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); TPR 151 src/dps8/doAppendCycleInstructionFetch.h if (! ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) TPR 156 src/dps8/doAppendCycleInstructionFetch.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); TPR 158 src/dps8/doAppendCycleInstructionFetch.h finalAddress = pageAddress + cpu.TPR.CA; TPR 216 src/dps8/doAppendCycleInstructionFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) TPR 221 src/dps8/doAppendCycleInstructionFetch.h if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) { TPR 223 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TPR 228 src/dps8/doAppendCycleInstructionFetch.h fetch_dsptw (cpup, cpu.TPR.TSR); TPR 234 src/dps8/doAppendCycleInstructionFetch.h modify_dsptw (cpup, cpu.TPR.TSR); TPR 236 src/dps8/doAppendCycleInstructionFetch.h fetch_psdw (cpup, cpu.TPR.TSR); TPR 238 src/dps8/doAppendCycleInstructionFetch.h fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table. TPR 246 src/dps8/doAppendCycleInstructionFetch.h load_sdwam (cpup, cpu.TPR.TSR, nomatch); TPR 312 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) { TPR 314 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(C) ACV1 ! ( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TPR 329 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR > cpu.PPR.PRR) TPR 330 src/dps8/doAppendCycleInstructionFetch.h sim_warn ("rtcd: outbound call cpu.TPR.TRR %d cpu.PPR.PRR %d\n", cpu.TPR.TRR, cpu.PPR.PRR); TPR 332 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.PPR.PRR) { TPR 377 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) { TPR 379 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TPR 394 src/dps8/doAppendCycleInstructionFetch.h if (cpu.PPR.PRR != cpu.TPR.TRR) { TPR 416 src/dps8/doAppendCycleInstructionFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { TPR 423 src/dps8/doAppendCycleInstructionFetch.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); TPR 442 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(G) CA %06o\n", cpu.TPR.CA); TPR 444 src/dps8/doAppendCycleInstructionFetch.h ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { TPR 445 src/dps8/doAppendCycleInstructionFetch.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 450 src/dps8/doAppendCycleInstructionFetch.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM TPR 462 src/dps8/doAppendCycleInstructionFetch.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); TPR 488 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); TPR 491 src/dps8/doAppendCycleInstructionFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; TPR 495 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 511 src/dps8/doAppendCycleInstructionFetch.h word24 y2 = cpu.TPR.CA % 1024; TPR 524 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 552 src/dps8/doAppendCycleInstructionFetch.h sim_printf ("ins fetch err %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TPR 557 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TPR 562 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TPR 577 src/dps8/doAppendCycleInstructionFetch.h ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); TPR 615 src/dps8/doAppendCycleInstructionFetch.h cpu.PR[7].RNR = cpu.TPR.TRR; TPR 633 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.PSR = cpu.TPR.TSR; TPR 635 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.IC = cpu.TPR.CA; TPR 643 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR == 0) { TPR 652 src/dps8/doAppendCycleInstructionFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) TPR 660 src/dps8/doAppendCycleInstructionFetch.h cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TPR 22 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) CA %06o\n", cpu.TPR.CA); TPR 25 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TPR 74 src/dps8/doAppendCycleOperandRMW.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) TPR 79 src/dps8/doAppendCycleOperandRMW.h if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) { TPR 81 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TPR 85 src/dps8/doAppendCycleOperandRMW.h fetch_dsptw (cpup, cpu.TPR.TSR); TPR 91 src/dps8/doAppendCycleOperandRMW.h modify_dsptw (cpup, cpu.TPR.TSR); TPR 93 src/dps8/doAppendCycleOperandRMW.h fetch_psdw (cpup, cpu.TPR.TSR); TPR 95 src/dps8/doAppendCycleOperandRMW.h fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table. TPR 103 src/dps8/doAppendCycleOperandRMW.h load_sdwam (cpup, cpu.TPR.TSR, nomatch); TPR 154 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TRR > cpu.SDW->R2) { TPR 165 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 168 src/dps8/doAppendCycleOperandRMW.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TPR 186 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TSR == cpu.PPR.PSR) TPR 187 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 190 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TRR > cpu.SDW->R1) { TPR 191 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1); TPR 200 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 222 src/dps8/doAppendCycleOperandRMW.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { TPR 229 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); TPR 246 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(G) CA %06o\n", cpu.TPR.CA); TPR 247 src/dps8/doAppendCycleOperandRMW.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { TPR 248 src/dps8/doAppendCycleOperandRMW.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 253 src/dps8/doAppendCycleOperandRMW.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM TPR 263 src/dps8/doAppendCycleOperandRMW.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); TPR 286 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); TPR 288 src/dps8/doAppendCycleOperandRMW.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; TPR 292 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 302 src/dps8/doAppendCycleOperandRMW.h modify_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 308 src/dps8/doAppendCycleOperandRMW.h word24 y2 = cpu.TPR.CA % 1024; TPR 320 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 346 src/dps8/doAppendCycleOperandRMW.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) TPR 352 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TPR 64 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) CA %06o\n", cpu.TPR.CA); TPR 67 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TPR 135 src/dps8/doAppendCycleOperandRead.h ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); TPR 138 src/dps8/doAppendCycleOperandRead.h cacheHit ? "hit" : "miss", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, cachedBound, TPR 143 src/dps8/doAppendCycleOperandRead.h if (! ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) { TPR 145 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TPR 152 src/dps8/doAppendCycleOperandRead.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); TPR 154 src/dps8/doAppendCycleOperandRead.h finalAddress = pageAddress + cpu.TPR.CA; TPR 161 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TPR 171 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "skip %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); TPR 229 src/dps8/doAppendCycleOperandRead.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) TPR 234 src/dps8/doAppendCycleOperandRead.h if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) { TPR 236 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TPR 240 src/dps8/doAppendCycleOperandRead.h fetch_dsptw (cpup, cpu.TPR.TSR); TPR 246 src/dps8/doAppendCycleOperandRead.h modify_dsptw (cpup, cpu.TPR.TSR); TPR 248 src/dps8/doAppendCycleOperandRead.h fetch_psdw (cpup, cpu.TPR.TSR); TPR 250 src/dps8/doAppendCycleOperandRead.h fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table. TPR 258 src/dps8/doAppendCycleOperandRead.h load_sdwam (cpup, cpu.TPR.TSR, nomatch); TPR 317 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.SDW->R2) { TPR 328 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 331 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TPR 387 src/dps8/doAppendCycleOperandRead.h cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu.SDW->EB, TPR 388 src/dps8/doAppendCycleOperandRead.h cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.TPR.TRR, cpu.PPR.PRR); TPR 405 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS) TPR 411 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.CA >= (word18) cpu.SDW->EB) { TPR 424 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.SDW->R3) { TPR 434 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR < cpu.SDW->R1) { TPR 444 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.PPR.PRR) { TPR 456 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o SDW->R2 %o\n", cpu.TPR.TRR, cpu.SDW->R2); TPR 459 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.SDW->R2) { TPR 461 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TRR = cpu.SDW->R2; TPR 464 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o\n", cpu.TPR.TRR); TPR 484 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) { TPR 486 src/dps8/doAppendCycleOperandRead.h DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TPR 501 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PRR != cpu.TPR.TRR) { TPR 523 src/dps8/doAppendCycleOperandRead.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { TPR 530 src/dps8/doAppendCycleOperandRead.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); TPR 550 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(G) CA %06o\n", cpu.TPR.CA); TPR 552 src/dps8/doAppendCycleOperandRead.h ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { TPR 553 src/dps8/doAppendCycleOperandRead.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 559 src/dps8/doAppendCycleOperandRead.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM TPR 569 src/dps8/doAppendCycleOperandRead.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); TPR 597 src/dps8/doAppendCycleOperandRead.h cpu.SDW->ADDR, cpu.TPR.CA); TPR 600 src/dps8/doAppendCycleOperandRead.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; TPR 605 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 624 src/dps8/doAppendCycleOperandRead.h word24 y2 = cpu.TPR.CA % 1024; TPR 638 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 673 src/dps8/doAppendCycleOperandRead.h evcnt, cpu.TPR.TSR, cpu.TPR.CA); TPR 679 src/dps8/doAppendCycleOperandRead.h evcnt, cpu.TPR.TSR, cpu.TPR.CA); TPR 685 src/dps8/doAppendCycleOperandRead.h evcnt, cpu.TPR.TSR, cpu.TPR.CA); TPR 690 src/dps8/doAppendCycleOperandRead.h ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); TPR 694 src/dps8/doAppendCycleOperandRead.h evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); TPR 753 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PSR = cpu.TPR.TSR; TPR 755 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; TPR 763 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR == 0) { TPR 777 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR == cpu.PPR.PRR) { TPR 783 src/dps8/doAppendCycleOperandRead.h cpu.PR[7].SNR = ((word15) (cpu.DSBR.STACK << 3)) | cpu.TPR.TRR; TPR 784 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(N) STACK %05o TRR %o\n", cpu.DSBR.STACK, cpu.TPR.TRR); TPR 789 src/dps8/doAppendCycleOperandRead.h cpu.PR[7].RNR = cpu.TPR.TRR; TPR 798 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PRR = cpu.TPR.TRR; TPR 800 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PSR = cpu.TPR.TSR; TPR 802 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; TPR 808 src/dps8/doAppendCycleOperandRead.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) TPR 814 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TPR 22 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) CA %06o\n", cpu.TPR.CA); TPR 25 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TPR 73 src/dps8/doAppendCycleOperandStore.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) TPR 78 src/dps8/doAppendCycleOperandStore.h if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) { TPR 80 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TPR 85 src/dps8/doAppendCycleOperandStore.h fetch_dsptw (cpup, cpu.TPR.TSR); TPR 91 src/dps8/doAppendCycleOperandStore.h modify_dsptw (cpup, cpu.TPR.TSR); TPR 93 src/dps8/doAppendCycleOperandStore.h fetch_psdw (cpup, cpu.TPR.TSR); TPR 95 src/dps8/doAppendCycleOperandStore.h fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table. TPR 103 src/dps8/doAppendCycleOperandStore.h load_sdwam (cpup, cpu.TPR.TSR, nomatch); TPR 146 src/dps8/doAppendCycleOperandStore.h if (cpu.TPR.TSR == cpu.PPR.PSR) TPR 147 src/dps8/doAppendCycleOperandStore.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 150 src/dps8/doAppendCycleOperandStore.h if (cpu.TPR.TRR > cpu.SDW->R1) { TPR 151 src/dps8/doAppendCycleOperandStore.h DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1); TPR 160 src/dps8/doAppendCycleOperandStore.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 182 src/dps8/doAppendCycleOperandStore.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { TPR 189 src/dps8/doAppendCycleOperandStore.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); TPR 206 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(G) CA %06o\n", cpu.TPR.CA); TPR 207 src/dps8/doAppendCycleOperandStore.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { TPR 208 src/dps8/doAppendCycleOperandStore.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 213 src/dps8/doAppendCycleOperandStore.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM TPR 223 src/dps8/doAppendCycleOperandStore.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); TPR 246 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); TPR 248 src/dps8/doAppendCycleOperandStore.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; TPR 252 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 262 src/dps8/doAppendCycleOperandStore.h modify_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 268 src/dps8/doAppendCycleOperandStore.h word24 y2 = cpu.TPR.CA % 1024; TPR 280 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 298 src/dps8/doAppendCycleOperandStore.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) TPR 304 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TPR 22 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) CA %06o\n", cpu.TPR.CA); TPR 25 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); TPR 85 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TSR = 0; TPR 86 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("RTCD_OPERAND_FETCH ABSOLUTE mode set TSR %05o TRR %o\n", cpu.TPR.TSR, cpu.TPR.TRR); TPR 104 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) TPR 109 src/dps8/doAppendCycleRTCDOperandFetch.h if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) { TPR 111 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); TPR 115 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_dsptw (cpup, cpu.TPR.TSR); TPR 121 src/dps8/doAppendCycleRTCDOperandFetch.h modify_dsptw (cpup, cpu.TPR.TSR); TPR 123 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_psdw (cpup, cpu.TPR.TSR); TPR 125 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table. TPR 133 src/dps8/doAppendCycleRTCDOperandFetch.h load_sdwam (cpup, cpu.TPR.TSR, nomatch); TPR 178 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.TPR.TRR > cpu.SDW->R2) { TPR 189 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TRR = cpu.PPR.PRR; TPR 192 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.PPR.PSR != cpu.TPR.TSR) { TPR 217 src/dps8/doAppendCycleRTCDOperandFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { TPR 224 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); TPR 241 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(G) CA %06o\n", cpu.TPR.CA); TPR 242 src/dps8/doAppendCycleRTCDOperandFetch.h if (nomatch || ! fetch_ptw_from_ptwam (cpup, cpu.SDW->POINTER, cpu.TPR.CA)) { TPR 243 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_ptw (cpup, cpu.SDW, cpu.TPR.CA); TPR 248 src/dps8/doAppendCycleRTCDOperandFetch.h loadPTWAM (cpup, cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM TPR 258 src/dps8/doAppendCycleRTCDOperandFetch.h do_ptw2 (cpup, cpu.SDW, cpu.TPR.CA); TPR 281 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); TPR 284 src/dps8/doAppendCycleRTCDOperandFetch.h finalAddress = cpu.TPR.CA; TPR 286 src/dps8/doAppendCycleRTCDOperandFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; TPR 291 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 305 src/dps8/doAppendCycleRTCDOperandFetch.h word24 y2 = cpu.TPR.CA % 1024; TPR 317 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 345 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TSR = GET_ITS_SEGNO (data); TPR 350 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1); TPR 354 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.CA = GET_ITS_WORDNO (data); TPR 364 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PSR = cpu.TPR.TSR; TPR 366 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.IC = cpu.TPR.CA; TPR 374 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.TPR.TRR == 0) { TPR 384 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) TPR 392 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TPR 221 src/dps8/dps8_addrmods.c cpu.TPR.TSR = cpu.PR[n].SNR; TPR 222 src/dps8/dps8_addrmods.c cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.RSDWH_R1, cpu.TPR.TRR); TPR 223 src/dps8/dps8_addrmods.c cpu.TPR.TBR = GET_ITP_BITNO (cpu.itxPair); TPR 224 src/dps8/dps8_addrmods.c cpu.TPR.CA = cpu.PAR[n].WORDNO + GET_ITP_WORDNO (cpu.itxPair); TPR 225 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; TPR 226 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; TPR 257 src/dps8/dps8_addrmods.c cpu.TPR.TSR = GET_ITS_SEGNO (cpu.itxPair); TPR 261 src/dps8/dps8_addrmods.c GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR, TPR 262 src/dps8/dps8_addrmods.c max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR)); TPR 264 src/dps8/dps8_addrmods.c cpu.TPR.TRR = max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR); TPR 265 src/dps8/dps8_addrmods.c cpu.TPR.TBR = GET_ITS_BITNO (cpu.itxPair); TPR 266 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ITS_WORDNO (cpu.itxPair); TPR 267 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; TPR 269 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; TPR 361 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ADDR (IWB_IRODD); TPR 370 src/dps8/dps8_addrmods.c cpu.TPR.CA = (cpu.PAR[n].WORDNO + SIGNEXT15_18 (offset)) TPR 376 src/dps8/dps8_addrmods.c __func__, op_desc_str (cpup, buf), cpu.TPR.CA); TPR 419 src/dps8/dps8_addrmods.c cpu.cu.pot == 1 && GET_ADDR (IWB_IRODD) == cpu.TPR.CA) TPR 421 src/dps8/dps8_addrmods.c cpu.TPR.CA--; TPR 491 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO; TPR 492 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; TPR 496 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr; TPR 501 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; TPR 502 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits TPR 505 src/dps8/dps8_addrmods.c cpu.TPR.CA); TPR 527 src/dps8/dps8_addrmods.c "RI_MOD: Cr=%06o CA(Before)=%06o\n", Cr, cpu.TPR.CA); TPR 538 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO; TPR 542 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr; TPR 544 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; TPR 548 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; TPR 549 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits TPR 552 src/dps8/dps8_addrmods.c "RI_MOD: CA(After)=%06o\n", cpu.TPR.CA); TPR 566 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; TPR 572 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); TPR 600 src/dps8/dps8_addrmods.c cpu.TPR.CA = GETHI (cpu.itxPair[0]); TPR 601 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; TPR 613 src/dps8/dps8_addrmods.c cpu.itxPair[0], cpu.TPR.CA, cpu.rTAG); TPR 640 src/dps8/dps8_addrmods.c cpu.TPR.CA); TPR 642 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; TPR 662 src/dps8/dps8_addrmods.c cpu.TPR.CA = GETHI (cpu.itxPair[0]); TPR 663 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; TPR 675 src/dps8/dps8_addrmods.c cpu.itxPair[0], cpu.TPR.CA, Tm, Td, TPR 688 src/dps8/dps8_addrmods.c updateIWB(cpup, cpu.TPR.CA, cpu.rTAG); TPR 693 src/dps8/dps8_addrmods.c cpu.TPR.CA = saveCA; TPR 698 src/dps8/dps8_addrmods.c cpu.TPR.CA = saveCA; TPR 720 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); TPR 734 src/dps8/dps8_addrmods.c Td, Cr, cpu.TPR.CA); TPR 736 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; TPR 737 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits TPR 740 src/dps8/dps8_addrmods.c "IR_MOD(TM_RI): TPR.CA=%06o\n", cpu.TPR.CA); TPR 744 src/dps8/dps8_addrmods.c cpu.TPR.CA); TPR 747 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_RI|TD_N)); TPR 753 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); // XXX guessing here... TPR 832 src/dps8/dps8_addrmods.c cpu.TPR.CA); TPR 839 src/dps8/dps8_addrmods.c word18 indaddr = cpu.TPR.CA; TPR 873 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; TPR 921 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; TPR 944 src/dps8/dps8_addrmods.c Read (cpu.TPR.CA, & cpu.ou.character_data, (i->info->flags & RMW) == \ TPR 947 src/dps8/dps8_addrmods.c ReadOperandRead (cpup, cpu.TPR.CA, & cpu.ou.character_data); TPR 1019 src/dps8/dps8_addrmods.c indword, cpu.TPR.CA); TPR 1024 src/dps8/dps8_addrmods.c cpu.TPR.CA = cpu.ou.character_address; TPR 1032 src/dps8/dps8_addrmods.c cpu.TPR.CA); TPR 1041 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ADDR (cpu.itxPair[0]); TPR 1042 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); TPR 1060 src/dps8/dps8_addrmods.c cpu.TPR.CA); TPR 1066 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; TPR 1068 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); TPR 1082 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; TPR 1083 src/dps8/dps8_addrmods.c word18 computedAddress = cpu.TPR.CA; TPR 1112 src/dps8/dps8_addrmods.c cpu.TPR.CA = computedAddress; TPR 1113 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); TPR 1133 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; TPR 1135 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); TPR 1139 src/dps8/dps8_addrmods.c cpu.TPR.CA); TPR 1154 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; TPR 1180 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; TPR 1181 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); TPR 1198 src/dps8/dps8_addrmods.c cpu.TPR.CA); TPR 1204 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; TPR 1206 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); TPR 1221 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; TPR 1229 src/dps8/dps8_addrmods.c indword = (word36) (((word36) cpu.TPR.CA << 18) | TPR 1247 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; TPR 1248 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); TPR 1263 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; TPR 1267 src/dps8/dps8_addrmods.c cpu.TPR.CA); TPR 1274 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); TPR 1285 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; TPR 1286 src/dps8/dps8_addrmods.c word18 computedAddress = cpu.TPR.CA; TPR 1319 src/dps8/dps8_addrmods.c cpu.TPR.CA = computedAddress; TPR 1320 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, (TM_R|TD_N)); TPR 1349 src/dps8/dps8_addrmods.c cpu.TPR.CA); TPR 1355 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; TPR 1357 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); TPR 1408 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; TPR 1432 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); TPR 1461 src/dps8/dps8_addrmods.c cpu.TPR.CA); TPR 1467 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; TPR 1469 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpup, cpu.TPR.CA, & indword); TPR 1522 src/dps8/dps8_addrmods.c cpu.TPR.CA = YiSafe; TPR 1543 src/dps8/dps8_addrmods.c updateIWB (cpup, cpu.TPR.CA, cpu.rTAG); TPR 1200 src/dps8/dps8_append.c cpu.TPR.CA); TPR 1206 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.TPR.TSR); TPR 1274 src/dps8/dps8_append.c cpu.TPR.TSR = 0; TPR 1276 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.TRR); TPR 1294 src/dps8/dps8_append.c PNL (cpu.APUMemAddr = cpu.TPR.CA;) TPR 1299 src/dps8/dps8_append.c if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) TPR 1303 src/dps8/dps8_append.c cpu.TPR.TSR); TPR 1310 src/dps8/dps8_append.c fetch_dsptw (cpu.TPR.TSR); TPR 1317 src/dps8/dps8_append.c modify_dsptw (cpu.TPR.TSR); TPR 1319 src/dps8/dps8_append.c fetch_psdw (cpu.TPR.TSR); TPR 1322 src/dps8/dps8_append.c fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. TPR 1335 src/dps8/dps8_append.c load_sdwam (cpu.TPR.TSR, nomatch); TPR 1428 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R2) TPR 1441 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1444 src/dps8/dps8_append.c if (cpu.PPR.PSR != cpu.TPR.TSR) TPR 1474 src/dps8/dps8_append.c if (cpu.TPR.TSR == cpu.PPR.PSR) TPR 1475 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1478 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R1) TPR 1481 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.SDW->R1); TPR 1491 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1520 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.SDW->R1 || TPR 1521 src/dps8/dps8_append.c cpu.TPR.TRR > cpu.SDW->R2) TPR 1525 src/dps8/dps8_append.c cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TPR 1541 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.PPR.PRR) TPR 1543 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.PPR.PRR); TPR 1545 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.PPR.PRR) TPR 1594 src/dps8/dps8_append.c cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, TPR 1596 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.PPR.PRR); TPR 1614 src/dps8/dps8_append.c if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS) TPR 1620 src/dps8/dps8_append.c if (cpu.TPR.CA >= (word18) cpu.SDW->EB) TPR 1634 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R3) TPR 1645 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.SDW->R1) TPR 1656 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.PPR.PRR) TPR 1672 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.SDW->R2); TPR 1675 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R2) TPR 1678 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.SDW->R2; TPR 1681 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(E1): CALL6 TPR.TRR %o\n", cpu.TPR.TRR); TPR 1701 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.SDW->R1 || TPR 1702 src/dps8/dps8_append.c cpu.TPR.TRR > cpu.SDW->R2) TPR 1706 src/dps8/dps8_append.c cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); TPR 1722 src/dps8/dps8_append.c if (cpu.PPR.PRR != cpu.TPR.TRR) TPR 1745 src/dps8/dps8_append.c if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) TPR 1754 src/dps8/dps8_append.c cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); TPR 1773 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(G) CA %06o\n", cpu.TPR.CA); TPR 1775 src/dps8/dps8_append.c ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) //TPR.CA)) TPR 1777 src/dps8/dps8_append.c fetch_ptw (cpu.SDW, cpu.TPR.CA); TPR 1787 src/dps8/dps8_append.c loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM TPR 1798 src/dps8/dps8_append.c do_ptw2 (cpu.SDW, cpu.TPR.CA); TPR 1824 src/dps8/dps8_append.c cpu.SDW->ADDR, cpu.TPR.CA); TPR 1830 src/dps8/dps8_append.c finalAddress = cpu.TPR.CA; TPR 1834 src/dps8/dps8_append.c finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; TPR 1840 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 1859 src/dps8/dps8_append.c modify_ptw (cpu.SDW, cpu.TPR.CA); TPR 1866 src/dps8/dps8_append.c word24 y2 = cpu.TPR.CA % 1024; TPR 1878 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.CA, finalAddress); TPR 1956 src/dps8/dps8_append.c (cpu.TPR.CA & 1) == 0) TPR 2024 src/dps8/dps8_append.c cpu.TPR.TSR = GET_ITS_SEGNO (data); TPR 2029 src/dps8/dps8_append.c cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1); TPR 2033 src/dps8/dps8_append.c cpu.TPR.CA = GET_ITS_WORDNO (data); TPR 2092 src/dps8/dps8_append.c cpu.PR[7].RNR = cpu.TPR.TRR; TPR 2110 src/dps8/dps8_append.c cpu.PPR.PSR = cpu.TPR.TSR; TPR 2112 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; TPR 2120 src/dps8/dps8_append.c if (cpu.TPR.TRR == 0) TPR 2137 src/dps8/dps8_append.c if (cpu.TPR.TRR == cpu.PPR.PRR) TPR 2146 src/dps8/dps8_append.c cpu.PR[7].SNR = ((word15) (cpu.DSBR.STACK << 3)) | cpu.TPR.TRR; TPR 2148 src/dps8/dps8_append.c cpu.DSBR.STACK, cpu.TPR.TRR); TPR 2153 src/dps8/dps8_append.c cpu.PR[7].RNR = cpu.TPR.TRR; TPR 2162 src/dps8/dps8_append.c cpu.PPR.PRR = cpu.TPR.TRR; TPR 2164 src/dps8/dps8_append.c cpu.PPR.PSR = cpu.TPR.TSR; TPR 2166 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; TPR 2180 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.RSDWH_R1, its_RNR); TPR 2184 src/dps8/dps8_append.c cpu.TPR.TRR = max3 (its_RNR, cpu.TPR.TRR, cpu.RSDWH_R1); TPR 2185 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(O) Set TRR to %o\n", cpu.TPR.TRR); TPR 2195 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.RSDWH_R1, cpu.PR[n].RNR); TPR 2199 src/dps8/dps8_append.c cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.TPR.TRR, cpu.RSDWH_R1); TPR 2200 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(P) Set TRR to %o\n", cpu.TPR.TRR); TPR 2206 src/dps8/dps8_append.c PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) TPR 2214 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); TPR 2575 src/dps8/dps8_cpu.c cpu.TPR.TRR = 0; TPR 2850 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 2851 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 2865 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 2866 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 2931 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 2932 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 3229 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 3230 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 3357 src/dps8/dps8_cpu.c cpu.TPR.TRR = 0; TPR 4423 src/dps8/dps8_cpu.c putbits36_18 (& w1, 0, cpu.TPR.CA); TPR 4619 src/dps8/dps8_cpu.c putbits36_15 (& w0, 0, cpu.TPR.TSR); TPR 4637 src/dps8/dps8_cpu.c putbits36_3 (& w1, 24, cpu.TPR.TRR); TPR 1683 src/dps8/dps8_cpu.h struct tpr_s TPR; // Temporary Pointer Register TPR 557 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; TPR 563 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; TPR 564 src/dps8/dps8_eis.c cpu.TPR.TSR = p -> SNR; TPR 577 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TPR 589 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 590 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 601 src/dps8/dps8_eis.c __func__, p -> cachedParagraph [i], cpu.TPR.TSR, p -> cachedAddr + i); TPR 605 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TPR 615 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; TPR 621 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; TPR 640 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; TPR 641 src/dps8/dps8_eis.c cpu.TPR.TSR = p -> SNR; TPR 644 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TPR 659 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 660 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 665 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } TPR 672 src/dps8/dps8_eis.c __func__, p -> cachedParagraph [i], cpu.TPR.TSR, paragraphAddress + i); TPR 680 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; TPR 799 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; TPR 803 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; TPR 804 src/dps8/dps8_eis.c cpu.TPR.TSR = p -> SNR; TPR 814 src/dps8/dps8_eis.c __func__, data [i], cpu.TPR.TSR, addressN + i); TPR 826 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 827 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 837 src/dps8/dps8_eis.c __func__, data [i], cpu.TPR.TSR, addressN + i); TPR 840 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; TPR 861 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; TPR 865 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; TPR 866 src/dps8/dps8_eis.c cpu.TPR.TSR = p -> SNR; TPR 876 src/dps8/dps8_eis.c __func__, data [i], cpu.TPR.TSR, addressN + i); TPR 888 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 889 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 899 src/dps8/dps8_eis.c __func__, data [i], cpu.TPR.TSR, addressN + i); TPR 902 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; TPR 1270 src/dps8/dps8_eis.c cpu.TPR.TRR, TPR 1419 src/dps8/dps8_eis.c e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TPR 1624 src/dps8/dps8_eis.c e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TPR 1676 src/dps8/dps8_eis.c e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TPR 1863 src/dps8/dps8_eis.c e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TPR 53 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 116 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); TPR 117 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 118 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 125 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read BAR"); TPR 126 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read BAR"); TPR 142 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read"); TPR 143 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read"); TPR 156 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 195 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 196 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 197 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 203 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRead BAR"); TPR 204 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead BAR"); TPR 215 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRead"); TPR 216 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead"); TPR 226 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 265 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 266 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 267 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 273 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "readOperandRead BAR"); TPR 274 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead BAR"); TPR 286 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "readOperandRead"); TPR 287 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead"); TPR 298 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 337 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 338 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 339 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 345 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadOperandRMW BAR"); TPR 346 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW BAR"); TPR 357 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadOperandRMW"); TPR 358 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW"); TPR 368 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 407 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 408 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 409 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 415 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRMW BAR"); TPR 416 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW BAR"); TPR 427 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRMW"); TPR 428 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW"); TPR 440 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 479 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 480 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 481 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 487 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadInstructionFetch BAR"); TPR 488 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch BAR"); TPR 499 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadInstructionFetch"); TPR 500 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch"); TPR 510 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 549 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 550 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 551 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 557 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch BAR"); TPR 558 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch BAR"); TPR 569 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch"); TPR 570 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch"); TPR 582 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 632 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 633 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 634 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 643 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR"); TPR 644 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn"); TPR 645 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd"); TPR 665 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2"); TPR 666 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn"); TPR 667 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd"); TPR 678 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 727 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 728 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 729 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 738 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRead BR"); TPR 739 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead BR evn"); TPR 740 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead BR odd"); TPR 758 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRead"); TPR 759 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead evn"); TPR 760 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead odd"); TPR 770 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 819 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 820 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 821 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 830 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRMW BR"); TPR 831 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW BR evn"); TPR 832 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW BR odd"); TPR 844 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRMW"); TPR 845 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW evn"); TPR 846 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW odd"); TPR 856 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 905 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 906 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 907 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 916 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2InstructionFetch BR"); TPR 917 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch BR evn"); TPR 918 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch BR odd"); TPR 930 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2InstructionFetch"); TPR 931 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch evn"); TPR 932 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch odd"); TPR 941 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 946 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 947 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 948 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 957 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR"); TPR 958 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn"); TPR 959 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd"); TPR 971 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2"); TPR 972 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn"); TPR 973 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd"); TPR 980 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 1029 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 1030 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 1031 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1040 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch BR"); TPR 1041 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch BR evn"); TPR 1042 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch BR odd"); TPR 1054 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch"); TPR 1055 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch evn"); TPR 1056 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch odd"); TPR 1067 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 1129 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 1130 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 1131 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1143 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read8 BAR"); TPR 1145 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result[i], "Read8 BAR"); TPR 1165 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read8"); TPR 1167 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "Read8"); TPR 1191 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 1253 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 1254 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 1255 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1267 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadPage B"); TPR 1269 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage B"); TPR 1290 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadPage"); TPR 1292 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage"); TPR 1303 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 1347 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 1348 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 1349 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1355 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write BR"); TPR 1356 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write BR"); TPR 1365 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write"); TPR 1366 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write"); TPR 1377 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 1417 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 1418 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 1419 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1425 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteAPUDataStore BR"); TPR 1426 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore BR"); TPR 1435 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteAPUDataStore"); TPR 1436 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore"); TPR 1445 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 1491 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 1492 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 1493 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1499 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteOperandStore BR"); TPR 1500 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore BR"); TPR 1509 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteOperandStore"); TPR 1510 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore"); TPR 1522 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 1573 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); TPR 1574 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 1575 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1582 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2 BR"); TPR 1583 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 BR evn"); TPR 1584 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 BR odd"); TPR 1596 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2"); TPR 1597 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 evn"); TPR 1598 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 odd"); TPR 1609 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 1650 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 1651 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 1652 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1658 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2OperandStore BR"); TPR 1659 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore BR evn"); TPR 1660 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore BR odd"); TPR 1669 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2OperandStore"); TPR 1670 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore evn"); TPR 1671 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore odd"); TPR 1682 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 1728 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 1729 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 1730 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1738 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write1 BR"); TPR 1739 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1 BR"); TPR 1752 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write1"); TPR 1753 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1"); TPR 1764 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 1823 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 1824 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 1825 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1837 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write8 BR"); TPR 1839 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8 BR"); TPR 1857 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write8"); TPR 1859 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8"); TPR 1893 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; TPR 1952 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (cpup, address); TPR 1953 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 1954 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1967 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WritePage BR"); TPR 1969 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage BR"); TPR 1986 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WritePage"); TPR 1988 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage"); TPR 1999 src/dps8/dps8_iefp.c if (cpu.TPR.CA & 1) // is odd? TPR 2001 src/dps8/dps8_iefp.c ReadIndirectWordFetch (cpup, cpu.TPR.CA, cpu.itxPair); TPR 2006 src/dps8/dps8_iefp.c Read2IndirectWordFetch (cpup, cpu.TPR.CA, cpu.itxPair); TPR 187 src/dps8/dps8_ins.c cpu.TPR.CA = cpu.ou.character_address; TPR 191 src/dps8/dps8_ins.c write_operand (cpup, cpu.TPR.CA, OPERAND_STORE); TPR 207 src/dps8/dps8_ins.c "%s a %d address %08o\n", __func__, i->b29, cpu.TPR.CA); TPR 224 src/dps8/dps8_ins.c SETHI (cpu.CY, cpu.TPR.CA); TPR 237 src/dps8/dps8_ins.c SETLO (cpu.CY, cpu.TPR.CA); TPR 270 src/dps8/dps8_ins.c cpu.TPR.CA = cpu.ou.character_address; TPR 276 src/dps8/dps8_ins.c readOperandRMW (cpup, cpu.TPR.CA); TPR 278 src/dps8/dps8_ins.c readOperandRead (cpup, cpu.TPR.CA); TPR 280 src/dps8/dps8_ins.c readOperandRead (cpup, cpu.TPR.CA); TPR 288 src/dps8/dps8_ins.c if (cpu.TPR.CA & 1) TPR 289 src/dps8/dps8_ins.c ReadOperandRead (cpup, cpu.TPR.CA, &cpu.CY); TPR 291 src/dps8/dps8_ins.c Read2OperandRead (cpup, cpu.TPR.CA, cpu.Ypair); TPR 318 src/dps8/dps8_ins.c cpu.PPR.IC = cpu.TPR.CA; TPR 417 src/dps8/dps8_ins.c putbits36_3 (& words[2], 0, cpu.TPR.TRR); TPR 418 src/dps8/dps8_ins.c putbits36_15 (& words[2], 3, cpu.TPR.TSR); TPR 433 src/dps8/dps8_ins.c putbits36_6 (& words[3], 30, cpu.TPR.TBR); TPR 479 src/dps8/dps8_ins.c putbits36 (& words[5], 0, 18, cpu.TPR.CA); TPR 693 src/dps8/dps8_ins.c cpu.TPR.TRR = getbits36_3 (words[2], 0); TPR 694 src/dps8/dps8_ins.c cpu.TPR.TSR = getbits36_15 (words[2], 3); TPR 711 src/dps8/dps8_ins.c cpu.TPR.TBR = getbits36_6 (words[3], 30); TPR 1153 src/dps8/dps8_ins.c cpu.TPR.TRR = 0; TPR 1835 src/dps8/dps8_ins.c "RPT/RPD CA %06o\n", cpu.TPR.CA); TPR 1867 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + offset) & AMASK; TPR 1868 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; TPR 1905 src/dps8/dps8_ins.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 1906 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 1955 src/dps8/dps8_ins.c cpu.TPR.TBR = GET_PR_BITNO (n); TPR 1957 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PAR[n].SNR; TPR 1959 src/dps8/dps8_ins.c cpu.TPR.TRR = max (cpu.PAR[n].RNR, cpu.PPR.PRR); TPR 1961 src/dps8/dps8_ins.c cpu.TPR.TRR = max3 (cpu.PAR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); TPR 1965 src/dps8/dps8_ins.c n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR); TPR 1980 src/dps8/dps8_ins.c cpu.TPR.TBR = 0; TPR 1982 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 1983 src/dps8/dps8_ins.c cpu.TPR.TRR = 0; TPR 2004 src/dps8/dps8_ins.c cpu.iefpFinalAddress = cpu.TPR.CA; TPR 2051 src/dps8/dps8_ins.c cpu.last_write = cpu.TPR.CA; TPR 2073 src/dps8/dps8_ins.c cpu.TPR.TRR = cpu.PPR.PRR; TPR 2074 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; TPR 2075 src/dps8/dps8_ins.c cpu.TPR.TBR = 0; TPR 2117 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; TPR 2118 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; TPR 2133 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; TPR 2134 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; TPR 2145 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; TPR 2146 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; TPR 2715 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.TPR.TRR; TPR 2716 src/dps8/dps8_ins.c cpu.PR[n].SNR = cpu.TPR.TSR; TPR 2717 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = cpu.TPR.CA; TPR 2718 src/dps8/dps8_ins.c SET_PR_BITNO (n, cpu.TPR.TBR); TPR 2893 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.TPR.TRR; TPR 2961 src/dps8/dps8_ins.c cpu.rX[n] = cpu.TPR.CA; TPR 2966 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); TPR 2967 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); TPR 3027 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.TPR.TRR; TPR 3028 src/dps8/dps8_ins.c cpu.PR[n].SNR = cpu.TPR.TSR; TPR 3159 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 TPR 3186 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 TPR 3213 src/dps8/dps8_ins.c Read2RTCDOperandFetch (cpup, cpu.TPR.CA, cpu.Ypair); TPR 3465 src/dps8/dps8_ins.c cpu.rA = cpu.TPR.TRR & MASK3; TPR 3466 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.TPR.TSR & MASK15) << 18; TPR 3471 src/dps8/dps8_ins.c cpu.rQ = cpu.TPR.TBR & MASK6; TPR 3472 src/dps8/dps8_ins.c cpu.rQ |= (word36) (cpu.TPR.CA & MASK18) << 18; TPR 3489 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 TPR 3515 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 TPR 3569 src/dps8/dps8_ins.c SETHI (cpu.rA, cpu.TPR.CA); TPR 3573 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); TPR 3574 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); TPR 3580 src/dps8/dps8_ins.c SETHI (cpu.rQ, cpu.TPR.CA); TPR 3585 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); TPR 3586 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); TPR 4079 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 TPR 4089 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 TPR 4119 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 TPR 4141 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 TPR 4159 src/dps8/dps8_ins.c word18 tmp18 = cpu.TPR.CA & 0177; // CY bits 11-17 TPR 4189 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 TPR 4204 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 TPR 4239 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 TPR 4284 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 TPR 4322 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 TPR 4353 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 TPR 4387 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 TPR 4424 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 TPR 4462 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 TPR 4472 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 TPR 4501 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 TPR 4525 src/dps8/dps8_ins.c uint cnt = (uint) cpu.TPR.CA & 0177; // 0-127 TPR 4543 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 TPR 6472 src/dps8/dps8_ins.c ReadOperandRead (cpup, cpu.TPR.CA, & cpu.CY); TPR 6656 src/dps8/dps8_ins.c cpu.TPR.CA = get_BAR_address (cpup, cpu.TPR.CA); TPR 6711 src/dps8/dps8_ins.c cpu.PR[0].SNR = cpu.TPR.CA & MASK15; TPR 6720 src/dps8/dps8_ins.c cpu.PR[1].SNR = cpu.TPR.CA & MASK15; TPR 6729 src/dps8/dps8_ins.c cpu.PR[2].SNR = cpu.TPR.CA & MASK15; TPR 6738 src/dps8/dps8_ins.c cpu.PR[3].SNR = cpu.TPR.CA & MASK15; TPR 6747 src/dps8/dps8_ins.c cpu.PR[4].SNR = cpu.TPR.CA & MASK15; TPR 6756 src/dps8/dps8_ins.c cpu.PR[5].SNR = cpu.TPR.CA & MASK15; TPR 6765 src/dps8/dps8_ins.c cpu.PR[6].SNR = cpu.TPR.CA & MASK15; TPR 6774 src/dps8/dps8_ins.c cpu.PR[7].SNR = cpu.TPR.CA & MASK15; TPR 6787 src/dps8/dps8_ins.c cpu.PR[0].WORDNO = cpu.TPR.CA; TPR 6788 src/dps8/dps8_ins.c SET_PR_BITNO (0, cpu.TPR.TBR); TPR 6799 src/dps8/dps8_ins.c cpu.PR[1].WORDNO = cpu.TPR.CA; TPR 6800 src/dps8/dps8_ins.c SET_PR_BITNO (1, cpu.TPR.TBR); TPR 6811 src/dps8/dps8_ins.c cpu.PR[2].WORDNO = cpu.TPR.CA; TPR 6812 src/dps8/dps8_ins.c SET_PR_BITNO (2, cpu.TPR.TBR); TPR 6823 src/dps8/dps8_ins.c cpu.PR[3].WORDNO = cpu.TPR.CA; TPR 6824 src/dps8/dps8_ins.c SET_PR_BITNO (3, cpu.TPR.TBR); TPR 6835 src/dps8/dps8_ins.c cpu.PR[4].WORDNO = cpu.TPR.CA; TPR 6836 src/dps8/dps8_ins.c SET_PR_BITNO (4, cpu.TPR.TBR); TPR 6847 src/dps8/dps8_ins.c cpu.PR[5].WORDNO = cpu.TPR.CA; TPR 6848 src/dps8/dps8_ins.c SET_PR_BITNO (5, cpu.TPR.TBR); TPR 6859 src/dps8/dps8_ins.c cpu.PR[6].WORDNO = cpu.TPR.CA; TPR 6860 src/dps8/dps8_ins.c SET_PR_BITNO (6, cpu.TPR.TBR); TPR 6871 src/dps8/dps8_ins.c cpu.PR[7].WORDNO = cpu.TPR.CA; TPR 6872 src/dps8/dps8_ins.c SET_PR_BITNO (7, cpu.TPR.TBR); TPR 6917 src/dps8/dps8_ins.c cpu.PR[n].RNR = max3 (Crr, cpu.SDW->R1, cpu.TPR.TRR); TPR 7089 src/dps8/dps8_ins.c cpu_port_num = (cpu.TPR.CA >> 15) & 07; TPR 7091 src/dps8/dps8_ins.c cpu_port_num = (cpu.TPR.CA >> 15) & 03; TPR 7815 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) TPR 7853 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) TPR 7873 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) TPR 7911 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 5) & 03;) TPR 7979 src/dps8/dps8_ins.c DPS8M_ (if (cpu.TPR.CA != 0000002 && (cpu.TPR.CA & 3) != 0) TPR 7980 src/dps8/dps8_ins.c sim_warn ("CAMP ignores enable/disable %06o\n", cpu.TPR.CA);) TPR 7981 src/dps8/dps8_ins.c if ((cpu.TPR.CA & 3) == 02) TPR 7983 src/dps8/dps8_ins.c else if ((cpu.TPR.CA & 3) == 01) TPR 8024 src/dps8/dps8_ins.c DPS8M_ (if (cpu.TPR.CA != 0000006 && (cpu.TPR.CA & 3) != 0) TPR 8025 src/dps8/dps8_ins.c sim_warn ("CAMS ignores enable/disable %06o\n", cpu.TPR.CA);) TPR 8026 src/dps8/dps8_ins.c if ((cpu.TPR.CA & 3) == 02) TPR 8028 src/dps8/dps8_ins.c else if ((cpu.TPR.CA & 3) == 01) TPR 8048 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) TPR 8049 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) TPR 8107 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 10) & 03;) TPR 8108 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 10) & 07;) TPR 8157 src/dps8/dps8_ins.c cpu.rA = PROM[cpu.TPR.CA & 1023]; TPR 8161 src/dps8/dps8_ins.c uint select = cpu.TPR.CA & 0x7; TPR 8575 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) TPR 8576 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) TPR 8603 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) TPR 8604 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) TPR 8634 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 10) & 03;) TPR 8635 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 10) & 07;) TPR 9819 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, & cpu_dev, "absa CA:%08o\n", cpu.TPR.CA); TPR 9825 src/dps8/dps8_ins.c * result = ((word36) (cpu.TPR.CA & MASK18)) << 12; // 24:12 format TPR 4090 src/dps8/dps8_sys.c { "cpus[].TPR", SYM_STRUCT_OFFSET, SYM_PTR, offsetof (cpu_state_t, TPR) }, TPR 372 src/dps8/panelScraper.c SETL (bank_a, 30+3, cpu.TPR.TBR, 6); TPR 432 src/dps8/panelScraper.c SETL (bank_a, 0+3, cpu.TPR.TRR, 3); TPR 433 src/dps8/panelScraper.c SETL (bank_a, 3+3, cpu.TPR.TSR, 15); TPR 446 src/dps8/panelScraper.c SETL (bank_a, 30+3, cpu.TPR.TBR, 6); TPR 462 src/dps8/panelScraper.c SETL (bank_a, 0+3, cpu.TPR.CA, 18); TPR 782 src/dps8/panelScraper.c TPR 817 src/dps8/panelScraper.c TPR 991 src/dps8/panelScraper.c SETL (bank_l, 3, cpu.TPR.CA, 18);