root/src/dps8/dps8_scu.c

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DEFINITIONS

This source file includes following definitions.
  1. scu_show_nunits
  2. scu_set_nunits
  3. scu_show_state
  4. scu_show_config
  5. scu_set_config
  6. dump_intr_regs
  7. scu_unit_reset
  8. scu_reset
  9. set_SCU_clock
  10. pcells
  11. deliver_interrupts
  12. scu_smic
  13. scu_sscr
  14. scu_rscr
  15. scu_cioc
  16. scu_set_interrupt
  17. scu_get_highest_intr
  18. scu_reset_unit
  19. scu_init
  20. scu_rmcm
  21. scu_smcm

   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * SPDX-License-Identifier: Multics
   5  * scspell-id: d49ab489-f62e-11ec-9ac1-80ee73e9b8e7
   6  *
   7  * ---------------------------------------------------------------------------
   8  *
   9  * Copyright (c) 2007-2013 Michael Mondy
  10  * Copyright (c) 2012-2016 Harry Reed
  11  * Copyright (c) 2013-2022 Charles Anthony
  12  * Copyright (c) 2021-2024 The DPS8M Development Team
  13  *
  14  * This software is made available under the terms of the ICU License.
  15  * See the LICENSE.md file at the top-level directory of this distribution.
  16  *
  17  * ---------------------------------------------------------------------------
  18  *
  19  * This source file may contain code comments that adapt, include, and/or
  20  * incorporate Multics program code and/or documentation distributed under
  21  * the Multics License.  In the event of any discrepancy between code
  22  * comments herein and the original Multics materials, the original Multics
  23  * materials should be considered authoritative unless otherwise noted.
  24  * For more details and historical background, see the LICENSE.md file at
  25  * the top-level directory of this distribution.
  26  *
  27  * ---------------------------------------------------------------------------
  28  */
  29 
  30 //-V536
  31 
  32 /*
  33  * scu.c -- System Controller
  34  *
  35  * See AN70, section 8 and GB61.
  36  *
  37  * There were a few variations of SCs and SCUs:
  38  * SCU -- Series 60 Level 66 Controller
  39  * SC -- Level 68 System Controller
  40  * 4MW SCU -- A later version of the Level 68 SC
  41  *
  42  * SCUs control access to memory.
  43  * Each SCU owns a certain range of absolute memory.
  44  * This emulator allows the CPU to access memory directly however.
  45  * SCUs contain clocks.
  46  * SCUS also contain facilities which allow CPUS and IOMs to communicate.
  47  * CPUs or IOMS request access to memory via the SCU.
  48  * CPUs use the CIOC instr to talk to IOMs and other CPUs via a SCU.
  49  * IOMs use interrupts to ask a SCU to signal a CPU.
  50  * Other Interesting instructions:
  51  * read system controller reg and set system controller reg (RSCR & SSCR)
  52  *
  53  */
  54 
  55 /*
  56  * Physical Details & Interconnection -- AN70, section 8.
  57  *
  58  * SCUs have 8 ports.
  59  * Active modules (CPUs and IOMs) have up to four of their ports
  60  * connected to SCU ports.
  61  *
  62  * The 4MW SCU has eight on/off switches to enable or disable
  63  * the ports.  However, the associated registers allow for
  64  * values of enabled, disabled, and program control.
  65  *
  66  * SCUs have stores (memory banks).
  67  *
  68  * SCUs have four sets of registers controlling interrupts.  Only two
  69  * of these sets, designated "A" and "B" are used.  Each set has:
  70  * Execute interrupt mask register -- 32 bits; enables/disables
  71  * the corresponding execute interrupt cell
  72  * Interrupt mask assignment register -- 9 bits total
  73  * two parts: assigned bit, set of assigned ports (8 bits)
  74  * In Multics, only one CPU will be assigned in either mask
  75  * and no CPU appears in both.   Earlier hardware versions had
  76  * four 10-position rotary switches.  Later hardware versions had
  77  * two 9-position (0..7 and off) rotary switches.
  78  *
  79  * Config panel -- Level 68 6000 SCU
  80  * -- from AM81
  81  * store A and store B
  82  * 3 position rotary switch: on line, maint, off line
  83  * size: 32K, 64K, 128K, 256K
  84  * exec interrupt mask assignment
  85  * four 10-position rotary switches (A through D): off, 0 .. 7, M
  86  * One switch for each program interrupt register
  87  * Assign mask registers to system ports
  88  * Normally assign one mask reg to each CPU
  89  *
  90  *   AM81:
  91  *     "        The EXECUTE INTERRUPT MASK ASSIGNMENT (EIMA) rotary switches
  92  *      determine where interrupts sent to memory are directed.  The four EIMA
  93  *      rotary switches, one for each program interrupt register, are used to
  94  *      assign mask registers to system ports. The normal settings assign one
  95  *      mask register to each CPU configured.
  96  *
  97  *      Each switch assigns mask registers as follows:
  98  *
  99  *          Position
 100  *            OFF     Unassigned
 101  *              0     Assigned to port 0
 102  *                ...
 103  *              7     Assigned to port 7
 104  *              M     Assigned to maintenance panel
 105  *
 106  *      Assignment of a mask register to a system port designates the
 107  *      port as a control port, and that port receives interrupt present
 108  *      signals. Up to four system ports can be designated as control
 109  *      ports. The normal settings assign one mask register to each CPU
 110  *      configured."
 111  *
 112  *
 113  *
 114  * Config panel -- Level 68 System Controller UNIT (4MW SCU)
 115  * -- from AM81
 116  * Store A, A1, B, B1 (online/offline)
 117  * LWR Store Size
 118  * PORT ENABLE
 119  * Eight on/off switches
 120  * Should be on for each port connected to a configured CPU
 121  * mask/port assignment
 122  * Two rotary switches (A & B); set to (off, 0..7)
 123  * See EXEC INTERRUPT on the 6000 SCU
 124  * When booting, one should be set to the port connected to
 125  * the bootload CPU.   The other should be off.
 126  *
 127  * If memory port B of CPU C goes to SCU D, then memory port B of all
 128  * other CPUs *and* IOMs must go to SCU D. -- AN70, 8-4.
 129  *
 130  * The base address of the SCU is the actual memory size * the port
 131  * assignment. -- AN70, 8-6.
 132  *
 133  *  43A239854 6000B Eng. Prod. Spec, 3.2.7 Interrupt Multiplex Word:
 134  *    "The IOM has the ability to set any of the 32 program interrupt
 135  *     cells located in the system controller containing the base address
 136  *     of the IOM. It should be noted that for any given IOM identity
 137  *     switch setting, the IOM can set only 8 of these program interrupt
 138  *     cells."
 139  *
 140  */
 141 
 142 /*
 143  * === Initialization and Booting -- Part 1 -- Operator's view
 144  *
 145  * Booting Instructions (GB61)
 146  * First boot the BCE OS (Bootload command Environment).  See below.
 147  * A config deck is used
 148  * Bootload SCU is the one with a base addr of zero.
 149  * BCE is on a BCE/Multics System tape
 150  * Booted from tape into the system via bootload console
 151 
 152  */
 153 
 154 /*
 155  * 58009906 (DPS8)
 156  * When CPU needs to address the SCU (for a write/read data cycle,
 157  * for example), the ETMCM board int the CU of the CPU issues a $INT
 158  * to the SCU.  This signal is sent ... to the SCAMX active port
 159  * control board in the SCU
 160  */
 161 
 162 // How?  If one of the 32 interrupt cells is set in one of the SCs,
 163 // our processor will have the interrupt present (XIP) line active.
 164 // Perhaps faults are flagged in the same way via the SXC system
 165 // controller command.
 166 
 167 // TEMPORARY
 168 // Each SCU owns a certain range of absolute memory.
 169 // CPUs use the cioc instr to talk to IOMs and other CPUs via a SCU.
 170 // IOMs use interrupts to ask a SCU to signal a CPU.
 171 // read system controller reg and set system controller reg (rscr & sscr)
 172 // Bootload SCU is the one with a base addr of zero.
 173 // 58009906
 174 // When CPU needs to address the SCU (for a write/read data cycle,
 175 // for example), the ETMCM board int the CU of the CPU issues a $INT
 176 // to the SCU.  This signal is sent ... to the SCAMX active port
 177 // control board in the
 178 // -----------------------
 179 // How?  If one of the 32 interrupt cells is set in one of the SCs,
 180 // our processor will have the interrupt present (XIP) line active.
 181 // Perhaps faults are flagged in the same way via the SXC system
 182 // controller command.
 183 
 184 /*
 185  * *** More (new) notes ***
 186  *
 187  * instr rmcm -- read mem controller mask register
 188  * ... for the selected controller, if the processor has a mask register
 189  * assigned ..
 190  * instr smcm -- set  mem controller mask register
 191  * ... for the selected controller, if the processor has a mask register
 192  * assigned, set it to C(AQ)
 193  * instr smic
 194  * turn on interrupt cells (any of 0..31)
 195  * instr cioc -- connect i/o channel, pg 173
 196  * SC addressed by Y sends a connect signal to the port specified
 197  * by C(Y)33,35
 198  * instr rscr & sscr -- Read/Store System Controller Register, pg 170
 199  *
 200  * 32 interrupt cells ... XIP
 201  * mask info
 202  * 8 mask registers
 203  * 58009906
 204  * =============
 205  *
 206  * AM81
 207  * Every active device (CPU, IOM) must be able to access all SCUs
 208  * Every SCU must have the same active device on the same SCU, so
 209  * all SCUs must have the same PORT ENABLE settings
 210  * Every active device must have the same SCU on the same port,
 211  * so all active devices will have the same config panel settings.
 212  * Ports must correspond -- port A on every CPU and IOM must either
 213  * be connected to the same SCU or not connected to any SCU.
 214  * IOMs should be on lower-numbered SCU ports than CPUs.
 215  * Multics can have 16MW words of memory.
 216  * CPUs have 8 ports, a..h.
 217  * SCUs have 8 ports, 0..7.
 218  *
 219  *
 220  * Level 68 6000 SCU Configuration Panel
 221  *   system control and monitor (cont&mon/mon/off)
 222  *   system boot control (on/off)
 223  *   alarm (disable/normal)
 224  *   maintenance panel mode (test/normal)
 225  *   store a
 226  *      mode (offline/maint/online)
 227  *      size (32k, 64k, 128k, 256k)
 228  *   store b
 229  *      mode (offline/maint/online)
 230  *      size (32k, 64k, 128k, 256k)
 231  *   execute interrupt mask assignment
 232  *      (A through D; off/0/1/2/3/4/5/6/7/m)
 233  *   [CAC] I interpret this as CPU [A..D] is connected to my port [0..7]
 234  *   address control
 235  *      lower store (a/b)
 236  *      offset (off, 16k, 32k, 64k)
 237  *      interlace (on/off)
 238  *   cycle port priority (on/off)
 239  *   port control (8 toggles) (enabled/prog cont/disable)
 240  *
 241  * The EXECUTE INTERRUPT MASK ASSIGNMENT (EIMA) rotary switches
 242  * determine where interrupts sent to memory are directed. The four EIMA
 243  * rotary switches, one for each program interrupt register, are used to
 244  * assign mask registers to system ports. The normal settings assign one
 245  * mask register to each CPU configured.
 246  *
 247  *  Assignment of a mask register to a system port designates the port as a
 248  *  control port, and that port receives interrupt present signals. Up to four
 249  *  system ports can be designated as control ports. The normal settings
 250  *  assign one mask register to each cpu configured.
 251  *
 252  *
 253  *
 254  * Configuration rules for Multics:
 255  *
 256  *   1. Each CPU in the system must be connected to each SCU in the system
 257  *
 258  *   2. Each IOM in the system must be connected to each SCU in the system
 259  *
 260  *   3. Each SCU in the system must be connected to every CPU and IOM in the
 261  *      system.
 262  *
 263  *   4. Corresponding ports on all CPUs and IOMs must be connected to the same
 264  *      SCU. For example, port A on every CPU and IOM must be connected to the
 265  *      same SCU or not connected to any SCU.
 266  *
 267  *   5. Corresponding ports on all SCUs must be connected to the same active
 268  *      device (CPU or IOM). For example, if port 0 on any SCU is connected to
 269  *      IOM A, then port 0 on all SCUs must be connected to IOM A.
 270  *
 271  *   6. IOMs should be connected to lower-number SCU ports the CPUs.
 272  *
 273  *   These rules are illustrated in Figure 3-5, where the port numbers for a
 274  *   small Multics system of 2 CPUS, 3 SCUs and 2 IOMs have been indicated
 275  *
 276  *
 277  *
 278  *
 279  *                    -----------------                      -----------------
 280  *                    |               |                      |               |
 281  *                    |     CPU A     |                      |     CPU B     |
 282  *                    |               |                      |               |
 283  *                    -----------------                      -----------------
 284  *                    | A | B | C | D |                      | A | B | C | D |
 285  *                    -----------------                      -----------------
 286  *                      |   |   |                              |   |   |
 287  *                      |   |   |                              |   |   -----------------
 288  *                      |   |   |                              |   |                   |
 289  *                      |   |   -------------------------------)---)----------------   |
 290  *                      |   |                                  |   |               |   |
 291  *   --------------------   -----------------                  |   |               |   |
 292  *   |                                      |                  |   |               |   |
 293  *   |   -----------------------------------)-------------------   |               |   |
 294  *   |   |                                  |                      |               |   |
 295  *   |   |                                  |   --------------------               |   |
 296  *   |   |                                  |   |                                  |   |
 297  * -----------------                      -----------------                      -----------------
 298  * | 7 | 6 | 5 | 4 |                      | 7 | 6 | 5 | 4 |                      | 7 | 6 | 5 | 4 |
 299  * -----------------                      -----------------                      -----------------
 300  * |               |                      |               |                      |               |
 301  * |     SCU C     |                      |     SCU B     |                      |     SCU A     |
 302  * |               |                      |               |                      |               |
 303  * -----------------                      -----------------                      -----------------
 304  * | 3 | 2 | 1 | 0 |                      | 3 | 2 | 1 | 0 |                      | 3 | 2 | 1 | 0 |
 305  * -----------------                      -----------------                      -----------------
 306  *           |   |                                  |   |                                  |   |
 307  *           |   |                                  |   -----------                        |   |
 308  *           |   |                                  |             |                        |   |
 309  *           |   -----------------------------------)---------    |                        |   |
 310  *           |                                      |        |    |                        |   |
 311  *           ----------    --------------------------        |    |                        |   |
 312  *                    |    |                                 |    |                        |   |
 313  *                    |    |   ------------------------------)----)-------------------------   |
 314  *                    |    |   |                             |    |                            |
 315  *                    |    |   |                             |    |  ---------------------------
 316  *                    |    |   |                             |    |  |
 317  *                   -----------------                      -----------------
 318  *                   | A | B | C | D |                      | A | B | C | D |
 319  *                   -----------------                      -----------------
 320  *                   |               |                      |               |
 321  *                   |     IOM A     |                      |     IOM B     |
 322  *                   |               |                      |               |
 323  *                   -----------------                      -----------------
 324  *
 325  *
 326  *
 327  *"During bootload, Multics requires a contiguous section of memory beginning at
 328  * absolute address 0 and sufficiently large to contain all routines and data
 329  * structures used during the first phase of Multics initialization (i.e.
 330  * collection 1).
 331  * The size of the section required varies among Multics release, and it also
 332  * depends on the size of the SST segment, which is dependent on the parameters
 333  * specified by the site on the SST config card. ... However
 334  * 512 KW is adequate for all circumstances. There can be no "holes" in memory
 335  * within this region. Beyond this region, "holes" can exist in memory."
 336  *
 337  *
 338  */
 339 
 340 /*
 341  * From AN70-1 May84, pg 86 (8-6)
 342  *
 343  * RSCR SC_CFG bits 9-11 lower store size
 344  *
 345  * A DPS-8 SCU may have up to four store units attached to it. If this
 346  * is the case, two store units form a pair of units. The size of a
 347  * pair of units (or a single unit) is 32K * 2 ** (lower store size)
 348  * above.
 349  */
 350 
 351 /*
 352  * From AN70-1 May84, pg 86 (8-6)
 353  *
 354  * SCU ADDRESSING
 355  *
 356  *       There are three ways in which an SCU is addressed.  In the
 357  * normal mode of operation (memory reading and writing), an active
 358  * unit (IOM or CPU) translates an absolute address into a memory
 359  * port (on it) and a relative memory address within the memory
 360  * described by the memory port. The active module sends the
 361  * address to the SCU on the proper memory port. If the active
 362  * module is enabled by the port enable mask in the referenced SCU,
 363  * the SCU will take the address given to it and provide the
 364  * necessary memory access.
 365  *
 366  *      The other two ways pertain to reading/setting control
 367  * registers in the SCU itself. For each of these, it is still
 368  * necessary to specify somehow the memory port on the CPU whose SCU
 369  * registers are desired. For the RMCM, SMCM and SMIC instructions,
 370  * this consists of providing a virtual address to the processor for
 371  * which bits 1 and 2 are the memory port desired.
 372  *
 373  *      The rscr and sscr instructions, though key off the final
 374  * absolute address to determine the SCI (or SCU store unit)
 375  * desired. Thus, software needs a way to translate a memory port
 376  * number into an absolute address to reach the SCU. This is done
 377  * with the paged segment scas, generated by int_scas (and
 378  * init_scu). scas has a page corresponding to each SCU and to each
 379  * store unit in each SCU. pmut$rscr and pmut$sscr use the memory
 380  * port number desired to generate a virtual address into scas whose
 381  * absolute address (courtesy of the ptws for sca) just happen to
 382  * describe memory within that SCU.
 383  *
 384  *       The cioc instruction (discussed below) also depends on the
 385  * final absolute address of the target operand to identify the SCU
 386  * to perform the operation. In the case of the cioc instruction,
 387  * though, the has no particular impact in Multics software. All
 388  * target operands for the cioc instruction when referencing IOMs
 389  * are in the low order SCU. When referencing CPUS, the SCU
 390  * performing the connecting has no real bearing.
 391  *
 392  * Inter-module communication
 393  *
 394  *       As mentioned earlier, communication between active modules
 395  * (CPUs and IOMs can only be performed through SCUs.
 396  *
 397  *       CPUs communicate to IOMs and other CPUs via the cioc
 398  * (connect i/o channel) instruction. The operand of the instruction
 399  * is a word in memory. The SCU containing this operand is the SCU
 400  * that performs the connect function. The word fetched from memory
 401  * contains in its low order bits the identity of a port on the SCU
 402  * to which this connection is to be sent. This only succeeds if the
 403  * target port is enabled (port enable mask) on the SCU. When the
 404  * target of the connection is an IOM; this generates a connect strobe
 405  * to the IOM. The IOM examines its mailbox in memory to determine
 406  * its course of action. When the target of the connect is another
 407  * CPU, this generates a connect fault in the target processor. The
 408  * target processor determines what course to follow on the basis
 409  * of information in memory analyzed by software. When a connect is
 410  * sent to a process (including the processor issuing the connect),
 411  * the connect is deferred until the processor stops
 412  * executing inhibited code (instructions with the inhibit bit set).
 413  *
 414  *       Signals sent from an IOM to a CPU are much more involved.
 415  * The basic flow is as follows. The IOM determines an interrupt
 416  * number. (The interrupt number is a five bit value, from 0 to 31.
 417  * The high order bits are the interrupt level.
 418  *
 419  * 0 - system fault
 420  * 1 - terminate
 421  * 2 - marker
 422  * 3 - special
 423  *
 424  * The low order three bits determines the IOM and IOM channel
 425  * group.
 426  *
 427  * 0 - IOM 0 channels 32-63
 428  * 1 - IOM 1 channels 32-63
 429  * 2 - IOM 2 channels 32-63
 430  * 3 - IOM 3 channels 32-63
 431  * 4 - IOM 0 channels 0-31
 432  * 5 - IOM 1 channels 0-31
 433  * 6 - IOM 2 channels 0-31
 434  * 7 - IOM 3 channels 0-31
 435  *
 436  * It also takes the channel number in the group (0-31 meaning
 437  * either channels 0-31 to 32-63) and sets the <channel number>th
 438  * bit in the <interrupt number>th memory location in the interrupt
 439  * mask word (IMW) array in memory. It then generates a word with
 440  * the <interrupt number>th bit set and sends this to the bootload
 441  * SCU with the SC (set execute cells) SCU command. This sets the
 442  * execute interrupt cell register in the SCU and sends an XIP
 443  * (execute interrupt present) signal to various processors
 444  * connected to the SCU. (The details of this are covered in the
 445  * next section.) One of the processors (the first to get to it)
 446  * sends an XEC (execute interrupt cells) SCU command to the SCU who
 447  * generated the XIP signal. The SCU provides the interrupt number
 448  * to the processor, who uses it to determine the address of a fault
 449  * pair in memory for the "fault" caused by this interrupt. The
 450  * processing of the XEC command acts upon the highest priority
 451  * (lowest number) bit in the execute interrupt cell register, and
 452  * also resets this bit in the register.
 453  *
 454  * Interrupts Masks and Assignment
 455  *
 456  *       The mechanism for determining which processors are candidates
 457  * for receiving an interrupt from an IOM is an involved
 458  * topic. First of all, a processor will not be interrupted as long
 459  * as it is executing inhibited instructions (instructions with the
 460  * inhibit bit set). Beyond this, though, lies the question of
 461  * interrupt masks and mask assignment.
 462  *
 463  *       Internal to the SCU are two sets of registers (A and B),
 464  * each set consisting of the execute interrupt mask register and
 465  * the interrupt mask assignment register. Each execute interrupt
 466  * mask register is 32 bits long, with each bit enabling the
 467  * corresponding bit in the execute interrupt cell register. Each
 468  * interrupt mask assignment register has two parts, an assigned bit
 469  * and a set of ports to which it is assigned (8 bits). When a bit
 470  * is set in the execute  interrupt sells register, the SCU ANDs this
 471  * bit with the corresponding bit in each of the execute interrupt
 472  * mask registers. If the corresponding bit of execute interrupt
 473  * mask register A, for example, is on, the SCU then looks at the A
 474  * interrupt mask assignment register. If this register is not
 475  * assigned (enable), no further action takes place in regards to
 476  * the A registers. (The B registers are still considered) (in
 477  * parallel, by the way).) If the register is assigned (enabled)
 478  * then interrupts will be send to all ports (processors) whose
 479  * corresponding bit is set in the interrupt mask assignment
 480  * register. This, only certain interrupts are allowed to be
 481  * signalled at any given time (base on the contents of the execute
 482  * interrupt mask registers) and only certain processors will
 483  * receive these interrupts (as controlled by the interrupt mask
 484  * assignment registers).
 485  *
 486  *       In Multics, only one processor is listed in each of the two
 487  * interrupt mask assignment registers, and no processor appears in
 488  * both. Thus there is a one for one correspondence between
 489  * interrupt masks that are assigned (interrupt mask registers whose
 490  * assigned (enabled) bit is on) and processors who have an
 491  * interrupt mask (SCU port number appears in an interrupt mask
 492  * register). So, at any one time only two processors
 493  * are eligible to receive interrupts. Other processors need not
 494  * worry about masking interrupts.
 495  *
 496  *       The contents of the interrupt mask registers may be
 497  * obtained with the SCU configuration information with the rscr
 498  * instruction and set with the sscr instruction.
 499  *
 500  *  bits   meaning
 501  *
 502  * 00-07   ports assigned to mask A (interrupt mask assignment A)
 503  * 08-08   mask A is unassigned (disabled)
 504  * 36-43   ports assigned to mask B (interrupt mask assignment B)
 505  * 44-44   mask B is unassigned (disabled)
 506  *
 507  *       The contents of a execute interrupt mask register are
 508  * obtained with the rmcm or the rscr instruction and set with the
 509  * smcm or the sscr instruction. The rmcm and smcm instruction only
 510  * work if the processor making the request has a mask register
 511  * assigned to it. If not, rmcm returns zero (no interrupt are
 512  * enabled to it) and a smcm is ignored (actually the port mask
 513  * setting is still done). The rscr and sscr instructions allow the
 514  * examining/setting of the execute interrupt mask register for any
 515  * port on a SCU; these have the same effect as smcm and rmcm if the
 516  * SCU port being referenced does not have a mask assigned to it.
 517  * The format of the data returned by these instructions is as
 518  * follows.
 519  *
 520  *  bits   meaning
 521  * 00-15   execute interrupt mask register 00-15
 522  * 32-35   SCU port mask 0-3
 523  * 36-51   execute interrupt mask register 16-31
 524  * 68-71   SCU port mask 4-7
 525  *
 526  */
 527 
 528 // SCU numbering:
 529 //
 530 // AM81-04, pg 49: "... the ports are listed in order of increasing base
 531 //    address, which corresponds to the order of mem config cards."
 532 // pg 97: "mem port size state ... port as a value (a through h) that
 533 //        corresponds to the number of the active module port to which the
 534 //        system controller is connected.
 535 //
 536 // From this, I conclude;
 537 //   The SCU connected to port A (0) is SCUA, 1 B, 2 C, etc.
 538 //   SCUA starts at address 0, and the SCUs are sorted by increasing addresses.
 539 //
 540 
 541 // ============================================================================
 542 
 543 #include <sys/time.h>
 544 #include "dps8.h"
 545 #include "dps8_sys.h"
 546 #include "dps8_iom.h"
 547 #include "dps8_cable.h"
 548 #include "dps8_cpu.h"
 549 #include "dps8_faults.h"
 550 #include "dps8_scu.h"
 551 #include "dps8_utils.h"
 552 #if defined(THREADZ) || defined(LOCKLESS)
 553 # include "threadz.h"
 554 #endif
 555 
 556 #define DBG_CTR 1
 557 
 558 scu_t scu [N_SCU_UNITS_MAX];
 559 
 560 #define N_SCU_UNITS 1 // Default
 561 
 562 static UNIT scu_unit [N_SCU_UNITS_MAX] = {
 563 #if defined(NO_C_ELLIPSIS)
 564   { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
 565   { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
 566   { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
 567   { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
 568   { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
 569   { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
 570   { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
 571   { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL }
 572 #else
 573   [0 ... N_SCU_UNITS_MAX-1] = {
 574     UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL
 575   }
 576 #endif
 577 };
 578 
 579 #define UNIT_NUM(uptr) ((uptr) - scu_unit)
 580 
 581 // Hardware configuration switches
 582 
 583 // sscr and other instructions override these settings
 584 
 585 static struct config_switches
 586   {
 587     uint mode;                            // program or manual
 588     uint port_enable [N_SCU_PORTS];       // enable/disable
 589     uint mask_enable [N_ASSIGNMENTS];     // enable/disable
 590     uint mask_assignment [N_ASSIGNMENTS]; // assigned port number
 591     uint lower_store_size;                // In K words, power of 2; 32 - 4096
 592     uint cyclic;                          // 7 bits
 593     uint nea;                             // 8 bits
 594     uint onl;                             // 4 bits
 595     uint interlace;                       // 1 bit
 596     uint lwr;                             // 1 bit
 597   } config_switches [N_SCU_UNITS_MAX];
 598 
 599 enum { MODE_MANUAL = 0, MODE_PROGRAM = 1 };
 600 
 601 unsigned int gtod_warned = 0;
 602 
 603 // ============================================================================
 604 
 605 static t_stat scu_show_nunits (UNUSED FILE * st, UNUSED UNIT * uptr,
     /* [previous][next][first][last][top][bottom][index][help] */
 606                                UNUSED int val, const UNUSED void * desc)
 607   {
 608     sim_printf("Number of SCU units in system is %d\n", scu_dev.numunits);
 609     return SCPE_OK;
 610   }
 611 
 612 static t_stat scu_set_nunits (UNUSED UNIT * uptr, UNUSED int32 value,
     /* [previous][next][first][last][top][bottom][index][help] */
 613                               const char * cptr, UNUSED void * desc)
 614   {
 615     if (! cptr)
 616       return SCPE_ARG;
 617     int n = atoi (cptr);
 618     if (n < 1 || n > N_SCU_UNITS_MAX)
 619       return SCPE_ARG;
 620     scu_dev.numunits = (uint) n;
 621     return SCPE_OK;
 622   }
 623 
 624 static t_stat scu_show_state (UNUSED FILE * st, UNIT *uptr, UNUSED int val,
     /* [previous][next][first][last][top][bottom][index][help] */
 625                               UNUSED const void * desc)
 626   {
 627 #if defined(TESTING)
 628     cpu_state_t * cpup = _cpup;
 629 #endif
 630     long scu_unit_idx = UNIT_NUM (uptr);
 631     if (scu_unit_idx < 0 || scu_unit_idx >= (int) scu_dev.numunits)
 632       {
 633         sim_debug (DBG_ERR, & scu_dev,
 634                    "scu_show_state: Invalid unit number %ld\n",
 635                    (long) scu_unit_idx);
 636         sim_printf ("error: Invalid unit number %ld\n", (long) scu_unit_idx);
 637         return SCPE_ARG;
 638       }
 639 
 640     sim_printf ("SCU unit number %ld\n", (long) scu_unit_idx);
 641     scu_t * scup = scu + scu_unit_idx;
 642     sim_printf ("    Mode %s\n",
 643                 config_switches[scu_unit_idx].mode ? "PROGRAM" : "MANUAL");
 644 
 645     for (int i = 0; i < N_SCU_PORTS; i ++)
 646       {
 647         struct ports * pp = scup -> ports + i;
 648 
 649         sim_printf ("    Port %d %s dev_idx %d dev_port %d type %s\n",
 650                     i, scup->port_enable[i] ? "ENABLE " : "DISABLE",
 651                     pp->dev_idx, pp->dev_port[XXX_TEMP_SCU_SUBPORT],
 652                     pp->type == ADEV_NONE ? "NONE" :
 653                     pp->type == ADEV_CPU ? "CPU" :
 654                     pp->type == ADEV_IOM ? "IOM" :
 655                     "<enum broken>");
 656       }
 657     for (int i = 0; i < N_ASSIGNMENTS; i ++)
 658       {
 659         //struct interrupts * ip = scup -> interrupts + i;
 660 
 661         sim_printf ("    Cell %c\n", 'A' + i);
 662         sim_printf ("        exec_intr_mask %012o\n",
 663                     scup -> exec_intr_mask [i]);
 664         sim_printf ("        mask_enable %s\n",
 665                     scup -> mask_enable [i] ? "ENABLE" : "DISABLE");
 666         sim_printf ("        mask_assignment %d\n",
 667                     scup -> mask_assignment [i]);
 668         sim_printf ("        cells ");
 669         for (int j = 0; j < N_CELL_INTERRUPTS; j ++)
 670           sim_printf("%d", scup -> cells [j]);
 671         sim_printf ("\n");
 672       }
 673     sim_printf("Lower store size: %d\n", scup -> lower_store_size);
 674     sim_printf("Cyclic: %03o\n",         scup -> cyclic);
 675     sim_printf("NEA: %03o\n",            scup -> nea);
 676     sim_printf("Online: %02o\n",         scup -> onl);
 677     sim_printf("Interlace: %o\n",        scup -> interlace);
 678     sim_printf("Lower: %o\n",            scup -> lwr);
 679     sim_printf("ID: %o\n",               scup -> id);
 680     sim_printf("mode_reg: %06o\n",       scup -> mode_reg);
 681     sim_printf("Elapsed days: %d\n",     scup -> elapsed_days);
 682     sim_printf("Steady clock: %d\n",     scup -> steady_clock);
 683     sim_printf("Bullet time: %d\n",      scup -> bullet_time);
 684     sim_printf("Y2K enabled: %d\n",      scup -> y2k);
 685     return SCPE_OK;
 686   }
 687 
 688 static t_stat scu_show_config (UNUSED FILE * st, UNUSED UNIT * uptr,
     /* [previous][next][first][last][top][bottom][index][help] */
 689                                UNUSED int val, UNUSED const void * desc)
 690 {
 691 #if defined(TESTING)
 692     cpu_state_t * cpup = _cpup;
 693 #endif
 694     static const char * map [N_SCU_PORTS] =
 695       {
 696         "0", "1", "2", "3", "4", "5", "6", "7"
 697       };
 698     long scu_unit_idx = UNIT_NUM (uptr);
 699     if (scu_unit_idx < 0 || scu_unit_idx >= (int) scu_dev.numunits)
 700       {
 701         sim_debug (DBG_ERR, & scu_dev,
 702                    "scu_show_config: Invalid unit number %ld\n",
 703                    (long) scu_unit_idx);
 704         sim_printf ("error: Invalid unit number %ld\n", (long) scu_unit_idx);
 705         return SCPE_ARG;
 706       }
 707 
 708     sim_printf ("SCU unit number %ld\n", (long) scu_unit_idx);
 709 
 710     struct config_switches * sw = config_switches + scu_unit_idx;
 711 
 712     const char * mode = "<out of range>";
 713     switch (sw -> mode)
 714       {
 715         case MODE_PROGRAM:
 716           mode = "Program";
 717           break;
 718         case MODE_MANUAL:
 719           mode = "Manual";
 720           break;
 721       }
 722 
 723     sim_printf ("Mode:                       %s\n", mode);
 724     sim_printf ("Port Enable:             ");
 725     for (int i = 0; i < N_SCU_PORTS; i ++)
 726       sim_printf (" %3o", sw -> port_enable [i]);
 727     sim_printf ("\n");
 728     for (int i = 0; i < N_ASSIGNMENTS; i ++)
 729       {
 730         sim_printf ("Mask %c:                     %s\n",
 731                     'A' + i,
 732                     sw->mask_enable[i] ? (map[sw->mask_assignment[i]]) : "Off");
 733       }
 734     sim_printf ("Lower Store Size:           %o\n",   sw -> lower_store_size);
 735     sim_printf ("Cyclic:                     %03o\n", sw -> cyclic);
 736     sim_printf ("Non-existent address:       %03o\n", sw -> nea);
 737 
 738     return SCPE_OK;
 739   }
 740 
 741 //
 742 // set scu0 config=<blah> [;<blah>]
 743 //
 744 //    blah =
 745 //           mode=  manual | program
 746 //           mask[A|B] = off | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
 747 //           portN = enable | disable
 748 //           lwrstoresize = 32 | 64 | 128 | 256 | 512 | 1024 | 2048 | 4096
 749 //           cyclic = n
 750 //           nea = n
 751 //
 752 //      o  nea is not implemented; will read as "nea off"
 753 //      o  Multics sets cyclic priority explicitly; config
 754 //         switches are ignored.
 755 //      o  STORE A, A1, B, B1 ONLINE/OFFLINE not implemented;
 756 //         will always read online.
 757 //      o  store size if not enforced; a full memory complement
 758 //         is provided.
 759 //      o  interlace not implemented; will read as 'off'
 760 //      o  LOWER STORE A/B not implemented.
 761 //      o  MASK is 'MASK/PORT ASSIGNMENT' analogous to the
 762 //         'EXECUTE INTERRUPT MASK ASSIGNMENT of a 6000 SCU
 763 
 764 static config_value_list_t cfg_mode_list [] =
 765   {
 766     { "manual",  0 },
 767     { "program", 1 },
 768     { NULL,      0 }
 769   };
 770 
 771 static config_value_list_t cfg_mask_list [] =
 772   {
 773     { "off", -1 },
 774     { NULL,  0  }
 775   };
 776 
 777 static config_value_list_t cfg_able_list [] =
 778   {
 779     { "disable", 0 },
 780     { "enable",  1 },
 781     { NULL,      0 }
 782   };
 783 
 784 static config_value_list_t cfg_size_list [] =
 785   {
 786     { "32",    0 },
 787     { "64",    1 },
 788     { "128",   2 },
 789     { "256",   3 },
 790     { "512",   4 },
 791     { "1024",  5 },
 792     { "2048",  6 },
 793     { "4096",  7 },
 794     { "32K",   0 },
 795     { "64K",   1 },
 796     { "128K",  2 },
 797     { "256K",  3 },
 798     { "512K",  4 },
 799     { "1024K", 5 },
 800     { "2048K", 6 },
 801     { "4096K", 7 },
 802     { "1M",    5 },
 803     { "2M",    6 },
 804     { "4M",    7 },
 805     { NULL,    0 }
 806   };
 807 
 808 static config_value_list_t cfg_on_off [] =
 809   {
 810     { "off",     0 },
 811     { "on",      1 },
 812     { "disable", 0 },
 813     { "enable",  1 },
 814     { NULL,      0 }
 815   };
 816 
 817 static config_list_t scu_config_list [] =
 818   {
 819     /*  0 */ { "mode",         1, 0,               cfg_mode_list },
 820     /*  1 */ { "maska",        0, N_SCU_PORTS - 1, cfg_mask_list },
 821     /*  2 */ { "maskb",        0, N_SCU_PORTS - 1, cfg_mask_list },
 822     /*  3 */ { "port0",        1, 0,               cfg_able_list },
 823     /*  4 */ { "port1",        1, 0,               cfg_able_list },
 824     /*  5 */ { "port2",        1, 0,               cfg_able_list },
 825     /*  6 */ { "port3",        1, 0,               cfg_able_list },
 826     /*  7 */ { "port4",        1, 0,               cfg_able_list },
 827     /*  8 */ { "port5",        1, 0,               cfg_able_list },
 828     /*  9 */ { "port6",        1, 0,               cfg_able_list },
 829     /* 10 */ { "port7",        1, 0,               cfg_able_list },
 830     /* 11 */ { "lwrstoresize", 0, 7,               cfg_size_list },
 831     /* 12 */ { "cyclic",       0, 0177,            NULL          },
 832     /* 13 */ { "nea",          0, 0377,            NULL          },
 833     // mask: 8 a_online, 4 a1_online, 2 b_online, 1, b1_online
 834     /* 14 */ { "onl",          0, 017,             NULL          },
 835     /* 15 */ { "int",          0, 1,               NULL          },
 836     /* 16 */ { "lwr",          0, 1,               NULL          },
 837 
 838     // Hacks
 839 
 840     /* 17 */ { "elapsed_days", 0, 20000,           NULL       },
 841     /* 18 */ { "steady_clock", 0, 1,               cfg_on_off },
 842     /* 19 */ { "bullet_time",  0, 1,               cfg_on_off },
 843     /* 20 */ { "y2k",          0, 1,               cfg_on_off },
 844              { NULL,           0, 0,               NULL       }
 845   };
 846 
 847 static t_stat scu_set_config (UNIT * uptr, UNUSED int32 value,
     /* [previous][next][first][last][top][bottom][index][help] */
 848                               const char * cptr, UNUSED void * desc)
 849   {
 850 #if defined(TESTING)
 851     cpu_state_t * cpup = _cpup;
 852 #endif
 853     long scu_unit_idx = UNIT_NUM (uptr);
 854     if (scu_unit_idx < 0 || scu_unit_idx >= (int) scu_dev.numunits)
 855       {
 856         sim_debug (DBG_ERR, & scu_dev,
 857                    "scu_set_config: Invalid unit number %ld\n", (long) scu_unit_idx);
 858         sim_printf ("error: scu_set_config: Invalid unit number %ld\n",
 859                     (long) scu_unit_idx);
 860         return SCPE_ARG;
 861       }
 862 
 863     struct config_switches * sw = config_switches + scu_unit_idx;
 864 
 865     config_state_t cfg_state = { NULL, NULL };
 866 
 867     for (;;)
 868       {
 869         int64_t v;
 870         int rc = cfg_parse ("scu_set_config", cptr, scu_config_list,
 871                            & cfg_state, & v);
 872         if (rc == -1) // done
 873           break;
 874 
 875         if (rc == -2) // error
 876           {
 877             cfg_parse_done (& cfg_state);
 878             return SCPE_ARG;
 879           }
 880 
 881         const char * p = scu_config_list [rc].name;
 882         if (strcmp (p, "mode") == 0)
 883           sw -> mode = (uint) v;
 884         else if (strcmp (p, "maska") == 0)
 885           {
 886             if (v == -1)
 887               sw -> mask_enable [0] = false;
 888             else
 889               {
 890                 sw -> mask_enable [0] = true;
 891                 sw -> mask_assignment [0] = (uint) v;
 892               }
 893           }
 894         else if (strcmp (p, "maskb") == 0)
 895           {
 896             if (v == -1)
 897               sw -> mask_enable [1] = false;
 898             else
 899               {
 900                 sw -> mask_enable [1] = true;
 901                 sw -> mask_assignment [1] = (uint) v;
 902               }
 903           }
 904         else if (strcmp (p, "port0") == 0)
 905           sw -> port_enable [0] = (uint) v;
 906         else if (strcmp (p, "port1") == 0)
 907           sw -> port_enable [1] = (uint) v;
 908         else if (strcmp (p, "port2") == 0)
 909           sw -> port_enable [2] = (uint) v;
 910         else if (strcmp (p, "port3") == 0)
 911           sw -> port_enable [3] = (uint) v;
 912         else if (strcmp (p, "port4") == 0)
 913           sw -> port_enable [4] = (uint) v;
 914         else if (strcmp (p, "port5") == 0)
 915           sw -> port_enable [5] = (uint) v;
 916         else if (strcmp (p, "port6") == 0)
 917           sw -> port_enable [6] = (uint) v;
 918         else if (strcmp (p, "port7") == 0)
 919           sw -> port_enable [7] = (uint) v;
 920         else if (strcmp (p, "lwrstoresize") == 0)
 921           sw -> lower_store_size = (uint) v;
 922         else if (strcmp (p, "cyclic") == 0)
 923           sw -> cyclic = (uint) v;
 924         else if (strcmp (p, "nea") == 0)
 925           sw -> nea = (uint) v;
 926         else if (strcmp (p, "onl") == 0)
 927           sw -> onl = (uint) v;
 928         else if (strcmp (p, "int") == 0)
 929           sw -> interlace = (uint) v;
 930         else if (strcmp (p, "lwr") == 0)
 931           sw -> lwr = (uint) v;
 932         else if (strcmp (p, "elapsed_days") == 0)
 933           scu [scu_unit_idx].elapsed_days = (uint) v;
 934         else if (strcmp (p, "steady_clock") == 0)
 935           scu [scu_unit_idx].steady_clock = (uint) v;
 936         else if (strcmp (p, "bullet_time") == 0)
 937           scu [scu_unit_idx].bullet_time = (uint) v;
 938         else if (strcmp (p, "y2k") == 0)
 939           scu [scu_unit_idx].y2k = (uint) v;
 940         else
 941           {
 942             sim_printf ("error: scu_set_config: invalid cfg_parse rc <%d>\n",
 943                          rc);
 944             cfg_parse_done (& cfg_state);
 945             return SCPE_ARG;
 946           }
 947       } // process statements
 948     cfg_parse_done (& cfg_state);
 949     return SCPE_OK;
 950   }
 951 
 952 static MTAB scu_mod [] =
 953   {
 954     {
 955       MTAB_XTD | MTAB_VUN | \
 956       MTAB_NMO | MTAB_VALR,                          /* Mask               */
 957       0,                                             /* Match              */
 958       (char *) "CONFIG",                             /* Print string       */
 959       (char *) "CONFIG",                             /* Match string       */
 960       scu_set_config,                                /* Validation routine */
 961       scu_show_config,                               /* Display routine    */
 962       NULL,                                          /* Value descriptor   */
 963       NULL                                           /* Help               */
 964     },
 965     {
 966       MTAB_XTD | MTAB_VDV | \
 967       MTAB_NMO | MTAB_VALR,                          /* Mask               */
 968       0,                                             /* Match              */
 969       (char *) "NUNITS",                             /* Print string       */
 970       (char *) "NUNITS",                             /* Match string       */
 971       scu_set_nunits,                                /* Validation routine */
 972       scu_show_nunits,                               /* Display routine    */
 973       (char *) "Number of SCU units in the system",  /* Value descriptor   */
 974       NULL                                           /* Help               */
 975     },
 976     {
 977       MTAB_XTD | MTAB_VUN | \
 978       MTAB_NMO | MTAB_VALR,                          /* Mask               */
 979       0,                                             /* Match              */
 980       (char *) "STATE",                              /* Print string       */
 981       (char *) "STATE",                              /* Match string       */
 982       NULL,                                          /* Validation routine */
 983       scu_show_state,                                /* Display routine    */
 984       (char *) "SCU unit internal state",            /* Value descriptor   */
 985       NULL                                           /* Help               */
 986     },
 987     {
 988       MTAB_XTD | MTAB_VUN | \
 989       MTAB_NMO | MTAB_VALR,                          /* Mask               */
 990       0,                                             /* Match              */
 991       (char *) "RESET",                              /* Print string       */
 992       (char *) "RESET",                              /* Match string       */
 993       scu_reset_unit,                                /* Validation routine */
 994       NULL,                                          /* Display routine    */
 995       (char *) "reset SCU unit",                     /* Value descriptor   */
 996       NULL                                           /* Help               */
 997     },
 998     {
 999       0, 0, NULL, NULL, NULL, NULL, NULL, NULL
1000     }
1001   };
1002 
1003 //static t_stat scu_reset (DEVICE *dptr);
1004 
1005 static DEBTAB scu_dt [] =
1006   {
1007     { (char *) "TRACE",  DBG_TRACE,  NULL },
1008     { (char *) "NOTIFY", DBG_NOTIFY, NULL },
1009     { (char *) "INFO",   DBG_INFO,   NULL },
1010     { (char *) "ERR",    DBG_ERR,    NULL },
1011     { (char *) "WARN",   DBG_WARN,   NULL },
1012     { (char *) "DEBUG",  DBG_DEBUG,  NULL },
1013     { (char *) "INTR",   DBG_INTR,   NULL }, // Don't move as it messes up DBG messages
1014     { (char *) "ALL",    DBG_ALL,    NULL },
1015     {  NULL,             0,          NULL }
1016   };
1017 
1018 DEVICE scu_dev =
1019   {
1020     (char *) "SCU",  /* Name                */
1021     scu_unit,        /* Units               */
1022     NULL,            /* Registers           */
1023     scu_mod,         /* Modifiers           */
1024     N_SCU_UNITS,     /* #Units              */
1025     10,              /* Address radix       */
1026     8,               /* Address width       */
1027     1,               /* Address increment   */
1028     8,               /* Data radix          */
1029     8,               /* Data width          */
1030     NULL,            /* Examine routine     */
1031     NULL,            /* Deposit routine     */
1032     & scu_reset,     /* Reset routine       */
1033     NULL,            /* Boot routine        */
1034     NULL,            /* Attach routine      */
1035     NULL,            /* Detach routine      */
1036     NULL,            /* Context             */
1037     DEV_DEBUG,       /* Flags               */
1038     0,               /* Debug control flags */
1039     scu_dt,          /* Debug flag names    */
1040     NULL,            /* Memory size change  */
1041     NULL,            /* Logical name        */
1042     NULL,            /* Help                */
1043     NULL,            /* Attach_help         */
1044     NULL,            /* Help_ctx            */
1045     NULL,            /* Description         */
1046     NULL             /* End                 */
1047   };
1048 
1049 static void dump_intr_regs (char * ctx, uint scu_unit_idx)
     /* [previous][next][first][last][top][bottom][index][help] */
1050   {
1051 #if defined(TESTING)
1052     scu_t * up = scu + scu_unit_idx;
1053     cpu_state_t * cpup = _cpup;
1054 
1055     sim_debug (DBG_DEBUG, & scu_dev,
1056                "%s A: mask %011o enable %o assignment %o\n",
1057                ctx, up -> exec_intr_mask [0], up -> mask_enable [0],
1058                up -> mask_assignment [0]);
1059     sim_debug (DBG_DEBUG, & scu_dev,
1060                "%s B: mask %011o enable %o assignment %o\n",
1061                ctx, up -> exec_intr_mask [1], up -> mask_enable [1],
1062                up -> mask_assignment [1]);
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1110 #endif
1111    }
1112 
1113 void scu_unit_reset (int scu_unit_idx)
     /* [previous][next][first][last][top][bottom][index][help] */
1114   {
1115     scu_t * up = scu + scu_unit_idx;
1116     struct config_switches * sw = config_switches + scu_unit_idx;
1117 
1118     for (int i = 0; i < N_SCU_PORTS; i ++)
1119       {
1120         up -> port_enable [i] = sw -> port_enable [i];
1121       }
1122 
1123     for (int i = 0; i < N_ASSIGNMENTS; i ++)
1124       {
1125         up -> mask_enable [i]     = sw -> mask_enable [i];
1126         up -> mask_assignment [i] = sw -> mask_assignment [i];
1127       }
1128     up -> lower_store_size = sw -> lower_store_size;
1129     up -> cyclic           = sw -> cyclic;
1130     up -> nea              = sw -> nea;
1131     up -> onl              = sw -> onl;
1132     up -> interlace        = sw -> interlace;
1133     up -> lwr              = sw -> lwr;
1134 
1135 // This is to allow the CPU reset to update the memory map. IAC clears the
1136 // attached SCUs; they clear the attached IOMs.
1137 
1138     for (uint port_num = 0; port_num < N_SCU_PORTS; port_num ++)
1139       {
1140         struct ports * portp = & scu [scu_unit_idx].ports [port_num];
1141         if (portp->type != ADEV_IOM)
1142           continue;
1143         //if (! scu [scu_unit_idx].port_enable [scu_port_num])
1144           //continue;
1145         iom_unit_reset_idx ((uint) portp->dev_idx);
1146       }
1147 
1148 // CAC - These settings were reversed engineer from the code instead
1149 // of from the documentation. In case of issues, try fixing these, not the
1150 // code.
1151 
1152     for (int i = 0; i < N_ASSIGNMENTS; i ++)
1153       {
1154         // XXX Hack for t4d
1155         up -> exec_intr_mask [i] = 037777777777;
1156       }
1157   }
1158 
1159 t_stat scu_reset (UNUSED DEVICE * dptr)
     /* [previous][next][first][last][top][bottom][index][help] */
1160   {
1161     // On reset, instantiate the config switch settings
1162 
1163     for (int scu_unit_idx = 0; scu_unit_idx < N_SCU_UNITS_MAX; scu_unit_idx ++)
1164       scu_unit_reset (scu_unit_idx);
1165     return SCPE_OK;
1166   }
1167 
1168 // ============================================================================
1169 
1170 #if defined(THREADZ) || defined(LOCKLESS)
1171 static pthread_mutex_t clock_lock = PTHREAD_MUTEX_INITIALIZER;
1172 #endif
1173 
1174 // The SCU clock is 52 bits long; fits in t_uint64
1175 static uint64 set_SCU_clock (cpu_state_t * cpup, uint scu_unit_idx)
     /* [previous][next][first][last][top][bottom][index][help] */
1176   {
1177 #if defined(THREADZ) || defined(LOCKLESS)
1178     pthread_mutex_lock (& clock_lock);
1179 #endif
1180 
1181 // The emulator supports two clock models: steady and real
1182 // In steady mode the time of day is coupled to the instruction clock,
1183 // allowing reproducible behavior. In real, the clock is
1184 // coupled to the actual time-of-day.
1185 
1186     if (scu [0].steady_clock)
1187       {
1188         // The is a bit of code that is waiting for 5000 ms; this
1189         // fools into going faster
1190 #if defined(NEED_128)
1191         uint128 big = construct_128 (0, cpu.instrCnt);
1192         // Sync up the clock and the TR; see wiki page "CAC 08-Oct-2014"
1193         //big *= 4u;
1194         big = lshift_128 (big, 2);
1195         if (scu [0].bullet_time)
1196           big = multiply_128 (big, construct_128 (0, 10000u));
1197 
1198         //big += scu [0].elapsed_days * 1000000llu * 60llu * 60llu * 24llu;
1199         uint128 days = construct_128 (0, scu[0].elapsed_days);
1200         days         = multiply_128 (days, construct_128 (0, 1000000));
1201         days         = multiply_128 (days, construct_128 (0, 60 * 60 * 24));
1202         big          = add_128 (big, days);
1203 #else
1204         __uint128_t big = cpu.instrCnt;
1205         // Sync up the clock and the TR; see wiki page "CAC 08-Oct-2014"
1206         big *= 4u;
1207         //big /= 100u;
1208         if (scu [0].bullet_time)
1209           big *= 10000;
1210 
1211         big += scu [0].elapsed_days * 1000000llu * 60llu * 60llu * 24llu;
1212 #endif
1213 
1214         // Boot time
1215 
1216         // load_fnp is complaining that FNP core image is more than 5 years old; try
1217         // moving the 'boot time' back to MR12.3 release date. (12/89 according to
1218         // https://www.multicians.org/chrono.html
1219 
1220         // date -d "1990-01-01 00:00:00 -9" +%s
1221         // 631184400
1222         // For debugging MR12.3 and earlier with steady_clock, uncomment --
1223         // uint64 UNIX_secs = 631184400;
1224 
1225         // Otherwise, we'll use the current time as the steady_clock starting point --
1226         uint64 UNIX_secs = (uint64)time(NULL);
1227 
1228 #if defined(NEED_128)
1229         uint64 UNIX_usecs = UNIX_secs * 1000000llu + big.l;
1230 #else
1231         uint64 UNIX_usecs = UNIX_secs * 1000000llu + (uint64) big;
1232 #endif
1233         // now determine uSecs since Jan 1, 1901 ...
1234         uint64 Multics_usecs = 2177452800000000llu + UNIX_usecs;
1235 
1236         // The casting to uint show be okay; both are 64 bit, so if
1237         // user_correction is <0, it will come out in the wash ok.
1238         Multics_usecs += (uint64) scu [scu_unit_idx].user_correction;
1239 
1240         // The get calendar clock function is guaranteed to return
1241         // different values on successive calls.
1242 
1243         if (scu [scu_unit_idx].last_time >= Multics_usecs)
1244           {
1245             sim_debug (DBG_TRACE, & scu_dev, "finagle clock\n");
1246             Multics_usecs = scu [scu_unit_idx].last_time + 1;
1247           }
1248         scu [scu_unit_idx].last_time = Multics_usecs;
1249         goto done;
1250       }
1251 
1252     // The calendar clock consists of a 52-bit register which counts
1253     // microseconds and is readable as a double-precision integer by a
1254     // single instruction from any central processor. This rate is in
1255     // the same order of magnitude as the instruction processing rate of
1256     // the GE-645, so that timing of 10-instruction subroutines is
1257     // meaningful. The register is wide enough that overflow requires
1258     // several tens of years; thus it serves as a calendar containing
1259     // the number of microseconds since 0000 GMT, January 1, 1901
1260     ///  Secs from Jan 1, 1901 to Jan 1, 1970 - 2 177 452 800 Seconds
1261     /// uSecs from Jan 1, 1901 to Jan 1, 1970 - 2 177 452 800 000 000 uSeconds
1262 
1263     struct timeval now;
1264     gettimeofday(& now, NULL);
1265 
1266     if (scu [0].y2k) // Apply clock skew when Y2K mode enabled
1267       {
1268         // Back the clock up to just after the MR12.5 release
1269         // $ date --date='30 years ago' +%s ; date +%s
1270         // 1685451324
1271         // 7738766524
1272         now.tv_sec -= (1685451324 - 738766524); // XXX(jhj): make dynamic!
1273       }
1274     uint64 UNIX_secs  = (uint64) now.tv_sec;
1275     uint64 UNIX_usecs = UNIX_secs * 1000000LL + (uint64) now.tv_usec;
1276 
1277     static uint64 last_UNIX_usecs = 0;
1278     if ( (!sim_quiet) && (UNIX_usecs < last_UNIX_usecs))
1279       {
1280         if (gtod_warned < 11)
1281           {
1282             sim_warn ("\rHost clock went backwards %llu uS!\r\n",
1283                       (unsigned long long)(last_UNIX_usecs - UNIX_usecs));
1284             gtod_warned++;
1285           }
1286         else if (gtod_warned == 11)
1287           {
1288             sim_warn ("\rHost clock went backwards %llu uS!  Suppressing further warnings.\r\n",
1289                       (unsigned long long)(last_UNIX_usecs - UNIX_usecs));
1290             gtod_warned++;
1291           }
1292       }
1293     last_UNIX_usecs = UNIX_usecs;
1294 
1295     // now determine uSecs since Jan 1, 1901 ...
1296     uint64 Multics_usecs = 2177452800000000LL + UNIX_usecs;
1297 
1298     // Correction factor from the set time command
1299 
1300     // The casting to uint show be okay; both are 64 bit, so if
1301     // user_correction is <0, it will come out in the wash ok.
1302     Multics_usecs += (uint64) scu [scu_unit_idx].user_correction;
1303 
1304     if (scu [scu_unit_idx].last_time >= Multics_usecs)
1305         Multics_usecs = scu [scu_unit_idx].last_time + 1;
1306     scu [scu_unit_idx].last_time = Multics_usecs;
1307 
1308 done:
1309 #if defined(THREADZ) || defined(LOCKLESS)
1310     pthread_mutex_unlock (& clock_lock);
1311 #endif
1312 
1313     return scu [scu_unit_idx].last_time;
1314   }
1315 
1316 //static char pcellb [N_CELL_INTERRUPTS + 1];
1317 static char * pcells (uint scu_unit_idx, char * buf)
     /* [previous][next][first][last][top][bottom][index][help] */
1318   {
1319     for (uint i = 0; i < N_CELL_INTERRUPTS; i ++)
1320       {
1321         if (scu [scu_unit_idx].cells [i])
1322           buf [i] = '1';
1323         else
1324           buf [i] = '0';
1325       }
1326     buf [N_CELL_INTERRUPTS] = '\0';
1327     return buf;
1328   }
1329 
1330 // Either an interrupt has arrived on a port, or a mask register has
1331 // been updated. Bring the CPU up date on the interrupts.
1332 
1333 // threadz notes:
1334 //
1335 // deliver_interrupts is called either from a CPU instruction or from
1336 // IOM set_general_interrupt on the IOM thread.
1337 //
1338 // potential race conditions:
1339 //   CPU variables: XIP
1340 //   SCU variables: cells, mask_enable, exec_intr_mask, mask assignment
1341 
1342 // Always called with SCU lock set
1343 
1344 static void deliver_interrupts (uint scu_unit_idx)
     /* [previous][next][first][last][top][bottom][index][help] */
1345   {
1346 #if defined(TESTING)
1347     cpu_state_t * cpup = _cpup;
1348     sim_debug (DBG_DEBUG, & scu_dev, "deliver_interrupts %o\n", scu_unit_idx);
1349 #endif
1350     for (uint cpun = 0; cpun < cpu_dev.numunits; cpun ++)
1351       {
1352         cpus[cpun].events.XIP[scu_unit_idx] = false;
1353       }
1354 
1355 // If the CIOC generates marker and terminate interrupts, they will be posted simultaneously.
1356 // Since the interrupts are recognized by priority and terminate has a higher priority then
1357 // marker, if will be delivered first. The following code will deliver marker before terminate.
1358 
1359 #if defined(REORDER)
1360     for (uint jnum = 0; jnum < N_CELL_INTERRUPTS; jnum ++)
1361       {
1362         static const uint reorder[N_CELL_INTERRUPTS] = {
1363            0,  1,  2,  3,  4,  5,  6,  7,
1364           16, 17, 18, 29, 20, 21, 22, 23,
1365            8,  9, 10, 11, 12, 13, 14, 15,
1366           25, 25, 26, 27, 28, 29, 30, 31 };
1367         uint inum = reorder[jnum];
1368         if (! scu [scu_unit_idx].cells [inum])
1369           continue; //
1370         sim_debug (DBG_DEBUG, & scu_dev, "trying to deliver %d\n", inum);
1371         sim_debug (DBG_INTR, & scu_dev,
1372                    "scu %u trying to deliver %d\n", scu_unit_idx, inum);
1373 
1374         for (uint pima = 0; pima < N_ASSIGNMENTS; pima ++) // A, B
1375           {
1376             //sim_debug (DBG_DEBUG, & scu_dev,
1377             //           "trying inum %u pima %u enable %u\n"
1378             //           , inum, pima, scu [scu_unit_idx].mask_enable [pima]);
1379             if (scu [scu_unit_idx].mask_enable [pima] == 0)
1380               continue;
1381             uint mask = scu [scu_unit_idx].exec_intr_mask [pima];
1382             uint port = scu [scu_unit_idx].mask_assignment [pima];
1383             //sim_debug (DBG_DEBUG, & scu_dev,
1384             //           "mask %u port %u type %u cells %o\n",
1385             //           mask, port, scu [scu_unit_idx].ports [port].type,
1386             //           scu [scu_unit_idx].cells [inum]);
1387             if (scu [scu_unit_idx].ports [port].type != ADEV_CPU)
1388               continue;
1389             if ((mask & (1u << (31 - inum))) != 0)
1390               {
1391                 uint sn = 0;
1392                 if (scu[scu_unit_idx].ports[port].is_exp)
1393                   {
1394                     sn = (uint) scu[scu_unit_idx].ports[port].xipmaskval;
1395                     if (sn >= N_SCU_SUBPORTS)
1396                       {
1397                         sim_warn ("XIP mask not set; defaulting to subport 0\n");
1398                         sn = 0;
1399                       }
1400                   }
1401                 if (! cables->scu_to_cpu[scu_unit_idx][port][sn].in_use)
1402                   {
1403                     sim_warn ("bad scu_unit_idx %u\n", scu_unit_idx);
1404                     continue;
1405                   }
1406                 uint cpu_unit_udx = cables->scu_to_cpu[scu_unit_idx][port][sn].cpu_unit_idx;
1407 # if defined(THREADZ) || defined(LOCKLESS)
1408                 cpus[cpu_unit_udx].events.XIP[scu_unit_idx] = true;
1409 #  if defined(TESTING)
1410                 HDBGIntrSet (inum, cpu_unit_udx, scu_unit_idx, __func__);
1411 #  endif
1412                 createCPUThread((uint) cpu_unit_udx);
1413 #  if !defined(NO_TIMEWAIT)
1414                 wakeCPU ((uint) cpu_unit_udx);
1415 #  endif
1416                 sim_debug (DBG_DEBUG, & scu_dev,
1417                            "interrupt set for CPU %d SCU %d\n",
1418                            cpu_unit_udx, scu_unit_idx);
1419 # else // ! THREADZ
1420 //if (cpu_unit_udx && ! cpu.isRunning) sim_printf ("starting CPU %c\n", cpu_unit_udx + 'A');
1421 #  if defined(ROUND_ROBIN)
1422                 cpus[cpu_unit_udx].isRunning = true;
1423 #  endif
1424                 cpus[cpu_unit_udx].events.XIP[scu_unit_idx] = true;
1425 sim_debug (DBG_DEBUG, & scu_dev, "interrupt set for CPU %d SCU %d\n", cpu_unit_udx, scu_unit_idx);
1426                 sim_debug (DBG_INTR, & scu_dev,
1427                            "XIP set for SCU %d\n", scu_unit_idx);
1428 # endif // ! THREADZ
1429               }
1430           }
1431       }
1432 #else // !REORDER
1433     for (uint inum = 0; inum < N_CELL_INTERRUPTS; inum ++)
1434       {
1435         if (! scu [scu_unit_idx].cells [inum])
1436           continue; //
1437         sim_debug (DBG_DEBUG, & scu_dev, "trying to deliver %d\n", inum);
1438         sim_debug (DBG_INTR, & scu_dev,
1439                    "scu %u trying to deliver %d\n", scu_unit_idx, inum);
1440 
1441         for (uint pima = 0; pima < N_ASSIGNMENTS; pima ++) // A, B
1442           {
1443             //sim_debug (DBG_DEBUG, & scu_dev,
1444             //           "trying inum %u pima %u enable %u\n"
1445             //           , inum, pima, scu [scu_unit_idx].mask_enable [pima]);
1446             if (scu [scu_unit_idx].mask_enable [pima] == 0)
1447               continue;
1448             uint mask = scu [scu_unit_idx].exec_intr_mask [pima];
1449             uint port = scu [scu_unit_idx].mask_assignment [pima];
1450             //sim_debug (DBG_DEBUG, & scu_dev,
1451             //           "mask %u port %u type %u cells %o\n",
1452             //           mask, port, scu [scu_unit_idx].ports [port].type,
1453             //           scu [scu_unit_idx].cells [inum]);
1454             if (scu [scu_unit_idx].ports [port].type != ADEV_CPU)
1455               continue;
1456             if ((mask & (1u << (31 - inum))) != 0)
1457               {
1458                 uint sn = 0;
1459                 if (scu[scu_unit_idx].ports[port].is_exp)
1460                   {
1461                     sn = (uint) scu[scu_unit_idx].ports[port].xipmaskval;
1462                     if (sn >= N_SCU_SUBPORTS)
1463                       {
1464                         sim_warn ("XIP mask not set; defaulting to subport 0\n");
1465                         sn = 0;
1466                       }
1467                   }
1468                 if (! cables->scu_to_cpu[scu_unit_idx][port][sn].in_use)
1469                   {
1470                     sim_warn ("bad scu_unit_idx %u\n", scu_unit_idx);
1471                     continue;
1472                   }
1473                 uint cpu_unit_udx = cables->scu_to_cpu[scu_unit_idx][port][sn].cpu_unit_idx;
1474 # if defined(THREADZ) || defined(LOCKLESS)
1475                 cpus[cpu_unit_udx].events.XIP[scu_unit_idx] = true;
1476 #  if defined(TESTING)
1477                 HDBGIntrSet (inum, cpu_unit_udx, scu_unit_idx, __func__);
1478 #  endif
1479                 createCPUThread((uint) cpu_unit_udx);
1480 #  if !defined(NO_TIMEWAIT)
1481                 wakeCPU ((uint) cpu_unit_udx);
1482 #  endif
1483                 sim_debug (DBG_DEBUG, & scu_dev,
1484                            "interrupt set for CPU %d SCU %d\n",
1485                            cpu_unit_udx, scu_unit_idx);
1486 # else // ! THREADZ
1487 //if (cpu_unit_udx && ! cpu.isRunning) sim_printf ("starting CPU %c\n", cpu_unit_udx + 'A');
1488 #  if defined(ROUND_ROBIN)
1489                 cpus[cpu_unit_udx].isRunning = true;
1490 #  endif
1491                 cpus[cpu_unit_udx].events.XIP[scu_unit_idx] = true;
1492 sim_debug (DBG_DEBUG, & scu_dev, "interrupt set for CPU %d SCU %d\n", cpu_unit_udx, scu_unit_idx);
1493                 sim_debug (DBG_INTR, & scu_dev,
1494                            "XIP set for SCU %d\n", scu_unit_idx);
1495 # endif // ! THREADZ
1496               }
1497           }
1498       }
1499 #endif // REORDER
1500   }
1501 
1502 t_stat scu_smic (uint scu_unit_idx, uint UNUSED cpu_unit_udx,
     /* [previous][next][first][last][top][bottom][index][help] */
1503                  uint UNUSED cpu_port_num, word36 rega)
1504   {
1505 #if defined(TESTING)
1506     cpu_state_t * cpup = _cpup;
1507 #endif
1508 #if defined(THREADZ) || defined(LOCKLESS)
1509     lock_scu ();
1510 #endif
1511 // smic can set cells but not reset them...
1512 
1513     if (getbits36_1 (rega, 35))
1514       {
1515         for (uint i = 0; i < 16; i ++)
1516           {
1517             if (getbits36_1 (rega, i))
1518               scu [scu_unit_idx].cells [i + 16] = 1;
1519           }
1520         char pcellb [N_CELL_INTERRUPTS + 1];
1521         sim_debug (DBG_TRACE, & scu_dev,
1522                    "SMIC low: Unit %u Cells: %s\n",
1523                    scu_unit_idx, pcells (scu_unit_idx, pcellb));
1524       }
1525     else
1526       {
1527         for (uint i = 0; i < 16; i ++)
1528           {
1529             if (getbits36_1 (rega, i))
1530               scu [scu_unit_idx].cells [i] = 1;
1531           }
1532         char pcellb [N_CELL_INTERRUPTS + 1];
1533         sim_debug (DBG_TRACE, & scu_dev,
1534                    "SMIC high: Unit %d Cells: %s\n",
1535                    scu_unit_idx, pcells (scu_unit_idx, pcellb));
1536       }
1537 
1538 
1539 
1540 
1541 
1542 
1543 
1544 
1545 
1546 
1547 
1548 
1549 
1550 
1551 
1552 
1553 
1554 
1555 
1556 
1557 
1558 
1559 
1560 
1561 
1562     dump_intr_regs ("smic", scu_unit_idx);
1563     deliver_interrupts (scu_unit_idx);
1564 #if defined(THREADZ) || defined(LOCKLESS)
1565     unlock_scu ();
1566 #endif
1567     return SCPE_OK;
1568   }
1569 
1570 // system controller and the function to be performed as follows:
1571 //
1572 //  Effective  Function
1573 //  Address
1574 //  y0000x     C(system controller mode register) -> C(AQ)
1575 //  y0001x     C(system controller configuration switches) -> C(AQ)
1576 //  y0002x     C(mask register assigned to port 0) -> C(AQ)
1577 //  y0012x     C(mask register assigned to port 1) -> C(AQ)
1578 //  y0022x     C(mask register assigned to port 2) -> C(AQ)
1579 //  y0032x     C(mask register assigned to port 3) -> C(AQ)
1580 //  y0042x     C(mask register assigned to port 4) -> C(AQ)
1581 //  y0052x     C(mask register assigned to port 5) -> C(AQ)
1582 //  y0062x     C(mask register assigned to port 6) -> C(AQ)
1583 //  y0072x     C(mask register assigned to port 7) -> C(AQ)
1584 //  y0003x     C(interrupt cells) -> C(AQ)
1585 //
1586 //  y0004x
1587 //    or       C(calendar clock) -> C(AQ)
1588 //  y0005x
1589 //
1590 //  y0006x
1591 //    or C(store unit mode register) -> C(AQ)
1592 //  y0007x
1593 //
1594 // where: y = value of C(TPR.CA)0,2 (C(TPR.CA)1,2 for the DPS 8M
1595 // processor) used to select the system controller
1596 // x = any octal digit
1597 //
1598 
1599 t_stat scu_sscr (cpu_state_t * cpup, uint scu_unit_idx, UNUSED uint cpu_unit_udx,
     /* [previous][next][first][last][top][bottom][index][help] */
1600                  UNUSED uint cpu_port_num, word18 addr,
1601                  word36 rega, word36 regq)
1602   {
1603     sim_debug (DBG_DEBUG, & scu_dev, "sscr SCU unit %o\n", scu_unit_idx);
1604 
1605     // Only valid for a 4MW SCU
1606 
1607     if (scu_unit_idx >= scu_dev.numunits)
1608       {
1609 // XXX should this be a store fault?
1610         sim_warn ("%s: scu_unit_idx out of range %d\n",
1611                    __func__, scu_unit_idx);
1612         return SCPE_OK;
1613       }
1614 
1615     // BCE uses clever addressing schemes to select SCUs; it appears we need
1616     // to be more selecting in picking out the function bits;
1617     //uint function = (addr >> 3) & 07777;
1618     uint function = (addr >> 3) & 07;
1619 
1620     // See scs.incl.pl1
1621 
1622     if (config_switches [scu_unit_idx].mode != MODE_PROGRAM)
1623       {
1624         sim_warn ("%s: SCU mode is 'MANUAL', not 'PROGRAM' -- sscr "
1625                    "not allowed to set switches.\n",
1626                    __func__);
1627 // XXX [CAC] Setting an unassigned register generates a STORE FAULT;
1628 // this probably should as well
1629         return SCPE_OK;
1630       }
1631 
1632 // Not used by 4MW
1633 
1634     switch (function)
1635       {
1636         case 00000: // Set system controller mode register
1637           {
1638 #if defined(THREADZ) || defined(LOCKLESS)
1639             lock_scu ();
1640 #endif
1641             scu [scu_unit_idx].id = (word4) getbits36_4 (regq, 50 - 36);
1642             scu [scu_unit_idx].mode_reg = getbits36_18 (regq, 54 - 36);
1643 #if defined(THREADZ) || defined(LOCKLESS)
1644             unlock_scu ();
1645 #endif
1646           }
1647           break;
1648 
1649         case 00001: // Set system controller configuration register
1650                     // (4MW SCU only)
1651           {
1652             sim_debug (DBG_DEBUG, & scu_dev,
1653                        "sscr 1 %d A: %012"PRIo64" Q: %012"PRIo64"\n",
1654                        scu_unit_idx, rega, regq);
1655 #if defined(THREADZ) || defined(LOCKLESS)
1656             lock_scu ();
1657 #endif
1658             scu_t * up = scu + scu_unit_idx;
1659             for (int maskab = 0; maskab < 2; maskab ++)
1660               {
1661                 word9 mask = ((maskab ? regq : rega) >> 27) & 0777;
1662                 if (mask & 01)
1663                   {
1664                     up -> mask_enable [maskab] = 0;
1665                     sim_debug (DBG_DEBUG, & scu_dev,
1666                                "sscr %u mask disable  %d\n",
1667                                scu_unit_idx, maskab);
1668                   }
1669                 else
1670                   {
1671                     up -> mask_enable [maskab] = 1;
1672                     sim_debug (DBG_DEBUG, & scu_dev,
1673                                "sscr %u mask enable  %d\n",
1674                                scu_unit_idx, maskab);
1675                     for (int pn = 0; pn < N_SCU_PORTS; pn ++)
1676                       {
1677                         if ((2 << (N_SCU_PORTS - 1 - pn)) & mask)
1678                           {
1679                             up -> mask_assignment [maskab] = (uint) pn;
1680                             break;
1681                           }
1682                       }
1683 
1684                   }
1685                 sim_debug (DBG_INTR, & scu_dev,
1686                            "SCU%u SSCR1 mask %c enable set to %u assigned to "
1687                            "port %u\n",
1688                            scu_unit_idx, 'a' + maskab, up->mask_enable[maskab],
1689                            up->mask_assignment[maskab]);
1690               }
1691             // AN87-00A, pg 2-5, 2-6 specify which fields are and are not
1692             //  settable.
1693 
1694             //if (up -> lower_store_size != ((rega >> 24) & 07))
1695               //sim_printf ("??? The CPU tried to change the SCU store size\n");
1696             up -> lower_store_size = (rega >> 24) & 07;
1697             up -> cyclic           = (regq >>  8) & 0177;
1698             up -> nea              = (rega >>  6) & 0377;
1699             up -> onl              = (rega >> 20) & 017;
1700             up -> interlace        = (rega >>  5) &  1;
1701             up -> lwr              = (rega >>  4) &  1;
1702             up -> port_enable [0]  = (rega >>  3) & 01;
1703             up -> port_enable [1]  = (rega >>  2) & 01;
1704             up -> port_enable [2]  = (rega >>  1) & 01;
1705             up -> port_enable [3]  = (rega >>  0) & 01;
1706             up -> port_enable [4]  = (regq >>  3) & 01;
1707             up -> port_enable [5]  = (regq >>  2) & 01;
1708             up -> port_enable [6]  = (regq >>  1) & 01;
1709             up -> port_enable [7]  = (regq >>  0) & 01;
1710 
1711 #if defined(THREADZ) || defined(LOCKLESS)
1712             unlock_scu ();
1713 #endif
1714             // XXX A, A1, B, B1, INT, LWR not implemented. (AG87-00A pgs 2-5,
1715             //  2-6)
1716             break;
1717           }
1718 
1719         case 00002: // Set mask register port 0
1720         //case 00012: // Set mask register port 1
1721         //case 00022: // Set mask register port 2
1722         //case 00032: // Set mask register port 3
1723         //case 00042: // Set mask register port 4
1724         //case 00052: // Set mask register port 5
1725         //case 00062: // Set mask register port 6
1726         //case 00072: // Set mask register port 7
1727           {
1728 #if defined(THREADZ) || defined(LOCKLESS)
1729             lock_scu ();
1730 #endif
1731             uint port_num = (addr >> 6) & 07;
1732             sim_debug (DBG_DEBUG, & scu_dev, "Set mask register port %d to "
1733                        "%012"PRIo64",%012"PRIo64"\n",
1734                        port_num, rega, regq);
1735 
1736             // Find mask reg assigned to specified port
1737             int mask_num = -1;
1738             uint n_masks_found = 0;
1739             for (int p = 0; p < N_ASSIGNMENTS; p ++)
1740               {
1741                 //if (scup -> interrupts [p].mask_assign.unassigned)
1742                 if (scu [scu_unit_idx].mask_enable [p] == 0)
1743                   continue;
1744                 //if (scup -> interrupts [p].mask_assign.port == port_num)
1745                 if (scu [scu_unit_idx ].mask_assignment [p] == port_num)
1746                   {
1747                     if (n_masks_found == 0)
1748                       mask_num = p;
1749                     n_masks_found ++;
1750                   }
1751               }
1752 
1753             if (! n_masks_found)
1754               {
1755 // According to bootload_tape_label.alm, this condition is OK
1756                 sim_debug (DBG_WARN, & scu_dev,
1757                            "%s: No masks assigned to cpu on port %d\n",
1758                            __func__, port_num);
1759 #if defined(THREADZ) || defined(LOCKLESS)
1760                 unlock_scu ();
1761 #endif
1762                 return SCPE_OK;
1763               }
1764 
1765             if (n_masks_found > 1)
1766               {
1767                 // Not legal for Multics
1768                 sim_debug (DBG_WARN, & scu_dev,
1769                            "%s: Multiple masks assigned to cpu on port %d\n",
1770                            __func__, port_num);
1771               }
1772 
1773             // See AN87
1774             //scup -> interrupts[mask_num].exec_intr_mask = 0;
1775             scu [scu_unit_idx].exec_intr_mask [mask_num] = 0;
1776             scu [scu_unit_idx].exec_intr_mask [mask_num] |=
1777               ((word32) getbits36_16(rega, 0) << 16);
1778             scu [scu_unit_idx].exec_intr_mask [mask_num] |=
1779               getbits36_16(regq, 0);
1780 
1781 
1782 
1783 
1784 
1785 
1786 
1787 
1788 
1789             sim_debug (DBG_TRACE, & scu_dev,
1790                        "SSCR Set mask unit %u port %u mask_num %u "
1791                        "mask 0x%08x\n",
1792                        scu_unit_idx, port_num, mask_num,
1793                        scu [scu_unit_idx].exec_intr_mask [mask_num]);
1794             dump_intr_regs ("sscr set mask", scu_unit_idx);
1795             scu [scu_unit_idx].mask_enable [mask_num] = 1;
1796             sim_debug (DBG_INTR, & scu_dev,
1797                        "SCU%u SSCR2 exec_intr mask %c set to 0x%08x"
1798                        " and enabled.\n",
1799                        scu_unit_idx, 'a' + mask_num,
1800                        scu[scu_unit_idx].exec_intr_mask[mask_num]);
1801 
1802             deliver_interrupts (scu_unit_idx);
1803 #if defined(THREADZ) || defined(LOCKLESS)
1804             unlock_scu ();
1805 #endif
1806           }
1807           break;
1808 
1809         case 00003: // Set interrupt cells
1810           {
1811 #if defined(THREADZ) || defined(LOCKLESS)
1812             lock_scu ();
1813 #endif
1814             for (uint i = 0; i < 16; i ++)
1815               {
1816                 scu [scu_unit_idx].cells [i] =
1817                   getbits36_1 (rega, i) ? 1 : 0;
1818                 scu [scu_unit_idx].cells [i + 16] =
1819                   getbits36_1 (regq, i) ? 1 : 0;
1820               }
1821             char pcellb [N_CELL_INTERRUPTS + 1];
1822             sim_debug (DBG_TRACE, & scu_dev,
1823                        "SSCR Set int. cells: Unit %u Cells: %s\n",
1824                        scu_unit_idx, pcells (scu_unit_idx, pcellb));
1825             sim_debug (DBG_INTR, & scu_dev,
1826                        "SCU%u SSCR3  Set int. cells %s\n",
1827                        scu_unit_idx, pcells (scu_unit_idx, pcellb));
1828             dump_intr_regs ("sscr set interrupt cells", scu_unit_idx);
1829             deliver_interrupts (scu_unit_idx);
1830 #if defined(THREADZ) || defined(LOCKLESS)
1831             unlock_scu ();
1832 #endif
1833           }
1834           break;
1835 
1836         case 00004: // Set calendar clock (4MW SCU only)
1837         case 00005:
1838           {
1839             // AQ: 20-35 clock bits 0-15, 36-71 clock bits 16-51
1840             word16 b0_15   = (word16) getbits36_16 (cpu.rA, 20);
1841             word36 b16_51  = cpu.rQ;
1842             uint64 new_clk = (((uint64) b0_15) << 36) | b16_51;
1843 #if defined(THREADZ) || defined(LOCKLESS)
1844             lock_scu ();
1845 #endif
1846             scu [scu_unit_idx].user_correction =
1847               (int64) (new_clk - set_SCU_clock (cpup, scu_unit_idx));
1848 #if defined(THREADZ) || defined(LOCKLESS)
1849             unlock_scu ();
1850 #endif
1851             //sim_printf ("sscr %o\n", function);
1852           }
1853           break;
1854 
1855         case 00006: // Set unit mode register
1856         case 00007:
1857           // XXX See notes in AL39 sscr re: store unit selection
1858           //sim_printf ("sscr %o\n", function);
1859           sim_warn ("sscr set unit mode register\n");
1860           //return STOP_UNIMP;
1861           return SCPE_OK;
1862 
1863         default:
1864           sim_warn ("sscr unhandled code\n");
1865           //return STOP_UNIMP;
1866           return SCPE_OK;
1867           //sim_printf ("sscr %o\n", function);
1868       }
1869     return SCPE_OK;
1870   }
1871 
1872 t_stat scu_rscr (cpu_state_t * cpup, uint scu_unit_idx, uint cpu_unit_udx, word18 addr,
     /* [previous][next][first][last][top][bottom][index][help] */
1873                  word36 * rega, word36 * regq)
1874   {
1875     // Only valid for a 4MW SCU
1876 
1877     if (scu_unit_idx >= scu_dev.numunits)
1878       {
1879         sim_warn ("%s: scu_unit_idx out of range %d\n",
1880                    __func__, scu_unit_idx);
1881         return SCPE_OK;
1882       }
1883 
1884     // BCE uses clever addressing schemes to select SCUs; it appears we need
1885     // to be more selecting in picking out the function bits;
1886     //uint function = (addr >> 3) & 07777;
1887     uint function = (addr >> 3) & 07;
1888 
1889     //sim_printf ("rscr %o\n", function);
1890 
1891     // See scs.incl.pl1
1892 
1893     switch (function)
1894       {
1895         case 00000: // Read system controller mode register
1896           {
1897             // AN-87
1898             // 0..0 -> A
1899             // 0..0 -> Q 36-49 (0-13)
1900             // ID -> Q 50-53 (14-17)
1901             // MODE REG -> Q 54-71 (18-35)
1902             //
1903             //  ID: 0000  8034, 8035
1904             //      0001  Level 68 SC
1905             //      0010  Level 66 SCU
1906             // CAC: According to scr.incl.pl1. 0010 is a 4MW SCU
1907             // MODE REG: these fields are only used by T&D
1908             * rega = 0;
1909             //* regq = 0000002000000; // ID = 0010
1910             * regq = 0;
1911 #if defined(THREADZ) || defined(LOCKLESS)
1912             lock_scu ();
1913 #endif
1914             putbits36_4 (regq, 50 - 36, scu [scu_unit_idx].id);
1915             putbits36_18 (regq, 54 - 36, scu [scu_unit_idx].mode_reg);
1916 #if defined(THREADZ) || defined(LOCKLESS)
1917             unlock_scu ();
1918 #endif
1919             break;
1920           }
1921 
1922         case 00001: // Read system controller configuration register
1923           {
1924             // AN-87, scr.incl.pl1
1925             //
1926             // SCU:
1927             // reg A:
1928             //   MASK A | SIZE | A | A1 | B | B1 | PORT | 0 | MOD | NEA |
1929             //   INT | LWR | PMR 0-3
1930             // reg Q:
1931             //   MASK B | not used | CYCLIC PRIOR | not used | PMR 4-7
1932             //
1933             //   MASK A/B (9 bits): EIMA switch setting for mask A/B. The
1934             //    assigned port corresponds to the but position within the
1935             //    field. A bit in position 9 indicates that the mask is
1936             //    not assigned.
1937             // From scr.incl.pl1:
1938             // 400 => assigned to port 0
1939             //  .
1940             //  .
1941             // 002 => assigned to port 7
1942             // 001 => mask off */
1943 
1944             //
1945             //  SIZE (3 bits): Size of lower store
1946             //    000 = 32K ... 111 = 4M
1947             //
1948             //  A A1 B B1 (1 bit): store unit A/A1/B/B1 online
1949             //
1950             //  PORT (4 bits): Port number of the SCU port through which
1951             //    the RSCR instruction was received
1952             //
1953             //struct config_switches * sw = config_switches + scu_unit_idx;
1954             sim_debug (DBG_DEBUG, & scu_dev, "rscr 1 %d\n", scu_unit_idx);
1955 #if defined(THREADZ) || defined(LOCKLESS)
1956             lock_scu ();
1957 #endif
1958             scu_t * up = scu + scu_unit_idx;
1959             word9 maskab [2];
1960             for (int i = 0; i < 2; i ++)
1961               {
1962                 if (up -> mask_enable [i])
1963                   {
1964                     maskab [i] = (2 << (N_SCU_PORTS - 1 -
1965                                         up -> mask_assignment [i])) & 0777;
1966                   }
1967                 else
1968                   maskab [i] = 0001;
1969               }
1970 
1971             int scu_port_num = -1; // The port that the rscr instruction was
1972                                    // received on
1973 
1974             for (int pn = 0; pn < N_SCU_PORTS; pn ++)
1975               {
1976                 for (int sn = 0; sn < N_SCU_SUBPORTS; sn ++)
1977                   {
1978                     if (cables->scu_to_cpu[scu_unit_idx][pn][sn].in_use &&
1979                         cables->scu_to_cpu[scu_unit_idx][pn][sn].cpu_unit_idx ==
1980                           cpu_unit_udx)
1981                      {
1982                         scu_port_num = pn;
1983                         goto gotit;
1984                       }
1985                   }
1986               }
1987 gotit:;
1988             if (scu_port_num < 0)
1989               {
1990 #if defined(THREADZ) || defined(LOCKLESS)
1991                 unlock_scu ();
1992 #endif
1993                 sim_warn ("%s: can't find cpu port in the snarl of cables; "
1994                            "scu_unit_no %d, cpu_unit_udx %d\n",
1995                            __func__, scu_unit_idx, cpu_unit_udx);
1996                 return SCPE_OK;
1997               }
1998 
1999             // AN87, pg 2-5
2000             word36 a, q;
2001 
2002             a = 0;
2003 // (data, starting bit position, number of bits, value)
2004             putbits36_9 (& a,  0,  maskab [0]);
2005             putbits36_3 (& a,  9,  (word3) up -> lower_store_size);
2006             putbits36_4 (& a, 12,  (word4) up -> onl); // A, A1, B, B1 online
2007             putbits36_4 (& a, 16,  (word4) scu_port_num);
2008             putbits36_1 (& a, 21,  (word1) config_switches[scu_unit_idx].mode);
2009             putbits36_8 (& a, 22,  (word8) up -> nea);
2010             putbits36_1 (& a, 30,  (word1) up -> interlace);
2011             putbits36_1 (& a, 31,  (word1) up -> lwr);
2012             // XXX INT, LWR not implemented. (AG87-00A pgs 2-5. 2-6)
2013             // interlace <- 0
2014             // lower <- 0
2015             // Looking at scr_util.list, I *think* the port order
2016             // 0,1,2,3.
2017             putbits36_1 (& a, 32,  (word1) up -> port_enable [0]);
2018             putbits36_1 (& a, 33,  (word1) up -> port_enable [1]);
2019             putbits36_1 (& a, 34,  (word1) up -> port_enable [2]);
2020             putbits36_1 (& a, 35,  (word1) up -> port_enable [3]);
2021             * rega = a;
2022 
2023             q = 0;
2024             putbits36_9 (& q,  0,  maskab [1]);
2025             // cyclic prior <- 0
2026             putbits36_7 (& q, 57-36, (word7) up -> cyclic & MASK7);
2027             // Looking at scr_util.list, I *think* the port order
2028             // 0,1,2,3.
2029             putbits36_1 (& q, 32,  (word1) up -> port_enable [4]);
2030             putbits36_1 (& q, 33,  (word1) up -> port_enable [5]);
2031             putbits36_1 (& q, 34,  (word1) up -> port_enable [6]);
2032             putbits36_1 (& q, 35,  (word1) up -> port_enable [7]);
2033             * regq = q;
2034 
2035 #if defined(THREADZ) || defined(LOCKLESS)
2036             unlock_scu ();
2037 #endif
2038             sim_debug (DBG_DEBUG, & scu_dev,
2039                        "rscr 1 %d A: %012"PRIo64" Q: %012"PRIo64"\n",
2040                        scu_unit_idx, * rega, * regq);
2041             break;
2042           }
2043 
2044         case 00002: // mask register
2045           {
2046             uint port_num = (addr >> 6) & MASK3;
2047 #if defined(THREADZ) || defined(LOCKLESS)
2048             lock_scu ();
2049 #endif
2050             scu_t * up = scu + scu_unit_idx;
2051             uint mask_contents = 0;
2052             if (up -> mask_assignment [0] == port_num)
2053               {
2054                 mask_contents = up -> exec_intr_mask [0];
2055               }
2056             else if (up -> mask_assignment [1] == port_num)
2057               {
2058                 mask_contents = up -> exec_intr_mask [1];
2059               }
2060             mask_contents &= MASK32;
2061 
2062             * rega = 0;
2063             putbits36 (rega,  0, 16, (mask_contents >> 16) & MASK16);
2064             putbits36 (rega, 32,  1, up -> port_enable [0]);
2065             putbits36 (rega, 33,  1, up -> port_enable [1]);
2066             putbits36 (rega, 34,  1, up -> port_enable [2]);
2067             putbits36 (rega, 35,  1, up -> port_enable [3]);
2068 
2069             * regq = 0;
2070             putbits36 (rega,  0, 16, (mask_contents >>  0) & MASK16);
2071             putbits36 (regq, 32,  1, up -> port_enable [4]);
2072             putbits36 (regq, 33,  1, up -> port_enable [5]);
2073             putbits36 (regq, 34,  1, up -> port_enable [6]);
2074             putbits36 (regq, 35,  1, up -> port_enable [7]);
2075 
2076 #if defined(THREADZ) || defined(LOCKLESS)
2077             unlock_scu ();
2078 #endif
2079             sim_debug (DBG_TRACE, & scu_dev,
2080                        "RSCR mask unit %u port %u assigns %u %u mask 0x%08x\n",
2081                        scu_unit_idx, port_num, up -> mask_assignment [0],
2082                        up -> mask_assignment [1],
2083                        mask_contents);
2084           }
2085           break;
2086 
2087         case 00003: // Interrupt cells
2088           {
2089 #if defined(THREADZ) || defined(LOCKLESS)
2090             lock_scu ();
2091 #endif
2092             scu_t * up = scu + scu_unit_idx;
2093             // * rega = up -> exec_intr_mask [0];
2094             // * regq = up -> exec_intr_mask [1];
2095             for (uint i = 0; i < N_CELL_INTERRUPTS; i ++)
2096               {
2097                 word1 cell = up -> cells [i] ? 1 : 0;
2098                 if (i < 16)
2099                   putbits36_1 (rega, i, cell);
2100                 else
2101                   putbits36_1 (regq, i - 16, cell);
2102               }
2103 #if defined(THREADZ) || defined(LOCKLESS)
2104             unlock_scu ();
2105 #endif
2106           }
2107           break;
2108 
2109         case 00004: // Get calendar clock (4MW SCU only)
2110         case 00005:
2111           {
2112             uint64 clk = set_SCU_clock (cpup, scu_unit_idx);
2113             cpu.rQ =  clk  & 0777777777777;    // lower 36-bits of clock
2114             cpu.rA = (clk >> 36) & 0177777;    // upper 16-bits of clock
2115 #if defined(TESTING)
2116             HDBGRegAW ("rscr get clock");
2117             HDBGRegQW ("rscr get clock");
2118 #endif
2119           }
2120         break;
2121 
2122         case 00006: // SU Mode register
2123         case 00007: // SU Mode register
2124           {
2125             //sim_printf ("rscr SU Mode Register%o\n", function);
2126 
2127 // Completely undocumented...
2128 //   scr.incl.alm
2129 //"         Structure scr_su
2130 //"
2131 //          equ       scr_su_size,2
2132 //
2133 //
2134 //          equ       scr_su.ZAC_line_word,1
2135 //          equ       scr_su.ZAC_line_shift,30
2136 //          bool      scr_su.ZAC_line_mask,000077
2137 //          equ       scr_su.syndrome_word,1
2138 //          equ       scr_su.syndrome_shift,22
2139 //          bool      scr_su.syndrome_mask,000377
2140 //          equ       scr_su.identification_word,1
2141 //          equ       scr_su.identification_shift,18
2142 //          bool      scr_su.identification_mask,000017
2143 //          equ       scr_su.EDAC_disabled_word,1
2144 //          bool      scr_su.EDAC_disabled,400000   " DL
2145 //          equ       scr_su.MINUS_5_VOLT_margin_word,1
2146 //"         equ       scr_su.MINUS_5_VOLT_margin_shift,11
2147 //          bool      scr_su.MINUS_5_VOLT_margin_mask,000003
2148 //          equ       scr_su.PLUS_5_VOLT_margin_word,1
2149 //          equ       scr_su.PLUS_5_VOLT_margin_shift,9
2150 //          bool      scr_su.PLUS_5_VOLT_margin_mask,000003
2151 //          equ       scr_su.spare_margin_word,1
2152 //          equ       scr_su.spare_margin_shift,7
2153 //          bool      scr_su.spare_margin_mask,000003
2154 //          equ       scr_su.PLUS_19_VOLT_margin_word,1
2155 //"         equ       scr_su.PLUS_19_VOLT_margin_shift,5
2156 //          bool      scr_su.PLUS_19_VOLT_margin_mask,000003
2157 //          equ       scr_su.SENSE_strobe_margin_word,1
2158 //"         equ       scr_su.SENSE_strobe_margin_shift,2
2159 //          bool      scr_su.SENSE_strobe_margin_mask,000003
2160 //"         equ       scr_su.maint_functions_enabled_word,1
2161 //          bool      scr_su.maint_functions_enabled,000001 " DL
2162 
2163 //                 1   1      1   2    2    2       2     3   3        3  3
2164 //   0     6       4   8      9   3    5    7       9     1   2        4  5
2165 //  ------------------------------------------------------------------------------
2166 //  | ZAC | synd | id | EDAC | 0 | -5 | +5 | spare | +19 | 0 | sense | 0 | maint |
2167 //  ------------------------------------------------------------------------------
2168 //       6      8    4      1   4    2    2      2      2   1       2   1       1
2169 
2170 // Okay, it looks safe to return 0.
2171 
2172             * rega = 0;
2173             * regq = 0;
2174           }
2175           break;
2176 
2177         default:
2178           sim_warn ("rscr %o\n", function);
2179           return SCPE_OK;
2180       }
2181     return SCPE_OK;
2182   }
2183 
2184 
2185 
2186 
2187 
2188 int scu_cioc (uint cpu_unit_udx, uint scu_unit_idx, uint scu_port_num,
     /* [previous][next][first][last][top][bottom][index][help] */
2189               uint expander_command, uint sub_mask)
2190   {
2191 
2192 
2193 
2194 #if defined(TESTING)
2195     cpu_state_t * cpup = _cpup;
2196     sim_debug (DBG_DEBUG, & scu_dev,
2197                "scu_cioc: Connect from %o sent to "
2198                "unit %o port %o exp %o mask %03o\n",
2199                cpu_unit_udx, scu_unit_idx, scu_port_num,
2200               expander_command, sub_mask);
2201 #endif
2202 #if defined(THREADZ) || defined(LOCKLESS)
2203     lock_scu ();
2204 #endif
2205     struct ports * portp = & scu [scu_unit_idx].ports [scu_port_num];
2206 
2207     int rc = 0;
2208     if (! scu [scu_unit_idx].port_enable [scu_port_num])
2209       {
2210         sim_debug (DBG_ERR, & scu_dev,
2211                    "scu_cioc: Connect sent to disabled port; dropping\n");
2212         sim_debug (DBG_ERR, & scu_dev,
2213                    "scu_cioc: scu_unit_idx %u scu_port_num %u\n",
2214                    scu_unit_idx, scu_port_num);
2215         rc = 1;
2216         goto done;
2217       }
2218 
2219     if (expander_command == 1) // "set subport enables"
2220       {
2221         for (uint i = 0; i < N_SCU_SUBPORTS; i++)
2222           {
2223             portp->subport_enables [i] = !! (sub_mask & (0200u >> i));
2224           }
2225         goto done;
2226       }
2227 
2228     if (expander_command == 2) // "set xipmask"
2229       {
2230         int cnt = 0;
2231         int val = -1;
2232         for (uint i = 0; i < N_SCU_SUBPORTS; i++)
2233           {
2234             portp->xipmask [i] = !! (sub_mask & (0200u >> i));
2235             if (portp->xipmask [i])
2236               {
2237                 val = (int) i;
2238                 cnt ++;
2239               }
2240           }
2241         if (cnt > 1)
2242           {
2243             sim_warn ("xip mask cnt > 1\n");
2244             val = -1;
2245           }
2246         portp->xipmaskval = val;
2247         goto done;
2248       }
2249 
2250     if (portp -> type == ADEV_IOM)
2251       {
2252         int iom_unit_idx = portp->dev_idx;
2253 #if defined(THREADZ) || defined(LOCKLESS)
2254         unlock_scu ();
2255 # if !defined(IO_ASYNC_PAYLOAD_CHAN) && !defined(IO_ASYNC_PAYLOAD_CHAN_THREAD)
2256         lock_iom ();
2257         lock_libuv ();
2258 # endif
2259         iom_interrupt (scu_unit_idx, (uint) iom_unit_idx);
2260 # if !defined(IO_ASYNC_PAYLOAD_CHAN) && !defined(IO_ASYNC_PAYLOAD_CHAN_THREAD)
2261         unlock_libuv ();
2262         unlock_iom ();
2263 # endif
2264         return 0;
2265 #else // ! THREADZ
2266         if (sys_opts.iom_times.connect <= 0)
2267           {
2268             iom_interrupt (scu_unit_idx, (uint) iom_unit_idx);
2269             goto done;
2270           }
2271         else
2272           {
2273 //sim_printf ("scu_cioc: Queuing an IOM in %d cycles "
2274 //"(for the connect channel) %u %d\n",
2275 //sys_opts.iom_times.connect, scu_unit_idx, iom_unit_idx);
2276             sim_debug (DBG_INFO, & scu_dev,
2277                        "scu_cioc: Queuing an IOM in %d cycles "
2278                        "(for the connect channel)\n",
2279                        sys_opts.iom_times.connect);
2280             // Stash the iom_interrupt call parameters
2281             iom_dev.units[iom_unit_idx].u3 = (int32) scu_unit_idx;
2282             iom_dev.units[iom_unit_idx].u4 = (int32) iom_unit_idx;
2283             int rc;
2284             if ((rc = sim_activate (& iom_dev.units [iom_unit_idx],
2285                 sys_opts.iom_times.connect)) != SCPE_OK)
2286               {
2287                 sim_warn ("sim_activate failed (%d)\n", rc);
2288                 goto done;
2289               }
2290             goto done;
2291           }
2292 #endif // ! THREADZ
2293       }
2294     else if (portp -> type == ADEV_CPU)
2295       {
2296 
2297 // by subport_enables
2298         if (portp->is_exp)
2299           {
2300             for (uint sn = 0; sn < N_SCU_SUBPORTS; sn ++)
2301               {
2302                 if (portp->subport_enables[sn])
2303                   {
2304                     if (! cables->
2305                             scu_to_cpu[scu_unit_idx][scu_port_num][sn].in_use)
2306                       {
2307                         sim_warn ("Can't find CPU to interrupt\n");
2308                         continue;
2309                       }
2310                     uint cpu_unit_udx = cables->
2311                       scu_to_cpu[scu_unit_idx][scu_port_num][sn].cpu_unit_idx;
2312                     setG7fault ((uint) cpu_unit_udx, FAULT_CON, fst_zero);
2313                   }
2314               }
2315           }
2316         else
2317           {
2318             if (! cables->scu_to_cpu[scu_unit_idx][scu_port_num][0].in_use)
2319               {
2320                 sim_warn ("Can't find CPU to interrupt\n");
2321                 rc = 1;
2322                 goto done;
2323               }
2324             uint cpu_unit_udx =
2325               cables->scu_to_cpu[scu_unit_idx][scu_port_num][0].cpu_unit_idx;
2326             setG7fault ((uint) cpu_unit_udx, FAULT_CON, fst_zero);
2327           }
2328 
2329 
2330 
2331 
2332 
2333 
2334 
2335 
2336 
2337 
2338 
2339 
2340 
2341 
2342 
2343 
2344 
2345 
2346 
2347 
2348 
2349 
2350         goto done;
2351       }
2352     else
2353       {
2354         sim_debug (DBG_ERR, & scu_dev,
2355                    "scu_cioc: Connect sent to not-an-IOM or CPU; dropping\n");
2356         rc = 1;
2357         goto done;
2358       }
2359 done:
2360 #if defined(THREADZ) || defined(LOCKLESS)
2361     unlock_scu ();
2362 #endif
2363     return rc;
2364 }
2365 
2366 // =============================================================================
2367 
2368 // The SXC (set execute cells) SCU command.
2369 
2370 // From AN70:
2371 //  It then generates a word with
2372 // the <interrupt number>th bit set and sends this to the bootload
2373 // SCU with the SC (set execute cells) SCU command.
2374 //
2375 
2376 int scu_set_interrupt (uint scu_unit_idx, uint inum)
     /* [previous][next][first][last][top][bottom][index][help] */
2377   {
2378 #if defined(TESTING)
2379     cpu_state_t * cpup = _cpup;
2380 #endif
2381     const char* moi = "SCU::interrupt";
2382 
2383     if (inum >= N_CELL_INTERRUPTS)
2384       {
2385         sim_debug (DBG_WARN, & scu_dev,
2386                    "%s: Bad interrupt number %d\n", moi, inum);
2387         return 1;
2388       }
2389 
2390 #if defined(THREADZ) || defined(LOCKLESS)
2391     lock_scu ();
2392 #endif
2393     scu [scu_unit_idx].cells [inum] = 1;
2394     dump_intr_regs ("scu_set_interrupt", scu_unit_idx);
2395     deliver_interrupts (scu_unit_idx);
2396 #if defined(THREADZ) || defined(LOCKLESS)
2397     unlock_scu ();
2398 #endif
2399     return 0;
2400 }
2401 
2402 // Scan a SCU for interrupts from highest to lowest. If an interrupt is
2403 // present, clear it, update the interrupt state bits and return the fault
2404 // pair address for the interrupt (2 * interrupt number). If no interrupt
2405 // is present, return 1.
2406 //
2407 
2408 uint scu_get_highest_intr (uint scu_unit_idx)
     /* [previous][next][first][last][top][bottom][index][help] */
2409   {
2410 #if defined(TESTING)
2411     cpu_state_t * cpup = _cpup;
2412 #endif
2413 #if defined(THREADZ) || defined(LOCKLESS)
2414     lock_scu ();
2415 #endif
2416     // lower numbered cells have higher priority
2417     for (int inum = 0; inum < N_CELL_INTERRUPTS; inum ++)
2418       {
2419         for (uint pima = 0; pima < N_ASSIGNMENTS; pima ++) // A, B
2420           {
2421             if (scu [scu_unit_idx].mask_enable [pima] == 0)
2422               continue;
2423             uint mask = scu [scu_unit_idx].exec_intr_mask [pima];
2424             uint port = scu [scu_unit_idx].mask_assignment [pima];
2425 //            if (scu [scu_unit_idx].ports [port].type != ADEV_CPU ||
2426 //              scu [scu_unit_idx].ports [port].dev_idx != current_running_cpu_idx)
2427             if (scu[scu_unit_idx].ports[port].type != ADEV_CPU ||
2428                 cpus[current_running_cpu_idx].scu_port[scu_unit_idx] != port)
2429               continue;
2430             if (scu [scu_unit_idx].cells [inum] &&
2431                 (mask & (1u << (31 - inum))) != 0)
2432               {
2433                 sim_debug (DBG_TRACE, & scu_dev,
2434                            "scu_get_highest_intr inum %d pima %u mask 0%011o port %u cells 0%011o\n",
2435                            inum, pima, mask, port, scu [scu_unit_idx].cells [inum]);
2436                 scu [scu_unit_idx].cells [inum] = false;
2437                 dump_intr_regs ("scu_get_highest_intr", scu_unit_idx);
2438                 deliver_interrupts (scu_unit_idx);
2439 #if defined(THREADZ) || defined(LOCKLESS)
2440                 unlock_scu ();
2441 #endif
2442                 return (uint) inum * 2;
2443               }
2444           }
2445       }
2446 #if defined(THREADZ) || defined(LOCKLESS)
2447     unlock_scu ();
2448 #endif
2449     return 1;
2450   }
2451 
2452 t_stat scu_reset_unit (UNIT * uptr, UNUSED int32 value,
     /* [previous][next][first][last][top][bottom][index][help] */
2453                        UNUSED const char * cptr,
2454                        UNUSED void * desc)
2455   {
2456     uint scu_unit_idx = (uint) (uptr - scu_unit);
2457     scu_unit_reset ((int) scu_unit_idx);
2458     return SCPE_OK;
2459   }
2460 
2461 void scu_init (void)
     /* [previous][next][first][last][top][bottom][index][help] */
2462   {
2463     // One time only initializations
2464 
2465     for (int u = 0; u < N_SCU_UNITS_MAX; u ++)
2466       {
2467         for (int p = 0; p < N_SCU_PORTS; p ++)
2468           {
2469             for (int s = 0; s < N_SCU_SUBPORTS; s ++)
2470               {
2471                 scu[u].ports[p].dev_port[s]        = -1;
2472                 scu[u].ports[p].subport_enables[s] = false;
2473                 scu[u].ports[p].xipmask[s]         = false;
2474                 // Invalid value for detecting uninitialized XIP mask.
2475                 scu[u].ports[p].xipmaskval         = N_SCU_SUBPORTS;
2476               }
2477             scu[u].ports[p].type   = ADEV_NONE;
2478             scu[u].ports[p].is_exp = false;
2479           }
2480 
2481         //  ID: 0000  8034, 8035
2482         //      0001  Level 68 SC
2483         //      0010  Level 66 SCU
2484         scu [u].id           = 02l; // 0b0010
2485         scu [u].mode_reg     = 0;   // used by T&D
2486         scu [u].elapsed_days = 0;
2487       }
2488 
2489   }
2490 
2491 t_stat scu_rmcm (uint scu_unit_idx, uint cpu_unit_udx, word36 * rega,
     /* [previous][next][first][last][top][bottom][index][help] */
2492                  word36 * regq)
2493   {
2494 #if defined(TESTING)
2495     cpu_state_t * cpup = _cpup;
2496 #endif
2497     scu_t * up = scu + scu_unit_idx;
2498 
2499     // Assume no mask register assigned
2500     * rega = 0;
2501     * regq = 0;
2502 
2503     // Which port is cpu_unit_udx connected to? (i.e. which port did the
2504     // command come in on?
2505     int scu_port_num = -1; // The port that the rscr instruction was
2506                            // received on
2507 
2508     for (int pn = 0; pn < N_SCU_PORTS; pn ++)
2509       {
2510         for (int sn = 0; sn < N_SCU_SUBPORTS; sn ++)
2511           {
2512             if (cables->scu_to_cpu[scu_unit_idx][pn][sn].in_use &&
2513                 cables->scu_to_cpu[scu_unit_idx][pn][sn].cpu_unit_idx ==
2514                   cpu_unit_udx)
2515               {
2516                 scu_port_num = pn;
2517                 goto gotit;
2518               }
2519           }
2520       }
2521 
2522 gotit:;
2523 
2524     //sim_printf ("rmcm scu_port_num %d\n", scu_port_num);
2525 
2526     if (scu_port_num < 0)
2527       {
2528         sim_warn ("%s: can't find cpu port in the snarl of cables; "
2529                   "scu_unit_no %d, cpu_unit_udx %d\n",
2530                   __func__, scu_unit_idx, cpu_unit_udx);
2531         sim_debug (DBG_ERR, & scu_dev,
2532                    "%s: can't find cpu port in the snarl of cables; "
2533                    "scu_unit_no %d, cpu_unit_udx %d\n",
2534                    __func__, scu_unit_idx, cpu_unit_udx);
2535         // Non 4MWs do a store fault
2536         return SCPE_OK;
2537       }
2538 
2539     // A reg:
2540     //  0          15  16           31  32       35
2541     //    IER 0-15        00000000        PER 0-3
2542     // Q reg:
2543     //  0          15  16           31  32       35
2544     //    IER 16-32       00000000        PER 4-7
2545 
2546     sim_debug (DBG_TRACE, & scu_dev, "rmcm selected scu port %u\n",
2547                scu_port_num);
2548 #if defined(THREADZ) || defined(LOCKLESS)
2549     lock_scu ();
2550 #endif
2551     uint mask_contents = 0;
2552     if (up -> mask_assignment [0] == (uint) scu_port_num)
2553       {
2554         mask_contents = up -> exec_intr_mask [0];
2555         sim_debug (DBG_TRACE, & scu_dev, "rmcm got mask %011o from pima A\n",
2556                    mask_contents);
2557       }
2558     else if (up -> mask_assignment [1] == (uint) scu_port_num)
2559       {
2560         mask_contents = up -> exec_intr_mask [1];
2561         sim_debug (DBG_TRACE, & scu_dev, "rmcm got mask %011o from pima B\n",
2562                    mask_contents);
2563       }
2564     mask_contents &= MASK32;
2565 
2566     * rega = 0;  //-V1048
2567     putbits36_16 (rega,  0, (mask_contents >> 16) & MASK16);
2568     putbits36_1  (rega, 32,  (word1) up -> port_enable [0]);
2569     putbits36_1  (rega, 33,  (word1) up -> port_enable [1]);
2570     putbits36_1  (rega, 34,  (word1) up -> port_enable [2]);
2571     putbits36_1  (rega, 35,  (word1) up -> port_enable [3]);
2572 
2573     * regq = 0;  //-V1048
2574     putbits36_16 (regq,  0, (mask_contents >>  0) & MASK16);
2575     putbits36_1  (regq, 32,  (word1) up -> port_enable [4]);
2576     putbits36_1  (regq, 33,  (word1) up -> port_enable [5]);
2577     putbits36_1  (regq, 34,  (word1) up -> port_enable [6]);
2578     putbits36_1  (regq, 35,  (word1) up -> port_enable [7]);
2579 
2580 #if defined(THREADZ) || defined(LOCKLESS)
2581     unlock_scu ();
2582 #endif
2583     sim_debug (DBG_TRACE, & scu_dev,
2584                "RMCM returns %012"PRIo64" %012"PRIo64"\n",
2585                * rega, * regq);
2586     dump_intr_regs ("rmcm", scu_unit_idx);
2587     return SCPE_OK;
2588   }
2589 
2590 t_stat scu_smcm (uint scu_unit_idx, uint cpu_unit_udx, word36 rega, word36 regq)
     /* [previous][next][first][last][top][bottom][index][help] */
2591   {
2592 #if defined(TESTING)
2593     cpu_state_t * cpup = _cpup;
2594 #endif
2595     sim_debug (DBG_TRACE, & scu_dev,
2596               "SMCM SCU unit %d CPU unit %d A %012"PRIo64" Q %012"PRIo64"\n",
2597                scu_unit_idx, cpu_unit_udx, rega, regq);
2598 
2599     scu_t * up = scu + scu_unit_idx;
2600 
2601     // Which port is cpu_unit_udx connected to? (i.e. which port did the
2602     // command come in on?
2603     int scu_port_num = -1; // The port that the rscr instruction was
2604                            // received on
2605 
2606     for (int pn = 0; pn < N_SCU_PORTS; pn ++)
2607       {
2608         for (int sn = 0; sn < N_SCU_SUBPORTS; sn ++)
2609           {
2610             if (cables->scu_to_cpu[scu_unit_idx][pn][sn].in_use &&
2611                 cables->scu_to_cpu[scu_unit_idx][pn][sn].cpu_unit_idx ==
2612                   cpu_unit_udx)
2613               {
2614                 scu_port_num = pn;
2615                 goto gotit;
2616               }
2617           }
2618       }
2619 gotit:;
2620 
2621     //sim_printf ("rmcm scu_port_num %d\n", scu_port_num);
2622 
2623     if (scu_port_num < 0)
2624       {
2625         sim_warn ("%s: can't find cpu port in the snarl of cables; "
2626                    "scu_unit_no %d, cpu_unit_udx %d\n",
2627                    __func__, scu_unit_idx, cpu_unit_udx);
2628         return SCPE_OK;
2629       }
2630 
2631     sim_debug (DBG_TRACE, & scu_dev, "SMCM SCU port num %d\n", scu_port_num);
2632 
2633     // A reg:
2634     //  0          15  16           31  32       35
2635     //    IER 0-15        00000000        PER 0-3
2636     // Q reg:
2637     //  0          15  16           31  32       35
2638     //    IER 16-32       00000000        PER 4-7
2639 
2640     uint imask =
2641       ((uint) getbits36_16(rega, 0) << 16) |
2642       ((uint) getbits36_16(regq, 0) <<  0);
2643 #if defined(THREADZ) || defined(LOCKLESS)
2644     lock_scu ();
2645 #endif
2646     if (up -> mask_assignment [0] == (uint) scu_port_num)
2647       {
2648         up -> exec_intr_mask [0] = imask;
2649         sim_debug (DBG_TRACE, & scu_dev, "SMCM intr mask 0 set to %011o\n",
2650                    imask);
2651       }
2652     else if (up -> mask_assignment [1] == (uint) scu_port_num)
2653       {
2654         up -> exec_intr_mask [1] = imask;
2655         sim_debug (DBG_TRACE, & scu_dev, "SMCM intr mask 1 set to %011o\n",
2656                    imask);
2657       }
2658 
2659     scu [scu_unit_idx].port_enable [0] = (uint) getbits36_1 (rega, 32);
2660     scu [scu_unit_idx].port_enable [1] = (uint) getbits36_1 (rega, 33);
2661     scu [scu_unit_idx].port_enable [2] = (uint) getbits36_1 (rega, 34);
2662     scu [scu_unit_idx].port_enable [3] = (uint) getbits36_1 (rega, 35);
2663     scu [scu_unit_idx].port_enable [4] = (uint) getbits36_1 (regq, 32);
2664     scu [scu_unit_idx].port_enable [5] = (uint) getbits36_1 (regq, 33);
2665     scu [scu_unit_idx].port_enable [6] = (uint) getbits36_1 (regq, 34);
2666     scu [scu_unit_idx].port_enable [7] = (uint) getbits36_1 (regq, 35);
2667 
2668     dump_intr_regs ("smcm", scu_unit_idx);
2669     deliver_interrupts (scu_unit_idx);
2670 #if defined(THREADZ) || defined(LOCKLESS)
2671     unlock_scu ();
2672 #endif
2673 
2674     return SCPE_OK;
2675   }

/* [previous][next][first][last][top][bottom][index][help] */