This source file includes following definitions.
- scu_show_nunits
- scu_set_nunits
- scu_show_state
- scu_show_config
- scu_set_config
- dump_intr_regs
- scu_unit_reset
- scu_reset
- set_SCU_clock
- pcells
- deliver_interrupts
- scu_smic
- scu_sscr
- scu_rscr
- scu_cioc
- scu_set_interrupt
- scu_get_highest_intr
- scu_reset_unit
- scu_init
- scu_rmcm
- scu_smcm
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543 #include <sys/time.h>
544 #include "dps8.h"
545 #include "dps8_sys.h"
546 #include "dps8_iom.h"
547 #include "dps8_cable.h"
548 #include "dps8_cpu.h"
549 #include "dps8_faults.h"
550 #include "dps8_scu.h"
551 #include "dps8_utils.h"
552 #if defined(THREADZ) || defined(LOCKLESS)
553 # include "threadz.h"
554 #endif
555
556 #define DBG_CTR 1
557
558 scu_t scu [N_SCU_UNITS_MAX];
559
560 #define N_SCU_UNITS 1
561
562 static UNIT scu_unit [N_SCU_UNITS_MAX] = {
563 #if defined(NO_C_ELLIPSIS)
564 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
565 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
566 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
567 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
568 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
569 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
570 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
571 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL }
572 #else
573 [0 ... N_SCU_UNITS_MAX-1] = {
574 UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL
575 }
576 #endif
577 };
578
579 #define UNIT_NUM(uptr) ((uptr) - scu_unit)
580
581
582
583
584
585 static struct config_switches
586 {
587 uint mode;
588 uint port_enable [N_SCU_PORTS];
589 uint mask_enable [N_ASSIGNMENTS];
590 uint mask_assignment [N_ASSIGNMENTS];
591 uint lower_store_size;
592 uint cyclic;
593 uint nea;
594 uint onl;
595 uint interlace;
596 uint lwr;
597 } config_switches [N_SCU_UNITS_MAX];
598
599 enum { MODE_MANUAL = 0, MODE_PROGRAM = 1 };
600
601 unsigned int gtod_warned = 0;
602
603
604
605 static t_stat scu_show_nunits (UNUSED FILE * st, UNUSED UNIT * uptr,
606 UNUSED int val, const UNUSED void * desc)
607 {
608 sim_printf("Number of SCU units in system is %d\n", scu_dev.numunits);
609 return SCPE_OK;
610 }
611
612 static t_stat scu_set_nunits (UNUSED UNIT * uptr, UNUSED int32 value,
613 const char * cptr, UNUSED void * desc)
614 {
615 if (! cptr)
616 return SCPE_ARG;
617 int n = atoi (cptr);
618 if (n < 1 || n > N_SCU_UNITS_MAX)
619 return SCPE_ARG;
620 scu_dev.numunits = (uint) n;
621 return SCPE_OK;
622 }
623
624 static t_stat scu_show_state (UNUSED FILE * st, UNIT *uptr, UNUSED int val,
625 UNUSED const void * desc)
626 {
627 #if defined(TESTING)
628 cpu_state_t * cpup = _cpup;
629 #endif
630 long scu_unit_idx = UNIT_NUM (uptr);
631 if (scu_unit_idx < 0 || scu_unit_idx >= (int) scu_dev.numunits)
632 {
633 sim_debug (DBG_ERR, & scu_dev,
634 "scu_show_state: Invalid unit number %ld\n",
635 (long) scu_unit_idx);
636 sim_printf ("error: Invalid unit number %ld\n", (long) scu_unit_idx);
637 return SCPE_ARG;
638 }
639
640 sim_printf ("SCU unit number %ld\n", (long) scu_unit_idx);
641 scu_t * scup = scu + scu_unit_idx;
642 sim_printf (" Mode %s\n",
643 config_switches[scu_unit_idx].mode ? "PROGRAM" : "MANUAL");
644
645 for (int i = 0; i < N_SCU_PORTS; i ++)
646 {
647 struct ports * pp = scup -> ports + i;
648
649 sim_printf (" Port %d %s dev_idx %d dev_port %d type %s\n",
650 i, scup->port_enable[i] ? "ENABLE " : "DISABLE",
651 pp->dev_idx, pp->dev_port[XXX_TEMP_SCU_SUBPORT],
652 pp->type == ADEV_NONE ? "NONE" :
653 pp->type == ADEV_CPU ? "CPU" :
654 pp->type == ADEV_IOM ? "IOM" :
655 "<enum broken>");
656 }
657 for (int i = 0; i < N_ASSIGNMENTS; i ++)
658 {
659
660
661 sim_printf (" Cell %c\n", 'A' + i);
662 sim_printf (" exec_intr_mask %012o\n",
663 scup -> exec_intr_mask [i]);
664 sim_printf (" mask_enable %s\n",
665 scup -> mask_enable [i] ? "ENABLE" : "DISABLE");
666 sim_printf (" mask_assignment %d\n",
667 scup -> mask_assignment [i]);
668 sim_printf (" cells ");
669 for (int j = 0; j < N_CELL_INTERRUPTS; j ++)
670 sim_printf("%d", scup -> cells [j]);
671 sim_printf ("\n");
672 }
673 sim_printf("Lower store size: %d\n", scup -> lower_store_size);
674 sim_printf("Cyclic: %03o\n", scup -> cyclic);
675 sim_printf("NEA: %03o\n", scup -> nea);
676 sim_printf("Online: %02o\n", scup -> onl);
677 sim_printf("Interlace: %o\n", scup -> interlace);
678 sim_printf("Lower: %o\n", scup -> lwr);
679 sim_printf("ID: %o\n", scup -> id);
680 sim_printf("mode_reg: %06o\n", scup -> mode_reg);
681 sim_printf("Elapsed days: %d\n", scup -> elapsed_days);
682 sim_printf("Steady clock: %d\n", scup -> steady_clock);
683 sim_printf("Bullet time: %d\n", scup -> bullet_time);
684 sim_printf("Y2K enabled: %d\n", scup -> y2k);
685 return SCPE_OK;
686 }
687
688 static t_stat scu_show_config (UNUSED FILE * st, UNUSED UNIT * uptr,
689 UNUSED int val, UNUSED const void * desc)
690 {
691 #if defined(TESTING)
692 cpu_state_t * cpup = _cpup;
693 #endif
694 static const char * map [N_SCU_PORTS] =
695 {
696 "0", "1", "2", "3", "4", "5", "6", "7"
697 };
698 long scu_unit_idx = UNIT_NUM (uptr);
699 if (scu_unit_idx < 0 || scu_unit_idx >= (int) scu_dev.numunits)
700 {
701 sim_debug (DBG_ERR, & scu_dev,
702 "scu_show_config: Invalid unit number %ld\n",
703 (long) scu_unit_idx);
704 sim_printf ("error: Invalid unit number %ld\n", (long) scu_unit_idx);
705 return SCPE_ARG;
706 }
707
708 sim_printf ("SCU unit number %ld\n", (long) scu_unit_idx);
709
710 struct config_switches * sw = config_switches + scu_unit_idx;
711
712 const char * mode = "<out of range>";
713 switch (sw -> mode)
714 {
715 case MODE_PROGRAM:
716 mode = "Program";
717 break;
718 case MODE_MANUAL:
719 mode = "Manual";
720 break;
721 }
722
723 sim_printf ("Mode: %s\n", mode);
724 sim_printf ("Port Enable: ");
725 for (int i = 0; i < N_SCU_PORTS; i ++)
726 sim_printf (" %3o", sw -> port_enable [i]);
727 sim_printf ("\n");
728 for (int i = 0; i < N_ASSIGNMENTS; i ++)
729 {
730 sim_printf ("Mask %c: %s\n",
731 'A' + i,
732 sw->mask_enable[i] ? (map[sw->mask_assignment[i]]) : "Off");
733 }
734 sim_printf ("Lower Store Size: %o\n", sw -> lower_store_size);
735 sim_printf ("Cyclic: %03o\n", sw -> cyclic);
736 sim_printf ("Non-existent address: %03o\n", sw -> nea);
737
738 return SCPE_OK;
739 }
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764 static config_value_list_t cfg_mode_list [] =
765 {
766 { "manual", 0 },
767 { "program", 1 },
768 { NULL, 0 }
769 };
770
771 static config_value_list_t cfg_mask_list [] =
772 {
773 { "off", -1 },
774 { NULL, 0 }
775 };
776
777 static config_value_list_t cfg_able_list [] =
778 {
779 { "disable", 0 },
780 { "enable", 1 },
781 { NULL, 0 }
782 };
783
784 static config_value_list_t cfg_size_list [] =
785 {
786 { "32", 0 },
787 { "64", 1 },
788 { "128", 2 },
789 { "256", 3 },
790 { "512", 4 },
791 { "1024", 5 },
792 { "2048", 6 },
793 { "4096", 7 },
794 { "32K", 0 },
795 { "64K", 1 },
796 { "128K", 2 },
797 { "256K", 3 },
798 { "512K", 4 },
799 { "1024K", 5 },
800 { "2048K", 6 },
801 { "4096K", 7 },
802 { "1M", 5 },
803 { "2M", 6 },
804 { "4M", 7 },
805 { NULL, 0 }
806 };
807
808 static config_value_list_t cfg_on_off [] =
809 {
810 { "off", 0 },
811 { "on", 1 },
812 { "disable", 0 },
813 { "enable", 1 },
814 { NULL, 0 }
815 };
816
817 static config_list_t scu_config_list [] =
818 {
819 { "mode", 1, 0, cfg_mode_list },
820 { "maska", 0, N_SCU_PORTS - 1, cfg_mask_list },
821 { "maskb", 0, N_SCU_PORTS - 1, cfg_mask_list },
822 { "port0", 1, 0, cfg_able_list },
823 { "port1", 1, 0, cfg_able_list },
824 { "port2", 1, 0, cfg_able_list },
825 { "port3", 1, 0, cfg_able_list },
826 { "port4", 1, 0, cfg_able_list },
827 { "port5", 1, 0, cfg_able_list },
828 { "port6", 1, 0, cfg_able_list },
829 { "port7", 1, 0, cfg_able_list },
830 { "lwrstoresize", 0, 7, cfg_size_list },
831 { "cyclic", 0, 0177, NULL },
832 { "nea", 0, 0377, NULL },
833
834 { "onl", 0, 017, NULL },
835 { "int", 0, 1, NULL },
836 { "lwr", 0, 1, NULL },
837
838
839
840 { "elapsed_days", 0, 20000, NULL },
841 { "steady_clock", 0, 1, cfg_on_off },
842 { "bullet_time", 0, 1, cfg_on_off },
843 { "y2k", 0, 1, cfg_on_off },
844 { NULL, 0, 0, NULL }
845 };
846
847 static t_stat scu_set_config (UNIT * uptr, UNUSED int32 value,
848 const char * cptr, UNUSED void * desc)
849 {
850 #if defined(TESTING)
851 cpu_state_t * cpup = _cpup;
852 #endif
853 long scu_unit_idx = UNIT_NUM (uptr);
854 if (scu_unit_idx < 0 || scu_unit_idx >= (int) scu_dev.numunits)
855 {
856 sim_debug (DBG_ERR, & scu_dev,
857 "scu_set_config: Invalid unit number %ld\n", (long) scu_unit_idx);
858 sim_printf ("error: scu_set_config: Invalid unit number %ld\n",
859 (long) scu_unit_idx);
860 return SCPE_ARG;
861 }
862
863 struct config_switches * sw = config_switches + scu_unit_idx;
864
865 config_state_t cfg_state = { NULL, NULL };
866
867 for (;;)
868 {
869 int64_t v;
870 int rc = cfg_parse ("scu_set_config", cptr, scu_config_list,
871 & cfg_state, & v);
872 if (rc == -1)
873 break;
874
875 if (rc == -2)
876 {
877 cfg_parse_done (& cfg_state);
878 return SCPE_ARG;
879 }
880
881 const char * p = scu_config_list [rc].name;
882 if (strcmp (p, "mode") == 0)
883 sw -> mode = (uint) v;
884 else if (strcmp (p, "maska") == 0)
885 {
886 if (v == -1)
887 sw -> mask_enable [0] = false;
888 else
889 {
890 sw -> mask_enable [0] = true;
891 sw -> mask_assignment [0] = (uint) v;
892 }
893 }
894 else if (strcmp (p, "maskb") == 0)
895 {
896 if (v == -1)
897 sw -> mask_enable [1] = false;
898 else
899 {
900 sw -> mask_enable [1] = true;
901 sw -> mask_assignment [1] = (uint) v;
902 }
903 }
904 else if (strcmp (p, "port0") == 0)
905 sw -> port_enable [0] = (uint) v;
906 else if (strcmp (p, "port1") == 0)
907 sw -> port_enable [1] = (uint) v;
908 else if (strcmp (p, "port2") == 0)
909 sw -> port_enable [2] = (uint) v;
910 else if (strcmp (p, "port3") == 0)
911 sw -> port_enable [3] = (uint) v;
912 else if (strcmp (p, "port4") == 0)
913 sw -> port_enable [4] = (uint) v;
914 else if (strcmp (p, "port5") == 0)
915 sw -> port_enable [5] = (uint) v;
916 else if (strcmp (p, "port6") == 0)
917 sw -> port_enable [6] = (uint) v;
918 else if (strcmp (p, "port7") == 0)
919 sw -> port_enable [7] = (uint) v;
920 else if (strcmp (p, "lwrstoresize") == 0)
921 sw -> lower_store_size = (uint) v;
922 else if (strcmp (p, "cyclic") == 0)
923 sw -> cyclic = (uint) v;
924 else if (strcmp (p, "nea") == 0)
925 sw -> nea = (uint) v;
926 else if (strcmp (p, "onl") == 0)
927 sw -> onl = (uint) v;
928 else if (strcmp (p, "int") == 0)
929 sw -> interlace = (uint) v;
930 else if (strcmp (p, "lwr") == 0)
931 sw -> lwr = (uint) v;
932 else if (strcmp (p, "elapsed_days") == 0)
933 scu [scu_unit_idx].elapsed_days = (uint) v;
934 else if (strcmp (p, "steady_clock") == 0)
935 scu [scu_unit_idx].steady_clock = (uint) v;
936 else if (strcmp (p, "bullet_time") == 0)
937 scu [scu_unit_idx].bullet_time = (uint) v;
938 else if (strcmp (p, "y2k") == 0)
939 scu [scu_unit_idx].y2k = (uint) v;
940 else
941 {
942 sim_printf ("error: scu_set_config: invalid cfg_parse rc <%d>\n",
943 rc);
944 cfg_parse_done (& cfg_state);
945 return SCPE_ARG;
946 }
947 }
948 cfg_parse_done (& cfg_state);
949 return SCPE_OK;
950 }
951
952 static MTAB scu_mod [] =
953 {
954 {
955 MTAB_XTD | MTAB_VUN | \
956 MTAB_NMO | MTAB_VALR,
957 0,
958 (char *) "CONFIG",
959 (char *) "CONFIG",
960 scu_set_config,
961 scu_show_config,
962 NULL,
963 NULL
964 },
965 {
966 MTAB_XTD | MTAB_VDV | \
967 MTAB_NMO | MTAB_VALR,
968 0,
969 (char *) "NUNITS",
970 (char *) "NUNITS",
971 scu_set_nunits,
972 scu_show_nunits,
973 (char *) "Number of SCU units in the system",
974 NULL
975 },
976 {
977 MTAB_XTD | MTAB_VUN | \
978 MTAB_NMO | MTAB_VALR,
979 0,
980 (char *) "STATE",
981 (char *) "STATE",
982 NULL,
983 scu_show_state,
984 (char *) "SCU unit internal state",
985 NULL
986 },
987 {
988 MTAB_XTD | MTAB_VUN | \
989 MTAB_NMO | MTAB_VALR,
990 0,
991 (char *) "RESET",
992 (char *) "RESET",
993 scu_reset_unit,
994 NULL,
995 (char *) "reset SCU unit",
996 NULL
997 },
998 {
999 0, 0, NULL, NULL, NULL, NULL, NULL, NULL
1000 }
1001 };
1002
1003
1004
1005 static DEBTAB scu_dt [] =
1006 {
1007 { (char *) "TRACE", DBG_TRACE, NULL },
1008 { (char *) "NOTIFY", DBG_NOTIFY, NULL },
1009 { (char *) "INFO", DBG_INFO, NULL },
1010 { (char *) "ERR", DBG_ERR, NULL },
1011 { (char *) "WARN", DBG_WARN, NULL },
1012 { (char *) "DEBUG", DBG_DEBUG, NULL },
1013 { (char *) "INTR", DBG_INTR, NULL },
1014 { (char *) "ALL", DBG_ALL, NULL },
1015 { NULL, 0, NULL }
1016 };
1017
1018 DEVICE scu_dev =
1019 {
1020 (char *) "SCU",
1021 scu_unit,
1022 NULL,
1023 scu_mod,
1024 N_SCU_UNITS,
1025 10,
1026 8,
1027 1,
1028 8,
1029 8,
1030 NULL,
1031 NULL,
1032 & scu_reset,
1033 NULL,
1034 NULL,
1035 NULL,
1036 NULL,
1037 DEV_DEBUG,
1038 0,
1039 scu_dt,
1040 NULL,
1041 NULL,
1042 NULL,
1043 NULL,
1044 NULL,
1045 NULL,
1046 NULL
1047 };
1048
1049 static void dump_intr_regs (char * ctx, uint scu_unit_idx)
1050 {
1051 #if defined(TESTING)
1052 scu_t * up = scu + scu_unit_idx;
1053 cpu_state_t * cpup = _cpup;
1054
1055 sim_debug (DBG_DEBUG, & scu_dev,
1056 "%s A: mask %011o enable %o assignment %o\n",
1057 ctx, up -> exec_intr_mask [0], up -> mask_enable [0],
1058 up -> mask_assignment [0]);
1059 sim_debug (DBG_DEBUG, & scu_dev,
1060 "%s B: mask %011o enable %o assignment %o\n",
1061 ctx, up -> exec_intr_mask [1], up -> mask_enable [1],
1062 up -> mask_assignment [1]);
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1110 #endif
1111 }
1112
1113 void scu_unit_reset (int scu_unit_idx)
1114 {
1115 scu_t * up = scu + scu_unit_idx;
1116 struct config_switches * sw = config_switches + scu_unit_idx;
1117
1118 for (int i = 0; i < N_SCU_PORTS; i ++)
1119 {
1120 up -> port_enable [i] = sw -> port_enable [i];
1121 }
1122
1123 for (int i = 0; i < N_ASSIGNMENTS; i ++)
1124 {
1125 up -> mask_enable [i] = sw -> mask_enable [i];
1126 up -> mask_assignment [i] = sw -> mask_assignment [i];
1127 }
1128 up -> lower_store_size = sw -> lower_store_size;
1129 up -> cyclic = sw -> cyclic;
1130 up -> nea = sw -> nea;
1131 up -> onl = sw -> onl;
1132 up -> interlace = sw -> interlace;
1133 up -> lwr = sw -> lwr;
1134
1135
1136
1137
1138 for (uint port_num = 0; port_num < N_SCU_PORTS; port_num ++)
1139 {
1140 struct ports * portp = & scu [scu_unit_idx].ports [port_num];
1141 if (portp->type != ADEV_IOM)
1142 continue;
1143
1144
1145 iom_unit_reset_idx ((uint) portp->dev_idx);
1146 }
1147
1148
1149
1150
1151
1152 for (int i = 0; i < N_ASSIGNMENTS; i ++)
1153 {
1154
1155 up -> exec_intr_mask [i] = 037777777777;
1156 }
1157 }
1158
1159 t_stat scu_reset (UNUSED DEVICE * dptr)
1160 {
1161
1162
1163 for (int scu_unit_idx = 0; scu_unit_idx < N_SCU_UNITS_MAX; scu_unit_idx ++)
1164 scu_unit_reset (scu_unit_idx);
1165 return SCPE_OK;
1166 }
1167
1168
1169
1170 #if defined(THREADZ) || defined(LOCKLESS)
1171 static pthread_mutex_t clock_lock = PTHREAD_MUTEX_INITIALIZER;
1172 #endif
1173
1174
1175 static uint64 set_SCU_clock (cpu_state_t * cpup, uint scu_unit_idx)
1176 {
1177 #if defined(THREADZ) || defined(LOCKLESS)
1178 pthread_mutex_lock (& clock_lock);
1179 #endif
1180
1181
1182
1183
1184
1185
1186 if (scu [0].steady_clock)
1187 {
1188
1189
1190 #if defined(NEED_128)
1191 uint128 big = construct_128 (0, cpu.instrCnt);
1192
1193
1194 big = lshift_128 (big, 2);
1195 if (scu [0].bullet_time)
1196 big = multiply_128 (big, construct_128 (0, 10000u));
1197
1198
1199 uint128 days = construct_128 (0, scu[0].elapsed_days);
1200 days = multiply_128 (days, construct_128 (0, 1000000));
1201 days = multiply_128 (days, construct_128 (0, 60 * 60 * 24));
1202 big = add_128 (big, days);
1203 #else
1204 __uint128_t big = cpu.instrCnt;
1205
1206 big *= 4u;
1207
1208 if (scu [0].bullet_time)
1209 big *= 10000;
1210
1211 big += scu [0].elapsed_days * 1000000llu * 60llu * 60llu * 24llu;
1212 #endif
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226 uint64 UNIX_secs = (uint64)time(NULL);
1227
1228 #if defined(NEED_128)
1229 uint64 UNIX_usecs = UNIX_secs * 1000000llu + big.l;
1230 #else
1231 uint64 UNIX_usecs = UNIX_secs * 1000000llu + (uint64) big;
1232 #endif
1233
1234 uint64 Multics_usecs = 2177452800000000llu + UNIX_usecs;
1235
1236
1237
1238 Multics_usecs += (uint64) scu [scu_unit_idx].user_correction;
1239
1240
1241
1242
1243 if (scu [scu_unit_idx].last_time >= Multics_usecs)
1244 {
1245 sim_debug (DBG_TRACE, & scu_dev, "finagle clock\n");
1246 Multics_usecs = scu [scu_unit_idx].last_time + 1;
1247 }
1248 scu [scu_unit_idx].last_time = Multics_usecs;
1249 goto done;
1250 }
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263 struct timeval now;
1264 gettimeofday(& now, NULL);
1265
1266 if (scu [0].y2k)
1267 {
1268
1269
1270
1271
1272 now.tv_sec -= (1685451324 - 738766524);
1273 }
1274 uint64 UNIX_secs = (uint64) now.tv_sec;
1275 uint64 UNIX_usecs = UNIX_secs * 1000000LL + (uint64) now.tv_usec;
1276
1277 static uint64 last_UNIX_usecs = 0;
1278 if ( (!sim_quiet) && (UNIX_usecs < last_UNIX_usecs))
1279 {
1280 if (gtod_warned < 11)
1281 {
1282 sim_warn ("\rHost clock went backwards %llu uS!\r\n",
1283 (unsigned long long)(last_UNIX_usecs - UNIX_usecs));
1284 gtod_warned++;
1285 }
1286 else if (gtod_warned == 11)
1287 {
1288 sim_warn ("\rHost clock went backwards %llu uS! Suppressing further warnings.\r\n",
1289 (unsigned long long)(last_UNIX_usecs - UNIX_usecs));
1290 gtod_warned++;
1291 }
1292 }
1293 last_UNIX_usecs = UNIX_usecs;
1294
1295
1296 uint64 Multics_usecs = 2177452800000000LL + UNIX_usecs;
1297
1298
1299
1300
1301
1302 Multics_usecs += (uint64) scu [scu_unit_idx].user_correction;
1303
1304 if (scu [scu_unit_idx].last_time >= Multics_usecs)
1305 Multics_usecs = scu [scu_unit_idx].last_time + 1;
1306 scu [scu_unit_idx].last_time = Multics_usecs;
1307
1308 done:
1309 #if defined(THREADZ) || defined(LOCKLESS)
1310 pthread_mutex_unlock (& clock_lock);
1311 #endif
1312
1313 return scu [scu_unit_idx].last_time;
1314 }
1315
1316
1317 static char * pcells (uint scu_unit_idx, char * buf)
1318 {
1319 for (uint i = 0; i < N_CELL_INTERRUPTS; i ++)
1320 {
1321 if (scu [scu_unit_idx].cells [i])
1322 buf [i] = '1';
1323 else
1324 buf [i] = '0';
1325 }
1326 buf [N_CELL_INTERRUPTS] = '\0';
1327 return buf;
1328 }
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344 static void deliver_interrupts (uint scu_unit_idx)
1345 {
1346 #if defined(TESTING)
1347 cpu_state_t * cpup = _cpup;
1348 sim_debug (DBG_DEBUG, & scu_dev, "deliver_interrupts %o\n", scu_unit_idx);
1349 #endif
1350 for (uint cpun = 0; cpun < cpu_dev.numunits; cpun ++)
1351 {
1352 cpus[cpun].events.XIP[scu_unit_idx] = false;
1353 }
1354
1355
1356
1357
1358
1359 #if defined(REORDER)
1360 for (uint jnum = 0; jnum < N_CELL_INTERRUPTS; jnum ++)
1361 {
1362 static const uint reorder[N_CELL_INTERRUPTS] = {
1363 0, 1, 2, 3, 4, 5, 6, 7,
1364 16, 17, 18, 29, 20, 21, 22, 23,
1365 8, 9, 10, 11, 12, 13, 14, 15,
1366 25, 25, 26, 27, 28, 29, 30, 31 };
1367 uint inum = reorder[jnum];
1368 if (! scu [scu_unit_idx].cells [inum])
1369 continue;
1370 sim_debug (DBG_DEBUG, & scu_dev, "trying to deliver %d\n", inum);
1371 sim_debug (DBG_INTR, & scu_dev,
1372 "scu %u trying to deliver %d\n", scu_unit_idx, inum);
1373
1374 for (uint pima = 0; pima < N_ASSIGNMENTS; pima ++)
1375 {
1376
1377
1378
1379 if (scu [scu_unit_idx].mask_enable [pima] == 0)
1380 continue;
1381 uint mask = scu [scu_unit_idx].exec_intr_mask [pima];
1382 uint port = scu [scu_unit_idx].mask_assignment [pima];
1383
1384
1385
1386
1387 if (scu [scu_unit_idx].ports [port].type != ADEV_CPU)
1388 continue;
1389 if ((mask & (1u << (31 - inum))) != 0)
1390 {
1391 uint sn = 0;
1392 if (scu[scu_unit_idx].ports[port].is_exp)
1393 {
1394 sn = (uint) scu[scu_unit_idx].ports[port].xipmaskval;
1395 if (sn >= N_SCU_SUBPORTS)
1396 {
1397 sim_warn ("XIP mask not set; defaulting to subport 0\n");
1398 sn = 0;
1399 }
1400 }
1401 if (! cables->scu_to_cpu[scu_unit_idx][port][sn].in_use)
1402 {
1403 sim_warn ("bad scu_unit_idx %u\n", scu_unit_idx);
1404 continue;
1405 }
1406 uint cpu_unit_udx = cables->scu_to_cpu[scu_unit_idx][port][sn].cpu_unit_idx;
1407 # if defined(THREADZ) || defined(LOCKLESS)
1408 cpus[cpu_unit_udx].events.XIP[scu_unit_idx] = true;
1409 # if defined(TESTING)
1410 HDBGIntrSet (inum, cpu_unit_udx, scu_unit_idx, __func__);
1411 # endif
1412 createCPUThread((uint) cpu_unit_udx);
1413 # if !defined(NO_TIMEWAIT)
1414 wakeCPU ((uint) cpu_unit_udx);
1415 # endif
1416 sim_debug (DBG_DEBUG, & scu_dev,
1417 "interrupt set for CPU %d SCU %d\n",
1418 cpu_unit_udx, scu_unit_idx);
1419 # else
1420
1421 # if defined(ROUND_ROBIN)
1422 cpus[cpu_unit_udx].isRunning = true;
1423 # endif
1424 cpus[cpu_unit_udx].events.XIP[scu_unit_idx] = true;
1425 sim_debug (DBG_DEBUG, & scu_dev, "interrupt set for CPU %d SCU %d\n", cpu_unit_udx, scu_unit_idx);
1426 sim_debug (DBG_INTR, & scu_dev,
1427 "XIP set for SCU %d\n", scu_unit_idx);
1428 # endif
1429 }
1430 }
1431 }
1432 #else
1433 for (uint inum = 0; inum < N_CELL_INTERRUPTS; inum ++)
1434 {
1435 if (! scu [scu_unit_idx].cells [inum])
1436 continue;
1437 sim_debug (DBG_DEBUG, & scu_dev, "trying to deliver %d\n", inum);
1438 sim_debug (DBG_INTR, & scu_dev,
1439 "scu %u trying to deliver %d\n", scu_unit_idx, inum);
1440
1441 for (uint pima = 0; pima < N_ASSIGNMENTS; pima ++)
1442 {
1443
1444
1445
1446 if (scu [scu_unit_idx].mask_enable [pima] == 0)
1447 continue;
1448 uint mask = scu [scu_unit_idx].exec_intr_mask [pima];
1449 uint port = scu [scu_unit_idx].mask_assignment [pima];
1450
1451
1452
1453
1454 if (scu [scu_unit_idx].ports [port].type != ADEV_CPU)
1455 continue;
1456 if ((mask & (1u << (31 - inum))) != 0)
1457 {
1458 uint sn = 0;
1459 if (scu[scu_unit_idx].ports[port].is_exp)
1460 {
1461 sn = (uint) scu[scu_unit_idx].ports[port].xipmaskval;
1462 if (sn >= N_SCU_SUBPORTS)
1463 {
1464 sim_warn ("XIP mask not set; defaulting to subport 0\n");
1465 sn = 0;
1466 }
1467 }
1468 if (! cables->scu_to_cpu[scu_unit_idx][port][sn].in_use)
1469 {
1470 sim_warn ("bad scu_unit_idx %u\n", scu_unit_idx);
1471 continue;
1472 }
1473 uint cpu_unit_udx = cables->scu_to_cpu[scu_unit_idx][port][sn].cpu_unit_idx;
1474 # if defined(THREADZ) || defined(LOCKLESS)
1475 cpus[cpu_unit_udx].events.XIP[scu_unit_idx] = true;
1476 # if defined(TESTING)
1477 HDBGIntrSet (inum, cpu_unit_udx, scu_unit_idx, __func__);
1478 # endif
1479 createCPUThread((uint) cpu_unit_udx);
1480 # if !defined(NO_TIMEWAIT)
1481 wakeCPU ((uint) cpu_unit_udx);
1482 # endif
1483 sim_debug (DBG_DEBUG, & scu_dev,
1484 "interrupt set for CPU %d SCU %d\n",
1485 cpu_unit_udx, scu_unit_idx);
1486 # else
1487
1488 # if defined(ROUND_ROBIN)
1489 cpus[cpu_unit_udx].isRunning = true;
1490 # endif
1491 cpus[cpu_unit_udx].events.XIP[scu_unit_idx] = true;
1492 sim_debug (DBG_DEBUG, & scu_dev, "interrupt set for CPU %d SCU %d\n", cpu_unit_udx, scu_unit_idx);
1493 sim_debug (DBG_INTR, & scu_dev,
1494 "XIP set for SCU %d\n", scu_unit_idx);
1495 # endif
1496 }
1497 }
1498 }
1499 #endif
1500 }
1501
1502 t_stat scu_smic (uint scu_unit_idx, uint UNUSED cpu_unit_udx,
1503 uint UNUSED cpu_port_num, word36 rega)
1504 {
1505 #if defined(TESTING)
1506 cpu_state_t * cpup = _cpup;
1507 #endif
1508 #if defined(THREADZ) || defined(LOCKLESS)
1509 lock_scu ();
1510 #endif
1511
1512
1513 if (getbits36_1 (rega, 35))
1514 {
1515 for (uint i = 0; i < 16; i ++)
1516 {
1517 if (getbits36_1 (rega, i))
1518 scu [scu_unit_idx].cells [i + 16] = 1;
1519 }
1520 char pcellb [N_CELL_INTERRUPTS + 1];
1521 sim_debug (DBG_TRACE, & scu_dev,
1522 "SMIC low: Unit %u Cells: %s\n",
1523 scu_unit_idx, pcells (scu_unit_idx, pcellb));
1524 }
1525 else
1526 {
1527 for (uint i = 0; i < 16; i ++)
1528 {
1529 if (getbits36_1 (rega, i))
1530 scu [scu_unit_idx].cells [i] = 1;
1531 }
1532 char pcellb [N_CELL_INTERRUPTS + 1];
1533 sim_debug (DBG_TRACE, & scu_dev,
1534 "SMIC high: Unit %d Cells: %s\n",
1535 scu_unit_idx, pcells (scu_unit_idx, pcellb));
1536 }
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562 dump_intr_regs ("smic", scu_unit_idx);
1563 deliver_interrupts (scu_unit_idx);
1564 #if defined(THREADZ) || defined(LOCKLESS)
1565 unlock_scu ();
1566 #endif
1567 return SCPE_OK;
1568 }
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599 t_stat scu_sscr (cpu_state_t * cpup, uint scu_unit_idx, UNUSED uint cpu_unit_udx,
1600 UNUSED uint cpu_port_num, word18 addr,
1601 word36 rega, word36 regq)
1602 {
1603 sim_debug (DBG_DEBUG, & scu_dev, "sscr SCU unit %o\n", scu_unit_idx);
1604
1605
1606
1607 if (scu_unit_idx >= scu_dev.numunits)
1608 {
1609
1610 sim_warn ("%s: scu_unit_idx out of range %d\n",
1611 __func__, scu_unit_idx);
1612 return SCPE_OK;
1613 }
1614
1615
1616
1617
1618 uint function = (addr >> 3) & 07;
1619
1620
1621
1622 if (config_switches [scu_unit_idx].mode != MODE_PROGRAM)
1623 {
1624 sim_warn ("%s: SCU mode is 'MANUAL', not 'PROGRAM' -- sscr "
1625 "not allowed to set switches.\n",
1626 __func__);
1627
1628
1629 return SCPE_OK;
1630 }
1631
1632
1633
1634 switch (function)
1635 {
1636 case 00000:
1637 {
1638 #if defined(THREADZ) || defined(LOCKLESS)
1639 lock_scu ();
1640 #endif
1641 scu [scu_unit_idx].id = (word4) getbits36_4 (regq, 50 - 36);
1642 scu [scu_unit_idx].mode_reg = getbits36_18 (regq, 54 - 36);
1643 #if defined(THREADZ) || defined(LOCKLESS)
1644 unlock_scu ();
1645 #endif
1646 }
1647 break;
1648
1649 case 00001:
1650
1651 {
1652 sim_debug (DBG_DEBUG, & scu_dev,
1653 "sscr 1 %d A: %012"PRIo64" Q: %012"PRIo64"\n",
1654 scu_unit_idx, rega, regq);
1655 #if defined(THREADZ) || defined(LOCKLESS)
1656 lock_scu ();
1657 #endif
1658 scu_t * up = scu + scu_unit_idx;
1659 for (int maskab = 0; maskab < 2; maskab ++)
1660 {
1661 word9 mask = ((maskab ? regq : rega) >> 27) & 0777;
1662 if (mask & 01)
1663 {
1664 up -> mask_enable [maskab] = 0;
1665 sim_debug (DBG_DEBUG, & scu_dev,
1666 "sscr %u mask disable %d\n",
1667 scu_unit_idx, maskab);
1668 }
1669 else
1670 {
1671 up -> mask_enable [maskab] = 1;
1672 sim_debug (DBG_DEBUG, & scu_dev,
1673 "sscr %u mask enable %d\n",
1674 scu_unit_idx, maskab);
1675 for (int pn = 0; pn < N_SCU_PORTS; pn ++)
1676 {
1677 if ((2 << (N_SCU_PORTS - 1 - pn)) & mask)
1678 {
1679 up -> mask_assignment [maskab] = (uint) pn;
1680 break;
1681 }
1682 }
1683
1684 }
1685 sim_debug (DBG_INTR, & scu_dev,
1686 "SCU%u SSCR1 mask %c enable set to %u assigned to "
1687 "port %u\n",
1688 scu_unit_idx, 'a' + maskab, up->mask_enable[maskab],
1689 up->mask_assignment[maskab]);
1690 }
1691
1692
1693
1694
1695
1696 up -> lower_store_size = (rega >> 24) & 07;
1697 up -> cyclic = (regq >> 8) & 0177;
1698 up -> nea = (rega >> 6) & 0377;
1699 up -> onl = (rega >> 20) & 017;
1700 up -> interlace = (rega >> 5) & 1;
1701 up -> lwr = (rega >> 4) & 1;
1702 up -> port_enable [0] = (rega >> 3) & 01;
1703 up -> port_enable [1] = (rega >> 2) & 01;
1704 up -> port_enable [2] = (rega >> 1) & 01;
1705 up -> port_enable [3] = (rega >> 0) & 01;
1706 up -> port_enable [4] = (regq >> 3) & 01;
1707 up -> port_enable [5] = (regq >> 2) & 01;
1708 up -> port_enable [6] = (regq >> 1) & 01;
1709 up -> port_enable [7] = (regq >> 0) & 01;
1710
1711 #if defined(THREADZ) || defined(LOCKLESS)
1712 unlock_scu ();
1713 #endif
1714
1715
1716 break;
1717 }
1718
1719 case 00002:
1720
1721
1722
1723
1724
1725
1726
1727 {
1728 #if defined(THREADZ) || defined(LOCKLESS)
1729 lock_scu ();
1730 #endif
1731 uint port_num = (addr >> 6) & 07;
1732 sim_debug (DBG_DEBUG, & scu_dev, "Set mask register port %d to "
1733 "%012"PRIo64",%012"PRIo64"\n",
1734 port_num, rega, regq);
1735
1736
1737 int mask_num = -1;
1738 uint n_masks_found = 0;
1739 for (int p = 0; p < N_ASSIGNMENTS; p ++)
1740 {
1741
1742 if (scu [scu_unit_idx].mask_enable [p] == 0)
1743 continue;
1744
1745 if (scu [scu_unit_idx ].mask_assignment [p] == port_num)
1746 {
1747 if (n_masks_found == 0)
1748 mask_num = p;
1749 n_masks_found ++;
1750 }
1751 }
1752
1753 if (! n_masks_found)
1754 {
1755
1756 sim_debug (DBG_WARN, & scu_dev,
1757 "%s: No masks assigned to cpu on port %d\n",
1758 __func__, port_num);
1759 #if defined(THREADZ) || defined(LOCKLESS)
1760 unlock_scu ();
1761 #endif
1762 return SCPE_OK;
1763 }
1764
1765 if (n_masks_found > 1)
1766 {
1767
1768 sim_debug (DBG_WARN, & scu_dev,
1769 "%s: Multiple masks assigned to cpu on port %d\n",
1770 __func__, port_num);
1771 }
1772
1773
1774
1775 scu [scu_unit_idx].exec_intr_mask [mask_num] = 0;
1776 scu [scu_unit_idx].exec_intr_mask [mask_num] |=
1777 ((word32) getbits36_16(rega, 0) << 16);
1778 scu [scu_unit_idx].exec_intr_mask [mask_num] |=
1779 getbits36_16(regq, 0);
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789 sim_debug (DBG_TRACE, & scu_dev,
1790 "SSCR Set mask unit %u port %u mask_num %u "
1791 "mask 0x%08x\n",
1792 scu_unit_idx, port_num, mask_num,
1793 scu [scu_unit_idx].exec_intr_mask [mask_num]);
1794 dump_intr_regs ("sscr set mask", scu_unit_idx);
1795 scu [scu_unit_idx].mask_enable [mask_num] = 1;
1796 sim_debug (DBG_INTR, & scu_dev,
1797 "SCU%u SSCR2 exec_intr mask %c set to 0x%08x"
1798 " and enabled.\n",
1799 scu_unit_idx, 'a' + mask_num,
1800 scu[scu_unit_idx].exec_intr_mask[mask_num]);
1801
1802 deliver_interrupts (scu_unit_idx);
1803 #if defined(THREADZ) || defined(LOCKLESS)
1804 unlock_scu ();
1805 #endif
1806 }
1807 break;
1808
1809 case 00003:
1810 {
1811 #if defined(THREADZ) || defined(LOCKLESS)
1812 lock_scu ();
1813 #endif
1814 for (uint i = 0; i < 16; i ++)
1815 {
1816 scu [scu_unit_idx].cells [i] =
1817 getbits36_1 (rega, i) ? 1 : 0;
1818 scu [scu_unit_idx].cells [i + 16] =
1819 getbits36_1 (regq, i) ? 1 : 0;
1820 }
1821 char pcellb [N_CELL_INTERRUPTS + 1];
1822 sim_debug (DBG_TRACE, & scu_dev,
1823 "SSCR Set int. cells: Unit %u Cells: %s\n",
1824 scu_unit_idx, pcells (scu_unit_idx, pcellb));
1825 sim_debug (DBG_INTR, & scu_dev,
1826 "SCU%u SSCR3 Set int. cells %s\n",
1827 scu_unit_idx, pcells (scu_unit_idx, pcellb));
1828 dump_intr_regs ("sscr set interrupt cells", scu_unit_idx);
1829 deliver_interrupts (scu_unit_idx);
1830 #if defined(THREADZ) || defined(LOCKLESS)
1831 unlock_scu ();
1832 #endif
1833 }
1834 break;
1835
1836 case 00004:
1837 case 00005:
1838 {
1839
1840 word16 b0_15 = (word16) getbits36_16 (cpu.rA, 20);
1841 word36 b16_51 = cpu.rQ;
1842 uint64 new_clk = (((uint64) b0_15) << 36) | b16_51;
1843 #if defined(THREADZ) || defined(LOCKLESS)
1844 lock_scu ();
1845 #endif
1846 scu [scu_unit_idx].user_correction =
1847 (int64) (new_clk - set_SCU_clock (cpup, scu_unit_idx));
1848 #if defined(THREADZ) || defined(LOCKLESS)
1849 unlock_scu ();
1850 #endif
1851
1852 }
1853 break;
1854
1855 case 00006:
1856 case 00007:
1857
1858
1859 sim_warn ("sscr set unit mode register\n");
1860
1861 return SCPE_OK;
1862
1863 default:
1864 sim_warn ("sscr unhandled code\n");
1865
1866 return SCPE_OK;
1867
1868 }
1869 return SCPE_OK;
1870 }
1871
1872 t_stat scu_rscr (cpu_state_t * cpup, uint scu_unit_idx, uint cpu_unit_udx, word18 addr,
1873 word36 * rega, word36 * regq)
1874 {
1875
1876
1877 if (scu_unit_idx >= scu_dev.numunits)
1878 {
1879 sim_warn ("%s: scu_unit_idx out of range %d\n",
1880 __func__, scu_unit_idx);
1881 return SCPE_OK;
1882 }
1883
1884
1885
1886
1887 uint function = (addr >> 3) & 07;
1888
1889
1890
1891
1892
1893 switch (function)
1894 {
1895 case 00000:
1896 {
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908 * rega = 0;
1909
1910 * regq = 0;
1911 #if defined(THREADZ) || defined(LOCKLESS)
1912 lock_scu ();
1913 #endif
1914 putbits36_4 (regq, 50 - 36, scu [scu_unit_idx].id);
1915 putbits36_18 (regq, 54 - 36, scu [scu_unit_idx].mode_reg);
1916 #if defined(THREADZ) || defined(LOCKLESS)
1917 unlock_scu ();
1918 #endif
1919 break;
1920 }
1921
1922 case 00001:
1923 {
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954 sim_debug (DBG_DEBUG, & scu_dev, "rscr 1 %d\n", scu_unit_idx);
1955 #if defined(THREADZ) || defined(LOCKLESS)
1956 lock_scu ();
1957 #endif
1958 scu_t * up = scu + scu_unit_idx;
1959 word9 maskab [2];
1960 for (int i = 0; i < 2; i ++)
1961 {
1962 if (up -> mask_enable [i])
1963 {
1964 maskab [i] = (2 << (N_SCU_PORTS - 1 -
1965 up -> mask_assignment [i])) & 0777;
1966 }
1967 else
1968 maskab [i] = 0001;
1969 }
1970
1971 int scu_port_num = -1;
1972
1973
1974 for (int pn = 0; pn < N_SCU_PORTS; pn ++)
1975 {
1976 for (int sn = 0; sn < N_SCU_SUBPORTS; sn ++)
1977 {
1978 if (cables->scu_to_cpu[scu_unit_idx][pn][sn].in_use &&
1979 cables->scu_to_cpu[scu_unit_idx][pn][sn].cpu_unit_idx ==
1980 cpu_unit_udx)
1981 {
1982 scu_port_num = pn;
1983 goto gotit;
1984 }
1985 }
1986 }
1987 gotit:;
1988 if (scu_port_num < 0)
1989 {
1990 #if defined(THREADZ) || defined(LOCKLESS)
1991 unlock_scu ();
1992 #endif
1993 sim_warn ("%s: can't find cpu port in the snarl of cables; "
1994 "scu_unit_no %d, cpu_unit_udx %d\n",
1995 __func__, scu_unit_idx, cpu_unit_udx);
1996 return SCPE_OK;
1997 }
1998
1999
2000 word36 a, q;
2001
2002 a = 0;
2003
2004 putbits36_9 (& a, 0, maskab [0]);
2005 putbits36_3 (& a, 9, (word3) up -> lower_store_size);
2006 putbits36_4 (& a, 12, (word4) up -> onl);
2007 putbits36_4 (& a, 16, (word4) scu_port_num);
2008 putbits36_1 (& a, 21, (word1) config_switches[scu_unit_idx].mode);
2009 putbits36_8 (& a, 22, (word8) up -> nea);
2010 putbits36_1 (& a, 30, (word1) up -> interlace);
2011 putbits36_1 (& a, 31, (word1) up -> lwr);
2012
2013
2014
2015
2016
2017 putbits36_1 (& a, 32, (word1) up -> port_enable [0]);
2018 putbits36_1 (& a, 33, (word1) up -> port_enable [1]);
2019 putbits36_1 (& a, 34, (word1) up -> port_enable [2]);
2020 putbits36_1 (& a, 35, (word1) up -> port_enable [3]);
2021 * rega = a;
2022
2023 q = 0;
2024 putbits36_9 (& q, 0, maskab [1]);
2025
2026 putbits36_7 (& q, 57-36, (word7) up -> cyclic & MASK7);
2027
2028
2029 putbits36_1 (& q, 32, (word1) up -> port_enable [4]);
2030 putbits36_1 (& q, 33, (word1) up -> port_enable [5]);
2031 putbits36_1 (& q, 34, (word1) up -> port_enable [6]);
2032 putbits36_1 (& q, 35, (word1) up -> port_enable [7]);
2033 * regq = q;
2034
2035 #if defined(THREADZ) || defined(LOCKLESS)
2036 unlock_scu ();
2037 #endif
2038 sim_debug (DBG_DEBUG, & scu_dev,
2039 "rscr 1 %d A: %012"PRIo64" Q: %012"PRIo64"\n",
2040 scu_unit_idx, * rega, * regq);
2041 break;
2042 }
2043
2044 case 00002:
2045 {
2046 uint port_num = (addr >> 6) & MASK3;
2047 #if defined(THREADZ) || defined(LOCKLESS)
2048 lock_scu ();
2049 #endif
2050 scu_t * up = scu + scu_unit_idx;
2051 uint mask_contents = 0;
2052 if (up -> mask_assignment [0] == port_num)
2053 {
2054 mask_contents = up -> exec_intr_mask [0];
2055 }
2056 else if (up -> mask_assignment [1] == port_num)
2057 {
2058 mask_contents = up -> exec_intr_mask [1];
2059 }
2060 mask_contents &= MASK32;
2061
2062 * rega = 0;
2063 putbits36 (rega, 0, 16, (mask_contents >> 16) & MASK16);
2064 putbits36 (rega, 32, 1, up -> port_enable [0]);
2065 putbits36 (rega, 33, 1, up -> port_enable [1]);
2066 putbits36 (rega, 34, 1, up -> port_enable [2]);
2067 putbits36 (rega, 35, 1, up -> port_enable [3]);
2068
2069 * regq = 0;
2070 putbits36 (rega, 0, 16, (mask_contents >> 0) & MASK16);
2071 putbits36 (regq, 32, 1, up -> port_enable [4]);
2072 putbits36 (regq, 33, 1, up -> port_enable [5]);
2073 putbits36 (regq, 34, 1, up -> port_enable [6]);
2074 putbits36 (regq, 35, 1, up -> port_enable [7]);
2075
2076 #if defined(THREADZ) || defined(LOCKLESS)
2077 unlock_scu ();
2078 #endif
2079 sim_debug (DBG_TRACE, & scu_dev,
2080 "RSCR mask unit %u port %u assigns %u %u mask 0x%08x\n",
2081 scu_unit_idx, port_num, up -> mask_assignment [0],
2082 up -> mask_assignment [1],
2083 mask_contents);
2084 }
2085 break;
2086
2087 case 00003:
2088 {
2089 #if defined(THREADZ) || defined(LOCKLESS)
2090 lock_scu ();
2091 #endif
2092 scu_t * up = scu + scu_unit_idx;
2093
2094
2095 for (uint i = 0; i < N_CELL_INTERRUPTS; i ++)
2096 {
2097 word1 cell = up -> cells [i] ? 1 : 0;
2098 if (i < 16)
2099 putbits36_1 (rega, i, cell);
2100 else
2101 putbits36_1 (regq, i - 16, cell);
2102 }
2103 #if defined(THREADZ) || defined(LOCKLESS)
2104 unlock_scu ();
2105 #endif
2106 }
2107 break;
2108
2109 case 00004:
2110 case 00005:
2111 {
2112 uint64 clk = set_SCU_clock (cpup, scu_unit_idx);
2113 cpu.rQ = clk & 0777777777777;
2114 cpu.rA = (clk >> 36) & 0177777;
2115 #if defined(TESTING)
2116 HDBGRegAW ("rscr get clock");
2117 HDBGRegQW ("rscr get clock");
2118 #endif
2119 }
2120 break;
2121
2122 case 00006:
2123 case 00007:
2124 {
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172 * rega = 0;
2173 * regq = 0;
2174 }
2175 break;
2176
2177 default:
2178 sim_warn ("rscr %o\n", function);
2179 return SCPE_OK;
2180 }
2181 return SCPE_OK;
2182 }
2183
2184
2185
2186
2187
2188 int scu_cioc (uint cpu_unit_udx, uint scu_unit_idx, uint scu_port_num,
2189 uint expander_command, uint sub_mask)
2190 {
2191
2192
2193
2194 #if defined(TESTING)
2195 cpu_state_t * cpup = _cpup;
2196 sim_debug (DBG_DEBUG, & scu_dev,
2197 "scu_cioc: Connect from %o sent to "
2198 "unit %o port %o exp %o mask %03o\n",
2199 cpu_unit_udx, scu_unit_idx, scu_port_num,
2200 expander_command, sub_mask);
2201 #endif
2202 #if defined(THREADZ) || defined(LOCKLESS)
2203 lock_scu ();
2204 #endif
2205 struct ports * portp = & scu [scu_unit_idx].ports [scu_port_num];
2206
2207 int rc = 0;
2208 if (! scu [scu_unit_idx].port_enable [scu_port_num])
2209 {
2210 sim_debug (DBG_ERR, & scu_dev,
2211 "scu_cioc: Connect sent to disabled port; dropping\n");
2212 sim_debug (DBG_ERR, & scu_dev,
2213 "scu_cioc: scu_unit_idx %u scu_port_num %u\n",
2214 scu_unit_idx, scu_port_num);
2215 rc = 1;
2216 goto done;
2217 }
2218
2219 if (expander_command == 1)
2220 {
2221 for (uint i = 0; i < N_SCU_SUBPORTS; i++)
2222 {
2223 portp->subport_enables [i] = !! (sub_mask & (0200u >> i));
2224 }
2225 goto done;
2226 }
2227
2228 if (expander_command == 2)
2229 {
2230 int cnt = 0;
2231 int val = -1;
2232 for (uint i = 0; i < N_SCU_SUBPORTS; i++)
2233 {
2234 portp->xipmask [i] = !! (sub_mask & (0200u >> i));
2235 if (portp->xipmask [i])
2236 {
2237 val = (int) i;
2238 cnt ++;
2239 }
2240 }
2241 if (cnt > 1)
2242 {
2243 sim_warn ("xip mask cnt > 1\n");
2244 val = -1;
2245 }
2246 portp->xipmaskval = val;
2247 goto done;
2248 }
2249
2250 if (portp -> type == ADEV_IOM)
2251 {
2252 int iom_unit_idx = portp->dev_idx;
2253 #if defined(THREADZ) || defined(LOCKLESS)
2254 unlock_scu ();
2255 # if !defined(IO_ASYNC_PAYLOAD_CHAN) && !defined(IO_ASYNC_PAYLOAD_CHAN_THREAD)
2256 lock_iom ();
2257 lock_libuv ();
2258 # endif
2259 iom_interrupt (scu_unit_idx, (uint) iom_unit_idx);
2260 # if !defined(IO_ASYNC_PAYLOAD_CHAN) && !defined(IO_ASYNC_PAYLOAD_CHAN_THREAD)
2261 unlock_libuv ();
2262 unlock_iom ();
2263 # endif
2264 return 0;
2265 #else
2266 if (sys_opts.iom_times.connect <= 0)
2267 {
2268 iom_interrupt (scu_unit_idx, (uint) iom_unit_idx);
2269 goto done;
2270 }
2271 else
2272 {
2273
2274
2275
2276 sim_debug (DBG_INFO, & scu_dev,
2277 "scu_cioc: Queuing an IOM in %d cycles "
2278 "(for the connect channel)\n",
2279 sys_opts.iom_times.connect);
2280
2281 iom_dev.units[iom_unit_idx].u3 = (int32) scu_unit_idx;
2282 iom_dev.units[iom_unit_idx].u4 = (int32) iom_unit_idx;
2283 int rc;
2284 if ((rc = sim_activate (& iom_dev.units [iom_unit_idx],
2285 sys_opts.iom_times.connect)) != SCPE_OK)
2286 {
2287 sim_warn ("sim_activate failed (%d)\n", rc);
2288 goto done;
2289 }
2290 goto done;
2291 }
2292 #endif
2293 }
2294 else if (portp -> type == ADEV_CPU)
2295 {
2296
2297
2298 if (portp->is_exp)
2299 {
2300 for (uint sn = 0; sn < N_SCU_SUBPORTS; sn ++)
2301 {
2302 if (portp->subport_enables[sn])
2303 {
2304 if (! cables->
2305 scu_to_cpu[scu_unit_idx][scu_port_num][sn].in_use)
2306 {
2307 sim_warn ("Can't find CPU to interrupt\n");
2308 continue;
2309 }
2310 uint cpu_unit_udx = cables->
2311 scu_to_cpu[scu_unit_idx][scu_port_num][sn].cpu_unit_idx;
2312 setG7fault ((uint) cpu_unit_udx, FAULT_CON, fst_zero);
2313 }
2314 }
2315 }
2316 else
2317 {
2318 if (! cables->scu_to_cpu[scu_unit_idx][scu_port_num][0].in_use)
2319 {
2320 sim_warn ("Can't find CPU to interrupt\n");
2321 rc = 1;
2322 goto done;
2323 }
2324 uint cpu_unit_udx =
2325 cables->scu_to_cpu[scu_unit_idx][scu_port_num][0].cpu_unit_idx;
2326 setG7fault ((uint) cpu_unit_udx, FAULT_CON, fst_zero);
2327 }
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350 goto done;
2351 }
2352 else
2353 {
2354 sim_debug (DBG_ERR, & scu_dev,
2355 "scu_cioc: Connect sent to not-an-IOM or CPU; dropping\n");
2356 rc = 1;
2357 goto done;
2358 }
2359 done:
2360 #if defined(THREADZ) || defined(LOCKLESS)
2361 unlock_scu ();
2362 #endif
2363 return rc;
2364 }
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376 int scu_set_interrupt (uint scu_unit_idx, uint inum)
2377 {
2378 #if defined(TESTING)
2379 cpu_state_t * cpup = _cpup;
2380 #endif
2381 const char* moi = "SCU::interrupt";
2382
2383 if (inum >= N_CELL_INTERRUPTS)
2384 {
2385 sim_debug (DBG_WARN, & scu_dev,
2386 "%s: Bad interrupt number %d\n", moi, inum);
2387 return 1;
2388 }
2389
2390 #if defined(THREADZ) || defined(LOCKLESS)
2391 lock_scu ();
2392 #endif
2393 scu [scu_unit_idx].cells [inum] = 1;
2394 dump_intr_regs ("scu_set_interrupt", scu_unit_idx);
2395 deliver_interrupts (scu_unit_idx);
2396 #if defined(THREADZ) || defined(LOCKLESS)
2397 unlock_scu ();
2398 #endif
2399 return 0;
2400 }
2401
2402
2403
2404
2405
2406
2407
2408 uint scu_get_highest_intr (uint scu_unit_idx)
2409 {
2410 #if defined(TESTING)
2411 cpu_state_t * cpup = _cpup;
2412 #endif
2413 #if defined(THREADZ) || defined(LOCKLESS)
2414 lock_scu ();
2415 #endif
2416
2417 for (int inum = 0; inum < N_CELL_INTERRUPTS; inum ++)
2418 {
2419 for (uint pima = 0; pima < N_ASSIGNMENTS; pima ++)
2420 {
2421 if (scu [scu_unit_idx].mask_enable [pima] == 0)
2422 continue;
2423 uint mask = scu [scu_unit_idx].exec_intr_mask [pima];
2424 uint port = scu [scu_unit_idx].mask_assignment [pima];
2425
2426
2427 if (scu[scu_unit_idx].ports[port].type != ADEV_CPU ||
2428 cpus[current_running_cpu_idx].scu_port[scu_unit_idx] != port)
2429 continue;
2430 if (scu [scu_unit_idx].cells [inum] &&
2431 (mask & (1u << (31 - inum))) != 0)
2432 {
2433 sim_debug (DBG_TRACE, & scu_dev,
2434 "scu_get_highest_intr inum %d pima %u mask 0%011o port %u cells 0%011o\n",
2435 inum, pima, mask, port, scu [scu_unit_idx].cells [inum]);
2436 scu [scu_unit_idx].cells [inum] = false;
2437 dump_intr_regs ("scu_get_highest_intr", scu_unit_idx);
2438 deliver_interrupts (scu_unit_idx);
2439 #if defined(THREADZ) || defined(LOCKLESS)
2440 unlock_scu ();
2441 #endif
2442 return (uint) inum * 2;
2443 }
2444 }
2445 }
2446 #if defined(THREADZ) || defined(LOCKLESS)
2447 unlock_scu ();
2448 #endif
2449 return 1;
2450 }
2451
2452 t_stat scu_reset_unit (UNIT * uptr, UNUSED int32 value,
2453 UNUSED const char * cptr,
2454 UNUSED void * desc)
2455 {
2456 uint scu_unit_idx = (uint) (uptr - scu_unit);
2457 scu_unit_reset ((int) scu_unit_idx);
2458 return SCPE_OK;
2459 }
2460
2461 void scu_init (void)
2462 {
2463
2464
2465 for (int u = 0; u < N_SCU_UNITS_MAX; u ++)
2466 {
2467 for (int p = 0; p < N_SCU_PORTS; p ++)
2468 {
2469 for (int s = 0; s < N_SCU_SUBPORTS; s ++)
2470 {
2471 scu[u].ports[p].dev_port[s] = -1;
2472 scu[u].ports[p].subport_enables[s] = false;
2473 scu[u].ports[p].xipmask[s] = false;
2474
2475 scu[u].ports[p].xipmaskval = N_SCU_SUBPORTS;
2476 }
2477 scu[u].ports[p].type = ADEV_NONE;
2478 scu[u].ports[p].is_exp = false;
2479 }
2480
2481
2482
2483
2484 scu [u].id = 02l;
2485 scu [u].mode_reg = 0;
2486 scu [u].elapsed_days = 0;
2487 }
2488
2489 }
2490
2491 t_stat scu_rmcm (uint scu_unit_idx, uint cpu_unit_udx, word36 * rega,
2492 word36 * regq)
2493 {
2494 #if defined(TESTING)
2495 cpu_state_t * cpup = _cpup;
2496 #endif
2497 scu_t * up = scu + scu_unit_idx;
2498
2499
2500 * rega = 0;
2501 * regq = 0;
2502
2503
2504
2505 int scu_port_num = -1;
2506
2507
2508 for (int pn = 0; pn < N_SCU_PORTS; pn ++)
2509 {
2510 for (int sn = 0; sn < N_SCU_SUBPORTS; sn ++)
2511 {
2512 if (cables->scu_to_cpu[scu_unit_idx][pn][sn].in_use &&
2513 cables->scu_to_cpu[scu_unit_idx][pn][sn].cpu_unit_idx ==
2514 cpu_unit_udx)
2515 {
2516 scu_port_num = pn;
2517 goto gotit;
2518 }
2519 }
2520 }
2521
2522 gotit:;
2523
2524
2525
2526 if (scu_port_num < 0)
2527 {
2528 sim_warn ("%s: can't find cpu port in the snarl of cables; "
2529 "scu_unit_no %d, cpu_unit_udx %d\n",
2530 __func__, scu_unit_idx, cpu_unit_udx);
2531 sim_debug (DBG_ERR, & scu_dev,
2532 "%s: can't find cpu port in the snarl of cables; "
2533 "scu_unit_no %d, cpu_unit_udx %d\n",
2534 __func__, scu_unit_idx, cpu_unit_udx);
2535
2536 return SCPE_OK;
2537 }
2538
2539
2540
2541
2542
2543
2544
2545
2546 sim_debug (DBG_TRACE, & scu_dev, "rmcm selected scu port %u\n",
2547 scu_port_num);
2548 #if defined(THREADZ) || defined(LOCKLESS)
2549 lock_scu ();
2550 #endif
2551 uint mask_contents = 0;
2552 if (up -> mask_assignment [0] == (uint) scu_port_num)
2553 {
2554 mask_contents = up -> exec_intr_mask [0];
2555 sim_debug (DBG_TRACE, & scu_dev, "rmcm got mask %011o from pima A\n",
2556 mask_contents);
2557 }
2558 else if (up -> mask_assignment [1] == (uint) scu_port_num)
2559 {
2560 mask_contents = up -> exec_intr_mask [1];
2561 sim_debug (DBG_TRACE, & scu_dev, "rmcm got mask %011o from pima B\n",
2562 mask_contents);
2563 }
2564 mask_contents &= MASK32;
2565
2566 * rega = 0;
2567 putbits36_16 (rega, 0, (mask_contents >> 16) & MASK16);
2568 putbits36_1 (rega, 32, (word1) up -> port_enable [0]);
2569 putbits36_1 (rega, 33, (word1) up -> port_enable [1]);
2570 putbits36_1 (rega, 34, (word1) up -> port_enable [2]);
2571 putbits36_1 (rega, 35, (word1) up -> port_enable [3]);
2572
2573 * regq = 0;
2574 putbits36_16 (regq, 0, (mask_contents >> 0) & MASK16);
2575 putbits36_1 (regq, 32, (word1) up -> port_enable [4]);
2576 putbits36_1 (regq, 33, (word1) up -> port_enable [5]);
2577 putbits36_1 (regq, 34, (word1) up -> port_enable [6]);
2578 putbits36_1 (regq, 35, (word1) up -> port_enable [7]);
2579
2580 #if defined(THREADZ) || defined(LOCKLESS)
2581 unlock_scu ();
2582 #endif
2583 sim_debug (DBG_TRACE, & scu_dev,
2584 "RMCM returns %012"PRIo64" %012"PRIo64"\n",
2585 * rega, * regq);
2586 dump_intr_regs ("rmcm", scu_unit_idx);
2587 return SCPE_OK;
2588 }
2589
2590 t_stat scu_smcm (uint scu_unit_idx, uint cpu_unit_udx, word36 rega, word36 regq)
2591 {
2592 #if defined(TESTING)
2593 cpu_state_t * cpup = _cpup;
2594 #endif
2595 sim_debug (DBG_TRACE, & scu_dev,
2596 "SMCM SCU unit %d CPU unit %d A %012"PRIo64" Q %012"PRIo64"\n",
2597 scu_unit_idx, cpu_unit_udx, rega, regq);
2598
2599 scu_t * up = scu + scu_unit_idx;
2600
2601
2602
2603 int scu_port_num = -1;
2604
2605
2606 for (int pn = 0; pn < N_SCU_PORTS; pn ++)
2607 {
2608 for (int sn = 0; sn < N_SCU_SUBPORTS; sn ++)
2609 {
2610 if (cables->scu_to_cpu[scu_unit_idx][pn][sn].in_use &&
2611 cables->scu_to_cpu[scu_unit_idx][pn][sn].cpu_unit_idx ==
2612 cpu_unit_udx)
2613 {
2614 scu_port_num = pn;
2615 goto gotit;
2616 }
2617 }
2618 }
2619 gotit:;
2620
2621
2622
2623 if (scu_port_num < 0)
2624 {
2625 sim_warn ("%s: can't find cpu port in the snarl of cables; "
2626 "scu_unit_no %d, cpu_unit_udx %d\n",
2627 __func__, scu_unit_idx, cpu_unit_udx);
2628 return SCPE_OK;
2629 }
2630
2631 sim_debug (DBG_TRACE, & scu_dev, "SMCM SCU port num %d\n", scu_port_num);
2632
2633
2634
2635
2636
2637
2638
2639
2640 uint imask =
2641 ((uint) getbits36_16(rega, 0) << 16) |
2642 ((uint) getbits36_16(regq, 0) << 0);
2643 #if defined(THREADZ) || defined(LOCKLESS)
2644 lock_scu ();
2645 #endif
2646 if (up -> mask_assignment [0] == (uint) scu_port_num)
2647 {
2648 up -> exec_intr_mask [0] = imask;
2649 sim_debug (DBG_TRACE, & scu_dev, "SMCM intr mask 0 set to %011o\n",
2650 imask);
2651 }
2652 else if (up -> mask_assignment [1] == (uint) scu_port_num)
2653 {
2654 up -> exec_intr_mask [1] = imask;
2655 sim_debug (DBG_TRACE, & scu_dev, "SMCM intr mask 1 set to %011o\n",
2656 imask);
2657 }
2658
2659 scu [scu_unit_idx].port_enable [0] = (uint) getbits36_1 (rega, 32);
2660 scu [scu_unit_idx].port_enable [1] = (uint) getbits36_1 (rega, 33);
2661 scu [scu_unit_idx].port_enable [2] = (uint) getbits36_1 (rega, 34);
2662 scu [scu_unit_idx].port_enable [3] = (uint) getbits36_1 (rega, 35);
2663 scu [scu_unit_idx].port_enable [4] = (uint) getbits36_1 (regq, 32);
2664 scu [scu_unit_idx].port_enable [5] = (uint) getbits36_1 (regq, 33);
2665 scu [scu_unit_idx].port_enable [6] = (uint) getbits36_1 (regq, 34);
2666 scu [scu_unit_idx].port_enable [7] = (uint) getbits36_1 (regq, 35);
2667
2668 dump_intr_regs ("smcm", scu_unit_idx);
2669 deliver_interrupts (scu_unit_idx);
2670 #if defined(THREADZ) || defined(LOCKLESS)
2671 unlock_scu ();
2672 #endif
2673
2674 return SCPE_OK;
2675 }