TSR                27 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TSR                74 src/dps8/doAppendCycleABSA.h   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
TSR                76 src/dps8/doAppendCycleABSA.h     DBGAPP ("doAppendCycleABSA(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TSR                81 src/dps8/doAppendCycleABSA.h       fetch_dsptw (cpup, cpu.TPR.TSR);
TSR                87 src/dps8/doAppendCycleABSA.h         modify_dsptw (cpup, cpu.TPR.TSR);
TSR                89 src/dps8/doAppendCycleABSA.h       fetch_psdw (cpup, cpu.TPR.TSR);
TSR                91 src/dps8/doAppendCycleABSA.h       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TSR                94 src/dps8/doAppendCycleABSA.h     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
TSR               154 src/dps8/doAppendCycleABSA.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TSR               242 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               264 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               281 src/dps8/doAppendCycleABSA.h   DBGAPP ("doAppendCycleABSA (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TSR                25 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TSR                78 src/dps8/doAppendCycleAPUDataRMW.h   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
TSR                80 src/dps8/doAppendCycleAPUDataRMW.h     DBGAPP ("doAppendCycleAPUDataRMW(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TSR                85 src/dps8/doAppendCycleAPUDataRMW.h       fetch_dsptw (cpup, cpu.TPR.TSR);
TSR                91 src/dps8/doAppendCycleAPUDataRMW.h         modify_dsptw (cpup, cpu.TPR.TSR);
TSR                93 src/dps8/doAppendCycleAPUDataRMW.h       fetch_psdw (cpup, cpu.TPR.TSR);
TSR                95 src/dps8/doAppendCycleAPUDataRMW.h       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TSR               103 src/dps8/doAppendCycleAPUDataRMW.h     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
TSR               168 src/dps8/doAppendCycleAPUDataRMW.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TSR               186 src/dps8/doAppendCycleAPUDataRMW.h   if (cpu.TPR.TSR == cpu.PPR.PSR)
TSR               294 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               322 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               348 src/dps8/doAppendCycleAPUDataRMW.h   DBGAPP ("doAppendCycleAPUDataRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TSR                25 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TSR                79 src/dps8/doAppendCycleAPUDataRead.h   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
TSR                81 src/dps8/doAppendCycleAPUDataRead.h     DBGAPP ("doAppendCycleAPUDataRead(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TSR                86 src/dps8/doAppendCycleAPUDataRead.h       fetch_dsptw (cpup, cpu.TPR.TSR);
TSR                92 src/dps8/doAppendCycleAPUDataRead.h         modify_dsptw (cpup, cpu.TPR.TSR);
TSR                94 src/dps8/doAppendCycleAPUDataRead.h       fetch_psdw (cpup, cpu.TPR.TSR);
TSR                96 src/dps8/doAppendCycleAPUDataRead.h       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TSR               104 src/dps8/doAppendCycleAPUDataRead.h     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
TSR               163 src/dps8/doAppendCycleAPUDataRead.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TSR               254 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               280 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               299 src/dps8/doAppendCycleAPUDataRead.h   DBGAPP ("doAppendCycleAPUDataRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TSR                25 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TSR                77 src/dps8/doAppendCycleAPUDataStore.h   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
TSR                79 src/dps8/doAppendCycleAPUDataStore.h     DBGAPP ("doAppendCycleAPUDataStore(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TSR                84 src/dps8/doAppendCycleAPUDataStore.h       fetch_dsptw (cpup, cpu.TPR.TSR);
TSR                90 src/dps8/doAppendCycleAPUDataStore.h           modify_dsptw (cpup, cpu.TPR.TSR);
TSR                92 src/dps8/doAppendCycleAPUDataStore.h       fetch_psdw (cpup, cpu.TPR.TSR);
TSR                94 src/dps8/doAppendCycleAPUDataStore.h       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TSR               102 src/dps8/doAppendCycleAPUDataStore.h     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
TSR               151 src/dps8/doAppendCycleAPUDataStore.h   if (cpu.TPR.TSR == cpu.PPR.PSR)
TSR               254 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               282 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               301 src/dps8/doAppendCycleAPUDataStore.h   DBGAPP ("doAppendCycleAPUDataStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TSR                61 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TSR                94 src/dps8/doAppendCycleIndirectWordFetch.h   if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged))
TSR               170 src/dps8/doAppendCycleIndirectWordFetch.h   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
TSR               172 src/dps8/doAppendCycleIndirectWordFetch.h     DBGAPP ("doAppendCycleIndirectWordFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TSR               176 src/dps8/doAppendCycleIndirectWordFetch.h       fetch_dsptw (cpup, cpu.TPR.TSR);
TSR               182 src/dps8/doAppendCycleIndirectWordFetch.h           modify_dsptw (cpup, cpu.TPR.TSR);
TSR               184 src/dps8/doAppendCycleIndirectWordFetch.h       fetch_psdw (cpup, cpu.TPR.TSR);
TSR               186 src/dps8/doAppendCycleIndirectWordFetch.h       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TSR               194 src/dps8/doAppendCycleIndirectWordFetch.h     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
TSR               259 src/dps8/doAppendCycleIndirectWordFetch.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TSR               362 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               391 src/dps8/doAppendCycleIndirectWordFetch.h   DBGAPP ("doAppendCycleIndirectWordFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               398 src/dps8/doAppendCycleIndirectWordFetch.h   ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged);
TSR               471 src/dps8/doAppendCycleIndirectWordFetch.h           cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TSR                72 src/dps8/doAppendCycleInstructionFetch.h   DBGAPP ("doAppendCycleInstructionFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TSR               148 src/dps8/doAppendCycleInstructionFetch.h       ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged);
TSR               151 src/dps8/doAppendCycleInstructionFetch.h   if (! ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged))
TSR               221 src/dps8/doAppendCycleInstructionFetch.h   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
TSR               223 src/dps8/doAppendCycleInstructionFetch.h     DBGAPP ("doAppendCycleInstructionFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TSR               228 src/dps8/doAppendCycleInstructionFetch.h       fetch_dsptw (cpup, cpu.TPR.TSR);
TSR               234 src/dps8/doAppendCycleInstructionFetch.h         modify_dsptw (cpup, cpu.TPR.TSR);
TSR               236 src/dps8/doAppendCycleInstructionFetch.h       fetch_psdw (cpup, cpu.TPR.TSR);
TSR               238 src/dps8/doAppendCycleInstructionFetch.h       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TSR               246 src/dps8/doAppendCycleInstructionFetch.h     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
TSR               495 src/dps8/doAppendCycleInstructionFetch.h   DBGAPP ("doAppendCycleInstructionFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               524 src/dps8/doAppendCycleInstructionFetch.h   DBGAPP ("doAppendCycleInstructionFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               552 src/dps8/doAppendCycleInstructionFetch.h       sim_printf ("ins fetch err  %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TSR               557 src/dps8/doAppendCycleInstructionFetch.h     hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TSR               562 src/dps8/doAppendCycleInstructionFetch.h     hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TSR               577 src/dps8/doAppendCycleInstructionFetch.h   ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged);
TSR               633 src/dps8/doAppendCycleInstructionFetch.h   cpu.PPR.PSR = cpu.TPR.TSR;
TSR               660 src/dps8/doAppendCycleInstructionFetch.h           cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TSR                25 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TSR                79 src/dps8/doAppendCycleOperandRMW.h   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
TSR                81 src/dps8/doAppendCycleOperandRMW.h     DBGAPP ("doAppendCycleOperandRMW(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TSR                85 src/dps8/doAppendCycleOperandRMW.h       fetch_dsptw (cpup, cpu.TPR.TSR);
TSR                91 src/dps8/doAppendCycleOperandRMW.h         modify_dsptw (cpup, cpu.TPR.TSR);
TSR                93 src/dps8/doAppendCycleOperandRMW.h       fetch_psdw (cpup, cpu.TPR.TSR);
TSR                95 src/dps8/doAppendCycleOperandRMW.h       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TSR               103 src/dps8/doAppendCycleOperandRMW.h     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
TSR               168 src/dps8/doAppendCycleOperandRMW.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TSR               186 src/dps8/doAppendCycleOperandRMW.h   if (cpu.TPR.TSR == cpu.PPR.PSR)
TSR               292 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               320 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               352 src/dps8/doAppendCycleOperandRMW.h   DBGAPP ("doAppendCycleOperandRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TSR                67 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TSR               135 src/dps8/doAppendCycleOperandRead.h       ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged);
TSR               138 src/dps8/doAppendCycleOperandRead.h             cacheHit ? "hit" : "miss", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, cachedBound,
TSR               143 src/dps8/doAppendCycleOperandRead.h   if (! ucCacheCheck (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) {
TSR               145 src/dps8/doAppendCycleOperandRead.h     hdbgNote ("doAppendCycleOperandRead.h", "miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TSR               161 src/dps8/doAppendCycleOperandRead.h   hdbgNote ("doAppendCycleOperandRead.h", "hit  %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TSR               171 src/dps8/doAppendCycleOperandRead.h   hdbgNote ("doAppendCycleOperandRead.h", "skip %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TSR               234 src/dps8/doAppendCycleOperandRead.h   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
TSR               236 src/dps8/doAppendCycleOperandRead.h     DBGAPP ("doAppendCycleOperandRead(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TSR               240 src/dps8/doAppendCycleOperandRead.h       fetch_dsptw (cpup, cpu.TPR.TSR);
TSR               246 src/dps8/doAppendCycleOperandRead.h         modify_dsptw (cpup, cpu.TPR.TSR);
TSR               248 src/dps8/doAppendCycleOperandRead.h       fetch_psdw (cpup, cpu.TPR.TSR);
TSR               250 src/dps8/doAppendCycleOperandRead.h       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TSR               258 src/dps8/doAppendCycleOperandRead.h     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
TSR               331 src/dps8/doAppendCycleOperandRead.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TSR               387 src/dps8/doAppendCycleOperandRead.h           cpu.SDW->E,  cpu.SDW->G,  cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu.SDW->EB,
TSR               405 src/dps8/doAppendCycleOperandRead.h   if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS)
TSR               605 src/dps8/doAppendCycleOperandRead.h           cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               638 src/dps8/doAppendCycleOperandRead.h           cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               673 src/dps8/doAppendCycleOperandRead.h               evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TSR               679 src/dps8/doAppendCycleOperandRead.h             evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TSR               685 src/dps8/doAppendCycleOperandRead.h             evcnt, cpu.TPR.TSR, cpu.TPR.CA);
TSR               690 src/dps8/doAppendCycleOperandRead.h   ucCacheSave (cpup, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged);
TSR               694 src/dps8/doAppendCycleOperandRead.h           evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged);
TSR               753 src/dps8/doAppendCycleOperandRead.h   cpu.PPR.PSR = cpu.TPR.TSR;
TSR               800 src/dps8/doAppendCycleOperandRead.h   cpu.PPR.PSR = cpu.TPR.TSR;
TSR               814 src/dps8/doAppendCycleOperandRead.h   DBGAPP ("doAppendCycleOperandRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TSR                25 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TSR                78 src/dps8/doAppendCycleOperandStore.h   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
TSR                80 src/dps8/doAppendCycleOperandStore.h     DBGAPP ("doAppendCycleOperandStore(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TSR                85 src/dps8/doAppendCycleOperandStore.h       fetch_dsptw (cpup, cpu.TPR.TSR);
TSR                91 src/dps8/doAppendCycleOperandStore.h         modify_dsptw (cpup, cpu.TPR.TSR);
TSR                93 src/dps8/doAppendCycleOperandStore.h       fetch_psdw (cpup, cpu.TPR.TSR);
TSR                95 src/dps8/doAppendCycleOperandStore.h       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TSR               103 src/dps8/doAppendCycleOperandStore.h     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
TSR               146 src/dps8/doAppendCycleOperandStore.h   if (cpu.TPR.TSR == cpu.PPR.PSR)
TSR               252 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               280 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               304 src/dps8/doAppendCycleOperandStore.h   DBGAPP ("doAppendCycleOperandStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TSR                25 src/dps8/doAppendCycleRTCDOperandFetch.h   DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR);
TSR                85 src/dps8/doAppendCycleRTCDOperandFetch.h     cpu.TPR.TSR = 0;
TSR                86 src/dps8/doAppendCycleRTCDOperandFetch.h     DBGAPP ("RTCD_OPERAND_FETCH ABSOLUTE mode set TSR %05o TRR %o\n", cpu.TPR.TSR, cpu.TPR.TRR);
TSR               109 src/dps8/doAppendCycleRTCDOperandFetch.h   if (nomatch || ! fetch_sdw_from_sdwam (cpup, cpu.TPR.TSR)) {
TSR               111 src/dps8/doAppendCycleRTCDOperandFetch.h     DBGAPP ("doAppendCycleRTCDOperandFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR);
TSR               115 src/dps8/doAppendCycleRTCDOperandFetch.h       fetch_dsptw (cpup, cpu.TPR.TSR);
TSR               121 src/dps8/doAppendCycleRTCDOperandFetch.h         modify_dsptw (cpup, cpu.TPR.TSR);
TSR               123 src/dps8/doAppendCycleRTCDOperandFetch.h       fetch_psdw (cpup, cpu.TPR.TSR);
TSR               125 src/dps8/doAppendCycleRTCDOperandFetch.h       fetch_nsdw (cpup, cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TSR               133 src/dps8/doAppendCycleRTCDOperandFetch.h     load_sdwam (cpup, cpu.TPR.TSR, nomatch);
TSR               192 src/dps8/doAppendCycleRTCDOperandFetch.h     if (cpu.PPR.PSR != cpu.TPR.TSR) {
TSR               291 src/dps8/doAppendCycleRTCDOperandFetch.h   DBGAPP ("doAppendCycleRTCDOperandFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               317 src/dps8/doAppendCycleRTCDOperandFetch.h   DBGAPP ("doAppendCycleRTCDOperandFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR               345 src/dps8/doAppendCycleRTCDOperandFetch.h   cpu.TPR.TSR = GET_ITS_SEGNO (data);
TSR               364 src/dps8/doAppendCycleRTCDOperandFetch.h   cpu.PPR.PSR = cpu.TPR.TSR;
TSR               392 src/dps8/doAppendCycleRTCDOperandFetch.h           cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TSR               221 src/dps8/dps8_addrmods.c     cpu.TPR.TSR  = cpu.PR[n].SNR;
TSR               257 src/dps8/dps8_addrmods.c     cpu.TPR.TSR = GET_ITS_SEGNO (cpu.itxPair);
TSR              1206 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.TPR.TSR);
TSR              1274 src/dps8/dps8_append.c         cpu.TPR.TSR = 0;
TSR              1276 src/dps8/dps8_append.c                 cpu.TPR.TSR, cpu.TPR.TRR);
TSR              1299 src/dps8/dps8_append.c     if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR))
TSR              1303 src/dps8/dps8_append.c                  cpu.TPR.TSR);
TSR              1310 src/dps8/dps8_append.c             fetch_dsptw (cpu.TPR.TSR);
TSR              1317 src/dps8/dps8_append.c               modify_dsptw (cpu.TPR.TSR);
TSR              1319 src/dps8/dps8_append.c             fetch_psdw (cpu.TPR.TSR);
TSR              1322 src/dps8/dps8_append.c           fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table.
TSR              1335 src/dps8/dps8_append.c         load_sdwam (cpu.TPR.TSR, nomatch);
TSR              1444 src/dps8/dps8_append.c             if (cpu.PPR.PSR != cpu.TPR.TSR)
TSR              1474 src/dps8/dps8_append.c         if (cpu.TPR.TSR == cpu.PPR.PSR)
TSR              1594 src/dps8/dps8_append.c             cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA,
TSR              1614 src/dps8/dps8_append.c     if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS)
TSR              1840 src/dps8/dps8_append.c             cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR              1878 src/dps8/dps8_append.c             cpu.TPR.TSR, cpu.TPR.CA, finalAddress);
TSR              2024 src/dps8/dps8_append.c     cpu.TPR.TSR = GET_ITS_SEGNO (data);
TSR              2110 src/dps8/dps8_append.c     cpu.PPR.PSR   = cpu.TPR.TSR;
TSR              2164 src/dps8/dps8_append.c     cpu.PPR.PSR   = cpu.TPR.TSR;
TSR              2214 src/dps8/dps8_append.c             cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA);
TSR              2642 src/dps8/dps8_cpu.c                 cpu.TPR.TSR          = cpu.PPR.PSR;
TSR              2657 src/dps8/dps8_cpu.c                 cpu.TPR.TSR              = cpu.PPR.PSR;
TSR              2725 src/dps8/dps8_cpu.c                   cpu.TPR.TSR          = cpu.PPR.PSR;
TSR              3017 src/dps8/dps8_cpu.c                   cpu.TPR.TSR          = cpu.PPR.PSR;
TSR              4413 src/dps8/dps8_cpu.c     putbits36_15 (& w0,      0,  cpu.TPR.TSR);
TSR                79 src/dps8/dps8_cpu.h     word15  TSR; // The current effective segment number
TSR               564 src/dps8/dps8_eis.c             cpu.TPR.TSR = p -> SNR;
TSR               577 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
TSR               590 src/dps8/dps8_eis.c             cpu.TPR.TSR = cpu.PPR.PSR;
TSR               601 src/dps8/dps8_eis.c                              __func__, p -> cachedParagraph [i], cpu.TPR.TSR, p -> cachedAddr + i);
TSR               605 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
TSR               641 src/dps8/dps8_eis.c         cpu.TPR.TSR = p -> SNR;
TSR               644 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
TSR               660 src/dps8/dps8_eis.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR               665 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
TSR               672 src/dps8/dps8_eis.c                          __func__, p -> cachedParagraph [i], cpu.TPR.TSR, paragraphAddress + i);
TSR               804 src/dps8/dps8_eis.c         cpu.TPR.TSR = p -> SNR;
TSR               814 src/dps8/dps8_eis.c                            __func__, data [i], cpu.TPR.TSR, addressN + i);
TSR               827 src/dps8/dps8_eis.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR               837 src/dps8/dps8_eis.c                          __func__, data [i], cpu.TPR.TSR, addressN + i);
TSR               866 src/dps8/dps8_eis.c         cpu.TPR.TSR = p -> SNR;
TSR               876 src/dps8/dps8_eis.c                            __func__, data [i], cpu.TPR.TSR, addressN + i);
TSR               889 src/dps8/dps8_eis.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR               899 src/dps8/dps8_eis.c                          __func__, data [i], cpu.TPR.TSR, addressN + i);
TSR               117 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TSR               125 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read BAR");
TSR               126 src/dps8/dps8_iefp.c                 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read BAR");
TSR               142 src/dps8/dps8_iefp.c                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read");
TSR               143 src/dps8/dps8_iefp.c                     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read");
TSR               196 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR               203 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRead BAR");
TSR               204 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead BAR");
TSR               215 src/dps8/dps8_iefp.c           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRead");
TSR               216 src/dps8/dps8_iefp.c           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead");
TSR               266 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR               273 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "readOperandRead BAR");
TSR               274 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead BAR");
TSR               286 src/dps8/dps8_iefp.c           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "readOperandRead");
TSR               287 src/dps8/dps8_iefp.c           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead");
TSR               338 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR               345 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadOperandRMW BAR");
TSR               346 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW BAR");
TSR               357 src/dps8/dps8_iefp.c           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadOperandRMW");
TSR               358 src/dps8/dps8_iefp.c           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW");
TSR               408 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR               415 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRMW BAR");
TSR               416 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW BAR");
TSR               427 src/dps8/dps8_iefp.c           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRMW");
TSR               428 src/dps8/dps8_iefp.c           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW");
TSR               480 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR               487 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadInstructionFetch BAR");
TSR               488 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch BAR");
TSR               499 src/dps8/dps8_iefp.c           HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadInstructionFetch");
TSR               500 src/dps8/dps8_iefp.c           HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch");
TSR               550 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR               557 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch BAR");
TSR               558 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch BAR");
TSR               569 src/dps8/dps8_iefp.c             HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch");
TSR               570 src/dps8/dps8_iefp.c             HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch");
TSR               633 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR               643 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR");
TSR               644 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn");
TSR               645 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd");
TSR               665 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2");
TSR               666 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn");
TSR               667 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd");
TSR               728 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR               738 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRead BR");
TSR               739 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead BR evn");
TSR               740 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead BR odd");
TSR               758 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRead");
TSR               759 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead evn");
TSR               760 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead odd");
TSR               820 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR               830 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRMW BR");
TSR               831 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW BR evn");
TSR               832 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW BR odd");
TSR               844 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRMW");
TSR               845 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW evn");
TSR               846 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW odd");
TSR               906 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR               916 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2InstructionFetch BR");
TSR               917 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch BR evn");
TSR               918 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch BR odd");
TSR               930 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2InstructionFetch");
TSR               931 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch evn");
TSR               932 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch odd");
TSR               947 src/dps8/dps8_iefp.c     cpu.TPR.TSR = cpu.PPR.PSR;
TSR               957 src/dps8/dps8_iefp.c     HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR");
TSR               958 src/dps8/dps8_iefp.c     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn");
TSR               959 src/dps8/dps8_iefp.c     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd");
TSR               971 src/dps8/dps8_iefp.c     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2");
TSR               972 src/dps8/dps8_iefp.c     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn");
TSR               973 src/dps8/dps8_iefp.c     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd");
TSR              1030 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR              1040 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch BR");
TSR              1041 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch BR evn");
TSR              1042 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch BR odd");
TSR              1054 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch");
TSR              1055 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch evn");
TSR              1056 src/dps8/dps8_iefp.c         HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch odd");
TSR              1130 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TSR              1143 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read8 BAR");
TSR              1145 src/dps8/dps8_iefp.c                   HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result[i], "Read8 BAR");
TSR              1165 src/dps8/dps8_iefp.c                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read8");
TSR              1167 src/dps8/dps8_iefp.c                       HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "Read8");
TSR              1254 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TSR              1267 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadPage B");
TSR              1269 src/dps8/dps8_iefp.c                   HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage B");
TSR              1290 src/dps8/dps8_iefp.c                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadPage");
TSR              1292 src/dps8/dps8_iefp.c                       HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage");
TSR              1348 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR              1355 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write BR");
TSR              1356 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write BR");
TSR              1365 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write");
TSR              1366 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write");
TSR              1418 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR              1425 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteAPUDataStore BR");
TSR              1426 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore BR");
TSR              1435 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteAPUDataStore");
TSR              1436 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore");
TSR              1492 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR              1499 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteOperandStore BR");
TSR              1500 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore BR");
TSR              1509 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteOperandStore");
TSR              1510 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore");
TSR              1574 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TSR              1582 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2 BR");
TSR              1583 src/dps8/dps8_iefp.c                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 BR evn");
TSR              1584 src/dps8/dps8_iefp.c                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 BR odd");
TSR              1596 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2");
TSR              1597 src/dps8/dps8_iefp.c                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 evn");
TSR              1598 src/dps8/dps8_iefp.c                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 odd");
TSR              1651 src/dps8/dps8_iefp.c         cpu.TPR.TSR = cpu.PPR.PSR;
TSR              1658 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2OperandStore BR");
TSR              1659 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore BR evn");
TSR              1660 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore BR odd");
TSR              1669 src/dps8/dps8_iefp.c         HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2OperandStore");
TSR              1670 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore evn");
TSR              1671 src/dps8/dps8_iefp.c         HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore odd");
TSR              1729 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TSR              1738 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write1 BR");
TSR              1739 src/dps8/dps8_iefp.c                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1 BR");
TSR              1752 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write1");
TSR              1753 src/dps8/dps8_iefp.c                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1");
TSR              1824 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TSR              1837 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write8 BR");
TSR              1839 src/dps8/dps8_iefp.c                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8 BR");
TSR              1857 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write8");
TSR              1859 src/dps8/dps8_iefp.c                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8");
TSR              1953 src/dps8/dps8_iefp.c                 cpu.TPR.TSR = cpu.PPR.PSR;
TSR              1967 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WritePage BR");
TSR              1969 src/dps8/dps8_iefp.c                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage BR");
TSR              1986 src/dps8/dps8_iefp.c                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WritePage");
TSR              1988 src/dps8/dps8_iefp.c                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage");
TSR               418 src/dps8/dps8_ins.c     putbits36_15 (& words[2], 3, cpu.TPR.TSR);
TSR               694 src/dps8/dps8_ins.c     cpu.TPR.TSR         = getbits36_15 (words[2], 3);
TSR              1906 src/dps8/dps8_ins.c             cpu.TPR.TSR = cpu.PPR.PSR;
TSR              1957 src/dps8/dps8_ins.c       cpu.TPR.TSR = cpu.PAR[n].SNR;
TSR              1965 src/dps8/dps8_ins.c                  n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR);
TSR              1982 src/dps8/dps8_ins.c           cpu.TPR.TSR  = cpu.PPR.PSR;
TSR              2074 src/dps8/dps8_ins.c     cpu.TPR.TSR = cpu.PPR.PSR;
TSR              2716 src/dps8/dps8_ins.c             cpu.PR[n].SNR    = cpu.TPR.TSR;
TSR              3028 src/dps8/dps8_ins.c             cpu.PR[n].SNR    = cpu.TPR.TSR;
TSR              3465 src/dps8/dps8_ins.c           cpu.rA |= (word36) (cpu.TPR.TSR & MASK15) << 18;
TSR                29 src/dps8/dps8_mp.h     word15 TSR;
TSR              4091 src/dps8/dps8_sys.c     { "cpus[].TPR.TSR",         SYM_STRUCT_OFFSET, SYM_UINT16_15, offsetof (struct tpr_s,          TSR)         },
TSR               433 src/dps8/panelScraper.c                 SETL (bank_a,  3+3, cpu.TPR.TSR, 15);
TSR               782 src/dps8/panelScraper.c