enable_wam 34 src/dps8/doAppendCycleABSA.h if (cpu.tweaks.enable_wam) { enable_wam 32 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.tweaks.enable_wam) { enable_wam 32 src/dps8/doAppendCycleAPUDataRead.h if (cpu.tweaks.enable_wam) { enable_wam 32 src/dps8/doAppendCycleAPUDataStore.h if (cpu.tweaks.enable_wam) { enable_wam 117 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.tweaks.enable_wam) { enable_wam 177 src/dps8/doAppendCycleInstructionFetch.h if (cpu.tweaks.enable_wam) { enable_wam 32 src/dps8/doAppendCycleOperandRMW.h if (cpu.tweaks.enable_wam) { enable_wam 181 src/dps8/doAppendCycleOperandRead.h if (cpu.tweaks.enable_wam) { enable_wam 32 src/dps8/doAppendCycleOperandStore.h if (cpu.tweaks.enable_wam) { enable_wam 32 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.tweaks.enable_wam) { enable_wam 171 src/dps8/dps8_append.c if (cpu.tweaks.enable_wam) enable_wam 340 src/dps8/dps8_append.c if ((! cpu.tweaks.enable_wam || ! cpu.cu.SD_ON)) { enable_wam 595 src/dps8/dps8_append.c if (nomatch || (! cpu.tweaks.enable_wam) || (! cpu.cu.SD_ON)) enable_wam 680 src/dps8/dps8_append.c if ((! cpu.tweaks.enable_wam) || (! cpu.cu.PT_ON)) enable_wam 830 src/dps8/dps8_append.c if (nomatch || (! cpu.tweaks.enable_wam) || (! cpu.cu.PT_ON)) enable_wam 1218 src/dps8/dps8_append.c if (cpu.tweaks.enable_wam) enable_wam 210 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].tweaks.enable_wam); enable_wam 574 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].tweaks.enable_wam = (uint) v; enable_wam 623 src/dps8/dps8_cpu.c cpus[cpu_unit_idx].tweaks.enable_wam = true; enable_wam 737 src/dps8/dps8_cpu.h uint enable_wam; // If zero, the simulated cache is ignored and always returns "miss"; enable_wam 7962 src/dps8/dps8_ins.c if (cpu.tweaks.enable_wam) enable_wam 8008 src/dps8/dps8_ins.c if (cpu.tweaks.enable_wam)