cpu 24 src/dps8/doAppendCycleABSA.h DCDstruct * i = & cpu.currentInstruction; cpu 26 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle)); cpu 27 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) CA %06o\n", cpu.TPR.CA); cpu 29 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); cpu 30 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); cpu 37 src/dps8/doAppendCycleABSA.h if (cpu.tweaks.enable_wam) { cpu 50 src/dps8/doAppendCycleABSA.h processor_cycle_type lastCycle = cpu.apu.lastCycle; cpu 51 src/dps8/doAppendCycleABSA.h cpu.apu.lastCycle = ABSA_CYCLE; cpu 53 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) XSF %o\n", cpu.cu.XSF); cpu 55 src/dps8/doAppendCycleABSA.h PNL (L68_ (cpu.apu.state = 0;)) cpu 57 src/dps8/doAppendCycleABSA.h cpu.RSDWH_R1 = 0; cpu 59 src/dps8/doAppendCycleABSA.h cpu.acvFaults = 0; cpu 72 src/dps8/doAppendCycleABSA.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) cpu 77 src/dps8/doAppendCycleABSA.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { cpu 79 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); cpu 81 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(A):DSBR.U=%o\n", cpu.DSBR.U); cpu 83 src/dps8/doAppendCycleABSA.h if (cpu.DSBR.U == 0) { cpu 84 src/dps8/doAppendCycleABSA.h fetch_dsptw (cpu.TPR.TSR); cpu 86 src/dps8/doAppendCycleABSA.h if (! cpu.PTW0.DF) cpu 87 src/dps8/doAppendCycleABSA.h doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleABSA(A): PTW0.F == 0"); cpu 89 src/dps8/doAppendCycleABSA.h if (! cpu.PTW0.U) cpu 90 src/dps8/doAppendCycleABSA.h modify_dsptw (cpu.TPR.TSR); cpu 92 src/dps8/doAppendCycleABSA.h fetch_psdw (cpu.TPR.TSR); cpu 94 src/dps8/doAppendCycleABSA.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. cpu 97 src/dps8/doAppendCycleABSA.h load_sdwam (cpu.TPR.TSR, nomatch); cpu 99 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E); cpu 102 src/dps8/doAppendCycleABSA.h cpu.RSDWH_R1 = cpu.SDW->R1; cpu 119 src/dps8/doAppendCycleABSA.h if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) { cpu 121 src/dps8/doAppendCycleABSA.h cpu.acvFaults |= ACV0; cpu 122 src/dps8/doAppendCycleABSA.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 143 src/dps8/doAppendCycleABSA.h if (cpu.TPR.TRR > cpu.SDW->R2) { cpu 147 src/dps8/doAppendCycleABSA.h cpu.acvFaults |= ACV3; cpu 148 src/dps8/doAppendCycleABSA.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 152 src/dps8/doAppendCycleABSA.h if (cpu.SDW->R == 0) { cpu 154 src/dps8/doAppendCycleABSA.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 157 src/dps8/doAppendCycleABSA.h if (cpu.PPR.PSR != cpu.TPR.TSR) { cpu 161 src/dps8/doAppendCycleABSA.h cpu.acvFaults |= ACV4; cpu 162 src/dps8/doAppendCycleABSA.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 178 src/dps8/doAppendCycleABSA.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { cpu 181 src/dps8/doAppendCycleABSA.h cpu.acvFaults |= ACV15; cpu 182 src/dps8/doAppendCycleABSA.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 186 src/dps8/doAppendCycleABSA.h cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); cpu 189 src/dps8/doAppendCycleABSA.h if (cpu.acvFaults) { cpu 191 src/dps8/doAppendCycleABSA.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 193 src/dps8/doAppendCycleABSA.h doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault"); cpu 197 src/dps8/doAppendCycleABSA.h if (cpu.SDW->U) cpu 203 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(G) CA %06o\n", cpu.TPR.CA); cpu 204 src/dps8/doAppendCycleABSA.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { //TPR.CA)) cpu 205 src/dps8/doAppendCycleABSA.h fetch_ptw (cpu.SDW, cpu.TPR.CA); cpu 206 src/dps8/doAppendCycleABSA.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM cpu 215 src/dps8/doAppendCycleABSA.h do_ptw2 (cpu.SDW, cpu.TPR.CA); cpu 228 src/dps8/doAppendCycleABSA.h PNL (L68_ (cpu.apu.state |= apu_FANP;)) cpu 238 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); cpu 240 src/dps8/doAppendCycleABSA.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; cpu 242 src/dps8/doAppendCycleABSA.h PNL (cpu.APUMemAddr = finalAddress;) cpu 244 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 252 src/dps8/doAppendCycleABSA.h PNL (L68_ (cpu.apu.state |= apu_FAP;)) cpu 254 src/dps8/doAppendCycleABSA.h word24 y2 = cpu.TPR.CA % 1024; cpu 258 src/dps8/doAppendCycleABSA.h finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2; cpu 260 src/dps8/doAppendCycleABSA.h PNL (cpu.APUMemAddr = finalAddress;) cpu 263 src/dps8/doAppendCycleABSA.h if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 266 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 277 src/dps8/doAppendCycleABSA.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) cpu 278 src/dps8/doAppendCycleABSA.h PNL (cpu.APUDataBusAddr = finalAddress;) cpu 280 src/dps8/doAppendCycleABSA.h PNL (L68_ (cpu.apu.state |= apu_FA;)) cpu 282 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu 283 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); cpu 22 src/dps8/doAppendCycleAPUDataRMW.h DCDstruct * i = & cpu.currentInstruction; cpu 24 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle)); cpu 25 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) CA %06o\n", cpu.TPR.CA); cpu 27 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); cpu 28 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); cpu 35 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.tweaks.enable_wam) { cpu 48 src/dps8/doAppendCycleAPUDataRMW.h processor_cycle_type lastCycle = cpu.apu.lastCycle; cpu 49 src/dps8/doAppendCycleAPUDataRMW.h cpu.apu.lastCycle = APU_DATA_RMW; cpu 51 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) XSF %o\n", cpu.cu.XSF); cpu 53 src/dps8/doAppendCycleAPUDataRMW.h PNL (L68_ (cpu.apu.state = 0;)) cpu 55 src/dps8/doAppendCycleAPUDataRMW.h cpu.RSDWH_R1 = 0; cpu 57 src/dps8/doAppendCycleAPUDataRMW.h cpu.acvFaults = 0; cpu 76 src/dps8/doAppendCycleAPUDataRMW.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) cpu 81 src/dps8/doAppendCycleAPUDataRMW.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { cpu 83 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); cpu 85 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(A):DSBR.U=%o\n", cpu.DSBR.U); cpu 87 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.DSBR.U == 0) { cpu 88 src/dps8/doAppendCycleAPUDataRMW.h fetch_dsptw (cpu.TPR.TSR); cpu 90 src/dps8/doAppendCycleAPUDataRMW.h if (! cpu.PTW0.DF) cpu 91 src/dps8/doAppendCycleAPUDataRMW.h doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleAPUDataRMW(A): PTW0.F == 0"); cpu 93 src/dps8/doAppendCycleAPUDataRMW.h if (! cpu.PTW0.U) cpu 94 src/dps8/doAppendCycleAPUDataRMW.h modify_dsptw (cpu.TPR.TSR); cpu 96 src/dps8/doAppendCycleAPUDataRMW.h fetch_psdw (cpu.TPR.TSR); cpu 98 src/dps8/doAppendCycleAPUDataRMW.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. cpu 100 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.SDW0.DF == 0) { cpu 103 src/dps8/doAppendCycleAPUDataRMW.h doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0"); cpu 106 src/dps8/doAppendCycleAPUDataRMW.h load_sdwam (cpu.TPR.TSR, nomatch); cpu 108 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E); cpu 111 src/dps8/doAppendCycleAPUDataRMW.h cpu.RSDWH_R1 = cpu.SDW->R1; cpu 128 src/dps8/doAppendCycleAPUDataRMW.h if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) { cpu 130 src/dps8/doAppendCycleAPUDataRMW.h cpu.acvFaults |= ACV0; cpu 131 src/dps8/doAppendCycleAPUDataRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 157 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TRR > cpu.SDW->R2) { cpu 161 src/dps8/doAppendCycleAPUDataRMW.h cpu.acvFaults |= ACV3; cpu 162 src/dps8/doAppendCycleAPUDataRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 166 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.SDW->R == 0) { cpu 168 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 171 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.PPR.PSR != cpu.TPR.TSR) { cpu 175 src/dps8/doAppendCycleAPUDataRMW.h cpu.acvFaults |= ACV4; cpu 176 src/dps8/doAppendCycleAPUDataRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 189 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TSR == cpu.PPR.PSR) cpu 190 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 193 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TRR > cpu.SDW->R1) { cpu 194 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1); cpu 196 src/dps8/doAppendCycleAPUDataRMW.h cpu.acvFaults |= ACV5; cpu 197 src/dps8/doAppendCycleAPUDataRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 201 src/dps8/doAppendCycleAPUDataRMW.h if (! cpu.SDW->W) { cpu 203 src/dps8/doAppendCycleAPUDataRMW.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 207 src/dps8/doAppendCycleAPUDataRMW.h cpu.acvFaults |= ACV6; cpu 208 src/dps8/doAppendCycleAPUDataRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 225 src/dps8/doAppendCycleAPUDataRMW.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { cpu 228 src/dps8/doAppendCycleAPUDataRMW.h cpu.acvFaults |= ACV15; cpu 229 src/dps8/doAppendCycleAPUDataRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 231 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); cpu 234 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.acvFaults) { cpu 236 src/dps8/doAppendCycleAPUDataRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 238 src/dps8/doAppendCycleAPUDataRMW.h doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault"); cpu 242 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.SDW->U) cpu 248 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(G) CA %06o\n", cpu.TPR.CA); cpu 249 src/dps8/doAppendCycleAPUDataRMW.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { cpu 250 src/dps8/doAppendCycleAPUDataRMW.h fetch_ptw (cpu.SDW, cpu.TPR.CA); cpu 251 src/dps8/doAppendCycleAPUDataRMW.h if (! cpu.PTW0.DF) { cpu 253 src/dps8/doAppendCycleAPUDataRMW.h doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0"); cpu 255 src/dps8/doAppendCycleAPUDataRMW.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM cpu 264 src/dps8/doAppendCycleAPUDataRMW.h do_ptw2 (cpu.SDW, cpu.TPR.CA); cpu 277 src/dps8/doAppendCycleAPUDataRMW.h PNL (L68_ (cpu.apu.state |= apu_FANP;)) cpu 289 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); cpu 291 src/dps8/doAppendCycleAPUDataRMW.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; cpu 293 src/dps8/doAppendCycleAPUDataRMW.h PNL (cpu.APUMemAddr = finalAddress;) cpu 295 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 304 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.PTW->M == 0) // is this the right way to do this? cpu 305 src/dps8/doAppendCycleAPUDataRMW.h modify_ptw (cpu.SDW, cpu.TPR.CA); cpu 309 src/dps8/doAppendCycleAPUDataRMW.h PNL (L68_ (cpu.apu.state |= apu_FAP;)) cpu 311 src/dps8/doAppendCycleAPUDataRMW.h word24 y2 = cpu.TPR.CA % 1024; cpu 315 src/dps8/doAppendCycleAPUDataRMW.h finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2; cpu 317 src/dps8/doAppendCycleAPUDataRMW.h PNL (cpu.APUMemAddr = finalAddress;) cpu 320 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 323 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 331 src/dps8/doAppendCycleAPUDataRMW.h cpu.cu.XSF = 1; cpu 343 src/dps8/doAppendCycleAPUDataRMW.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) cpu 344 src/dps8/doAppendCycleAPUDataRMW.h PNL (cpu.APUDataBusAddr = finalAddress;) cpu 346 src/dps8/doAppendCycleAPUDataRMW.h PNL (L68_ (cpu.apu.state |= apu_FA;)) cpu 348 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu 349 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); cpu 22 src/dps8/doAppendCycleAPUDataRead.h DCDstruct * i = & cpu.currentInstruction; cpu 24 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle)); cpu 25 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) CA %06o\n", cpu.TPR.CA); cpu 27 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); cpu 28 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); cpu 35 src/dps8/doAppendCycleAPUDataRead.h if (cpu.tweaks.enable_wam) { cpu 48 src/dps8/doAppendCycleAPUDataRead.h processor_cycle_type lastCycle = cpu.apu.lastCycle; cpu 49 src/dps8/doAppendCycleAPUDataRead.h cpu.apu.lastCycle = APU_DATA_READ; cpu 51 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) XSF %o\n", cpu.cu.XSF); cpu 53 src/dps8/doAppendCycleAPUDataRead.h PNL (L68_ (cpu.apu.state = 0;)) cpu 55 src/dps8/doAppendCycleAPUDataRead.h cpu.RSDWH_R1 = 0; cpu 57 src/dps8/doAppendCycleAPUDataRead.h cpu.acvFaults = 0; cpu 77 src/dps8/doAppendCycleAPUDataRead.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) cpu 82 src/dps8/doAppendCycleAPUDataRead.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { cpu 84 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); cpu 86 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(A):DSBR.U=%o\n", cpu.DSBR.U); cpu 88 src/dps8/doAppendCycleAPUDataRead.h if (cpu.DSBR.U == 0) { cpu 89 src/dps8/doAppendCycleAPUDataRead.h fetch_dsptw (cpu.TPR.TSR); cpu 91 src/dps8/doAppendCycleAPUDataRead.h if (! cpu.PTW0.DF) cpu 92 src/dps8/doAppendCycleAPUDataRead.h doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleAPUDataRead(A): PTW0.F == 0"); cpu 94 src/dps8/doAppendCycleAPUDataRead.h if (! cpu.PTW0.U) cpu 95 src/dps8/doAppendCycleAPUDataRead.h modify_dsptw (cpu.TPR.TSR); cpu 97 src/dps8/doAppendCycleAPUDataRead.h fetch_psdw (cpu.TPR.TSR); cpu 99 src/dps8/doAppendCycleAPUDataRead.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. cpu 101 src/dps8/doAppendCycleAPUDataRead.h if (cpu.SDW0.DF == 0) { cpu 104 src/dps8/doAppendCycleAPUDataRead.h doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0"); cpu 107 src/dps8/doAppendCycleAPUDataRead.h load_sdwam (cpu.TPR.TSR, nomatch); cpu 109 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E); cpu 112 src/dps8/doAppendCycleAPUDataRead.h cpu.RSDWH_R1 = cpu.SDW->R1; cpu 129 src/dps8/doAppendCycleAPUDataRead.h if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) { cpu 131 src/dps8/doAppendCycleAPUDataRead.h cpu.acvFaults |= ACV0; cpu 132 src/dps8/doAppendCycleAPUDataRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 152 src/dps8/doAppendCycleAPUDataRead.h if (cpu.TPR.TRR > cpu.SDW->R2) { cpu 156 src/dps8/doAppendCycleAPUDataRead.h cpu.acvFaults |= ACV3; cpu 157 src/dps8/doAppendCycleAPUDataRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 161 src/dps8/doAppendCycleAPUDataRead.h if (cpu.SDW->R == 0) { cpu 163 src/dps8/doAppendCycleAPUDataRead.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 166 src/dps8/doAppendCycleAPUDataRead.h if (cpu.PPR.PSR != cpu.TPR.TSR) { cpu 170 src/dps8/doAppendCycleAPUDataRead.h cpu.acvFaults |= ACV4; cpu 171 src/dps8/doAppendCycleAPUDataRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 187 src/dps8/doAppendCycleAPUDataRead.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { cpu 190 src/dps8/doAppendCycleAPUDataRead.h cpu.acvFaults |= ACV15; cpu 191 src/dps8/doAppendCycleAPUDataRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 193 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); cpu 196 src/dps8/doAppendCycleAPUDataRead.h if (cpu.acvFaults) { cpu 198 src/dps8/doAppendCycleAPUDataRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 200 src/dps8/doAppendCycleAPUDataRead.h doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault"); cpu 204 src/dps8/doAppendCycleAPUDataRead.h if (cpu.SDW->U) cpu 210 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(G) CA %06o\n", cpu.TPR.CA); cpu 211 src/dps8/doAppendCycleAPUDataRead.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { cpu 212 src/dps8/doAppendCycleAPUDataRead.h fetch_ptw (cpu.SDW, cpu.TPR.CA); cpu 213 src/dps8/doAppendCycleAPUDataRead.h if (! cpu.PTW0.DF) cpu 215 src/dps8/doAppendCycleAPUDataRead.h doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0"); cpu 216 src/dps8/doAppendCycleAPUDataRead.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM cpu 225 src/dps8/doAppendCycleAPUDataRead.h do_ptw2 (cpu.SDW, cpu.TPR.CA); cpu 238 src/dps8/doAppendCycleAPUDataRead.h PNL (L68_ (cpu.apu.state |= apu_FANP;)) cpu 249 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); cpu 251 src/dps8/doAppendCycleAPUDataRead.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; cpu 253 src/dps8/doAppendCycleAPUDataRead.h PNL (cpu.APUMemAddr = finalAddress;) cpu 255 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 267 src/dps8/doAppendCycleAPUDataRead.h PNL (L68_ (cpu.apu.state |= apu_FAP;)) cpu 269 src/dps8/doAppendCycleAPUDataRead.h word24 y2 = cpu.TPR.CA % 1024; cpu 273 src/dps8/doAppendCycleAPUDataRead.h finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2; cpu 275 src/dps8/doAppendCycleAPUDataRead.h PNL (cpu.APUMemAddr = finalAddress;) cpu 278 src/dps8/doAppendCycleAPUDataRead.h if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 281 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 287 src/dps8/doAppendCycleAPUDataRead.h cpu.cu.XSF = 1; cpu 294 src/dps8/doAppendCycleAPUDataRead.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) cpu 295 src/dps8/doAppendCycleAPUDataRead.h PNL (cpu.APUDataBusAddr = finalAddress;) cpu 297 src/dps8/doAppendCycleAPUDataRead.h PNL (L68_ (cpu.apu.state |= apu_FA;)) cpu 299 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu 300 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); cpu 22 src/dps8/doAppendCycleAPUDataStore.h DCDstruct * i = & cpu.currentInstruction; cpu 24 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle)); cpu 25 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) CA %06o\n", cpu.TPR.CA); cpu 27 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); cpu 28 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); cpu 35 src/dps8/doAppendCycleAPUDataStore.h if (cpu.tweaks.enable_wam) { cpu 48 src/dps8/doAppendCycleAPUDataStore.h processor_cycle_type lastCycle = cpu.apu.lastCycle; cpu 49 src/dps8/doAppendCycleAPUDataStore.h cpu.apu.lastCycle = APU_DATA_STORE; cpu 51 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) XSF %o\n", cpu.cu.XSF); cpu 53 src/dps8/doAppendCycleAPUDataStore.h PNL (L68_ (cpu.apu.state = 0;)) cpu 55 src/dps8/doAppendCycleAPUDataStore.h cpu.RSDWH_R1 = 0; cpu 57 src/dps8/doAppendCycleAPUDataStore.h cpu.acvFaults = 0; cpu 75 src/dps8/doAppendCycleAPUDataStore.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) cpu 80 src/dps8/doAppendCycleAPUDataStore.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { cpu 82 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); cpu 84 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(A):DSBR.U=%o\n", cpu.DSBR.U); cpu 86 src/dps8/doAppendCycleAPUDataStore.h if (cpu.DSBR.U == 0) { cpu 87 src/dps8/doAppendCycleAPUDataStore.h fetch_dsptw (cpu.TPR.TSR); cpu 89 src/dps8/doAppendCycleAPUDataStore.h if (! cpu.PTW0.DF) cpu 90 src/dps8/doAppendCycleAPUDataStore.h doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleAPUDataStore(A): PTW0.F == 0"); cpu 92 src/dps8/doAppendCycleAPUDataStore.h if (! cpu.PTW0.U) cpu 93 src/dps8/doAppendCycleAPUDataStore.h modify_dsptw (cpu.TPR.TSR); cpu 95 src/dps8/doAppendCycleAPUDataStore.h fetch_psdw (cpu.TPR.TSR); cpu 97 src/dps8/doAppendCycleAPUDataStore.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. cpu 99 src/dps8/doAppendCycleAPUDataStore.h if (cpu.SDW0.DF == 0) { cpu 102 src/dps8/doAppendCycleAPUDataStore.h doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0"); cpu 105 src/dps8/doAppendCycleAPUDataStore.h load_sdwam (cpu.TPR.TSR, nomatch); cpu 107 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E); cpu 110 src/dps8/doAppendCycleAPUDataStore.h cpu.RSDWH_R1 = cpu.SDW->R1; cpu 127 src/dps8/doAppendCycleAPUDataStore.h if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) { cpu 129 src/dps8/doAppendCycleAPUDataStore.h cpu.acvFaults |= ACV0; cpu 130 src/dps8/doAppendCycleAPUDataStore.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 154 src/dps8/doAppendCycleAPUDataStore.h if (cpu.TPR.TSR == cpu.PPR.PSR) cpu 155 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 158 src/dps8/doAppendCycleAPUDataStore.h if (cpu.TPR.TRR > cpu.SDW->R1) { cpu 159 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1); cpu 161 src/dps8/doAppendCycleAPUDataStore.h cpu.acvFaults |= ACV5; cpu 162 src/dps8/doAppendCycleAPUDataStore.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 166 src/dps8/doAppendCycleAPUDataStore.h if (! cpu.SDW->W) { cpu 168 src/dps8/doAppendCycleAPUDataStore.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 172 src/dps8/doAppendCycleAPUDataStore.h cpu.acvFaults |= ACV6; cpu 173 src/dps8/doAppendCycleAPUDataStore.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 186 src/dps8/doAppendCycleAPUDataStore.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { cpu 189 src/dps8/doAppendCycleAPUDataStore.h cpu.acvFaults |= ACV15; cpu 190 src/dps8/doAppendCycleAPUDataStore.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 192 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); cpu 195 src/dps8/doAppendCycleAPUDataStore.h if (cpu.acvFaults) { cpu 197 src/dps8/doAppendCycleAPUDataStore.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 199 src/dps8/doAppendCycleAPUDataStore.h doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault"); cpu 203 src/dps8/doAppendCycleAPUDataStore.h if (cpu.SDW->U) cpu 209 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(G) CA %06o\n", cpu.TPR.CA); cpu 210 src/dps8/doAppendCycleAPUDataStore.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { cpu 211 src/dps8/doAppendCycleAPUDataStore.h fetch_ptw (cpu.SDW, cpu.TPR.CA); cpu 212 src/dps8/doAppendCycleAPUDataStore.h if (! cpu.PTW0.DF) { cpu 214 src/dps8/doAppendCycleAPUDataStore.h doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0"); cpu 216 src/dps8/doAppendCycleAPUDataStore.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM cpu 226 src/dps8/doAppendCycleAPUDataStore.h do_ptw2 (cpu.SDW, cpu.TPR.CA); cpu 239 src/dps8/doAppendCycleAPUDataStore.h PNL (L68_ (cpu.apu.state |= apu_FANP;)) cpu 250 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); cpu 252 src/dps8/doAppendCycleAPUDataStore.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; cpu 254 src/dps8/doAppendCycleAPUDataStore.h PNL (cpu.APUMemAddr = finalAddress;) cpu 256 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 265 src/dps8/doAppendCycleAPUDataStore.h if (cpu.PTW->M == 0) // is this the right way to do this? cpu 266 src/dps8/doAppendCycleAPUDataStore.h modify_ptw (cpu.SDW, cpu.TPR.CA); cpu 270 src/dps8/doAppendCycleAPUDataStore.h PNL (L68_ (cpu.apu.state |= apu_FAP;)) cpu 272 src/dps8/doAppendCycleAPUDataStore.h word24 y2 = cpu.TPR.CA % 1024; cpu 276 src/dps8/doAppendCycleAPUDataStore.h finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2; cpu 278 src/dps8/doAppendCycleAPUDataStore.h PNL (cpu.APUMemAddr = finalAddress;) cpu 281 src/dps8/doAppendCycleAPUDataStore.h if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 284 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 292 src/dps8/doAppendCycleAPUDataStore.h cpu.cu.XSF = 1; cpu 297 src/dps8/doAppendCycleAPUDataStore.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) cpu 298 src/dps8/doAppendCycleAPUDataStore.h PNL (cpu.APUDataBusAddr = finalAddress;) cpu 300 src/dps8/doAppendCycleAPUDataStore.h PNL (L68_ (cpu.apu.state |= apu_FA;)) cpu 302 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu 303 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); cpu 58 src/dps8/doAppendCycleIndirectWordFetch.h DCDstruct * i = & cpu.currentInstruction; cpu 60 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle)); cpu 61 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) CA %06o\n", cpu.TPR.CA); cpu 63 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); cpu 64 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); cpu 97 src/dps8/doAppendCycleIndirectWordFetch.h if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) cpu 101 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); cpu 103 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = pageAddress + cpu.TPR.CA; cpu 105 src/dps8/doAppendCycleIndirectWordFetch.h cpu.RSDWH_R1 = RSDWH_R1; cpu 107 src/dps8/doAppendCycleIndirectWordFetch.h cpu.apu.lastCycle = INDIRECT_WORD_FETCH; cpu 112 src/dps8/doAppendCycleIndirectWordFetch.h cpu.uCache.skips[this] ++; cpu 120 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.tweaks.enable_wam) { cpu 133 src/dps8/doAppendCycleIndirectWordFetch.h processor_cycle_type lastCycle = cpu.apu.lastCycle; cpu 134 src/dps8/doAppendCycleIndirectWordFetch.h cpu.apu.lastCycle = INDIRECT_WORD_FETCH; cpu 136 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) XSF %o\n", cpu.cu.XSF); cpu 138 src/dps8/doAppendCycleIndirectWordFetch.h PNL (L68_ (cpu.apu.state = 0;)) cpu 140 src/dps8/doAppendCycleIndirectWordFetch.h cpu.RSDWH_R1 = 0; cpu 142 src/dps8/doAppendCycleIndirectWordFetch.h cpu.acvFaults = 0; cpu 168 src/dps8/doAppendCycleIndirectWordFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) cpu 173 src/dps8/doAppendCycleIndirectWordFetch.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { cpu 175 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); cpu 176 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(A):DSBR.U=%o\n", cpu.DSBR.U); cpu 178 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.DSBR.U == 0) { cpu 179 src/dps8/doAppendCycleIndirectWordFetch.h fetch_dsptw (cpu.TPR.TSR); cpu 181 src/dps8/doAppendCycleIndirectWordFetch.h if (! cpu.PTW0.DF) cpu 182 src/dps8/doAppendCycleIndirectWordFetch.h doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleIndirectWordFetch(A): PTW0.F == 0"); cpu 184 src/dps8/doAppendCycleIndirectWordFetch.h if (! cpu.PTW0.U) cpu 185 src/dps8/doAppendCycleIndirectWordFetch.h modify_dsptw (cpu.TPR.TSR); cpu 187 src/dps8/doAppendCycleIndirectWordFetch.h fetch_psdw (cpu.TPR.TSR); cpu 189 src/dps8/doAppendCycleIndirectWordFetch.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. cpu 191 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.SDW0.DF == 0) { cpu 194 src/dps8/doAppendCycleIndirectWordFetch.h doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0"); cpu 197 src/dps8/doAppendCycleIndirectWordFetch.h load_sdwam (cpu.TPR.TSR, nomatch); cpu 199 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E); cpu 202 src/dps8/doAppendCycleIndirectWordFetch.h RSDWH_R1 = cpu.RSDWH_R1 = cpu.SDW->R1; cpu 219 src/dps8/doAppendCycleIndirectWordFetch.h if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) { cpu 221 src/dps8/doAppendCycleIndirectWordFetch.h cpu.acvFaults |= ACV0; cpu 222 src/dps8/doAppendCycleIndirectWordFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 248 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.TPR.TRR > cpu.SDW->R2) { cpu 252 src/dps8/doAppendCycleIndirectWordFetch.h cpu.acvFaults |= ACV3; cpu 253 src/dps8/doAppendCycleIndirectWordFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 257 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.SDW->R == 0) { cpu 259 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 262 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.PPR.PSR != cpu.TPR.TSR) { cpu 266 src/dps8/doAppendCycleIndirectWordFetch.h cpu.acvFaults |= ACV4; cpu 267 src/dps8/doAppendCycleIndirectWordFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 287 src/dps8/doAppendCycleIndirectWordFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { cpu 290 src/dps8/doAppendCycleIndirectWordFetch.h cpu.acvFaults |= ACV15; cpu 291 src/dps8/doAppendCycleIndirectWordFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 293 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); cpu 295 src/dps8/doAppendCycleIndirectWordFetch.h bound = cpu.SDW->BOUND; cpu 296 src/dps8/doAppendCycleIndirectWordFetch.h p = cpu.SDW->P; cpu 298 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.acvFaults) { cpu 300 src/dps8/doAppendCycleIndirectWordFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 302 src/dps8/doAppendCycleIndirectWordFetch.h doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault"); cpu 306 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.SDW->U) cpu 312 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(G) CA %06o\n", cpu.TPR.CA); cpu 314 src/dps8/doAppendCycleIndirectWordFetch.h ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { cpu 315 src/dps8/doAppendCycleIndirectWordFetch.h fetch_ptw (cpu.SDW, cpu.TPR.CA); cpu 316 src/dps8/doAppendCycleIndirectWordFetch.h if (! cpu.PTW0.DF) { cpu 318 src/dps8/doAppendCycleIndirectWordFetch.h doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0"); cpu 320 src/dps8/doAppendCycleIndirectWordFetch.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM cpu 330 src/dps8/doAppendCycleIndirectWordFetch.h do_ptw2 (cpu.SDW, cpu.TPR.CA); cpu 345 src/dps8/doAppendCycleIndirectWordFetch.h PNL (L68_ (cpu.apu.state |= apu_FANP;)) cpu 356 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); cpu 358 src/dps8/doAppendCycleIndirectWordFetch.h pageAddress = (cpu.SDW->ADDR & 077777760); cpu 359 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; cpu 361 src/dps8/doAppendCycleIndirectWordFetch.h PNL (cpu.APUMemAddr = finalAddress;) cpu 363 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 377 src/dps8/doAppendCycleIndirectWordFetch.h PNL (L68_ (cpu.apu.state |= apu_FAP;)) cpu 379 src/dps8/doAppendCycleIndirectWordFetch.h word24 y2 = cpu.TPR.CA % 1024; cpu 381 src/dps8/doAppendCycleIndirectWordFetch.h pageAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6); cpu 384 src/dps8/doAppendCycleIndirectWordFetch.h finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2; cpu 386 src/dps8/doAppendCycleIndirectWordFetch.h PNL (cpu.APUMemAddr = finalAddress;) cpu 389 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 392 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 399 src/dps8/doAppendCycleIndirectWordFetch.h ucCacheSave (this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); cpu 402 src/dps8/doAppendCycleIndirectWordFetch.h cpu.cu.XSF = 1; cpu 419 src/dps8/doAppendCycleIndirectWordFetch.h if ((GET_TM (tag) == TM_IR || GET_TM (tag) == TM_RI) && (cpu.TPR.CA & 1) == 0) { cpu 437 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(O) TRR %o RSDWH.R1 %o ITS.RNR %o\n", cpu.TPR.TRR, cpu.RSDWH_R1, its_RNR); cpu 441 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = max3 (its_RNR, cpu.TPR.TRR, cpu.RSDWH_R1); cpu 442 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(O) Set TRR to %o\n", cpu.TPR.TRR); cpu 451 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(P) TRR %o RSDWH.R1 %o PR[n].RNR %o\n", cpu.TPR.TRR, cpu.RSDWH_R1, cpu.PR[n].RNR); cpu 455 src/dps8/doAppendCycleIndirectWordFetch.h cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.TPR.TRR, cpu.RSDWH_R1); cpu 456 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(P) Set TRR to %o\n", cpu.TPR.TRR); cpu 462 src/dps8/doAppendCycleIndirectWordFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) cpu 463 src/dps8/doAppendCycleIndirectWordFetch.h PNL (cpu.APUDataBusAddr = finalAddress;) cpu 465 src/dps8/doAppendCycleIndirectWordFetch.h PNL (L68_ (cpu.apu.state |= apu_FA;)) cpu 467 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu 468 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); cpu 68 src/dps8/doAppendCycleInstructionFetch.h DCDstruct * i = & cpu.currentInstruction; cpu 71 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle)); cpu 72 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) CA %06o\n", cpu.TPR.CA); cpu 74 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); cpu 75 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); cpu 123 src/dps8/doAppendCycleInstructionFetch.h if (cpu.rRALR) { cpu 148 src/dps8/doAppendCycleInstructionFetch.h cacheHit = ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); cpu 151 src/dps8/doAppendCycleInstructionFetch.h if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) cpu 156 src/dps8/doAppendCycleInstructionFetch.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); cpu 158 src/dps8/doAppendCycleInstructionFetch.h finalAddress = pageAddress + cpu.TPR.CA; cpu 160 src/dps8/doAppendCycleInstructionFetch.h cpu.RSDWH_R1 = RSDWH_R1; cpu 165 src/dps8/doAppendCycleInstructionFetch.h cpu.apu.lastCycle = INSTRUCTION_FETCH; cpu 171 src/dps8/doAppendCycleInstructionFetch.h cpu.uCache.skips[this] ++; cpu 177 src/dps8/doAppendCycleInstructionFetch.h if (cpu.tweaks.enable_wam) { cpu 190 src/dps8/doAppendCycleInstructionFetch.h processor_cycle_type lastCycle = cpu.apu.lastCycle; cpu 191 src/dps8/doAppendCycleInstructionFetch.h cpu.apu.lastCycle = INSTRUCTION_FETCH; cpu 193 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) XSF %o\n", cpu.cu.XSF); cpu 195 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state = 0;)) cpu 197 src/dps8/doAppendCycleInstructionFetch.h cpu.RSDWH_R1 = 0; cpu 199 src/dps8/doAppendCycleInstructionFetch.h cpu.acvFaults = 0; cpu 216 src/dps8/doAppendCycleInstructionFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) cpu 221 src/dps8/doAppendCycleInstructionFetch.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { cpu 223 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); cpu 225 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(A):DSBR.U=%o\n", cpu.DSBR.U); cpu 227 src/dps8/doAppendCycleInstructionFetch.h if (cpu.DSBR.U == 0) { cpu 228 src/dps8/doAppendCycleInstructionFetch.h fetch_dsptw (cpu.TPR.TSR); cpu 230 src/dps8/doAppendCycleInstructionFetch.h if (! cpu.PTW0.DF) cpu 231 src/dps8/doAppendCycleInstructionFetch.h doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleInstructionFetch(A): PTW0.F == 0"); cpu 233 src/dps8/doAppendCycleInstructionFetch.h if (! cpu.PTW0.U) cpu 234 src/dps8/doAppendCycleInstructionFetch.h modify_dsptw (cpu.TPR.TSR); cpu 236 src/dps8/doAppendCycleInstructionFetch.h fetch_psdw (cpu.TPR.TSR); cpu 238 src/dps8/doAppendCycleInstructionFetch.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. cpu 240 src/dps8/doAppendCycleInstructionFetch.h if (cpu.SDW0.DF == 0) { cpu 243 src/dps8/doAppendCycleInstructionFetch.h doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0"); cpu 246 src/dps8/doAppendCycleInstructionFetch.h load_sdwam (cpu.TPR.TSR, nomatch); cpu 248 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E); cpu 251 src/dps8/doAppendCycleInstructionFetch.h RSDWH_R1 = cpu.RSDWH_R1 = cpu.SDW->R1; cpu 268 src/dps8/doAppendCycleInstructionFetch.h if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) { cpu 270 src/dps8/doAppendCycleInstructionFetch.h cpu.acvFaults |= ACV0; cpu 271 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 312 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) { cpu 314 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(C) ACV1 ! ( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); cpu 316 src/dps8/doAppendCycleInstructionFetch.h cpu.acvFaults |= ACV1; cpu 317 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 321 src/dps8/doAppendCycleInstructionFetch.h if (! cpu.SDW->E) { cpu 325 src/dps8/doAppendCycleInstructionFetch.h cpu.acvFaults |= ACV2; cpu 326 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 329 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR > cpu.PPR.PRR) cpu 330 src/dps8/doAppendCycleInstructionFetch.h sim_warn ("rtcd: outbound call cpu.TPR.TRR %d cpu.PPR.PRR %d\n", cpu.TPR.TRR, cpu.PPR.PRR); cpu 332 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.PPR.PRR) { cpu 336 src/dps8/doAppendCycleInstructionFetch.h cpu.acvFaults |= ACV11; cpu 337 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 348 src/dps8/doAppendCycleInstructionFetch.h if (cpu.rRALR == 0) cpu 352 src/dps8/doAppendCycleInstructionFetch.h if (! (cpu.PPR.PRR < cpu.rRALR)) { cpu 354 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(D) C(PPR.PRR) %o < RALR %o\n", cpu.PPR.PRR, cpu.rRALR); cpu 355 src/dps8/doAppendCycleInstructionFetch.h cpu.acvFaults |= ACV13; cpu 356 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 369 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_PIAU;)) cpu 377 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) { cpu 379 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); cpu 380 src/dps8/doAppendCycleInstructionFetch.h cpu.acvFaults |= ACV1; cpu 381 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 385 src/dps8/doAppendCycleInstructionFetch.h if (! cpu.SDW->E) { cpu 388 src/dps8/doAppendCycleInstructionFetch.h cpu.acvFaults |= ACV2; cpu 389 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 394 src/dps8/doAppendCycleInstructionFetch.h if (cpu.PPR.PRR != cpu.TPR.TRR) { cpu 398 src/dps8/doAppendCycleInstructionFetch.h cpu.acvFaults |= ACV12; cpu 399 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 416 src/dps8/doAppendCycleInstructionFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { cpu 419 src/dps8/doAppendCycleInstructionFetch.h cpu.acvFaults |= ACV15; cpu 420 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 422 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); cpu 424 src/dps8/doAppendCycleInstructionFetch.h bound = cpu.SDW->BOUND; cpu 425 src/dps8/doAppendCycleInstructionFetch.h p = cpu.SDW->P; cpu 427 src/dps8/doAppendCycleInstructionFetch.h if (cpu.acvFaults) { cpu 429 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 431 src/dps8/doAppendCycleInstructionFetch.h doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault"); cpu 435 src/dps8/doAppendCycleInstructionFetch.h if (cpu.SDW->U) cpu 441 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(G) CA %06o\n", cpu.TPR.CA); cpu 443 src/dps8/doAppendCycleInstructionFetch.h ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { cpu 444 src/dps8/doAppendCycleInstructionFetch.h fetch_ptw (cpu.SDW, cpu.TPR.CA); cpu 445 src/dps8/doAppendCycleInstructionFetch.h if (! cpu.PTW0.DF) { cpu 447 src/dps8/doAppendCycleInstructionFetch.h doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0"); cpu 449 src/dps8/doAppendCycleInstructionFetch.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM cpu 461 src/dps8/doAppendCycleInstructionFetch.h do_ptw2 (cpu.SDW, cpu.TPR.CA); cpu 476 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_FANP;)) cpu 487 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); cpu 489 src/dps8/doAppendCycleInstructionFetch.h pageAddress = (cpu.SDW->ADDR & 077777760); cpu 490 src/dps8/doAppendCycleInstructionFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; cpu 492 src/dps8/doAppendCycleInstructionFetch.h PNL (cpu.APUMemAddr = finalAddress;) cpu 494 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 508 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_FAP;)) cpu 510 src/dps8/doAppendCycleInstructionFetch.h word24 y2 = cpu.TPR.CA % 1024; cpu 512 src/dps8/doAppendCycleInstructionFetch.h pageAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6); cpu 515 src/dps8/doAppendCycleInstructionFetch.h finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2; cpu 517 src/dps8/doAppendCycleInstructionFetch.h PNL (cpu.APUMemAddr = finalAddress;) cpu 520 src/dps8/doAppendCycleInstructionFetch.h if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 523 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 551 src/dps8/doAppendCycleInstructionFetch.h sim_printf ("ins fetch err %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); cpu 556 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); cpu 561 src/dps8/doAppendCycleInstructionFetch.h hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); cpu 576 src/dps8/doAppendCycleInstructionFetch.h ucCacheSave (this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); cpu 579 src/dps8/doAppendCycleInstructionFetch.h cpu.cu.XSF = 1; cpu 607 src/dps8/doAppendCycleInstructionFetch.h cpu.PR[0].RNR = cpu 608 src/dps8/doAppendCycleInstructionFetch.h cpu.PR[1].RNR = cpu 609 src/dps8/doAppendCycleInstructionFetch.h cpu.PR[2].RNR = cpu 610 src/dps8/doAppendCycleInstructionFetch.h cpu.PR[3].RNR = cpu 611 src/dps8/doAppendCycleInstructionFetch.h cpu.PR[4].RNR = cpu 612 src/dps8/doAppendCycleInstructionFetch.h cpu.PR[5].RNR = cpu 613 src/dps8/doAppendCycleInstructionFetch.h cpu.PR[6].RNR = cpu 614 src/dps8/doAppendCycleInstructionFetch.h cpu.PR[7].RNR = cpu.TPR.TRR; cpu 632 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.PSR = cpu.TPR.TSR; cpu 634 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.IC = cpu.TPR.CA; cpu 642 src/dps8/doAppendCycleInstructionFetch.h if (cpu.TPR.TRR == 0) { cpu 645 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.P = p; cpu 648 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.P = 0; cpu 651 src/dps8/doAppendCycleInstructionFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) cpu 652 src/dps8/doAppendCycleInstructionFetch.h PNL (cpu.APUDataBusAddr = finalAddress;) cpu 654 src/dps8/doAppendCycleInstructionFetch.h PNL (L68_ (cpu.apu.state |= apu_FA;)) cpu 656 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu 657 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); cpu 22 src/dps8/doAppendCycleOperandRMW.h DCDstruct * i = & cpu.currentInstruction; cpu 24 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle)); cpu 25 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) CA %06o\n", cpu.TPR.CA); cpu 27 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); cpu 28 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); cpu 35 src/dps8/doAppendCycleOperandRMW.h if (cpu.tweaks.enable_wam) { cpu 48 src/dps8/doAppendCycleOperandRMW.h processor_cycle_type lastCycle = cpu.apu.lastCycle; cpu 49 src/dps8/doAppendCycleOperandRMW.h cpu.apu.lastCycle = OPERAND_RMW; cpu 51 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) XSF %o\n", cpu.cu.XSF); cpu 53 src/dps8/doAppendCycleOperandRMW.h PNL (L68_ (cpu.apu.state = 0;)) cpu 55 src/dps8/doAppendCycleOperandRMW.h cpu.RSDWH_R1 = 0; cpu 57 src/dps8/doAppendCycleOperandRMW.h cpu.acvFaults = 0; cpu 77 src/dps8/doAppendCycleOperandRMW.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) cpu 82 src/dps8/doAppendCycleOperandRMW.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { cpu 84 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); cpu 85 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(A):DSBR.U=%o\n", cpu.DSBR.U); cpu 87 src/dps8/doAppendCycleOperandRMW.h if (cpu.DSBR.U == 0) { cpu 88 src/dps8/doAppendCycleOperandRMW.h fetch_dsptw (cpu.TPR.TSR); cpu 90 src/dps8/doAppendCycleOperandRMW.h if (! cpu.PTW0.DF) cpu 91 src/dps8/doAppendCycleOperandRMW.h doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleOperandRMW(A): PTW0.F == 0"); cpu 93 src/dps8/doAppendCycleOperandRMW.h if (! cpu.PTW0.U) cpu 94 src/dps8/doAppendCycleOperandRMW.h modify_dsptw (cpu.TPR.TSR); cpu 96 src/dps8/doAppendCycleOperandRMW.h fetch_psdw (cpu.TPR.TSR); cpu 98 src/dps8/doAppendCycleOperandRMW.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. cpu 100 src/dps8/doAppendCycleOperandRMW.h if (cpu.SDW0.DF == 0) { cpu 103 src/dps8/doAppendCycleOperandRMW.h doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0"); cpu 106 src/dps8/doAppendCycleOperandRMW.h load_sdwam (cpu.TPR.TSR, nomatch); cpu 108 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E); cpu 111 src/dps8/doAppendCycleOperandRMW.h cpu.RSDWH_R1 = cpu.SDW->R1; cpu 128 src/dps8/doAppendCycleOperandRMW.h if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) { cpu 130 src/dps8/doAppendCycleOperandRMW.h cpu.acvFaults |= ACV0; cpu 131 src/dps8/doAppendCycleOperandRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 157 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TRR > cpu.SDW->R2) { cpu 161 src/dps8/doAppendCycleOperandRMW.h cpu.acvFaults |= ACV3; cpu 162 src/dps8/doAppendCycleOperandRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 166 src/dps8/doAppendCycleOperandRMW.h if (cpu.SDW->R == 0) { cpu 168 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 171 src/dps8/doAppendCycleOperandRMW.h if (cpu.PPR.PSR != cpu.TPR.TSR) { cpu 175 src/dps8/doAppendCycleOperandRMW.h cpu.acvFaults |= ACV4; cpu 176 src/dps8/doAppendCycleOperandRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 189 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TSR == cpu.PPR.PSR) cpu 190 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 193 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TRR > cpu.SDW->R1) { cpu 194 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1); cpu 196 src/dps8/doAppendCycleOperandRMW.h cpu.acvFaults |= ACV5; cpu 197 src/dps8/doAppendCycleOperandRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 201 src/dps8/doAppendCycleOperandRMW.h if (! cpu.SDW->W) { cpu 203 src/dps8/doAppendCycleOperandRMW.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 207 src/dps8/doAppendCycleOperandRMW.h cpu.acvFaults |= ACV6; cpu 208 src/dps8/doAppendCycleOperandRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 225 src/dps8/doAppendCycleOperandRMW.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { cpu 228 src/dps8/doAppendCycleOperandRMW.h cpu.acvFaults |= ACV15; cpu 229 src/dps8/doAppendCycleOperandRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 231 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); cpu 234 src/dps8/doAppendCycleOperandRMW.h if (cpu.acvFaults) { cpu 236 src/dps8/doAppendCycleOperandRMW.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 238 src/dps8/doAppendCycleOperandRMW.h doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault"); cpu 242 src/dps8/doAppendCycleOperandRMW.h if (cpu.SDW->U) cpu 248 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(G) CA %06o\n", cpu.TPR.CA); cpu 249 src/dps8/doAppendCycleOperandRMW.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { cpu 250 src/dps8/doAppendCycleOperandRMW.h fetch_ptw (cpu.SDW, cpu.TPR.CA); cpu 251 src/dps8/doAppendCycleOperandRMW.h if (! cpu.PTW0.DF) { cpu 253 src/dps8/doAppendCycleOperandRMW.h doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0"); cpu 255 src/dps8/doAppendCycleOperandRMW.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM cpu 265 src/dps8/doAppendCycleOperandRMW.h do_ptw2 (cpu.SDW, cpu.TPR.CA); cpu 278 src/dps8/doAppendCycleOperandRMW.h PNL (L68_ (cpu.apu.state |= apu_FANP;)) cpu 288 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); cpu 290 src/dps8/doAppendCycleOperandRMW.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; cpu 292 src/dps8/doAppendCycleOperandRMW.h PNL (cpu.APUMemAddr = finalAddress;) cpu 294 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 303 src/dps8/doAppendCycleOperandRMW.h if (cpu.PTW->M == 0) // is this the right way to do this? cpu 304 src/dps8/doAppendCycleOperandRMW.h modify_ptw (cpu.SDW, cpu.TPR.CA); cpu 308 src/dps8/doAppendCycleOperandRMW.h PNL (L68_ (cpu.apu.state |= apu_FAP;)) cpu 310 src/dps8/doAppendCycleOperandRMW.h word24 y2 = cpu.TPR.CA % 1024; cpu 314 src/dps8/doAppendCycleOperandRMW.h finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2; cpu 316 src/dps8/doAppendCycleOperandRMW.h PNL (cpu.APUMemAddr = finalAddress;) cpu 319 src/dps8/doAppendCycleOperandRMW.h if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 322 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 330 src/dps8/doAppendCycleOperandRMW.h cpu.cu.XSF = 1; cpu 348 src/dps8/doAppendCycleOperandRMW.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) cpu 349 src/dps8/doAppendCycleOperandRMW.h PNL (cpu.APUDataBusAddr = finalAddress;) cpu 351 src/dps8/doAppendCycleOperandRMW.h PNL (L68_ (cpu.apu.state |= apu_FA;)) cpu 353 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu 354 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); cpu 63 src/dps8/doAppendCycleOperandRead.h DCDstruct * i = & cpu.currentInstruction; cpu 66 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle)); cpu 67 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) CA %06o\n", cpu.TPR.CA); cpu 69 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); cpu 70 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); cpu 104 src/dps8/doAppendCycleOperandRead.h cpu.uCache.call6Skips ++; cpu 121 src/dps8/doAppendCycleOperandRead.h if (cpu.rRALR && (cpu.PPR.PRR >= cpu.rRALR)) { cpu 123 src/dps8/doAppendCycleOperandRead.h cpu.uCache.ralrSkips ++; cpu 137 src/dps8/doAppendCycleOperandRead.h cacheHit = ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & cachedBound, & cachedP, & cachedAddress, & cachedR1, & cachedPaged); cpu 139 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "test cache check %s %d %u %05o:%06o %05o %o %08o %o %o", cacheHit ? "hit" : "miss", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, cachedBound, cachedP, cachedAddress, cachedR1, cachedPaged); cpu 143 src/dps8/doAppendCycleOperandRead.h if (! ucCacheCheck (this, cpu.TPR.TSR, cpu.TPR.CA, & bound, & p, & pageAddress, & RSDWH_R1, & paged)) { cpu 145 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); cpu 152 src/dps8/doAppendCycleOperandRead.h finalAddress = pageAddress + (cpu.TPR.CA & OS18MASK); cpu 154 src/dps8/doAppendCycleOperandRead.h finalAddress = pageAddress + cpu.TPR.CA; cpu 156 src/dps8/doAppendCycleOperandRead.h cpu.RSDWH_R1 = RSDWH_R1; cpu 161 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); cpu 164 src/dps8/doAppendCycleOperandRead.h cpu.apu.lastCycle = OPERAND_READ; cpu 171 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "skip %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); cpu 174 src/dps8/doAppendCycleOperandRead.h cpu.uCache.skips[this] ++; cpu 181 src/dps8/doAppendCycleOperandRead.h if (cpu.tweaks.enable_wam) { cpu 194 src/dps8/doAppendCycleOperandRead.h processor_cycle_type lastCycle = cpu.apu.lastCycle; cpu 195 src/dps8/doAppendCycleOperandRead.h cpu.apu.lastCycle = OPERAND_READ; cpu 197 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) XSF %o\n", cpu.cu.XSF); cpu 199 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state = 0;)) cpu 201 src/dps8/doAppendCycleOperandRead.h cpu.RSDWH_R1 = 0; cpu 203 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults = 0; cpu 229 src/dps8/doAppendCycleOperandRead.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) cpu 234 src/dps8/doAppendCycleOperandRead.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { cpu 236 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); cpu 237 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(A):DSBR.U=%o\n", cpu.DSBR.U); cpu 239 src/dps8/doAppendCycleOperandRead.h if (cpu.DSBR.U == 0) { cpu 240 src/dps8/doAppendCycleOperandRead.h fetch_dsptw (cpu.TPR.TSR); cpu 242 src/dps8/doAppendCycleOperandRead.h if (! cpu.PTW0.DF) cpu 243 src/dps8/doAppendCycleOperandRead.h doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleOperandRead(A): PTW0.F == 0"); cpu 245 src/dps8/doAppendCycleOperandRead.h if (! cpu.PTW0.U) cpu 246 src/dps8/doAppendCycleOperandRead.h modify_dsptw (cpu.TPR.TSR); cpu 248 src/dps8/doAppendCycleOperandRead.h fetch_psdw (cpu.TPR.TSR); cpu 250 src/dps8/doAppendCycleOperandRead.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. cpu 252 src/dps8/doAppendCycleOperandRead.h if (cpu.SDW0.DF == 0) { cpu 255 src/dps8/doAppendCycleOperandRead.h doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0"); cpu 258 src/dps8/doAppendCycleOperandRead.h load_sdwam (cpu.TPR.TSR, nomatch); cpu 260 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E); cpu 263 src/dps8/doAppendCycleOperandRead.h RSDWH_R1 = cpu.RSDWH_R1 = cpu.SDW->R1; cpu 280 src/dps8/doAppendCycleOperandRead.h if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) { cpu 282 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults |= ACV0; cpu 283 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 317 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.SDW->R2) { cpu 321 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults |= ACV3; cpu 322 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 326 src/dps8/doAppendCycleOperandRead.h if (cpu.SDW->R == 0) { cpu 328 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 331 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PSR != cpu.TPR.TSR) { cpu 335 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults |= ACV4; cpu 336 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 358 src/dps8/doAppendCycleOperandRead.h if (cpu.rRALR == 0) cpu 362 src/dps8/doAppendCycleOperandRead.h if (! (cpu.PPR.PRR < cpu.rRALR)) { cpu 364 src/dps8/doAppendCycleOperandRead.h DBGAPP ("acvFaults(D) C(PPR.PRR) %o < RALR %o\n", cpu.PPR.PRR, cpu.rRALR); cpu 365 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults |= ACV13; cpu 366 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 386 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(E): E %o G %o PSR %05o TSR %05o CA %06o " "EB %06o R %o%o%o TRR %o PRR %o\n", cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu.SDW->EB, cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.TPR.TRR, cpu.PPR.PRR); cpu 389 src/dps8/doAppendCycleOperandRead.h if (! cpu.SDW->E) { cpu 393 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults |= ACV2; cpu 394 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 399 src/dps8/doAppendCycleOperandRead.h if (cpu.SDW->G) cpu 403 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS) cpu 409 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.CA >= (word18) cpu.SDW->EB) { cpu 413 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults |= ACV7; cpu 414 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 422 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.SDW->R3) { cpu 426 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults |= ACV8; cpu 427 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 432 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR < cpu.SDW->R1) { cpu 436 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults |= ACV9; cpu 437 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 442 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.PPR.PRR) { cpu 444 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PRR < cpu.SDW->R2) { cpu 448 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults |= ACV10; cpu 449 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 454 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o SDW->R2 %o\n", cpu.TPR.TRR, cpu.SDW->R2); cpu 457 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR > cpu.SDW->R2) { cpu 459 src/dps8/doAppendCycleOperandRead.h cpu.TPR.TRR = cpu.SDW->R2; cpu 462 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(E1): CALL6 TPR.TRR %o\n", cpu.TPR.TRR); cpu 473 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_PIAU;)) cpu 482 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR < cpu.SDW->R1 || cpu.TPR.TRR > cpu.SDW->R2) { cpu 484 src/dps8/doAppendCycleOperandRead.h DBGAPP ("acvFaults(F) ACV1 !( C(SDW .R1) %o <= C(TPR.TRR) %o <= C(SDW .R2) %o )\n", cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); cpu 485 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults |= ACV1; cpu 486 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 490 src/dps8/doAppendCycleOperandRead.h if (! cpu.SDW->E) { cpu 493 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults |= ACV2; cpu 494 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 499 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PRR != cpu.TPR.TRR) { cpu 503 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults |= ACV12; cpu 504 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 521 src/dps8/doAppendCycleOperandRead.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { cpu 524 src/dps8/doAppendCycleOperandRead.h cpu.acvFaults |= ACV15; cpu 525 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 527 src/dps8/doAppendCycleOperandRead.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); cpu 529 src/dps8/doAppendCycleOperandRead.h bound = cpu.SDW->BOUND; cpu 530 src/dps8/doAppendCycleOperandRead.h p = cpu.SDW->P; cpu 532 src/dps8/doAppendCycleOperandRead.h if (cpu.acvFaults) { cpu 534 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 536 src/dps8/doAppendCycleOperandRead.h doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault"); cpu 540 src/dps8/doAppendCycleOperandRead.h if (cpu.SDW->U) cpu 546 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(G) CA %06o\n", cpu.TPR.CA); cpu 548 src/dps8/doAppendCycleOperandRead.h ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { cpu 549 src/dps8/doAppendCycleOperandRead.h fetch_ptw (cpu.SDW, cpu.TPR.CA); cpu 550 src/dps8/doAppendCycleOperandRead.h if (! cpu.PTW0.DF) { cpu 552 src/dps8/doAppendCycleOperandRead.h doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0"); cpu 554 src/dps8/doAppendCycleOperandRead.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM cpu 564 src/dps8/doAppendCycleOperandRead.h do_ptw2 (cpu.SDW, cpu.TPR.CA); cpu 579 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FANP;)) cpu 591 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); cpu 593 src/dps8/doAppendCycleOperandRead.h pageAddress = (cpu.SDW->ADDR & 077777760); cpu 594 src/dps8/doAppendCycleOperandRead.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; cpu 596 src/dps8/doAppendCycleOperandRead.h PNL (cpu.APUMemAddr = finalAddress;) cpu 598 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 615 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FAP;)) cpu 617 src/dps8/doAppendCycleOperandRead.h word24 y2 = cpu.TPR.CA % 1024; cpu 619 src/dps8/doAppendCycleOperandRead.h pageAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6); cpu 622 src/dps8/doAppendCycleOperandRead.h finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2; cpu 624 src/dps8/doAppendCycleOperandRead.h PNL (cpu.APUMemAddr = finalAddress;) cpu 627 src/dps8/doAppendCycleOperandRead.h if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 630 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 660 src/dps8/doAppendCycleOperandRead.h sim_printf ("oprnd read err %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); cpu 665 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "test hit %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); cpu 670 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "test miss %d %05o:%06o\r\n", evcnt, cpu.TPR.TSR, cpu.TPR.CA); cpu 675 src/dps8/doAppendCycleOperandRead.h ucCacheSave (this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); cpu 678 src/dps8/doAppendCycleOperandRead.h hdbgNote ("doAppendCycleOperandRead.h", "cache %d %u %05o:%06o %05o %o %08o %o %o", evcnt, this, cpu.TPR.TSR, cpu.TPR.CA, bound, p, pageAddress, RSDWH_R1, paged); cpu 684 src/dps8/doAppendCycleOperandRead.h cpu.cu.XSF = 1; cpu 721 src/dps8/doAppendCycleOperandRead.h cpu.PR[n].RNR = cpu.PPR.PRR; cpu 725 src/dps8/doAppendCycleOperandRead.h cpu.PR[n].SNR = cpu.PPR.PSR; cpu 726 src/dps8/doAppendCycleOperandRead.h cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; cpu 737 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PSR = cpu.TPR.TSR; cpu 739 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; cpu 747 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR == 0) { cpu 749 src/dps8/doAppendCycleOperandRead.h cpu.PPR.P = p; cpu 752 src/dps8/doAppendCycleOperandRead.h cpu.PPR.P = 0; cpu 761 src/dps8/doAppendCycleOperandRead.h if (cpu.TPR.TRR == cpu.PPR.PRR) { cpu 763 src/dps8/doAppendCycleOperandRead.h cpu.PR[7].SNR = cpu.PR[6].SNR; cpu 764 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(N) PR7.SNR = PR6.SNR %05o\n", cpu.PR[7].SNR); cpu 767 src/dps8/doAppendCycleOperandRead.h cpu.PR[7].SNR = ((word15) (cpu.DSBR.STACK << 3)) | cpu.TPR.TRR; cpu 768 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(N) STACK %05o TRR %o\n", cpu.DSBR.STACK, cpu.TPR.TRR); cpu 769 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(N) PR7.SNR = STACK||TRR %05o\n", cpu.PR[7].SNR); cpu 773 src/dps8/doAppendCycleOperandRead.h cpu.PR[7].RNR = cpu.TPR.TRR; cpu 775 src/dps8/doAppendCycleOperandRead.h cpu.PR[7].WORDNO = 0; cpu 782 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PRR = cpu.TPR.TRR; cpu 784 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PSR = cpu.TPR.TSR; cpu 786 src/dps8/doAppendCycleOperandRead.h cpu.PPR.IC = cpu.TPR.CA; cpu 792 src/dps8/doAppendCycleOperandRead.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) cpu 793 src/dps8/doAppendCycleOperandRead.h PNL (cpu.APUDataBusAddr = finalAddress;) cpu 795 src/dps8/doAppendCycleOperandRead.h PNL (L68_ (cpu.apu.state |= apu_FA;)) cpu 797 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu 798 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); cpu 22 src/dps8/doAppendCycleOperandStore.h DCDstruct * i = & cpu.currentInstruction; cpu 24 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle)); cpu 25 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) CA %06o\n", cpu.TPR.CA); cpu 27 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); cpu 28 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); cpu 35 src/dps8/doAppendCycleOperandStore.h if (cpu.tweaks.enable_wam) { cpu 48 src/dps8/doAppendCycleOperandStore.h processor_cycle_type lastCycle = cpu.apu.lastCycle; cpu 49 src/dps8/doAppendCycleOperandStore.h cpu.apu.lastCycle = OPERAND_STORE; cpu 51 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) XSF %o\n", cpu.cu.XSF); cpu 53 src/dps8/doAppendCycleOperandStore.h PNL (L68_ (cpu.apu.state = 0;)) cpu 55 src/dps8/doAppendCycleOperandStore.h cpu.RSDWH_R1 = 0; cpu 57 src/dps8/doAppendCycleOperandStore.h cpu.acvFaults = 0; cpu 76 src/dps8/doAppendCycleOperandStore.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) cpu 81 src/dps8/doAppendCycleOperandStore.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { cpu 83 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); cpu 85 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(A):DSBR.U=%o\n", cpu.DSBR.U); cpu 87 src/dps8/doAppendCycleOperandStore.h if (cpu.DSBR.U == 0) { cpu 88 src/dps8/doAppendCycleOperandStore.h fetch_dsptw (cpu.TPR.TSR); cpu 90 src/dps8/doAppendCycleOperandStore.h if (! cpu.PTW0.DF) cpu 91 src/dps8/doAppendCycleOperandStore.h doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleOperandStore(A): PTW0.F == 0"); cpu 93 src/dps8/doAppendCycleOperandStore.h if (! cpu.PTW0.U) cpu 94 src/dps8/doAppendCycleOperandStore.h modify_dsptw (cpu.TPR.TSR); cpu 96 src/dps8/doAppendCycleOperandStore.h fetch_psdw (cpu.TPR.TSR); cpu 98 src/dps8/doAppendCycleOperandStore.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. cpu 100 src/dps8/doAppendCycleOperandStore.h if (cpu.SDW0.DF == 0) { cpu 103 src/dps8/doAppendCycleOperandStore.h doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0"); cpu 106 src/dps8/doAppendCycleOperandStore.h load_sdwam (cpu.TPR.TSR, nomatch); cpu 108 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E); cpu 111 src/dps8/doAppendCycleOperandStore.h cpu.RSDWH_R1 = cpu.SDW->R1; cpu 128 src/dps8/doAppendCycleOperandStore.h if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) { cpu 130 src/dps8/doAppendCycleOperandStore.h cpu.acvFaults |= ACV0; cpu 131 src/dps8/doAppendCycleOperandStore.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 149 src/dps8/doAppendCycleOperandStore.h if (cpu.TPR.TSR == cpu.PPR.PSR) cpu 150 src/dps8/doAppendCycleOperandStore.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 153 src/dps8/doAppendCycleOperandStore.h if (cpu.TPR.TRR > cpu.SDW->R1) { cpu 154 src/dps8/doAppendCycleOperandStore.h DBGAPP ("ACV5 TRR %o R1 %o\n", cpu.TPR.TRR, cpu.SDW->R1); cpu 156 src/dps8/doAppendCycleOperandStore.h cpu.acvFaults |= ACV5; cpu 157 src/dps8/doAppendCycleOperandStore.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 161 src/dps8/doAppendCycleOperandStore.h if (! cpu.SDW->W) { cpu 163 src/dps8/doAppendCycleOperandStore.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 167 src/dps8/doAppendCycleOperandStore.h cpu.acvFaults |= ACV6; cpu 168 src/dps8/doAppendCycleOperandStore.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 185 src/dps8/doAppendCycleOperandStore.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { cpu 188 src/dps8/doAppendCycleOperandStore.h cpu.acvFaults |= ACV15; cpu 189 src/dps8/doAppendCycleOperandStore.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 191 src/dps8/doAppendCycleOperandStore.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); cpu 194 src/dps8/doAppendCycleOperandStore.h if (cpu.acvFaults) { cpu 196 src/dps8/doAppendCycleOperandStore.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 198 src/dps8/doAppendCycleOperandStore.h doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault"); cpu 202 src/dps8/doAppendCycleOperandStore.h if (cpu.SDW->U) cpu 208 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(G) CA %06o\n", cpu.TPR.CA); cpu 209 src/dps8/doAppendCycleOperandStore.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { cpu 210 src/dps8/doAppendCycleOperandStore.h fetch_ptw (cpu.SDW, cpu.TPR.CA); cpu 211 src/dps8/doAppendCycleOperandStore.h if (! cpu.PTW0.DF) { cpu 213 src/dps8/doAppendCycleOperandStore.h doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0"); cpu 215 src/dps8/doAppendCycleOperandStore.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM cpu 225 src/dps8/doAppendCycleOperandStore.h do_ptw2 (cpu.SDW, cpu.TPR.CA); cpu 238 src/dps8/doAppendCycleOperandStore.h PNL (L68_ (cpu.apu.state |= apu_FANP;)) cpu 248 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); cpu 250 src/dps8/doAppendCycleOperandStore.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; cpu 252 src/dps8/doAppendCycleOperandStore.h PNL (cpu.APUMemAddr = finalAddress;) cpu 254 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 263 src/dps8/doAppendCycleOperandStore.h if (cpu.PTW->M == 0) // is this the right way to do this? cpu 264 src/dps8/doAppendCycleOperandStore.h modify_ptw (cpu.SDW, cpu.TPR.CA); cpu 268 src/dps8/doAppendCycleOperandStore.h PNL (L68_ (cpu.apu.state |= apu_FAP;)) cpu 270 src/dps8/doAppendCycleOperandStore.h word24 y2 = cpu.TPR.CA % 1024; cpu 274 src/dps8/doAppendCycleOperandStore.h finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2; cpu 276 src/dps8/doAppendCycleOperandStore.h PNL (cpu.APUMemAddr = finalAddress;) cpu 279 src/dps8/doAppendCycleOperandStore.h if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 282 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 290 src/dps8/doAppendCycleOperandStore.h cpu.cu.XSF = 1; cpu 293 src/dps8/doAppendCycleOperandStore.h if (cpu.useZone) cpu 300 src/dps8/doAppendCycleOperandStore.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) cpu 301 src/dps8/doAppendCycleOperandStore.h PNL (cpu.APUDataBusAddr = finalAddress;) cpu 303 src/dps8/doAppendCycleOperandStore.h PNL (L68_ (cpu.apu.state |= apu_FA;)) cpu 305 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu 306 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); cpu 22 src/dps8/doAppendCycleRTCDOperandFetch.h DCDstruct * i = & cpu.currentInstruction; cpu 24 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) lastCycle=%s\n", str_pct (cpu.apu.lastCycle)); cpu 25 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) CA %06o\n", cpu.TPR.CA); cpu 27 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\n", cpu.PPR.PRR, cpu.PPR.PSR); cpu 28 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) TPR.TRR=%o TPR.TSR=%05o\n", cpu.TPR.TRR, cpu.TPR.TSR); cpu 35 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.tweaks.enable_wam) { cpu 48 src/dps8/doAppendCycleRTCDOperandFetch.h processor_cycle_type lastCycle = cpu.apu.lastCycle; cpu 49 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.apu.lastCycle = RTCD_OPERAND_FETCH; cpu 51 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) XSF %o\n", cpu.cu.XSF); cpu 53 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (L68_ (cpu.apu.state = 0;)) cpu 55 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.RSDWH_R1 = 0; cpu 57 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.acvFaults = 0; cpu 87 src/dps8/doAppendCycleRTCDOperandFetch.h if (get_addr_mode() == ABSOLUTE_mode && ! (cpu.cu.XSF || cpu.currentInstruction.b29)) { cpu 88 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TSR = 0; cpu 89 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("RTCD_OPERAND_FETCH ABSOLUTE mode set TSR %05o TRR %o\n", cpu.TPR.TSR, cpu.TPR.TRR); cpu 107 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (cpu.APUMemAddr = cpu.TPR.CA;) cpu 112 src/dps8/doAppendCycleRTCDOperandFetch.h if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) { cpu 114 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(A):SDW for segment %05o not in SDWAM\n", cpu.TPR.TSR); cpu 115 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(A):DSBR.U=%o\n", cpu.DSBR.U); cpu 117 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.DSBR.U == 0) { cpu 118 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_dsptw (cpu.TPR.TSR); cpu 120 src/dps8/doAppendCycleRTCDOperandFetch.h if (! cpu.PTW0.DF) cpu 121 src/dps8/doAppendCycleRTCDOperandFetch.h doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, "doAppendCycleRTCDOperandFetch(A): PTW0.F == 0"); cpu 123 src/dps8/doAppendCycleRTCDOperandFetch.h if (! cpu.PTW0.U) cpu 124 src/dps8/doAppendCycleRTCDOperandFetch.h modify_dsptw (cpu.TPR.TSR); cpu 126 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_psdw (cpu.TPR.TSR); cpu 128 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. cpu 130 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.SDW0.DF == 0) { cpu 133 src/dps8/doAppendCycleRTCDOperandFetch.h doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0"); cpu 136 src/dps8/doAppendCycleRTCDOperandFetch.h load_sdwam (cpu.TPR.TSR, nomatch); cpu 138 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(A) R1 %o R2 %o R3 %o E %o\n", cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E); cpu 141 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.RSDWH_R1 = cpu.SDW->R1; cpu 158 src/dps8/doAppendCycleRTCDOperandFetch.h if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) { cpu 160 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.acvFaults |= ACV0; cpu 161 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 181 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.TPR.TRR > cpu.SDW->R2) { cpu 185 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.acvFaults |= ACV3; cpu 186 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 190 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.SDW->R == 0) { cpu 192 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TRR = cpu.PPR.PRR; cpu 195 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.PPR.PSR != cpu.TPR.TSR) { cpu 199 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.acvFaults |= ACV4; cpu 200 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 220 src/dps8/doAppendCycleRTCDOperandFetch.h if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) { cpu 223 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.acvFaults |= ACV15; cpu 224 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 226 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("acvFaults(G) C(TPR.CA)0,13 > SDW.BOUND\n" " CA %06o CA>>4 & 037777 %06o SDW->BOUND %06o", cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); cpu 229 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.acvFaults) { cpu 231 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 233 src/dps8/doAppendCycleRTCDOperandFetch.h doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, "ACV fault"); cpu 237 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.SDW->U) cpu 243 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(G) CA %06o\n", cpu.TPR.CA); cpu 244 src/dps8/doAppendCycleRTCDOperandFetch.h if (nomatch || ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) { cpu 245 src/dps8/doAppendCycleRTCDOperandFetch.h fetch_ptw (cpu.SDW, cpu.TPR.CA); cpu 246 src/dps8/doAppendCycleRTCDOperandFetch.h if (! cpu.PTW0.DF) { cpu 248 src/dps8/doAppendCycleRTCDOperandFetch.h doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, "PTW0.F == 0"); cpu 250 src/dps8/doAppendCycleRTCDOperandFetch.h loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM cpu 260 src/dps8/doAppendCycleRTCDOperandFetch.h do_ptw2 (cpu.SDW, cpu.TPR.CA); cpu 273 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (L68_ (cpu.apu.state |= apu_FANP;)) cpu 283 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H): SDW->ADDR=%08o CA=%06o \n", cpu.SDW->ADDR, cpu.TPR.CA); cpu 285 src/dps8/doAppendCycleRTCDOperandFetch.h if (get_addr_mode () == ABSOLUTE_mode && ! (cpu.cu.XSF || cpu.currentInstruction.b29)) { cpu 286 src/dps8/doAppendCycleRTCDOperandFetch.h finalAddress = cpu.TPR.CA; cpu 288 src/dps8/doAppendCycleRTCDOperandFetch.h finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; cpu 291 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (cpu.APUMemAddr = finalAddress;) cpu 293 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H:FANP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 305 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (L68_ (cpu.apu.state |= apu_FAP;)) cpu 307 src/dps8/doAppendCycleRTCDOperandFetch.h word24 y2 = cpu.TPR.CA % 1024; cpu 311 src/dps8/doAppendCycleRTCDOperandFetch.h finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2; cpu 313 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (cpu.APUMemAddr = finalAddress;) cpu 316 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 319 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(H:FAP): (%05o:%06o) finalAddress=%08o\n", cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 327 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.cu.XSF = 1; cpu 347 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.TSR = GET_ITS_SEGNO (data); cpu 352 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1); cpu 356 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.TPR.CA = GET_ITS_WORDNO (data); cpu 366 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PSR = cpu.TPR.TSR; cpu 368 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.IC = cpu.TPR.CA; cpu 376 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.TPR.TRR == 0) { cpu 378 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.P = cpu.SDW->P; cpu 381 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.P = 0; cpu 386 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) cpu 387 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (cpu.APUDataBusAddr = finalAddress;) cpu 389 src/dps8/doAppendCycleRTCDOperandFetch.h PNL (L68_ (cpu.apu.state |= apu_FA;)) cpu 391 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch (Exit) PRR %o PSR %05o P %o IC %06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu 392 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch (Exit) TRR %o TSR %05o TBR %02o CA %06o\n", cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); cpu 83 src/dps8/dps8.h # define L68_(x) if (cpu.tweaks.l68_mode) { x } cpu 84 src/dps8/dps8.h # define DPS8M_(x) if (! cpu.tweaks.l68_mode) { x } cpu 88 src/dps8/dps8.h # define IF1 if (cpu.tweaks.isolts_mode) cpu 40 src/dps8/dps8_addrmods.c #define DBG_CTR cpu.cycleCnt cpu 50 src/dps8/dps8_addrmods.c cpu.ou.directOperandFlag = false; cpu 56 src/dps8/dps8_addrmods.c return cpu.rX [X (Tdes)]; cpu 67 src/dps8/dps8_addrmods.c return GETHI (cpu.rA); cpu 73 src/dps8/dps8_addrmods.c return GETHI (cpu.rQ); cpu 76 src/dps8/dps8_addrmods.c cpu.ou.directOperand = 0; cpu 77 src/dps8/dps8_addrmods.c SETHI (cpu.ou.directOperand, cpu.rY); cpu 78 src/dps8/dps8_addrmods.c cpu.ou.directOperandFlag = true; cpu 82 src/dps8/dps8_addrmods.c __func__, cpu.rY, cpu.ou.directOperand); cpu 87 src/dps8/dps8_addrmods.c return cpu.PPR.IC; cpu 93 src/dps8/dps8_addrmods.c return GETLO (cpu.rA); cpu 99 src/dps8/dps8_addrmods.c return GETLO (cpu.rQ); cpu 102 src/dps8/dps8_addrmods.c cpu.ou.directOperand = 0; cpu 103 src/dps8/dps8_addrmods.c SETLO (cpu.ou.directOperand, cpu.rY); cpu 104 src/dps8/dps8_addrmods.c cpu.ou.directOperandFlag = true; cpu 108 src/dps8/dps8_addrmods.c __func__, cpu.rY, cpu.ou.directOperand); cpu 117 src/dps8/dps8_addrmods.c DCDstruct * i = & cpu.currentInstruction; cpu 200 src/dps8/dps8_addrmods.c GET_ITP_PRNUM (cpu.itxPair), GET_ITP_WORDNO (cpu.itxPair), cpu 201 src/dps8/dps8_addrmods.c GET_ITP_BITNO (cpu.itxPair), GET_ITP_MOD (cpu.itxPair)); cpu 219 src/dps8/dps8_addrmods.c word3 n = GET_ITP_PRNUM (cpu.itxPair); cpu 224 src/dps8/dps8_addrmods.c cpu.TPR.TSR = cpu.PR[n].SNR; cpu 225 src/dps8/dps8_addrmods.c cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.RSDWH_R1, cpu.TPR.TRR); cpu 226 src/dps8/dps8_addrmods.c cpu.TPR.TBR = GET_ITP_BITNO (cpu.itxPair); cpu 227 src/dps8/dps8_addrmods.c cpu.TPR.CA = cpu.PAR[n].WORDNO + GET_ITP_WORDNO (cpu.itxPair); cpu 228 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; cpu 229 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; cpu 231 src/dps8/dps8_addrmods.c cpu.rTAG = GET_ITP_MOD (cpu.itxPair); cpu 233 src/dps8/dps8_addrmods.c cpu.cu.itp = 1; cpu 234 src/dps8/dps8_addrmods.c cpu.cu.TSN_PRNO[0] = n; cpu 235 src/dps8/dps8_addrmods.c cpu.cu.TSN_VALID[0] = 1; cpu 244 src/dps8/dps8_addrmods.c GET_ITS_SEGNO (cpu.itxPair), GET_ITS_RN (cpu.itxPair), cpu 245 src/dps8/dps8_addrmods.c GET_ITS_WORDNO (cpu.itxPair), GET_ITS_BITNO (cpu.itxPair), cpu 246 src/dps8/dps8_addrmods.c GET_ITS_MOD (cpu.itxPair)); cpu 260 src/dps8/dps8_addrmods.c cpu.TPR.TSR = GET_ITS_SEGNO (cpu.itxPair); cpu 264 src/dps8/dps8_addrmods.c GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR, cpu 265 src/dps8/dps8_addrmods.c max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR)); cpu 267 src/dps8/dps8_addrmods.c cpu.TPR.TRR = max3 (GET_ITS_RN (cpu.itxPair), cpu.RSDWH_R1, cpu.TPR.TRR); cpu 268 src/dps8/dps8_addrmods.c cpu.TPR.TBR = GET_ITS_BITNO (cpu.itxPair); cpu 269 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ITS_WORDNO (cpu.itxPair); cpu 270 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; cpu 272 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; cpu 274 src/dps8/dps8_addrmods.c cpu.rTAG = GET_ITS_MOD (cpu.itxPair); cpu 276 src/dps8/dps8_addrmods.c cpu.cu.its = 1; cpu 284 src/dps8/dps8_addrmods.c word6 ind_tag = GET_TAG (cpu.itxPair [0]); cpu 288 src/dps8/dps8_addrmods.c cpu.itxPair[0], cpu.itxPair[1]); cpu 317 src/dps8/dps8_addrmods.c cpu.cu.XSF = 1; cpu 325 src/dps8/dps8_addrmods.c wb = & cpu.cu.IRODD; cpu 327 src/dps8/dps8_addrmods.c wb = & cpu.cu.IWB; cpu 342 src/dps8/dps8_addrmods.c decode_instruction (IWB_IRODD, & cpu.currentInstruction); cpu 362 src/dps8/dps8_addrmods.c if (cpu.currentInstruction.b29 == 0) cpu 364 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ADDR (IWB_IRODD); cpu 373 src/dps8/dps8_addrmods.c cpu.TPR.CA = (cpu.PAR[n].WORDNO + SIGNEXT15_18 (offset)) cpu 379 src/dps8/dps8_addrmods.c __func__, op_desc_str (buf), cpu.TPR.CA); cpu 382 src/dps8/dps8_addrmods.c __func__, cpu.cu.CT_HOLD); cpu 384 src/dps8/dps8_addrmods.c DCDstruct * i = & cpu.currentInstruction; cpu 391 src/dps8/dps8_addrmods.c cpu.ou.directOperandFlag = false; cpu 394 src/dps8/dps8_addrmods.c cpu.rTAG = 0; cpu 396 src/dps8/dps8_addrmods.c cpu.rTAG = GET_TAG (IWB_IRODD); cpu 408 src/dps8/dps8_addrmods.c Td = GET_TD (cpu.rTAG); cpu 409 src/dps8/dps8_addrmods.c Tm = GET_TM (cpu.rTAG); cpu 414 src/dps8/dps8_addrmods.c if (cpu.cu.CT_HOLD) cpu 418 src/dps8/dps8_addrmods.c __func__, cpu.cu.CT_HOLD); cpu 420 src/dps8/dps8_addrmods.c if (cpu.tweaks.isolts_mode && cpu 421 src/dps8/dps8_addrmods.c GET_TM(cpu.cu.CT_HOLD) == TM_IT && GET_TD (cpu.cu.CT_HOLD) == IT_DIC && cpu 422 src/dps8/dps8_addrmods.c cpu.cu.pot == 1 && GET_ADDR (IWB_IRODD) == cpu.TPR.CA) cpu 424 src/dps8/dps8_addrmods.c cpu.TPR.CA--; cpu 429 src/dps8/dps8_addrmods.c cpu.cu.pot = 1; cpu 435 src/dps8/dps8_addrmods.c cpu.cu.its = 0; cpu 436 src/dps8/dps8_addrmods.c cpu.cu.itp = 0; cpu 437 src/dps8/dps8_addrmods.c cpu.cu.pot = 0; cpu 441 src/dps8/dps8_addrmods.c __func__, cpu.rTAG, get_mod_string (buf, cpu.rTAG), Tm, Td, cpu.cu.CT_HOLD); cpu 458 src/dps8/dps8_addrmods.c __func__, GET_TM (cpu.rTAG)); cpu 475 src/dps8/dps8_addrmods.c if (cpu.ou.directOperandFlag) cpu 479 src/dps8/dps8_addrmods.c cpu.ou.directOperand); cpu 485 src/dps8/dps8_addrmods.c if (cpu.cu.rpt || cpu.cu.rd | cpu.cu.rl) cpu 487 src/dps8/dps8_addrmods.c if (cpu.currentInstruction.b29) cpu 494 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO; cpu 495 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; cpu 499 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr; cpu 504 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; cpu 505 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits cpu 508 src/dps8/dps8_addrmods.c cpu.TPR.CA); cpu 530 src/dps8/dps8_addrmods.c "RI_MOD: Cr=%06o CA(Before)=%06o\n", Cr, cpu.TPR.CA); cpu 532 src/dps8/dps8_addrmods.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) cpu 534 src/dps8/dps8_addrmods.c if (cpu.currentInstruction.b29) cpu 541 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr + cpu.PR [PRn].WORDNO; cpu 545 src/dps8/dps8_addrmods.c cpu.TPR.CA = Cr; cpu 547 src/dps8/dps8_addrmods.c cpu.TPR.CA &= AMASK; cpu 551 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; cpu 552 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits cpu 555 src/dps8/dps8_addrmods.c "RI_MOD: CA(After)=%06o\n", cpu.TPR.CA); cpu 561 src/dps8/dps8_addrmods.c if (GET_TM(cpu.cu.CT_HOLD) == TM_IR) cpu 569 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; cpu 572 src/dps8/dps8_addrmods.c if ((saveCA & 1) == 0 && (ISITP (cpu.itxPair[0]) || ISITS (cpu.itxPair[0]))) cpu 575 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, cpu.rTAG); cpu 579 src/dps8/dps8_addrmods.c cpu.rTAG = GET_TAG (cpu.itxPair[0]); cpu 580 src/dps8/dps8_addrmods.c if (ISITP (cpu.itxPair[0]) || ISITS (cpu.itxPair[0])) cpu 587 src/dps8/dps8_addrmods.c if (!(cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) cpu 589 src/dps8/dps8_addrmods.c updateIWB (GET_ADDR (cpu.itxPair[0]), cpu.rTAG); cpu 592 src/dps8/dps8_addrmods.c if (GET_TM (cpu.rTAG) == TM_IT) cpu 594 src/dps8/dps8_addrmods.c if (GET_TD (cpu.rTAG) == IT_F2) cpu 598 src/dps8/dps8_addrmods.c if (GET_TD (cpu.rTAG) == IT_F3) cpu 603 src/dps8/dps8_addrmods.c cpu.TPR.CA = GETHI (cpu.itxPair[0]); cpu 604 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; cpu 616 src/dps8/dps8_addrmods.c cpu.itxPair[0], cpu.TPR.CA, cpu.rTAG); cpu 620 src/dps8/dps8_addrmods.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) cpu 632 src/dps8/dps8_addrmods.c "IR_MOD: CT_HOLD=%o %o\n", cpu.cu.CT_HOLD, Td); cpu 643 src/dps8/dps8_addrmods.c cpu.TPR.CA); cpu 645 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; cpu 649 src/dps8/dps8_addrmods.c if (GET_TM(cpu.rTAG) == TM_IR) cpu 650 src/dps8/dps8_addrmods.c cpu.cu.CT_HOLD = cpu.rTAG; cpu 652 src/dps8/dps8_addrmods.c if ((saveCA & 1) == 0 && (ISITP (cpu.itxPair[0]) || ISITS (cpu.itxPair[0]))) cpu 658 src/dps8/dps8_addrmods.c if (ISITP (cpu.itxPair[0]) || ISITS (cpu.itxPair[0])) cpu 665 src/dps8/dps8_addrmods.c cpu.TPR.CA = GETHI (cpu.itxPair[0]); cpu 666 src/dps8/dps8_addrmods.c cpu.rY = cpu.TPR.CA; cpu 667 src/dps8/dps8_addrmods.c cpu.rTAG = GET_TAG (cpu.itxPair[0]); cpu 671 src/dps8/dps8_addrmods.c "IR_MOD: CT_HOLD=%o\n", cpu.cu.CT_HOLD); cpu 672 src/dps8/dps8_addrmods.c Td = GET_TD (cpu.rTAG); cpu 673 src/dps8/dps8_addrmods.c Tm = GET_TM (cpu.rTAG); cpu 678 src/dps8/dps8_addrmods.c cpu.itxPair[0], cpu.TPR.CA, Tm, Td, cpu 679 src/dps8/dps8_addrmods.c get_mod_string (buf, GET_TAG (cpu.itxPair[0]))); cpu 687 src/dps8/dps8_addrmods.c Td, cpu.cu.CT_HOLD); cpu 691 src/dps8/dps8_addrmods.c updateIWB(cpu.TPR.CA, cpu.rTAG); cpu 696 src/dps8/dps8_addrmods.c cpu.TPR.CA = saveCA; cpu 701 src/dps8/dps8_addrmods.c cpu.TPR.CA = saveCA; cpu 726 src/dps8/dps8_addrmods.c word6 Td_hold = GET_TD (cpu.cu.CT_HOLD); cpu 727 src/dps8/dps8_addrmods.c cpu.rTAG = (TM_R | Td_hold); cpu 728 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, cpu.rTAG); cpu 742 src/dps8/dps8_addrmods.c Td, Cr, cpu.TPR.CA); cpu 744 src/dps8/dps8_addrmods.c cpu.TPR.CA += Cr; cpu 745 src/dps8/dps8_addrmods.c cpu.TPR.CA &= MASK18; // keep to 18-bits cpu 748 src/dps8/dps8_addrmods.c "IR_MOD(TM_RI): TPR.CA=%06o\n", cpu.TPR.CA); cpu 752 src/dps8/dps8_addrmods.c cpu.TPR.CA); cpu 755 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, (TM_RI|TD_N)); cpu 761 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, cpu.rTAG); // XXX guessing here... cpu 767 src/dps8/dps8_addrmods.c __func__, GET_TM (cpu.rTAG)); cpu 840 src/dps8/dps8_addrmods.c cpu.TPR.CA); cpu 847 src/dps8/dps8_addrmods.c word18 indaddr = cpu.TPR.CA; cpu 850 src/dps8/dps8_addrmods.c word24 phys_address = cpu.iefpFinalAddress; cpu 881 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; cpu 882 src/dps8/dps8_addrmods.c cpu.ou.character_address = Yi; cpu 883 src/dps8/dps8_addrmods.c cpu.ou.characterOperandSize = sz; cpu 884 src/dps8/dps8_addrmods.c cpu.ou.characterOperandOffset = os; cpu 929 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; cpu 930 src/dps8/dps8_addrmods.c cpu.ou.character_address = Yi; cpu 931 src/dps8/dps8_addrmods.c cpu.ou.characterOperandSize = sz; cpu 932 src/dps8/dps8_addrmods.c cpu.ou.characterOperandOffset = os; cpu 948 src/dps8/dps8_addrmods.c cpu.cu.pot = 1; cpu 952 src/dps8/dps8_addrmods.c Read (cpu.TPR.CA, & cpu.ou.character_data, (i->info->flags & RMW) == \ cpu 955 src/dps8/dps8_addrmods.c ReadOperandRead (cpu.TPR.CA, & cpu.ou.character_data); cpu 958 src/dps8/dps8_addrmods.c cpu.char_word_address = cpu.iefpFinalAddress; cpu 963 src/dps8/dps8_addrmods.c cpu.ou.character_data); cpu 965 src/dps8/dps8_addrmods.c cpu.cu.pot = 0; cpu 1027 src/dps8/dps8_addrmods.c indword, cpu.TPR.CA); cpu 1032 src/dps8/dps8_addrmods.c cpu.TPR.CA = cpu.ou.character_address; cpu 1040 src/dps8/dps8_addrmods.c cpu.TPR.CA); cpu 1047 src/dps8/dps8_addrmods.c cpu.itxPair[0]); cpu 1049 src/dps8/dps8_addrmods.c cpu.TPR.CA = GET_ADDR (cpu.itxPair[0]); cpu 1050 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, (TM_R|TD_N)); cpu 1068 src/dps8/dps8_addrmods.c cpu.TPR.CA); cpu 1074 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; cpu 1076 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpu.TPR.CA, & indword); cpu 1078 src/dps8/dps8_addrmods.c cpu.AM_tally = GET_TALLY (indword); // 12-bits cpu 1088 src/dps8/dps8_addrmods.c Yi, cpu.AM_tally, delta); cpu 1090 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; cpu 1091 src/dps8/dps8_addrmods.c word18 computedAddress = cpu.TPR.CA; cpu 1096 src/dps8/dps8_addrmods.c cpu.AM_tally -= 1; cpu 1097 src/dps8/dps8_addrmods.c cpu.AM_tally &= 07777; // keep to 12-bits cpu 1101 src/dps8/dps8_addrmods.c SC_I_TALLY (cpu.AM_tally == 0); cpu 1103 src/dps8/dps8_addrmods.c (((word36) cpu.AM_tally & 07777) << 6) | cpu 1106 src/dps8/dps8_addrmods.c core_write_unlock(cpu.iefpFinalAddress, indword, __func__); cpu 1120 src/dps8/dps8_addrmods.c cpu.TPR.CA = computedAddress; cpu 1121 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, (TM_R|TD_N)); cpu 1141 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; cpu 1143 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpu.TPR.CA, & indword); cpu 1147 src/dps8/dps8_addrmods.c cpu.TPR.CA); cpu 1148 src/dps8/dps8_addrmods.c cpu.AM_tally = GET_TALLY (indword); // 12-bits cpu 1158 src/dps8/dps8_addrmods.c Yi, cpu.AM_tally, delta); cpu 1162 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; cpu 1164 src/dps8/dps8_addrmods.c cpu.AM_tally += 1; cpu 1165 src/dps8/dps8_addrmods.c cpu.AM_tally &= 07777; // keep to 12-bits cpu 1166 src/dps8/dps8_addrmods.c if (cpu.AM_tally == 0) cpu 1171 src/dps8/dps8_addrmods.c (((word36) cpu.AM_tally & 07777) << 6) | cpu 1174 src/dps8/dps8_addrmods.c core_write_unlock(cpu.iefpFinalAddress, indword, __func__); cpu 1188 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; cpu 1189 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, (TM_R|TD_N)); cpu 1206 src/dps8/dps8_addrmods.c cpu.TPR.CA); cpu 1212 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; cpu 1214 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpu.TPR.CA, & indword); cpu 1217 src/dps8/dps8_addrmods.c cpu.AM_tally = GET_TALLY (indword); // 12-bits cpu 1225 src/dps8/dps8_addrmods.c Yi, cpu.AM_tally); cpu 1229 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; cpu 1231 src/dps8/dps8_addrmods.c cpu.AM_tally += 1; cpu 1232 src/dps8/dps8_addrmods.c cpu.AM_tally &= 07777; // keep to 12-bits cpu 1233 src/dps8/dps8_addrmods.c SC_I_TALLY (cpu.AM_tally == 0); cpu 1237 src/dps8/dps8_addrmods.c indword = (word36) (((word36) cpu.TPR.CA << 18) | cpu 1238 src/dps8/dps8_addrmods.c ((word36) cpu.AM_tally << 6) | cpu 1247 src/dps8/dps8_addrmods.c core_write_unlock(cpu.iefpFinalAddress, indword, __func__); cpu 1255 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; cpu 1256 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, (TM_R|TD_N)); cpu 1271 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; cpu 1275 src/dps8/dps8_addrmods.c cpu.TPR.CA); cpu 1282 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpu.TPR.CA, & indword); cpu 1285 src/dps8/dps8_addrmods.c cpu.AM_tally = GET_TALLY (indword); // 12-bits cpu 1291 src/dps8/dps8_addrmods.c indword, Yi, cpu.AM_tally); cpu 1293 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; cpu 1294 src/dps8/dps8_addrmods.c word18 computedAddress = cpu.TPR.CA; cpu 1299 src/dps8/dps8_addrmods.c cpu.AM_tally -= 1; cpu 1300 src/dps8/dps8_addrmods.c cpu.AM_tally &= 07777; // keep to 12-bits cpu 1305 src/dps8/dps8_addrmods.c SC_I_TALLY (cpu.AM_tally == 0); cpu 1309 src/dps8/dps8_addrmods.c ((word36) cpu.AM_tally << 6) | cpu 1318 src/dps8/dps8_addrmods.c core_write_unlock(cpu.iefpFinalAddress, indword, __func__); cpu 1327 src/dps8/dps8_addrmods.c cpu.TPR.CA = computedAddress; cpu 1328 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, (TM_R|TD_N)); cpu 1357 src/dps8/dps8_addrmods.c cpu.TPR.CA); cpu 1363 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; cpu 1365 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpu.TPR.CA, & indword); cpu 1367 src/dps8/dps8_addrmods.c cpu.cu.pot = 0; cpu 1370 src/dps8/dps8_addrmods.c cpu.AM_tally = GET_TALLY (indword); // 12-bits cpu 1376 src/dps8/dps8_addrmods.c indword, Yi, cpu.AM_tally, idwtag); cpu 1383 src/dps8/dps8_addrmods.c cpu.AM_tally += 1; cpu 1384 src/dps8/dps8_addrmods.c cpu.AM_tally &= 07777; // keep to 12-bits cpu 1393 src/dps8/dps8_addrmods.c ((word36) cpu.AM_tally << 6) | idwtag); cpu 1400 src/dps8/dps8_addrmods.c core_write_unlock(cpu.iefpFinalAddress, indword, __func__); cpu 1416 src/dps8/dps8_addrmods.c cpu.TPR.CA = Yi; cpu 1420 src/dps8/dps8_addrmods.c cpu.rTAG, idwtag); cpu 1421 src/dps8/dps8_addrmods.c cpu.cu.CT_HOLD = cpu.rTAG; cpu 1422 src/dps8/dps8_addrmods.c cpu.rTAG = idwtag; cpu 1424 src/dps8/dps8_addrmods.c Tm = GET_TM (cpu.rTAG); cpu 1427 src/dps8/dps8_addrmods.c if (GET_TD (cpu.rTAG) != 0) cpu 1436 src/dps8/dps8_addrmods.c SC_I_TALLY (cpu.AM_tally == 0); cpu 1437 src/dps8/dps8_addrmods.c if (cpu.tweaks.isolts_mode) cpu 1438 src/dps8/dps8_addrmods.c updateIWB (YiSafe2, cpu.rTAG); cpu 1440 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, cpu.rTAG); cpu 1469 src/dps8/dps8_addrmods.c cpu.TPR.CA); cpu 1475 src/dps8/dps8_addrmods.c word18 saveCA = cpu.TPR.CA; cpu 1477 src/dps8/dps8_addrmods.c ReadAPUDataRMW (cpu.TPR.CA, & indword); cpu 1479 src/dps8/dps8_addrmods.c cpu.cu.pot = 0; cpu 1482 src/dps8/dps8_addrmods.c cpu.AM_tally = GET_TALLY (indword); // 12-bits cpu 1488 src/dps8/dps8_addrmods.c indword, Yi, cpu.AM_tally, idwtag); cpu 1495 src/dps8/dps8_addrmods.c cpu.AM_tally -= 1; cpu 1496 src/dps8/dps8_addrmods.c cpu.AM_tally &= 07777; // keep to 12-bits cpu 1503 src/dps8/dps8_addrmods.c ((word36) cpu.AM_tally << 6) | cpu 1512 src/dps8/dps8_addrmods.c core_write_unlock(cpu.iefpFinalAddress, indword, __func__); cpu 1530 src/dps8/dps8_addrmods.c cpu.TPR.CA = YiSafe; cpu 1534 src/dps8/dps8_addrmods.c cpu.rTAG, idwtag); cpu 1535 src/dps8/dps8_addrmods.c cpu.cu.CT_HOLD = cpu.rTAG; cpu 1536 src/dps8/dps8_addrmods.c cpu.rTAG = idwtag; cpu 1538 src/dps8/dps8_addrmods.c Tm = GET_TM (cpu.rTAG); cpu 1541 src/dps8/dps8_addrmods.c if (GET_TD (cpu.rTAG) != 0) cpu 1550 src/dps8/dps8_addrmods.c SC_I_TALLY (cpu.AM_tally == 0); cpu 1551 src/dps8/dps8_addrmods.c updateIWB (cpu.TPR.CA, cpu.rTAG); cpu 48 src/dps8/dps8_append.c #define DBG_CTR cpu.cycleCnt cpu 55 src/dps8/dps8_append.c # define DBG_CTR cpu.cycleCnt cpu 65 src/dps8/dps8_append.c cpu 66 src/dps8/dps8_append.c cpu 68 src/dps8/dps8_append.c cpu 69 src/dps8/dps8_append.c cpu 70 src/dps8/dps8_append.c cpu 71 src/dps8/dps8_append.c cpu 72 src/dps8/dps8_append.c cpu 73 src/dps8/dps8_append.c cpu 74 src/dps8/dps8_append.c cpu 75 src/dps8/dps8_append.c cpu 76 src/dps8/dps8_append.c cpu 80 src/dps8/dps8_append.c cpu 86 src/dps8/dps8_append.c cpu 89 src/dps8/dps8_append.c cpu 92 src/dps8/dps8_append.c cpu 98 src/dps8/dps8_append.c cpu 101 src/dps8/dps8_append.c cpu 104 src/dps8/dps8_append.c cpu 107 src/dps8/dps8_append.c cpu 110 src/dps8/dps8_append.c cpu 150 src/dps8/dps8_append.c ptw_s * p = cpu.PTWAM + i; cpu 174 src/dps8/dps8_append.c if (cpu.tweaks.enable_wam) cpu 176 src/dps8/dps8_append.c if (cpu.cu.SD_ON) cpu 183 src/dps8/dps8_append.c cpu.SDWAM[i].FE = 0; cpu 184 src/dps8/dps8_append.c L68_ (cpu.SDWAM[i].USE = (word4) i;) cpu 185 src/dps8/dps8_append.c DPS8M_ (cpu.SDWAM[i].USE = 0;) cpu 189 src/dps8/dps8_append.c if (cpu.cu.PT_ON) cpu 196 src/dps8/dps8_append.c cpu.PTWAM[i].FE = 0; cpu 197 src/dps8/dps8_append.c L68_ (cpu.PTWAM[i].USE = (word4) i;) cpu 198 src/dps8/dps8_append.c DPS8M_ (cpu.PTWAM[i].USE = 0;) cpu 207 src/dps8/dps8_append.c cpu.SDW0.FE = 0; cpu 208 src/dps8/dps8_append.c cpu.SDW0.USE = 0; cpu 209 src/dps8/dps8_append.c cpu.PTW0.FE = 0; cpu 210 src/dps8/dps8_append.c cpu.PTW0.USE = 0; cpu 217 src/dps8/dps8_append.c cpu.DSBR.ADDR = (Ypair[0] >> (35 - 23)) & PAMASK; cpu 220 src/dps8/dps8_append.c cpu.DSBR.BND = (Ypair[1] >> (71 - 50)) & 037777; cpu 223 src/dps8/dps8_append.c cpu.DSBR.U = (Ypair[1] >> (71 - 55)) & 01; cpu 226 src/dps8/dps8_append.c cpu.DSBR.STACK = (Ypair[1] >> (71 - 71)) & 07777; cpu 229 src/dps8/dps8_append.c cpu.DSBR.ADDR, cpu.DSBR.BND, cpu.DSBR.U, cpu.DSBR.STACK); cpu 241 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FDPT;)) cpu 243 src/dps8/dps8_append.c if (2 * segno >= 16 * (cpu.DSBR.BND + 1)) cpu 247 src/dps8/dps8_append.c PNL (cpu.acvFaults |= ACV15;) cpu 248 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 257 src/dps8/dps8_append.c PNL (cpu.lastPTWOffset = segno;) cpu 258 src/dps8/dps8_append.c PNL (cpu.lastPTWIsDS = true;) cpu 261 src/dps8/dps8_append.c core_read ((cpu.DSBR.ADDR + x1) & PAMASK, & PTWx1, __func__); cpu 263 src/dps8/dps8_append.c cpu.PTW0.ADDR = GETHI (PTWx1); cpu 264 src/dps8/dps8_append.c cpu.PTW0.U = TSTBIT (PTWx1, 9); cpu 265 src/dps8/dps8_append.c cpu.PTW0.M = TSTBIT (PTWx1, 6); cpu 266 src/dps8/dps8_append.c cpu.PTW0.DF = TSTBIT (PTWx1, 2); cpu 267 src/dps8/dps8_append.c cpu.PTW0.FC = PTWx1 & 3; cpu 269 src/dps8/dps8_append.c L68_ (if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 274 src/dps8/dps8_append.c __func__, x1, cpu.DSBR.ADDR, PTWx1, cpu.PTW0.ADDR, cpu.PTW0.U, cpu 275 src/dps8/dps8_append.c cpu.PTW0.M, cpu.PTW0.DF, cpu.PTW0.FC); cpu 287 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_MDPT;)) cpu 301 src/dps8/dps8_append.c core_read_lock ((cpu.DSBR.ADDR + x1) & PAMASK, & PTWx1, __func__); cpu 303 src/dps8/dps8_append.c core_write_unlock ((cpu.DSBR.ADDR + x1) & PAMASK, PTWx1, __func__); cpu 305 src/dps8/dps8_append.c core_read ((cpu.DSBR.ADDR + x1) & PAMASK, & PTWx1, __func__); cpu 307 src/dps8/dps8_append.c core_write ((cpu.DSBR.ADDR + x1) & PAMASK, PTWx1, __func__); cpu 315 src/dps8/dps8_append.c cpu.PTW0.U = 1; cpu 316 src/dps8/dps8_append.c L68_ (if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 341 src/dps8/dps8_append.c if ((! cpu.tweaks.enable_wam || ! cpu.cu.SD_ON)) { cpu 346 src/dps8/dps8_append.c if (cpu.tweaks.l68_mode) { // L68 cpu 350 src/dps8/dps8_append.c if (cpu.SDWAM[_n].FE && segno == cpu.SDWAM[_n].POINTER) { cpu 353 src/dps8/dps8_append.c cpu.cu.SDWAMM = 1; cpu 354 src/dps8/dps8_append.c cpu.SDWAMR = (word4) _n; cpu 355 src/dps8/dps8_append.c cpu.SDW = & cpu.SDWAM[_n]; cpu 364 src/dps8/dps8_append.c if (cpu.SDWAM[_h].USE > cpu.SDW->USE) cpu 365 src/dps8/dps8_append.c cpu.SDWAM[_h].USE -= 1; cpu 367 src/dps8/dps8_append.c cpu.SDW->USE = N_L68_WAM_ENTRIES - 1; cpu 372 src/dps8/dps8_append.c DBGAPP ("%s(2):SDWAM[%d]=%s\n", __func__, _n, str_sdw (buf, cpu.SDW)); cpu 374 src/dps8/dps8_append.c return cpu.SDW; cpu 379 src/dps8/dps8_append.c if (! cpu.tweaks.l68_mode) { // DPS8M cpu 384 src/dps8/dps8_append.c p = & cpu.SDWAM[toffset + setno]; cpu 388 src/dps8/dps8_append.c cpu.cu.SDWAMM = 1; cpu 389 src/dps8/dps8_append.c cpu.SDWAMR = (word6) (toffset + setno); cpu 390 src/dps8/dps8_append.c cpu.SDW = p; // export pointer for appending cpu 394 src/dps8/dps8_append.c p = & cpu.SDWAM[toffset + setno]; cpu 402 src/dps8/dps8_append.c DBGAPP ("%s(2):SDWAM[%d]=%s\n", __func__, toffset + setno, str_sdw (buf, cpu.SDW)); cpu 404 src/dps8/dps8_append.c return cpu.SDW; cpu 411 src/dps8/dps8_append.c cpu.cu.SDWAMM = 0; cpu 425 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FSDP;)) cpu 432 src/dps8/dps8_append.c core_read2 (((((word24) cpu.PTW0.ADDR & 0777760) << 6) + y1) & PAMASK, cpu 436 src/dps8/dps8_append.c cpu.SDW0.ADDR = (SDWeven >> 12) & 077777777; cpu 437 src/dps8/dps8_append.c cpu.SDW0.R1 = (SDWeven >> 9) & 7; cpu 438 src/dps8/dps8_append.c cpu.SDW0.R2 = (SDWeven >> 6) & 7; cpu 439 src/dps8/dps8_append.c cpu.SDW0.R3 = (SDWeven >> 3) & 7; cpu 440 src/dps8/dps8_append.c cpu.SDW0.DF = TSTBIT (SDWeven, 2); cpu 441 src/dps8/dps8_append.c cpu.SDW0.FC = SDWeven & 3; cpu 444 src/dps8/dps8_append.c cpu.SDW0.BOUND = (SDWodd >> 21) & 037777; cpu 445 src/dps8/dps8_append.c cpu.SDW0.R = TSTBIT (SDWodd, 20); cpu 446 src/dps8/dps8_append.c cpu.SDW0.E = TSTBIT (SDWodd, 19); cpu 447 src/dps8/dps8_append.c cpu.SDW0.W = TSTBIT (SDWodd, 18); cpu 448 src/dps8/dps8_append.c cpu.SDW0.P = TSTBIT (SDWodd, 17); cpu 449 src/dps8/dps8_append.c cpu.SDW0.U = TSTBIT (SDWodd, 16); cpu 450 src/dps8/dps8_append.c cpu.SDW0.G = TSTBIT (SDWodd, 15); cpu 451 src/dps8/dps8_append.c cpu.SDW0.C = TSTBIT (SDWodd, 14); cpu 452 src/dps8/dps8_append.c cpu.SDW0.EB = SDWodd & 037777; cpu 455 src/dps8/dps8_append.c if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 461 src/dps8/dps8_append.c __func__, y1, cpu.PTW0.ADDR, SDWeven, SDWodd, cpu.SDW0.ADDR, cpu 462 src/dps8/dps8_append.c cpu.SDW0.R1, cpu.SDW0.R2, cpu.SDW0.R3, cpu.SDW0.BOUND, cpu 463 src/dps8/dps8_append.c cpu.SDW0.R, cpu.SDW0.E, cpu.SDW0.W, cpu.SDW0.P, cpu.SDW0.U, cpu 464 src/dps8/dps8_append.c cpu.SDW0.G, cpu.SDW0.C, cpu.SDW0.DF, cpu.SDW0.FC, cpu.SDW0.FE, cpu 465 src/dps8/dps8_append.c cpu.SDW0.USE); cpu 476 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FSDN;)) cpu 480 src/dps8/dps8_append.c if (2 * segno >= 16 * (cpu.DSBR.BND + 1)) cpu 484 src/dps8/dps8_append.c __func__, segno, cpu.DSBR.BND); cpu 486 src/dps8/dps8_append.c PNL (cpu.acvFaults |= ACV15;) cpu 487 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 492 src/dps8/dps8_append.c __func__, cpu.DSBR.ADDR + 2u * segno); cpu 495 src/dps8/dps8_append.c core_read2 ((cpu.DSBR.ADDR + 2u * segno) & PAMASK, cpu 499 src/dps8/dps8_append.c cpu.SDW0.ADDR = (SDWeven >> 12) & 077777777; cpu 500 src/dps8/dps8_append.c cpu.SDW0.R1 = (SDWeven >> 9) & 7; cpu 501 src/dps8/dps8_append.c cpu.SDW0.R2 = (SDWeven >> 6) & 7; cpu 502 src/dps8/dps8_append.c cpu.SDW0.R3 = (SDWeven >> 3) & 7; cpu 503 src/dps8/dps8_append.c cpu.SDW0.DF = TSTBIT (SDWeven, 2); cpu 504 src/dps8/dps8_append.c cpu.SDW0.FC = SDWeven & 3; cpu 507 src/dps8/dps8_append.c cpu.SDW0.BOUND = (SDWodd >> 21) & 037777; cpu 508 src/dps8/dps8_append.c cpu.SDW0.R = TSTBIT (SDWodd, 20); cpu 509 src/dps8/dps8_append.c cpu.SDW0.E = TSTBIT (SDWodd, 19); cpu 510 src/dps8/dps8_append.c cpu.SDW0.W = TSTBIT (SDWodd, 18); cpu 511 src/dps8/dps8_append.c cpu.SDW0.P = TSTBIT (SDWodd, 17); cpu 512 src/dps8/dps8_append.c cpu.SDW0.U = TSTBIT (SDWodd, 16); cpu 513 src/dps8/dps8_append.c cpu.SDW0.G = TSTBIT (SDWodd, 15); cpu 514 src/dps8/dps8_append.c cpu.SDW0.C = TSTBIT (SDWodd, 14); cpu 515 src/dps8/dps8_append.c cpu.SDW0.EB = SDWodd & 037777; cpu 518 src/dps8/dps8_append.c if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 524 src/dps8/dps8_append.c DBGAPP ("%s (2):SDW0=%s\n", __func__, str_SDW0 (buf, & cpu.SDW0)); cpu 555 src/dps8/dps8_append.c sdw_s *p = & cpu.SDWAM[_n]; cpu 591 src/dps8/dps8_append.c cpu.SDW0.POINTER = segno; cpu 592 src/dps8/dps8_append.c cpu.SDW0.USE = 0; cpu 594 src/dps8/dps8_append.c cpu.SDW0.FE = true; // in use by SDWAM cpu 596 src/dps8/dps8_append.c cpu.SDW = & cpu.SDW0; cpu 598 src/dps8/dps8_append.c if (nomatch || (! cpu.tweaks.enable_wam) || (! cpu.cu.SD_ON)) cpu 604 src/dps8/dps8_append.c if (cpu.tweaks.l68_mode) { // L68 cpu 613 src/dps8/dps8_append.c sdw_s * p = & cpu.SDWAM[_n]; cpu 617 src/dps8/dps8_append.c * p = cpu.SDW0; cpu 623 src/dps8/dps8_append.c sdw_s * q = & cpu.SDWAM[_h]; cpu 628 src/dps8/dps8_append.c cpu.SDW = p; cpu 646 src/dps8/dps8_append.c if (! cpu.tweaks.l68_mode) { // DPS8M cpu 651 src/dps8/dps8_append.c p = & cpu.SDWAM[toffset + setno]; cpu 657 src/dps8/dps8_append.c p = & cpu.SDWAM[toffset + setno]; cpu 662 src/dps8/dps8_append.c * p = cpu.SDW0; // load the SDW cpu 665 src/dps8/dps8_append.c cpu.SDW = p; // export pointer for appending cpu 668 src/dps8/dps8_append.c p = & cpu.SDWAM[toffset1 + setno]; cpu 676 src/dps8/dps8_append.c DBGAPP ("%s(2):SDWAM[%d]=%s\n", __func__, toffset + setno, str_sdw (buf, cpu.SDW)); cpu 683 src/dps8/dps8_append.c if ((! cpu.tweaks.enable_wam) || (! cpu.cu.PT_ON)) cpu 689 src/dps8/dps8_append.c if (cpu.tweaks.l68_mode) { // L68 cpu 693 src/dps8/dps8_append.c if (cpu.PTWAM[_n].FE && ((CA >> 6) & 07760) == cpu.PTWAM[_n].PAGENO && cpu 694 src/dps8/dps8_append.c cpu.PTWAM[_n].POINTER == segno) //_initialized cpu 698 src/dps8/dps8_append.c __func__, segno, cpu.PTWAM[_n].PAGENO, _n); cpu 699 src/dps8/dps8_append.c cpu.cu.PTWAMM = 1; cpu 700 src/dps8/dps8_append.c cpu.PTWAMR = (word4) _n; cpu 701 src/dps8/dps8_append.c cpu.PTW = & cpu.PTWAM[_n]; cpu 711 src/dps8/dps8_append.c if (cpu.PTWAM[_h].USE > cpu.PTW->USE) cpu 712 src/dps8/dps8_append.c cpu.PTWAM[_h].USE -= 1; //PTW->USE -= 1; cpu 714 src/dps8/dps8_append.c cpu.PTW->USE = N_L68_WAM_ENTRIES - 1; cpu 719 src/dps8/dps8_append.c __func__, cpu.PTW->ADDR, cpu.PTW->U, cpu.PTW->M, cpu 720 src/dps8/dps8_append.c cpu.PTW->DF, cpu.PTW->FC); cpu 721 src/dps8/dps8_append.c return cpu.PTW; cpu 732 src/dps8/dps8_append.c p = & cpu.PTWAM[toffset + setno]; cpu 739 src/dps8/dps8_append.c cpu.cu.PTWAMM = 1; cpu 740 src/dps8/dps8_append.c cpu.PTWAMR = (word6) (toffset + setno); cpu 741 src/dps8/dps8_append.c cpu.PTW = p; // export pointer for appending cpu 746 src/dps8/dps8_append.c p = & cpu.PTWAM[toffset + setno]; cpu 752 src/dps8/dps8_append.c __func__, cpu.PTW->ADDR, cpu.PTW->U, cpu.PTW->M, cpu 753 src/dps8/dps8_append.c cpu.PTW->DF, cpu.PTW->FC); cpu 754 src/dps8/dps8_append.c return cpu.PTW; cpu 758 src/dps8/dps8_append.c cpu.cu.PTWAMM = 0; cpu 767 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FPTW;)) cpu 777 src/dps8/dps8_append.c PNL (cpu.lastPTWOffset = offset;) cpu 778 src/dps8/dps8_append.c PNL (cpu.lastPTWIsDS = false;) cpu 791 src/dps8/dps8_append.c cpu.PTW0.ADDR = GETHI (PTWx2); cpu 792 src/dps8/dps8_append.c cpu.PTW0.U = TSTBIT (PTWx2, 9); cpu 793 src/dps8/dps8_append.c cpu.PTW0.M = TSTBIT (PTWx2, 6); cpu 794 src/dps8/dps8_append.c cpu.PTW0.DF = TSTBIT (PTWx2, 2); cpu 795 src/dps8/dps8_append.c cpu.PTW0.FC = PTWx2 & 3; cpu 799 src/dps8/dps8_append.c if (! cpu.PTW0.U) cpu 808 src/dps8/dps8_append.c cpu.PTW0.U = 1; cpu 816 src/dps8/dps8_append.c L68_ (if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 821 src/dps8/dps8_append.c __func__, x2, sdw->ADDR, PTWx2, cpu.PTW0.ADDR, cpu.PTW0.U, cpu 822 src/dps8/dps8_append.c cpu.PTW0.M, cpu.PTW0.DF, cpu.PTW0.FC); cpu 827 src/dps8/dps8_append.c cpu.PTW0.PAGENO = (offset >> 6) & 07760; cpu 828 src/dps8/dps8_append.c cpu.PTW0.POINTER = segno; cpu 829 src/dps8/dps8_append.c cpu.PTW0.USE = 0; cpu 830 src/dps8/dps8_append.c cpu.PTW0.FE = true; cpu 832 src/dps8/dps8_append.c cpu.PTW = & cpu.PTW0; cpu 833 src/dps8/dps8_append.c if (nomatch || (! cpu.tweaks.enable_wam) || (! cpu.cu.PT_ON)) cpu 839 src/dps8/dps8_append.c if (cpu.tweaks.l68_mode) { // L68 cpu 848 src/dps8/dps8_append.c ptw_s * p = & cpu.PTWAM[_n]; cpu 852 src/dps8/dps8_append.c *p = cpu.PTW0; cpu 860 src/dps8/dps8_append.c ptw_s * q = & cpu.PTWAM[_h]; cpu 865 src/dps8/dps8_append.c cpu.PTW = p; cpu 868 src/dps8/dps8_append.c cpu.PTW->ADDR, cpu.PTW->U, cpu.PTW->M, cpu.PTW->DF, cpu 869 src/dps8/dps8_append.c cpu.PTW->FC, cpu.PTW->POINTER, cpu.PTW->PAGENO, cpu 870 src/dps8/dps8_append.c cpu.PTW->USE); cpu 888 src/dps8/dps8_append.c p = & cpu.PTWAM[toffset + setno]; cpu 895 src/dps8/dps8_append.c p = & cpu.PTWAM[toffset + setno]; cpu 902 src/dps8/dps8_append.c * p = cpu.PTW0; // load the PTW cpu 906 src/dps8/dps8_append.c cpu.PTW = p; // export pointer for appending cpu 910 src/dps8/dps8_append.c p = & cpu.PTWAM[toffset1 + setno]; cpu 917 src/dps8/dps8_append.c cpu.PTW->ADDR, cpu.PTW->U, cpu.PTW->M, cpu.PTW->DF, cpu 918 src/dps8/dps8_append.c cpu.PTW->FC, cpu.PTW->POINTER, cpu.PTW->PAGENO, cpu.PTW->USE); cpu 928 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_MPTW;)) cpu 954 src/dps8/dps8_append.c cpu.PTW->M = 1; cpu 955 src/dps8/dps8_append.c L68_ (if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 961 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FPTW2;)) cpu 980 src/dps8/dps8_append.c L68_ (if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 990 src/dps8/dps8_append.c if ((PTW2.ADDR & 0777760) == (cpu.PTW->ADDR & 0777760) + 16) cpu 1199 src/dps8/dps8_append.c DCDstruct * i = & cpu.currentInstruction; cpu 1203 src/dps8/dps8_append.c str_pct (cpu.apu.lastCycle)); cpu 1205 src/dps8/dps8_append.c cpu.TPR.CA); cpu 1209 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.PPR.PSR); cpu 1211 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.TPR.TSR); cpu 1223 src/dps8/dps8_append.c if (cpu.tweaks.enable_wam) cpu 1235 src/dps8/dps8_append.c processor_cycle_type lastCycle = cpu.apu.lastCycle; cpu 1236 src/dps8/dps8_append.c cpu.apu.lastCycle = thisCycle; cpu 1238 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(Entry) XSF %o\n", cpu.cu.XSF); cpu 1240 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state = 0;)) cpu 1242 src/dps8/dps8_append.c cpu.RSDWH_R1 = 0; cpu 1244 src/dps8/dps8_append.c cpu.acvFaults = 0; cpu 1277 src/dps8/dps8_append.c ! (cpu.cu.XSF || cpu.currentInstruction.b29) /*get_went_appending()*/) cpu 1279 src/dps8/dps8_append.c cpu.TPR.TSR = 0; cpu 1281 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.TRR); cpu 1299 src/dps8/dps8_append.c PNL (cpu.APUMemAddr = cpu.TPR.CA;) cpu 1304 src/dps8/dps8_append.c if (nomatch || ! fetch_sdw_from_sdwam (cpu.TPR.TSR)) cpu 1308 src/dps8/dps8_append.c cpu.TPR.TSR); cpu 1311 src/dps8/dps8_append.c cpu.DSBR.U); cpu 1313 src/dps8/dps8_append.c if (cpu.DSBR.U == 0) cpu 1315 src/dps8/dps8_append.c fetch_dsptw (cpu.TPR.TSR); cpu 1317 src/dps8/dps8_append.c if (! cpu.PTW0.DF) cpu 1318 src/dps8/dps8_append.c doFault (FAULT_DF0 + cpu.PTW0.FC, fst_zero, cpu 1321 src/dps8/dps8_append.c if (! cpu.PTW0.U) cpu 1322 src/dps8/dps8_append.c modify_dsptw (cpu.TPR.TSR); cpu 1324 src/dps8/dps8_append.c fetch_psdw (cpu.TPR.TSR); cpu 1327 src/dps8/dps8_append.c fetch_nsdw (cpu.TPR.TSR); // load SDW0 from descriptor segment table. cpu 1329 src/dps8/dps8_append.c if (cpu.SDW0.DF == 0) cpu 1336 src/dps8/dps8_append.c doFault (FAULT_DF0 + cpu.SDW0.FC, fst_zero, "SDW0.F == 0"); cpu 1340 src/dps8/dps8_append.c load_sdwam (cpu.TPR.TSR, nomatch); cpu 1343 src/dps8/dps8_append.c cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu.SDW->E); cpu 1346 src/dps8/dps8_append.c cpu.RSDWH_R1 = cpu.SDW->R1; cpu 1363 src/dps8/dps8_append.c if (! (cpu.SDW->R1 <= cpu.SDW->R2 && cpu.SDW->R2 <= cpu.SDW->R3)) cpu 1366 src/dps8/dps8_append.c cpu.acvFaults |= ACV0; cpu 1367 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1433 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R2) cpu 1438 src/dps8/dps8_append.c cpu.acvFaults |= ACV3; cpu 1439 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1443 src/dps8/dps8_append.c if (cpu.SDW->R == 0) cpu 1446 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1449 src/dps8/dps8_append.c if (cpu.PPR.PSR != cpu.TPR.TSR) cpu 1454 src/dps8/dps8_append.c cpu.acvFaults |= ACV4; cpu 1455 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1479 src/dps8/dps8_append.c if (cpu.TPR.TSR == cpu.PPR.PSR) cpu 1480 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1483 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R1) cpu 1486 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.SDW->R1); cpu 1488 src/dps8/dps8_append.c cpu.acvFaults |= ACV5; cpu 1489 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1493 src/dps8/dps8_append.c if (! cpu.SDW->W) cpu 1496 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1500 src/dps8/dps8_append.c cpu.acvFaults |= ACV6; cpu 1501 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1525 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.SDW->R1 || cpu 1526 src/dps8/dps8_append.c cpu.TPR.TRR > cpu.SDW->R2) cpu 1530 src/dps8/dps8_append.c cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); cpu 1532 src/dps8/dps8_append.c cpu.acvFaults |= ACV1; cpu 1533 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1537 src/dps8/dps8_append.c if (! cpu.SDW->E) cpu 1542 src/dps8/dps8_append.c cpu.acvFaults |= ACV2; cpu 1543 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1546 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.PPR.PRR) cpu 1548 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.PPR.PRR); cpu 1550 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.PPR.PRR) cpu 1555 src/dps8/dps8_append.c cpu.acvFaults |= ACV11; cpu 1556 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1567 src/dps8/dps8_append.c if (cpu.rRALR == 0) cpu 1571 src/dps8/dps8_append.c if (! (cpu.PPR.PRR < cpu.rRALR)) cpu 1575 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.rRALR); cpu 1576 src/dps8/dps8_append.c cpu.acvFaults |= ACV13; cpu 1577 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1599 src/dps8/dps8_append.c cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu 1600 src/dps8/dps8_append.c cpu.SDW->EB, cpu.SDW->R1, cpu.SDW->R2, cpu.SDW->R3, cpu 1601 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.PPR.PRR); cpu 1604 src/dps8/dps8_append.c if (! cpu.SDW->E) cpu 1609 src/dps8/dps8_append.c cpu.acvFaults |= ACV2; cpu 1610 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1615 src/dps8/dps8_append.c if (cpu.SDW->G) cpu 1619 src/dps8/dps8_append.c if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS) cpu 1625 src/dps8/dps8_append.c if (cpu.TPR.CA >= (word18) cpu.SDW->EB) cpu 1630 src/dps8/dps8_append.c cpu.acvFaults |= ACV7; cpu 1631 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1639 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R3) cpu 1644 src/dps8/dps8_append.c cpu.acvFaults |= ACV8; cpu 1645 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1650 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.SDW->R1) cpu 1655 src/dps8/dps8_append.c cpu.acvFaults |= ACV9; cpu 1656 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1661 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.PPR.PRR) cpu 1664 src/dps8/dps8_append.c if (cpu.PPR.PRR < cpu.SDW->R2) cpu 1669 src/dps8/dps8_append.c cpu.acvFaults |= ACV10; cpu 1670 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1677 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.SDW->R2); cpu 1680 src/dps8/dps8_append.c if (cpu.TPR.TRR > cpu.SDW->R2) cpu 1683 src/dps8/dps8_append.c cpu.TPR.TRR = cpu.SDW->R2; cpu 1686 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(E1): CALL6 TPR.TRR %o\n", cpu.TPR.TRR); cpu 1697 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_PIAU;)) cpu 1706 src/dps8/dps8_append.c if (cpu.TPR.TRR < cpu.SDW->R1 || cpu 1707 src/dps8/dps8_append.c cpu.TPR.TRR > cpu.SDW->R2) cpu 1711 src/dps8/dps8_append.c cpu.SDW->R1, cpu.TPR.TRR, cpu.SDW->R2); cpu 1712 src/dps8/dps8_append.c cpu.acvFaults |= ACV1; cpu 1713 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1717 src/dps8/dps8_append.c if (! cpu.SDW->E) cpu 1721 src/dps8/dps8_append.c cpu.acvFaults |= ACV2; cpu 1722 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1727 src/dps8/dps8_append.c if (cpu.PPR.PRR != cpu.TPR.TRR) cpu 1732 src/dps8/dps8_append.c cpu.acvFaults |= ACV12; cpu 1733 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1750 src/dps8/dps8_append.c if (((cpu.TPR.CA >> 4) & 037777) > cpu.SDW->BOUND) cpu 1754 src/dps8/dps8_append.c cpu.acvFaults |= ACV15; cpu 1755 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1759 src/dps8/dps8_append.c cpu.TPR.CA, ((cpu.TPR.CA >> 4) & 037777), cpu.SDW->BOUND); cpu 1762 src/dps8/dps8_append.c if (cpu.acvFaults) cpu 1765 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FLT;)) cpu 1767 src/dps8/dps8_append.c doFault (FAULT_ACV, (_fault_subtype) {.fault_acv_subtype=cpu.acvFaults}, cpu 1772 src/dps8/dps8_append.c if (cpu.SDW->U) cpu 1778 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(G) CA %06o\n", cpu.TPR.CA); cpu 1780 src/dps8/dps8_append.c ! fetch_ptw_from_ptwam (cpu.SDW->POINTER, cpu.TPR.CA)) //TPR.CA)) cpu 1782 src/dps8/dps8_append.c fetch_ptw (cpu.SDW, cpu.TPR.CA); cpu 1783 src/dps8/dps8_append.c if (! cpu.PTW0.DF) cpu 1788 src/dps8/dps8_append.c doFault (FAULT_DF0 + cpu.PTW0.FC, (_fault_subtype) {.bits=0}, cpu 1792 src/dps8/dps8_append.c loadPTWAM (cpu.SDW->POINTER, cpu.TPR.CA, nomatch); // load PTW0 to PTWAM cpu 1803 src/dps8/dps8_append.c do_ptw2 (cpu.SDW, cpu.TPR.CA); cpu 1816 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FANP;)) cpu 1829 src/dps8/dps8_append.c cpu.SDW->ADDR, cpu.TPR.CA); cpu 1833 src/dps8/dps8_append.c ! (cpu.cu.XSF || cpu.currentInstruction.b29) /*get_went_appending ()*/) cpu 1835 src/dps8/dps8_append.c finalAddress = cpu.TPR.CA; cpu 1839 src/dps8/dps8_append.c finalAddress = (cpu.SDW->ADDR & 077777760) + cpu.TPR.CA; cpu 1842 src/dps8/dps8_append.c PNL (cpu.APUMemAddr = finalAddress;) cpu 1845 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 1859 src/dps8/dps8_append.c thisCycle == APU_DATA_RMW) && cpu.PTW->M == 0) // is this the right way to do this? cpu 1861 src/dps8/dps8_append.c if (StrOp && cpu.PTW->M == 0) // is this the right way to do this? cpu 1864 src/dps8/dps8_append.c modify_ptw (cpu.SDW, cpu.TPR.CA); cpu 1869 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FAP;)) cpu 1871 src/dps8/dps8_append.c word24 y2 = cpu.TPR.CA % 1024; cpu 1875 src/dps8/dps8_append.c finalAddress = (((word24)cpu.PTW->ADDR & 0777760) << 6) + y2; cpu 1877 src/dps8/dps8_append.c PNL (cpu.APUMemAddr = finalAddress;) cpu 1879 src/dps8/dps8_append.c L68_ (if (cpu.MR_cache.emr && cpu.MR_cache.ihr) cpu 1883 src/dps8/dps8_append.c cpu.TPR.TSR, cpu.TPR.CA, finalAddress); cpu 1895 src/dps8/dps8_append.c cpu.cu.XSF = 1; cpu 1899 src/dps8/dps8_append.c if (thisCycle == OPERAND_STORE && cpu.useZone) cpu 1961 src/dps8/dps8_append.c (cpu.TPR.CA & 1) == 0) cpu 2029 src/dps8/dps8_append.c cpu.TPR.TSR = GET_ITS_SEGNO (data); cpu 2034 src/dps8/dps8_append.c cpu.PPR.PRR = cpu.TPR.TRR = max3 (y, cpu.TPR.TRR, cpu.RSDWH_R1); cpu 2038 src/dps8/dps8_append.c cpu.TPR.CA = GET_ITS_WORDNO (data); cpu 2063 src/dps8/dps8_append.c cpu.PR[n].RNR = cpu.PPR.PRR; cpu 2067 src/dps8/dps8_append.c cpu.PR[n].SNR = cpu.PPR.PSR; cpu 2068 src/dps8/dps8_append.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; cpu 2090 src/dps8/dps8_append.c cpu.PR[0].RNR = cpu 2091 src/dps8/dps8_append.c cpu.PR[1].RNR = cpu 2092 src/dps8/dps8_append.c cpu.PR[2].RNR = cpu 2093 src/dps8/dps8_append.c cpu.PR[3].RNR = cpu 2094 src/dps8/dps8_append.c cpu.PR[4].RNR = cpu 2095 src/dps8/dps8_append.c cpu.PR[5].RNR = cpu 2096 src/dps8/dps8_append.c cpu.PR[6].RNR = cpu 2097 src/dps8/dps8_append.c cpu.PR[7].RNR = cpu.TPR.TRR; cpu 2115 src/dps8/dps8_append.c cpu.PPR.PSR = cpu.TPR.TSR; cpu 2117 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; cpu 2125 src/dps8/dps8_append.c if (cpu.TPR.TRR == 0) cpu 2128 src/dps8/dps8_append.c cpu.PPR.P = cpu.SDW->P; cpu 2133 src/dps8/dps8_append.c cpu.PPR.P = 0; cpu 2142 src/dps8/dps8_append.c if (cpu.TPR.TRR == cpu.PPR.PRR) cpu 2145 src/dps8/dps8_append.c cpu.PR[7].SNR = cpu.PR[6].SNR; cpu 2146 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(N) PR7.SNR = PR6.SNR %05o\n", cpu.PR[7].SNR); cpu 2151 src/dps8/dps8_append.c cpu.PR[7].SNR = ((word15) (cpu.DSBR.STACK << 3)) | cpu.TPR.TRR; cpu 2153 src/dps8/dps8_append.c cpu.DSBR.STACK, cpu.TPR.TRR); cpu 2154 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(N) PR7.SNR = STACK||TRR %05o\n", cpu.PR[7].SNR); cpu 2158 src/dps8/dps8_append.c cpu.PR[7].RNR = cpu.TPR.TRR; cpu 2160 src/dps8/dps8_append.c cpu.PR[7].WORDNO = 0; cpu 2167 src/dps8/dps8_append.c cpu.PPR.PRR = cpu.TPR.TRR; cpu 2169 src/dps8/dps8_append.c cpu.PPR.PSR = cpu.TPR.TSR; cpu 2171 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; cpu 2185 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.RSDWH_R1, its_RNR); cpu 2189 src/dps8/dps8_append.c cpu.TPR.TRR = max3 (its_RNR, cpu.TPR.TRR, cpu.RSDWH_R1); cpu 2190 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(O) Set TRR to %o\n", cpu.TPR.TRR); cpu 2200 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.RSDWH_R1, cpu.PR[n].RNR); cpu 2204 src/dps8/dps8_append.c cpu.TPR.TRR = max3 (cpu.PR[n].RNR, cpu.TPR.TRR, cpu.RSDWH_R1); cpu 2205 src/dps8/dps8_append.c DBGAPP ("do_append_cycle(P) Set TRR to %o\n", cpu.TPR.TRR); cpu 2211 src/dps8/dps8_append.c PNL (cpu.APUDataBusOffset = cpu.TPR.CA;) cpu 2212 src/dps8/dps8_append.c PNL (cpu.APUDataBusAddr = finalAddress;) cpu 2214 src/dps8/dps8_append.c PNL (L68_ (cpu.apu.state |= apu_FA;)) cpu 2217 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu 2219 src/dps8/dps8_append.c cpu.TPR.TRR, cpu.TPR.TSR, cpu.TPR.TBR, cpu.TPR.CA); cpu 2237 src/dps8/dps8_append.c if (2u * segno >= 16u * (cpu.DSBR.BND + 1u)) cpu 2244 src/dps8/dps8_append.c if (cpu.DSBR.U == 0) cpu 2252 src/dps8/dps8_append.c core_read ((cpu.DSBR.ADDR + x1) & PAMASK, & PTWx1, __func__); cpu 2301 src/dps8/dps8_append.c core_read2 ((cpu.DSBR.ADDR + 2 * segno) & PAMASK, cpu 121 src/dps8/dps8_append.h word12 FCT = cpu.cu.APUCycleBits & MASK3; cpu 122 src/dps8/dps8_append.h cpu.cu.APUCycleBits = (status & 07770) | FCT; cpu 171 src/dps8/dps8_append.h cpu.apu.lastCycle = thisCycle; cpu 85 src/dps8/dps8_cpu.c #define DBG_CTR cpu.cycleCnt cpu 908 src/dps8/dps8_cpu.c cpu.cycle = cycle; cpu 943 src/dps8/dps8_cpu.c cpu.rA = 0; cpu 944 src/dps8/dps8_cpu.c cpu.rQ = 0; cpu 946 src/dps8/dps8_cpu.c cpu.PPR.IC = 0; cpu 947 src/dps8/dps8_cpu.c cpu.PPR.PRR = 0; cpu 948 src/dps8/dps8_cpu.c cpu.PPR.PSR = 0; cpu 949 src/dps8/dps8_cpu.c cpu.PPR.P = 1; cpu 950 src/dps8/dps8_cpu.c cpu.RSDWH_R1 = 0; cpu 951 src/dps8/dps8_cpu.c cpu.rTR = MASK27; cpu 953 src/dps8/dps8_cpu.c if (cpu.tweaks.isolts_mode) cpu 955 src/dps8/dps8_cpu.c cpu.shadowTR = 0; cpu 956 src/dps8/dps8_cpu.c cpu.rTRlsb = 0; cpu 958 src/dps8/dps8_cpu.c cpu.rTRticks = 0; cpu 963 src/dps8/dps8_cpu.c cpu.CMR.luf = 3; // default of 16 mS cpu 964 src/dps8/dps8_cpu.c cpu.cu.SD_ON = cpu.switches.sdwam_enable ? 1 : 0; cpu 965 src/dps8/dps8_cpu.c cpu.cu.PT_ON = cpu.switches.ptwam_enable ? 1 : 0; cpu 967 src/dps8/dps8_cpu.c if (cpu.tweaks.nodis) { cpu 971 src/dps8/dps8_cpu.c cpu.cu.IWB = 0000000616000; //-V536 // Stuff DIS instruction in instruction buffer cpu 976 src/dps8/dps8_cpu.c cpu.wasXfer = false; cpu 977 src/dps8/dps8_cpu.c cpu.wasInhibited = false; cpu 979 src/dps8/dps8_cpu.c cpu.interrupt_flag = false; cpu 980 src/dps8/dps8_cpu.c cpu.g7_flag = false; cpu 982 src/dps8/dps8_cpu.c cpu.faultRegister [0] = 0; cpu 983 src/dps8/dps8_cpu.c cpu.faultRegister [1] = 0; cpu 986 src/dps8/dps8_cpu.c cpu.apu.lastCycle = UNKNOWN_CYCLE; cpu 989 src/dps8/dps8_cpu.c memset (& cpu.PPR, 0, sizeof (struct ppr_s)); cpu 1289 src/dps8/dps8_cpu.c cpu.sc_addr_map [pg] = -1; cpu 1290 src/dps8/dps8_cpu.c cpu.sc_scu_map [pg] = -1; cpu 1293 src/dps8/dps8_cpu.c cpu.sc_num_banks[u] = 0; cpu 1296 src/dps8/dps8_cpu.c for (int port_num = 0; port_num < (cpu.tweaks.l68_mode ? N_L68_CPU_PORTS : N_DPS8M_CPU_PORTS); port_num ++) cpu 1299 src/dps8/dps8_cpu.c if (! cpu.switches.enable [port_num]) cpu 1311 src/dps8/dps8_cpu.c uint store_size = cpu.switches.store_size [port_num]; cpu 1334 src/dps8/dps8_cpu.c cpu.tweaks.l68_mode ? cpu 1335 src/dps8/dps8_cpu.c cpu.tweaks.isolts_mode ? cpu 1341 src/dps8/dps8_cpu.c uint base_addr_wds = sz_wds * cpu.switches.assignment[port_num]; cpu 1345 src/dps8/dps8_cpu.c cpu.sc_num_banks[port_num] = num_banks; cpu 1357 src/dps8/dps8_cpu.c if (cpu.sc_addr_map [addr_bks] != -1) cpu 1361 src/dps8/dps8_cpu.c addr_bks, addr_bks, cpu.sc_addr_map [addr_bks], port_num); cpu 1366 src/dps8/dps8_cpu.c cpu.sc_addr_map[addr_bks] = (int)((int)port_num * (int)ZONE_SZ + (int)pg * (int)SCBANK_SZ); cpu 1367 src/dps8/dps8_cpu.c cpu.sc_scu_map[addr_bks] = port_num; cpu 1389 src/dps8/dps8_cpu.c return cpu.sc_scu_map[scpg]; cpu 1413 src/dps8/dps8_cpu.c if (sscanf (buffer, "sn: %u", & cpu.switches.serno) == 1) cpu 1417 src/dps8/dps8_cpu.c sim_msg ("%s CPU serial number: %u\n", sim_name, cpu.switches.serno); cpu 1503 src/dps8/dps8_cpu.c cpu.instrCntT0 = cpu.instrCntT1; cpu 1504 src/dps8/dps8_cpu.c cpu.instrCntT1 = cpu.instrCnt; cpu 1580 src/dps8/dps8_cpu.c cpu.instrCnt = 0; cpu 1581 src/dps8/dps8_cpu.c cpu.cycleCnt = 0; cpu 1583 src/dps8/dps8_cpu.c cpu.faultCnt [i] = 0; cpu 1743 src/dps8/dps8_cpu.c if (cpu.events.XIP [scu_unit_idx]) cpu 1755 src/dps8/dps8_cpu.c cpu.lufCounter = 0; cpu 1758 src/dps8/dps8_cpu.c if (cpu.events.XIP [scu_unit_idx]) cpu 1773 src/dps8/dps8_cpu.c if (cpu.tweaks.isolts_mode == 0) cpu 1793 src/dps8/dps8_cpu.c sim_brk_test ((cpu.PPR.IC & 0777777) | cpu 1794 src/dps8/dps8_cpu.c ((((t_addr) cpu.PPR.PSR) & 037777) << 18), cpu 1798 src/dps8/dps8_cpu.c if (sim_deb_break && cpu.cycleCnt >= sim_deb_break) cpu 1810 src/dps8/dps8_cpu.c if (cpu.panelInitialize && cpu.DATA_panel_s_trig_sw == 0) cpu 1813 src/dps8/dps8_cpu.c while (cpu.panelInitialize) cpu 1815 src/dps8/dps8_cpu.c if (cpu.DATA_panel_init_sw) cpu 1823 src/dps8/dps8_cpu.c if (cpu.DATA_panel_s_trig_sw == 0 && cpu 1824 src/dps8/dps8_cpu.c cpu.DATA_panel_execute_sw && // EXECUTE button cpu 1825 src/dps8/dps8_cpu.c cpu.DATA_panel_scope_sw && // 'EXECUTE PB/SCOPE REPEAT' set to PB cpu 1826 src/dps8/dps8_cpu.c cpu.DATA_panel_exec_sw == 0) // 'EXECUTE SWITCH/EXECUTE FAULT' cpu 1830 src/dps8/dps8_cpu.c while (cpu.DATA_panel_execute_sw) cpu 1833 src/dps8/dps8_cpu.c if (cpu.DATA_panel_exec_sw) // EXECUTE SWITCH cpu 1836 src/dps8/dps8_cpu.c cpu.cu.IWB = cpu.switches.data_switches; cpu 2103 src/dps8/dps8_cpu.c cpu.lufCounter = 0; cpu 2104 src/dps8/dps8_cpu.c cpu.lufOccurred = false; cpu 2123 src/dps8/dps8_cpu.c if (cpu.tweaks.isolts_mode) cpu 2124 src/dps8/dps8_cpu.c cpu.shadowTR = (word27) cpu.TR0 - (1024u << (is_priv_mode () ? 4 : cpu.CMR.luf)); cpu 2157 src/dps8/dps8_cpu.c cpu.secret_addressing_mode = true; cpu 2158 src/dps8/dps8_cpu.c cpu.cu.XSF = false; cpu 2166 src/dps8/dps8_cpu.c cpu.secret_addressing_mode = false; cpu 2167 src/dps8/dps8_cpu.c return cpu.cu.XSF; cpu 2198 src/dps8/dps8_cpu.c cpu.isRunning = true; cpu 2207 src/dps8/dps8_cpu.c if (cpu.isRunning) cpu 2216 src/dps8/dps8_cpu.c if (! cpu . isRunning) cpu 2222 src/dps8/dps8_cpu.c int val = setjmp (cpu.jmpMain); cpu 2244 src/dps8/dps8_cpu.c cpu.wasXfer = false; cpu 2258 src/dps8/dps8_cpu.c DCDstruct * ci = & cpu.currentInstruction; cpu 2260 src/dps8/dps8_cpu.c if (cpu.restart) cpu 2302 src/dps8/dps8_cpu.c cpu.cycleCnt ++; cpu 2324 src/dps8/dps8_cpu.c if (cpu.tweaks.isolts_mode) cpu 2326 src/dps8/dps8_cpu.c if (cpu.cycle != FETCH_cycle) cpu 2329 src/dps8/dps8_cpu.c cpu.rTRlsb ++; cpu 2330 src/dps8/dps8_cpu.c if (cpu.rTRlsb >= 4) cpu 2332 src/dps8/dps8_cpu.c cpu.rTRlsb = 0; cpu 2333 src/dps8/dps8_cpu.c cpu.shadowTR = (cpu.shadowTR - 1) & MASK27; cpu 2334 src/dps8/dps8_cpu.c if (cpu.shadowTR == 0) // passing through 0... cpu 2336 src/dps8/dps8_cpu.c if (cpu.tweaks.tro_enable) cpu 2352 src/dps8/dps8_cpu.c cpu 2354 src/dps8/dps8_cpu.c cpu 2360 src/dps8/dps8_cpu.c cpu.rTR = (word27) (((word27s) cpu.rTR) - (word27s) (cpu.rTRticks / TR_RATE)); cpu 2361 src/dps8/dps8_cpu.c cpu.rTRticks %= TR_RATE; cpu 2365 src/dps8/dps8_cpu.c if (cpu.rTR & ~MASK27) cpu 2367 src/dps8/dps8_cpu.c cpu.rTR &= MASK27; cpu 2368 src/dps8/dps8_cpu.c if (cpu.tweaks.tro_enable) { cpu 2374 src/dps8/dps8_cpu.c cycle_str (cpu.cycle)); cpu 2376 src/dps8/dps8_cpu.c switch (cpu.cycle) cpu 2396 src/dps8/dps8_cpu.c cpu.cu.FI_ADDR = (word5) (intr_pair_addr / 2); cpu 2406 src/dps8/dps8_cpu.c cpu.PPR.PRR = 0; cpu 2407 src/dps8/dps8_cpu.c cpu.TPR.TRR = 0; cpu 2410 src/dps8/dps8_cpu.c intr_pair_addr, cpu.interrupt_flag); cpu 2416 src/dps8/dps8_cpu.c if (cpu.interrupt_flag) cpu 2432 src/dps8/dps8_cpu.c & cpu.cu.IWB, & cpu.cu.IRODD, __func__); cpu 2434 src/dps8/dps8_cpu.c HDBGMRead (intr_pair_addr, cpu.cu.IWB, "intr even"); cpu 2435 src/dps8/dps8_cpu.c HDBGMRead (intr_pair_addr + 1, cpu.cu.IRODD, "intr odd"); cpu 2437 src/dps8/dps8_cpu.c cpu.cu.xde = 1; cpu 2438 src/dps8/dps8_cpu.c cpu.cu.xdo = 1; cpu 2439 src/dps8/dps8_cpu.c cpu.isExec = true; cpu 2440 src/dps8/dps8_cpu.c cpu.isXED = true; cpu 2443 src/dps8/dps8_cpu.c cpu.interrupt_flag = false; cpu 2452 src/dps8/dps8_cpu.c cpu.interrupt_flag = false; cpu 2458 src/dps8/dps8_cpu.c cpu.wasXfer = false; cpu 2467 src/dps8/dps8_cpu.c memset (cpu.cpt, 0, sizeof (cpu.cpt)); cpu 2471 src/dps8/dps8_cpu.c PNL (L68_ (cpu.INS_FETCH = false;)) cpu 2509 src/dps8/dps8_cpu.c get_BAR_address (cpu.PPR.IC); cpu 2515 src/dps8/dps8_cpu.c bool is_dis = cpu.currentInstruction.opcode == 0616 && cpu 2516 src/dps8/dps8_cpu.c cpu.currentInstruction.opcodeX == 0; cpu 2518 src/dps8/dps8_cpu.c !(is_dis && GET_I (cpu.cu.IWB) == 0); cpu 2524 src/dps8/dps8_cpu.c cpu.interrupt_flag = sample_interrupts (); cpu 2525 src/dps8/dps8_cpu.c cpu.g7_flag = cpu 2528 src/dps8/dps8_cpu.c else if (! (cpu.cu.xde | cpu.cu.xdo | cpu 2529 src/dps8/dps8_cpu.c cpu.cu.rpt | cpu.cu.rd | cpu.cu.rl)) cpu 2531 src/dps8/dps8_cpu.c if ((!cpu.wasInhibited) && cpu 2532 src/dps8/dps8_cpu.c (cpu.PPR.IC & 1) == 0 && cpu 2533 src/dps8/dps8_cpu.c (! cpu.wasXfer)) cpu 2536 src/dps8/dps8_cpu.c cpu.interrupt_flag = sample_interrupts (); cpu 2537 src/dps8/dps8_cpu.c cpu.g7_flag = cpu 2540 src/dps8/dps8_cpu.c cpu.wasInhibited = false; cpu 2549 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 1) cpu 2551 src/dps8/dps8_cpu.c cpu.wasInhibited = true; cpu 2586 src/dps8/dps8_cpu.c cpu 2587 src/dps8/dps8_cpu.c cpu 2589 src/dps8/dps8_cpu.c if (cpu.g7_flag) cpu 2591 src/dps8/dps8_cpu.c cpu.g7_flag = false; cpu 2592 src/dps8/dps8_cpu.c cpu.interrupt_flag = false; cpu 2597 src/dps8/dps8_cpu.c if (cpu.interrupt_flag) cpu 2619 src/dps8/dps8_cpu.c cpu.lufCounter ++; cpu 2621 src/dps8/dps8_cpu.c if (cpu.lufCounter > luf_limits[cpu.CMR.luf]) cpu 2626 src/dps8/dps8_cpu.c cpu.lufOccurred = true; cpu 2635 src/dps8/dps8_cpu.c if (cpu.lufCounter > luf_limits[4]) cpu 2642 src/dps8/dps8_cpu.c if (! tmp_priv_mode && cpu.lufOccurred) cpu 2647 src/dps8/dps8_cpu.c cpu 2649 src/dps8/dps8_cpu.c cpu 2652 src/dps8/dps8_cpu.c cpu 2672 src/dps8/dps8_cpu.c cpu 2673 src/dps8/dps8_cpu.c cpu 2678 src/dps8/dps8_cpu.c if (cpu.cycle == PSEUDO_FETCH_cycle) cpu 2680 src/dps8/dps8_cpu.c cpu.apu.lastCycle = INSTRUCTION_FETCH; cpu 2681 src/dps8/dps8_cpu.c cpu.cu.XSF = 0; cpu 2682 src/dps8/dps8_cpu.c cpu.cu.TSN_VALID [0] = 0; cpu 2683 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 2684 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 2685 src/dps8/dps8_cpu.c cpu.wasInhibited = false; cpu 2690 src/dps8/dps8_cpu.c cpu.isExec = false; cpu 2691 src/dps8/dps8_cpu.c cpu.isXED = false; cpu 2695 src/dps8/dps8_cpu.c cpu.cu.XSF = 0; cpu 2697 src/dps8/dps8_cpu.c cpu.cu.TSN_VALID [0] = 0; cpu 2698 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 2699 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 2700 src/dps8/dps8_cpu.c PNL (cpu.prepare_state = ps_PIA); cpu 2701 src/dps8/dps8_cpu.c PNL (L68_ (cpu.INS_FETCH = true;)) cpu 2702 src/dps8/dps8_cpu.c fetchInstruction (cpu.PPR.IC); cpu 2720 src/dps8/dps8_cpu.c if (stall_points[i].segno && stall_points[i].segno == cpu.PPR.PSR && cpu 2721 src/dps8/dps8_cpu.c stall_points[i].offset && stall_points[i].offset == cpu.PPR.IC) cpu 2736 src/dps8/dps8_cpu.c if (GET_I (cpu.cu.IWB)) cpu 2737 src/dps8/dps8_cpu.c cpu.wasInhibited = true; cpu 2741 src/dps8/dps8_cpu.c cpu.rTRticks ++; cpu 2745 src/dps8/dps8_cpu.c if (cpu.tweaks.l68_mode) cpu 2759 src/dps8/dps8_cpu.c cpu.wasXfer = false; cpu 2760 src/dps8/dps8_cpu.c cpu.isExec = true; cpu 2761 src/dps8/dps8_cpu.c if (cpu.cu.xdo) cpu 2762 src/dps8/dps8_cpu.c cpu.isXED = true; cpu 2764 src/dps8/dps8_cpu.c cpu.cu.XSF = 0; cpu 2765 src/dps8/dps8_cpu.c cpu.cu.TSN_VALID [0] = 0; cpu 2766 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 2767 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 2774 src/dps8/dps8_cpu.c cpu.cu.xde = cpu.cu.xdo = 0; cpu 2775 src/dps8/dps8_cpu.c cpu.isExec = false; cpu 2776 src/dps8/dps8_cpu.c cpu.isXED = false; cpu 2778 src/dps8/dps8_cpu.c cpu.wasXfer = true; cpu 2780 src/dps8/dps8_cpu.c if (cpu.cycle != EXEC_cycle) // fault or interrupt cpu 2789 src/dps8/dps8_cpu.c if (! (cpu.currentInstruction.opcode == 0715 && cpu 2790 src/dps8/dps8_cpu.c cpu.currentInstruction.opcodeX == 0)) cpu 2814 src/dps8/dps8_cpu.c if (TST_I_ABS && cpu.cu.XSF) cpu 2822 src/dps8/dps8_cpu.c cpu.wasXfer = false; cpu 2896 src/dps8/dps8_cpu.c if (cpu.rTR <= ticks) cpu 2898 src/dps8/dps8_cpu.c if (cpu.tweaks.tro_enable) { cpu 2901 src/dps8/dps8_cpu.c cpu.rTR = (cpu.rTR - ticks) & MASK27; cpu 2904 src/dps8/dps8_cpu.c cpu.rTR = (cpu.rTR - ticks) & MASK27; cpu 2906 src/dps8/dps8_cpu.c if (cpu.rTR == 0) cpu 2907 src/dps8/dps8_cpu.c cpu.rTR = MASK27; cpu 2911 src/dps8/dps8_cpu.c unsigned long left = (unsigned long) ((uint64) (cpu.rTR) * 125u / 64u); cpu 2924 src/dps8/dps8_cpu.c cpu.rTR = (word27) (left * 64 / 125); cpu 2930 src/dps8/dps8_cpu.c if (cpu.tweaks.tro_enable) cpu 2936 src/dps8/dps8_cpu.c cpu.rTR = MASK27; cpu 2939 src/dps8/dps8_cpu.c cpu.rTRticks = 0; cpu 2963 src/dps8/dps8_cpu.c cpu.rTRticks = 0; cpu 2970 src/dps8/dps8_cpu.c if (cpu.rTR <= sys_opts.sys_poll_interval * 512) cpu 2972 src/dps8/dps8_cpu.c if (cpu.tweaks.tro_enable) { cpu 2976 src/dps8/dps8_cpu.c cpu.rTR = (cpu.rTR - sys_opts.sys_poll_interval * 512) & MASK27; cpu 2979 src/dps8/dps8_cpu.c cpu.rTR = (cpu.rTR - sys_opts.sys_poll_interval * 512) & MASK27; cpu 2980 src/dps8/dps8_cpu.c if (cpu.rTR == 0) cpu 2981 src/dps8/dps8_cpu.c cpu.rTR = MASK27; cpu 2988 src/dps8/dps8_cpu.c cpu.wasXfer = false; cpu 2996 src/dps8/dps8_cpu.c if ((! cpu.cu.repeat_first) && cpu 2997 src/dps8/dps8_cpu.c (cpu.cu.rpt || cpu 2998 src/dps8/dps8_cpu.c (cpu.cu.rd && (cpu.PPR.IC & 1)) || cpu 2999 src/dps8/dps8_cpu.c cpu.cu.rl)) cpu 3002 src/dps8/dps8_cpu.c if (cpu.cu.rd) cpu 3003 src/dps8/dps8_cpu.c -- cpu.PPR.IC; cpu 3004 src/dps8/dps8_cpu.c cpu.wasXfer = false; cpu 3010 src/dps8/dps8_cpu.c if (cpu.cycle == FAULT_EXEC_cycle && cpu 3011 src/dps8/dps8_cpu.c !cpu.cu.xde && cpu.cu.xdo) cpu 3020 src/dps8/dps8_cpu.c cpu.wasXfer = false; cpu 3021 src/dps8/dps8_cpu.c cpu.isExec = false; cpu 3022 src/dps8/dps8_cpu.c cpu.isXED = false; cpu 3024 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; cpu 3025 src/dps8/dps8_cpu.c cpu.PPR.IC ++; cpu 3032 src/dps8/dps8_cpu.c if (cpu.cycle == INTERRUPT_EXEC_cycle && cpu 3033 src/dps8/dps8_cpu.c !cpu.cu.xde && cpu.cu.xdo) cpu 3041 src/dps8/dps8_cpu.c cpu.wasXfer = false; cpu 3042 src/dps8/dps8_cpu.c cpu.isExec = false; cpu 3043 src/dps8/dps8_cpu.c cpu.isXED = false; cpu 3050 src/dps8/dps8_cpu.c if (cpu.cu.xde && cpu.cu.xdo) cpu 3053 src/dps8/dps8_cpu.c cpu.cu.IWB = cpu.cu.IRODD; cpu 3054 src/dps8/dps8_cpu.c cpu.cu.xde = 0; cpu 3055 src/dps8/dps8_cpu.c cpu.isExec = true; cpu 3056 src/dps8/dps8_cpu.c cpu.isXED = true; cpu 3057 src/dps8/dps8_cpu.c cpu.cu.XSF = 0; cpu 3058 src/dps8/dps8_cpu.c cpu.cu.TSN_VALID [0] = 0; cpu 3059 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 3060 src/dps8/dps8_cpu.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 3064 src/dps8/dps8_cpu.c if (cpu.cu.xde || cpu.cu.xdo) // we are in an XEC/XED cpu 3066 src/dps8/dps8_cpu.c cpu.cu.xde = cpu.cu.xdo = 0; cpu 3067 src/dps8/dps8_cpu.c cpu.isExec = false; cpu 3068 src/dps8/dps8_cpu.c cpu.isXED = false; cpu 3070 src/dps8/dps8_cpu.c cpu.wasXfer = false; cpu 3071 src/dps8/dps8_cpu.c cpu.PPR.IC ++; cpu 3073 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; cpu 3074 src/dps8/dps8_cpu.c cpu.wasInhibited = true; cpu 3080 src/dps8/dps8_cpu.c if (cpu.cycle != EXEC_cycle) cpu 3081 src/dps8/dps8_cpu.c sim_warn ("expected EXEC_cycle (%d)\n", cpu.cycle); cpu 3083 src/dps8/dps8_cpu.c cpu.cu.xde = cpu.cu.xdo = 0; cpu 3084 src/dps8/dps8_cpu.c cpu.isExec = false; cpu 3085 src/dps8/dps8_cpu.c cpu.isXED = false; cpu 3096 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 0 && cpu 3098 src/dps8/dps8_cpu.c !cpu.cu.repeat_first && !cpu.cu.rpt && !cpu.cu.rd && !cpu.cu.rl && cpu 3099 src/dps8/dps8_cpu.c !(cpu.currentInstruction.opcode == 0616 && cpu.currentInstruction.opcodeX == 0) && cpu 3100 src/dps8/dps8_cpu.c (cpu.PPR.IC & ~3u) != (cpu.last_write & ~3u)) cpu 3102 src/dps8/dps8_cpu.c cpu.PPR.IC ++; cpu 3103 src/dps8/dps8_cpu.c cpu.wasXfer = false; cpu 3104 src/dps8/dps8_cpu.c cpu.cu.IWB = cpu.cu.IRODD; cpu 3109 src/dps8/dps8_cpu.c cpu.PPR.IC ++; cpu 3111 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; cpu 3114 src/dps8/dps8_cpu.c cpu.wasXfer = false; cpu 3126 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; cpu 3127 src/dps8/dps8_cpu.c cpu.PPR.IC ++; cpu 3128 src/dps8/dps8_cpu.c cpu.wasXfer = false; cpu 3157 src/dps8/dps8_cpu.c if ((cpu.cu.APUCycleBits & 060) || cpu.secret_addressing_mode) cpu 3170 src/dps8/dps8_cpu.c if (cpu.faultNumber != FAULT_TRB || cpu.cu.xde == 0) cpu 3176 src/dps8/dps8_cpu.c word36 tmpIRODD = cpu.scu_data[7]; cpu 3178 src/dps8/dps8_cpu.c cpu.scu_data[7] = tmpIRODD; cpu 3186 src/dps8/dps8_cpu.c cpu.PPR.PRR = 0; cpu 3187 src/dps8/dps8_cpu.c cpu.TPR.TRR = 0; cpu 3190 src/dps8/dps8_cpu.c uint fltAddress = (cpu.switches.FLT_BASE << 5) & 07740; cpu 3192 src/dps8/dps8_cpu.c if (cpu.is_FFV) cpu 3194 src/dps8/dps8_cpu.c cpu.is_FFV = false; cpu 3197 src/dps8/dps8_cpu.c fltAddress = (cpu.MR.FFV & MASK15) << 3; cpu 3202 src/dps8/dps8_cpu.c word24 addr = fltAddress + 2 * cpu.faultNumber; cpu 3204 src/dps8/dps8_cpu.c if (cpu.restart) cpu 3206 src/dps8/dps8_cpu.c cpu.restart = false; cpu 3207 src/dps8/dps8_cpu.c addr = cpu.restart_address; cpu 3210 src/dps8/dps8_cpu.c core_read2 (addr, & cpu.cu.IWB, & cpu.cu.IRODD, __func__); cpu 3212 src/dps8/dps8_cpu.c HDBGMRead (addr, cpu.cu.IWB, "fault even"); cpu 3213 src/dps8/dps8_cpu.c HDBGMRead (addr + 1, cpu.cu.IRODD, "fault odd"); cpu 3215 src/dps8/dps8_cpu.c cpu.cu.xde = 1; cpu 3216 src/dps8/dps8_cpu.c cpu.cu.xdo = 1; cpu 3217 src/dps8/dps8_cpu.c cpu.isExec = true; cpu 3218 src/dps8/dps8_cpu.c cpu.isXED = true; cpu 3258 src/dps8/dps8_cpu.c if (cycleCntAll > (unsigned long long)cpu.cycleCnt) cpu 3324 src/dps8/dps8_cpu.c cpu 3326 src/dps8/dps8_cpu.c cpu 3340 src/dps8/dps8_cpu.c dummy_IC = cpu.PPR.IC; cpu 3362 src/dps8/dps8_cpu.c DCDstruct * i = & cpu.currentInstruction; cpu 3382 src/dps8/dps8_cpu.c DCDstruct * i = & cpu.currentInstruction; cpu 3390 src/dps8/dps8_cpu.c ReadOperandRead (addr, & cpu.CY); cpu 3395 src/dps8/dps8_cpu.c Read2OperandRead (addr, cpu.Ypair); cpu 3400 src/dps8/dps8_cpu.c Read8 (addr, cpu.Yblock8, cpu.currentInstruction.b29); cpu 3405 src/dps8/dps8_cpu.c Read16 (addr, cpu.Yblock16); cpu 3411 src/dps8/dps8_cpu.c ReadOperandRead (addr + j, cpu.Yblock32 + j); cpu 3421 src/dps8/dps8_cpu.c ReadOperandRMW (addr, & cpu.CY); cpu 3426 src/dps8/dps8_cpu.c Read2OperandRead (addr, cpu.Ypair); cpu 3431 src/dps8/dps8_cpu.c Read8 (addr, cpu.Yblock8, cpu.currentInstruction.b29); cpu 3436 src/dps8/dps8_cpu.c Read16 (addr, cpu.Yblock16); cpu 3442 src/dps8/dps8_cpu.c ReadOperandRMW (addr + j, cpu.Yblock32 + j); cpu 3455 src/dps8/dps8_cpu.c WriteOperandStore (addr, cpu.CY); cpu 3460 src/dps8/dps8_cpu.c Write2OperandStore (addr + 0, cpu.Ypair); cpu 3465 src/dps8/dps8_cpu.c Write8 (addr, cpu.Yblock8, cpu.currentInstruction.b29); cpu 3470 src/dps8/dps8_cpu.c Write16 (addr, cpu.Yblock16); cpu 3477 src/dps8/dps8_cpu.c Write32 (addr, cpu.Yblock32); cpu 3484 src/dps8/dps8_cpu.c DCDstruct * i = & cpu.currentInstruction; cpu 3547 src/dps8/dps8_cpu.c PNL (cpu.portBusy = true;) cpu 3555 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); cpu 3562 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, addr, cpu 3578 src/dps8/dps8_cpu.c cpu.rTRticks ++; cpu 3593 src/dps8/dps8_cpu.c if (cpu.locked_addr != 0) { cpu 3595 src/dps8/dps8_cpu.c addr, cpu.locked_addr, current_running_cpu_idx + 'A', cpu 3596 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); cpu 3599 src/dps8/dps8_cpu.c cpu.locked_addr = addr; cpu 3612 src/dps8/dps8_cpu.c PNL (cpu.portBusy = true;) cpu 3614 src/dps8/dps8_cpu.c if (cpu.tweaks.isolts_mode) cpu 3616 src/dps8/dps8_cpu.c if (cpu.MR.sdpap) cpu 3619 src/dps8/dps8_cpu.c cpu.MR.sdpap = 0; cpu 3621 src/dps8/dps8_cpu.c if (cpu.MR.separ) cpu 3624 src/dps8/dps8_cpu.c cpu.MR.separ = 0; cpu 3639 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, cpu 3645 src/dps8/dps8_cpu.c cpu.rTRticks ++; cpu 3659 src/dps8/dps8_cpu.c if (cpu.locked_addr != addr) cpu 3662 src/dps8/dps8_cpu.c addr, cpu.locked_addr, current_running_cpu_idx + 'A', cpu 3663 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); cpu 3670 src/dps8/dps8_cpu.c cpu.locked_addr = 0; cpu 3676 src/dps8/dps8_cpu.c if (cpu.locked_addr != 0) { cpu 3678 src/dps8/dps8_cpu.c cpu.locked_addr, current_running_cpu_idx + 'A', cpu 3679 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); cpu 3681 src/dps8/dps8_cpu.c STORE_REL_CORE_WORD(cpu.locked_addr, M[cpu.locked_addr]); cpu 3683 src/dps8/dps8_cpu.c cpu.locked_addr = 0; cpu 3692 src/dps8/dps8_cpu.c PNL (cpu.portBusy = true;) cpu 3693 src/dps8/dps8_cpu.c if (cpu.tweaks.isolts_mode) cpu 3695 src/dps8/dps8_cpu.c if (cpu.MR.sdpap) cpu 3698 src/dps8/dps8_cpu.c cpu.MR.sdpap = 0; cpu 3700 src/dps8/dps8_cpu.c if (cpu.MR.separ) cpu 3703 src/dps8/dps8_cpu.c cpu.MR.separ = 0; cpu 3711 src/dps8/dps8_cpu.c v = (v & ~cpu.zone) | (data & cpu.zone); cpu 3714 src/dps8/dps8_cpu.c M[mapAddr] = (M[mapAddr] & ~cpu.zone) | (data & cpu.zone); cpu 3716 src/dps8/dps8_cpu.c cpu.useZone = false; // Safety cpu 3721 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, cpu 3727 src/dps8/dps8_cpu.c cpu.rTRticks ++; cpu 3740 src/dps8/dps8_cpu.c PNL (cpu.portBusy = true;) cpu 3759 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); cpu 3766 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, cpu 3776 src/dps8/dps8_cpu.c addr, cpu.locked_addr, current_running_cpu_idx + 'A', cpu 3777 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); cpu 3796 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); cpu 3803 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, cpu 3813 src/dps8/dps8_cpu.c addr, cpu.locked_addr, current_running_cpu_idx + 'A', cpu 3814 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); cpu 3824 src/dps8/dps8_cpu.c cpu.rTRticks ++; cpu 3833 src/dps8/dps8_cpu.c PNL (cpu.portBusy = true;) cpu 3841 src/dps8/dps8_cpu.c if (cpu.tweaks.isolts_mode) { cpu 3842 src/dps8/dps8_cpu.c if (cpu.MR.sdpap) { cpu 3844 src/dps8/dps8_cpu.c cpu.MR.sdpap = 0; cpu 3846 src/dps8/dps8_cpu.c if (cpu.MR.separ) { cpu 3848 src/dps8/dps8_cpu.c cpu.MR.separ = 0; cpu 3855 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, cpu 3878 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, cpu 3892 src/dps8/dps8_cpu.c cpu.rTRticks ++; cpu 3933 src/dps8/dps8_cpu.c memset (& cpu.currentEISinstruction, 0, cpu 3934 src/dps8/dps8_cpu.c sizeof (cpu.currentEISinstruction)); cpu 3970 src/dps8/dps8_cpu.c else if (cpu.PPR.P) cpu 3985 src/dps8/dps8_cpu.c return ! (cpu.secret_addressing_mode || TST_I_NBAR); cpu 3990 src/dps8/dps8_cpu.c if (cpu.secret_addressing_mode) cpu 4028 src/dps8/dps8_cpu.c cpu.secret_addressing_mode = false; cpu 4035 src/dps8/dps8_cpu.c cpu.PPR.P = 1; cpu 4083 src/dps8/dps8_cpu.c if (cpu . BAR.BOUND == 0) cpu 4096 src/dps8/dps8_cpu.c if (addr >= (((word18) cpu . BAR.BOUND) << 9)) cpu 4100 src/dps8/dps8_cpu.c word18 barAddr = (addr + (((word18) cpu . BAR.BASE) << 9)) & 0777777; cpu 4110 src/dps8/dps8_cpu.c cpu.history [hset] [cpu.history_cyclic[hset]] [0] = w0; cpu 4111 src/dps8/dps8_cpu.c cpu.history [hset] [cpu.history_cyclic[hset]] [1] = w1; cpu 4112 src/dps8/dps8_cpu.c cpu.history_cyclic[hset] = (cpu.history_cyclic[hset] + 1) % N_MODEL_HIST_SIZE; cpu 4118 src/dps8/dps8_cpu.c cpu.history [hset] [cpu.history_cyclic[hset]] [0] = w0; cpu 4119 src/dps8/dps8_cpu.c cpu.history [hset] [cpu.history_cyclic[hset]] [1] = w1; cpu 4120 src/dps8/dps8_cpu.c cpu.history_cyclic[hset] = (cpu.history_cyclic[hset] + 1) % N_MODEL_HIST_SIZE; cpu 4125 src/dps8/dps8_cpu.c if (cpu.skip_cu_hist) cpu 4127 src/dps8/dps8_cpu.c if (! cpu.MR_cache.emr) cpu 4129 src/dps8/dps8_cpu.c if (! cpu.MR_cache.ihr) cpu 4131 src/dps8/dps8_cpu.c if (cpu.MR_cache.hrxfr && ! cpu.wasXfer) cpu 4140 src/dps8/dps8_cpu.c w1 |= (cpu.iefpFinalAddress & MASK24) << 12; cpu 4164 src/dps8/dps8_cpu.c add_history (cpu.tweaks.l68_mode ? L68_APU_HIST_REG : DPS8M_APU_HIST_REG, w0, w1); cpu 4218 src/dps8/dps8_cpu.c if (cpu.skip_cu_hist) cpu 4220 src/dps8/dps8_cpu.c if (! cpu.MR_cache.emr) cpu 4222 src/dps8/dps8_cpu.c if (! cpu.MR_cache.ihr) cpu 4235 src/dps8/dps8_cpu.c PNL (putbits36_8 (& w0, 0, cpu.prepare_state);) cpu 4237 src/dps8/dps8_cpu.c putbits36_1 (& w0, 8, cpu.wasXfer); cpu 4239 src/dps8/dps8_cpu.c putbits36_1 (& w0, 9, cpu.cu.xde); cpu 4241 src/dps8/dps8_cpu.c putbits36_1 (& w0, 10, cpu.cu.xdo); cpu 4245 src/dps8/dps8_cpu.c putbits36_1 (& w0, 12, cpu.cu.rpt); cpu 4248 src/dps8/dps8_cpu.c PNL (putbits36_1 (& w0, 14, cpu.AR_F_E);) cpu 4250 src/dps8/dps8_cpu.c putbits36_1 (& w0, 15, cpu.cycle != INTERRUPT_cycle?1:0); cpu 4252 src/dps8/dps8_cpu.c putbits36_1 (& w0, 16, cpu.cycle != FAULT_cycle?1:0); cpu 4254 src/dps8/dps8_cpu.c putbits36_1 (& w0, 17, TSTF (cpu.cu.IR, I_NBAR)?1:0); cpu 4259 src/dps8/dps8_cpu.c putbits36_18 (& w1, 0, cpu.TPR.CA); cpu 4262 src/dps8/dps8_cpu.c PNL (putbits36_1 (& w1, 59-36, (cpu.portSelect == 0)?1:0);) cpu 4263 src/dps8/dps8_cpu.c PNL (putbits36_1 (& w1, 60-36, (cpu.portSelect == 1)?1:0);) cpu 4264 src/dps8/dps8_cpu.c PNL (putbits36_1 (& w1, 61-36, (cpu.portSelect == 2)?1:0);) cpu 4265 src/dps8/dps8_cpu.c PNL (putbits36_1 (& w1, 62-36, (cpu.portSelect == 3)?1:0);) cpu 4267 src/dps8/dps8_cpu.c putbits36_1 (& w1, 63-36, cpu.interrupt_flag?1:0); cpu 4269 src/dps8/dps8_cpu.c PNL (putbits36_1 (& w1, 64-36, cpu.INS_FETCH?1:0);) cpu 4282 src/dps8/dps8_cpu.c if (cpu.MR.hrhlt && cpu.history_cyclic[CU_HIST_REG] == 0) cpu 4285 src/dps8/dps8_cpu.c if (cpu.MR.ihrrs) cpu 4287 src/dps8/dps8_cpu.c cpu.MR.ihr = 0; cpu 4335 src/dps8/dps8_cpu.c PNL (add_history (L68_DU_HIST_REG, cpu.du.cycle1, cpu.du.cycle2);) cpu 4345 src/dps8/dps8_cpu.c PNL (putbits36_9 (& w0, 0, cpu.ou.RS);) cpu 4348 src/dps8/dps8_cpu.c putbits36_1 (& w0, 9, cpu.ou.characterOperandSize ? 1 : 0); cpu 4351 src/dps8/dps8_cpu.c putbits36_3 (& w0, 10, cpu.ou.characterOperandOffset); cpu 4354 src/dps8/dps8_cpu.c putbits36_1 (& w0, 13, cpu.ou.crflag); cpu 4357 src/dps8/dps8_cpu.c putbits36_1 (& w0, 14, cpu.ou.directOperandFlag ? 1 : 0); cpu 4360 src/dps8/dps8_cpu.c putbits36_2 (& w0, 15, cpu.ou.eac); cpu 4364 src/dps8/dps8_cpu.c PNL (putbits36_9 (& w0, 18, cpu.ou.RS);) cpu 4367 src/dps8/dps8_cpu.c putbits36_1 (& w0, 27, cpu.ou.RB1_FULL); cpu 4370 src/dps8/dps8_cpu.c putbits36_1 (& w0, 28, cpu.ou.RP_FULL); cpu 4373 src/dps8/dps8_cpu.c putbits36_1 (& w0, 29, cpu.ou.RS_FULL); cpu 4376 src/dps8/dps8_cpu.c putbits36_6 (& w0, 30, (word6) (cpu.ou.cycle >> 3)); cpu 4379 src/dps8/dps8_cpu.c putbits36_3 (& w1, 36-36, (word3) cpu.ou.cycle); cpu 4382 src/dps8/dps8_cpu.c putbits36_1 (& w1, 39-36, cpu.ou.STR_OP); cpu 4388 src/dps8/dps8_cpu.c (word10) ~opcodes10 [cpu.ou.RS].reg_use);) cpu 4393 src/dps8/dps8_cpu.c putbits36_18 (& w1, 54 - 36, cpu.PPR.IC); cpu 4455 src/dps8/dps8_cpu.c putbits36_15 (& w0, 0, cpu.TPR.TSR); cpu 4457 src/dps8/dps8_cpu.c PNL (putbits36_1 (& w0, 15, (cpu.apu.state & apu_ESN_SNR) ? 1 : 0);) cpu 4458 src/dps8/dps8_cpu.c PNL (putbits36_1 (& w0, 16, (cpu.apu.state & apu_ESN_TSR) ? 1 : 0);) cpu 4460 src/dps8/dps8_cpu.c putbits36_1 (& w0, 25, cpu.cu.SDWAMM); cpu 4462 src/dps8/dps8_cpu.c putbits36_4 (& w0, 26, (word4) cpu.SDWAMR); cpu 4464 src/dps8/dps8_cpu.c putbits36_1 (& w0, 30, cpu.cu.PTWAMM); cpu 4466 src/dps8/dps8_cpu.c putbits36_4 (& w0, 31, (word4) cpu.PTWAMR); cpu 4468 src/dps8/dps8_cpu.c PNL (putbits36_1 (& w0, 35, (cpu.apu.state & apu_FLT) ? 1 : 0);) cpu 4471 src/dps8/dps8_cpu.c PNL (putbits36_24 (& w1, 0, cpu.APUMemAddr);) cpu 4473 src/dps8/dps8_cpu.c putbits36_3 (& w1, 24, cpu.TPR.TRR); cpu 4476 src/dps8/dps8_cpu.c putbits36_1 (& w1, 34, cpu.SDW0.C); cpu 581 src/dps8/dps8_cpu.h # define TA1 cpu.du.TAk[0] cpu 582 src/dps8/dps8_cpu.h # define TA2 cpu.du.TAk[1] cpu 583 src/dps8/dps8_cpu.h # define TA3 cpu.du.TAk[2] cpu 1036 src/dps8/dps8_cpu.h #define USE_IRODD (cpu.cu.rd && ((cpu. PPR.IC & 1) != 0)) cpu 1037 src/dps8/dps8_cpu.h #define IWB_IRODD (USE_IRODD ? cpu.cu.IRODD : cpu.cu.IWB) cpu 1194 src/dps8/dps8_cpu.h #define DU_CYCLE_GDLDA { clrmask (& cpu.du.cycle2, du2_nGDLDA); \ cpu 1195 src/dps8/dps8_cpu.h setmask (& cpu.du.cycle2, du2_nGDLDB | du2_nGDLDC); } cpu 1196 src/dps8/dps8_cpu.h #define DU_CYCLE_GDLDB { clrmask (& cpu.du.cycle2, du2_nGDLDB); \ cpu 1197 src/dps8/dps8_cpu.h setmask (& cpu.du.cycle2, du2_nGDLDA | du2_nGDLDC); } cpu 1198 src/dps8/dps8_cpu.h #define DU_CYCLE_GDLDC { clrmask (& cpu.du.cycle2, du2_nGDLDC); \ cpu 1199 src/dps8/dps8_cpu.h setmask (& cpu.du.cycle2, du2_nGDLDA | du2_nGDLDB); } cpu 1200 src/dps8/dps8_cpu.h #define DU_CYCLE_FA_I1 setmask (& cpu.du.cycle1, du1_FA_I1) cpu 1201 src/dps8/dps8_cpu.h #define DU_CYCLE_FA_I2 setmask (& cpu.du.cycle1, du1_FA_I2) cpu 1202 src/dps8/dps8_cpu.h #define DU_CYCLE_FA_I3 setmask (& cpu.du.cycle1, du1_FA_I3) cpu 1203 src/dps8/dps8_cpu.h #define DU_CYCLE_ANLD1 setmask (& cpu.du.cycle2, du2_ANLD1) cpu 1204 src/dps8/dps8_cpu.h #define DU_CYCLE_ANLD2 setmask (& cpu.du.cycle2, du2_ANLD2) cpu 1205 src/dps8/dps8_cpu.h #define DU_CYCLE_NLD1 setmask (& cpu.du.cycle2, du2_NLD1) cpu 1206 src/dps8/dps8_cpu.h #define DU_CYCLE_NLD2 setmask (& cpu.du.cycle2, du2_NLD2) cpu 1207 src/dps8/dps8_cpu.h #define DU_CYCLE_FRND setmask (& cpu.du.cycle2, du2_FRND) cpu 1208 src/dps8/dps8_cpu.h #define DU_CYCLE_DGBD setmask (& cpu.du.cycle2, du2_DGBD) cpu 1209 src/dps8/dps8_cpu.h #define DU_CYCLE_DGDB setmask (& cpu.du.cycle2, du2_DGDB) cpu 1210 src/dps8/dps8_cpu.h #define DU_CYCLE_DDU_LDEA clrmask (& cpu.du.cycle1, du1_nDDU_LDEA) cpu 1211 src/dps8/dps8_cpu.h #define DU_CYCLE_DDU_STEA clrmask (& cpu.du.cycle1, du1_nDDU_STEA) cpu 1212 src/dps8/dps8_cpu.h #define DU_CYCLE_END clrmask (& cpu.du.cycle1, du1_nEND) cpu 1213 src/dps8/dps8_cpu.h #define DU_CYCLE_LDWRT1 setmask (& cpu.du.cycle2, du2_LDWRT1) cpu 1214 src/dps8/dps8_cpu.h #define DU_CYCLE_LDWRT2 setmask (& cpu.du.cycle2, du2_LDWRT2) cpu 1215 src/dps8/dps8_cpu.h #define DU_CYCLE_FEXOP setmask (& cpu.du.cycle2, du2_FEXOP) cpu 1216 src/dps8/dps8_cpu.h #define DU_CYCLE_ANSTR setmask (& cpu.du.cycle2, du2_ANSTR) cpu 1217 src/dps8/dps8_cpu.h #define DU_CYCLE_GSTR setmask (& cpu.du.cycle2, du2_GSTR) cpu 1218 src/dps8/dps8_cpu.h #define DU_CYCLE_FLEN_128 clrmask (& cpu.du.cycle2, du2_nFLEN_128) cpu 1219 src/dps8/dps8_cpu.h #define DU_CYCLE_FDUD { cpu.du.cycle1 = \ cpu 1242 src/dps8/dps8_cpu.h cpu.du.cycle2 = \ cpu 1251 src/dps8/dps8_cpu.h #define DU_CYCLE_nDUD clrmask (& cpu.du.cycle2, du2_DUD) cpu 1256 src/dps8/dps8_cpu.h # define CPT(R,C) cpu.cpt[R][C]=1 cpu 1257 src/dps8/dps8_cpu.h # define CPTUR(C) cpu.cpt[cpt5L][C]=1 cpu 1524 src/dps8/dps8_cpu.h #define N_MODEL_WAM_ENTRIES (cpu.tweaks.l68_mode ? N_L68_WAM_ENTRIES : N_DPS8M_WAM_ENTRIES) cpu 1776 src/dps8/dps8_cpu.h if (cpu.tweaks.useMap) \ cpu 1780 src/dps8/dps8_cpu.h int base = cpu.sc_addr_map[pgnum]; \ cpu 1791 src/dps8/dps8_cpu.h if (cpu.tweaks.useMap) \ cpu 1795 src/dps8/dps8_cpu.h int base = cpu.sc_addr_map[pgnum]; \ cpu 1956 src/dps8/dps8_cpu.h #define GET_PR_BITNO(n) (cpu.PAR[n].PR_BITNO) cpu 1957 src/dps8/dps8_cpu.h #define GET_AR_BITNO(n) (cpu.PAR[n].AR_BITNO) cpu 1958 src/dps8/dps8_cpu.h #define GET_AR_CHAR(n) (cpu.PAR[n].AR_CHAR) cpu 1961 src/dps8/dps8_cpu.h cpu.PAR[n].PR_BITNO = b; cpu 1962 src/dps8/dps8_cpu.h cpu.PAR[n].AR_BITNO = (b % 9) & MASK4; cpu 1963 src/dps8/dps8_cpu.h cpu.PAR[n].AR_CHAR = (b / 9) & MASK2; cpu 1967 src/dps8/dps8_cpu.h cpu.PAR[n].PR_BITNO = c * 9 + b; cpu 1968 src/dps8/dps8_cpu.h cpu.PAR[n].AR_BITNO = b & MASK4; cpu 1969 src/dps8/dps8_cpu.h cpu.PAR[n].AR_CHAR = c & MASK2; cpu 1985 src/dps8/dps8_cpu.h cpu.portSelect = port; cpu 1986 src/dps8/dps8_cpu.h cpu.portAddr [port] = a; cpu 1987 src/dps8/dps8_cpu.h cpu.portData [port] = d; cpu 1988 src/dps8/dps8_cpu.h cpu.portBusy = false; cpu 2001 src/dps8/dps8_cpu.h PNL (cpu.portBusy = true;) cpu 2005 src/dps8/dps8_cpu.h cpu.rTRticks ++; cpu 2014 src/dps8/dps8_cpu.h PNL (cpu.portBusy = true;) cpu 2016 src/dps8/dps8_cpu.h if (cpu.tweaks.isolts_mode) cpu 2018 src/dps8/dps8_cpu.h if (cpu.MR.sdpap) cpu 2021 src/dps8/dps8_cpu.h cpu.MR.sdpap = 0; cpu 2023 src/dps8/dps8_cpu.h if (cpu.MR.separ) cpu 2026 src/dps8/dps8_cpu.h cpu.MR.separ = 0; cpu 2031 src/dps8/dps8_cpu.h cpu.rTRticks ++; cpu 2040 src/dps8/dps8_cpu.h PNL (cpu.portBusy = true;) cpu 2042 src/dps8/dps8_cpu.h if (cpu.tweaks.isolts_mode) cpu 2044 src/dps8/dps8_cpu.h if (cpu.MR.sdpap) cpu 2047 src/dps8/dps8_cpu.h cpu.MR.sdpap = 0; cpu 2049 src/dps8/dps8_cpu.h if (cpu.MR.separ) cpu 2052 src/dps8/dps8_cpu.h cpu.MR.separ = 0; cpu 2055 src/dps8/dps8_cpu.h M[addr] = (M[addr] & ~cpu.zone) | (data & cpu.zone); cpu 2056 src/dps8/dps8_cpu.h cpu.useZone = false; // Safety cpu 2058 src/dps8/dps8_cpu.h cpu.rTRticks ++; cpu 2067 src/dps8/dps8_cpu.h PNL (cpu.portBusy = true;) cpu 2072 src/dps8/dps8_cpu.h cpu.rTRticks ++; cpu 2081 src/dps8/dps8_cpu.h PNL (cpu.portBusy = true;) cpu 2083 src/dps8/dps8_cpu.h if (cpu.tweaks.isolts_mode) cpu 2085 src/dps8/dps8_cpu.h if (cpu.MR.sdpap) cpu 2088 src/dps8/dps8_cpu.h cpu.MR.sdpap = 0; cpu 2090 src/dps8/dps8_cpu.h if (cpu.MR.separ) cpu 2093 src/dps8/dps8_cpu.h cpu.MR.separ = 0; cpu 2100 src/dps8/dps8_cpu.h cpu.rTRticks ++; cpu 2189 src/dps8/dps8_cpu.h cpu.lockYield++; \ cpu 2218 src/dps8/dps8_cpu.h cpu.locked_addr, addr); \ cpu 2220 src/dps8/dps8_cpu.h cpu.lockCnt++; \ cpu 2222 src/dps8/dps8_cpu.h cpu.lockImmediate++; \ cpu 2223 src/dps8/dps8_cpu.h cpu.lockWait += (DEADLOCK_DETECT-i); \ cpu 2224 src/dps8/dps8_cpu.h cpu.lockWaitMax = ((DEADLOCK_DETECT-i) > cpu.lockWaitMax) ? \ cpu 2225 src/dps8/dps8_cpu.h (DEADLOCK_DETECT-i) : cpu.lockWaitMax; \ cpu 2261 src/dps8/dps8_cpu.h __func__, cpu.locked_addr, addr); \ cpu 2263 src/dps8/dps8_cpu.h cpu.lockCnt++; \ cpu 2265 src/dps8/dps8_cpu.h cpu.lockImmediate++; \ cpu 2266 src/dps8/dps8_cpu.h cpu.lockWait += (DEADLOCK_DETECT-i); \ cpu 2267 src/dps8/dps8_cpu.h cpu.lockWaitMax = ((DEADLOCK_DETECT-i) > \ cpu 2268 src/dps8/dps8_cpu.h cpu.lockWaitMax) ? (DEADLOCK_DETECT-i) : \ cpu 2269 src/dps8/dps8_cpu.h cpu.lockWaitMax; \ cpu 2311 src/dps8/dps8_cpu.h cpu.locked_addr, addr); \ cpu 2313 src/dps8/dps8_cpu.h cpu.lockCnt++; \ cpu 2315 src/dps8/dps8_cpu.h cpu.lockImmediate++; \ cpu 2316 src/dps8/dps8_cpu.h cpu.lockWait += (DEADLOCK_DETECT-i); \ cpu 2317 src/dps8/dps8_cpu.h cpu.lockWaitMax = ((DEADLOCK_DETECT-i) > cpu.lockWaitMax) ? \ cpu 2318 src/dps8/dps8_cpu.h (DEADLOCK_DETECT-i) : cpu.lockWaitMax; \ cpu 71 src/dps8/dps8_eis.c #define DBG_CTR cpu.cycleCnt cpu 333 src/dps8/dps8_eis.c return cpu.rX [X (reg)]; cpu 344 src/dps8/dps8_eis.c return GETHI (cpu.rA); cpu 350 src/dps8/dps8_eis.c return GETHI (cpu.rQ); cpu 353 src/dps8/dps8_eis.c return cpu.PPR.IC; cpu 359 src/dps8/dps8_eis.c return cpu.rA; // See AL36, Table 4-1 cpu 365 src/dps8/dps8_eis.c return cpu.rQ; // See AL36, Table 4-1 cpu 407 src/dps8/dps8_eis.c return GETHI (cpu.rA); cpu 413 src/dps8/dps8_eis.c return GETHI (cpu.rQ); cpu 423 src/dps8/dps8_eis.c cpu 424 src/dps8/dps8_eis.c cpu 450 src/dps8/dps8_eis.c return cpu.PPR.IC; cpu 456 src/dps8/dps8_eis.c return GETLO (cpu.rA); cpu 462 src/dps8/dps8_eis.c return GETLO (cpu.rQ); cpu 477 src/dps8/dps8_eis.c return cpu.rX [n - 8]; cpu 499 src/dps8/dps8_eis.c return GETHI (cpu.rA); cpu 505 src/dps8/dps8_eis.c return GETHI (cpu.rQ); cpu 525 src/dps8/dps8_eis.c return cpu.PPR.IC; cpu 531 src/dps8/dps8_eis.c return cpu.rA; cpu 537 src/dps8/dps8_eis.c return cpu.rQ; cpu 552 src/dps8/dps8_eis.c return cpu.rX [n - 8]; cpu 558 src/dps8/dps8_eis.c #define EISADDR_IDX(p) ((p) - cpu.currentEISinstruction.addr) cpu 563 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; cpu 569 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; cpu 570 src/dps8/dps8_eis.c cpu.TPR.TSR = p -> SNR; cpu 571 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cpu 583 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu 595 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 596 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 597 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cpu 607 src/dps8/dps8_eis.c __func__, p -> cachedParagraph [i], cpu.TPR.TSR, p -> cachedAddr + i); cpu 611 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu 621 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; cpu 627 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; cpu 646 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; cpu 647 src/dps8/dps8_eis.c cpu.TPR.TSR = p -> SNR; cpu 648 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cpu 650 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu 665 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 666 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 667 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cpu 671 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu 678 src/dps8/dps8_eis.c __func__, p -> cachedParagraph [i], cpu.TPR.TSR, paragraphAddress + i); cpu 686 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; cpu 694 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteIdx addr %06o n %u\n", cpu.du.Dk_PTR_W[eisaddr_idx], n); cpu 695 src/dps8/dps8_eis.c word18 addressN = (cpu.du.Dk_PTR_W[eisaddr_idx] + n) & AMASK; cpu 733 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadIdx addr %06o n %u\n", cpu.du.Dk_PTR_W[eisaddr_idx], n); cpu 734 src/dps8/dps8_eis.c word18 addressN = (cpu.du.Dk_PTR_W[eisaddr_idx] + n) & AMASK; cpu 763 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISRead addr %06o\n", cpu.du.Dk_PTR_W[eisaddr_idx]); cpu 776 src/dps8/dps8_eis.c cpu 792 src/dps8/dps8_eis.c word18 addressN = (cpu.du.Dk_PTR_W[eisaddr_idx] + n) & AMASK; cpu 805 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; cpu 809 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; cpu 810 src/dps8/dps8_eis.c cpu.TPR.TSR = p -> SNR; cpu 811 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cpu 820 src/dps8/dps8_eis.c __func__, data [i], cpu.TPR.TSR, addressN + i); cpu 832 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 833 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 834 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cpu 843 src/dps8/dps8_eis.c __func__, data [i], cpu.TPR.TSR, addressN + i); cpu 846 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; cpu 854 src/dps8/dps8_eis.c word18 addressN = (cpu.du.Dk_PTR_W[eisaddr_idx] + n) & AMASK; cpu 867 src/dps8/dps8_eis.c word3 saveTRR = cpu.TPR.TRR; cpu 871 src/dps8/dps8_eis.c cpu.TPR.TRR = p -> RNR; cpu 872 src/dps8/dps8_eis.c cpu.TPR.TSR = p -> SNR; cpu 873 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cpu 882 src/dps8/dps8_eis.c __func__, data [i], cpu.TPR.TSR, addressN + i); cpu 894 src/dps8/dps8_eis.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 895 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 896 src/dps8/dps8_eis.c cpu.cu.XSF = 0; cpu 905 src/dps8/dps8_eis.c __func__, data [i], cpu.TPR.TSR, addressN + i); cpu 908 src/dps8/dps8_eis.c cpu.TPR.TRR = saveTRR; cpu 913 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 917 src/dps8/dps8_eis.c switch (cpu.du.TAk[k-1]) cpu 937 src/dps8/dps8_eis.c PNL (cpu.du.Dk_PTR_W[k-1] = address); cpu 939 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[k-1] = address; cpu 947 src/dps8/dps8_eis.c switch (cpu.du.TAk[k-1]) cpu 965 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISGet469 : k: %u TAk %u coffset %u c %o \n", k, cpu.du.TAk[k - 1], residue, c); cpu 975 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 979 src/dps8/dps8_eis.c switch (cpu.du.TAk[k-1]) cpu 999 src/dps8/dps8_eis.c PNL (cpu.du.Dk_PTR_W[k-1] = address); cpu 1001 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[k-1] = address; cpu 1009 src/dps8/dps8_eis.c switch (cpu.du.TAk[k-1]) cpu 1045 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[eisaddr_idx] = (cpu.du.Dk_PTR_W[eisaddr_idx] + 1) & AMASK; cpu 1080 src/dps8/dps8_eis.c baseBitPosn += (int) cpu.du.CHTALLY; cpu 1086 src/dps8/dps8_eis.c word18 saveAddr = cpu.du.Dk_PTR_W[eisaddr_idx]; cpu 1087 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[eisaddr_idx] += (uint) woff; cpu 1088 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[eisaddr_idx] &= AMASK; cpu 1110 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[eisaddr_idx] = saveAddr; cpu 1119 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 1159 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 1165 src/dps8/dps8_eis.c e -> MF1 = getbits36_7 (cpu.cu.IWB, 29); cpu 1170 src/dps8/dps8_eis.c e -> MF2 = getbits36_7 (cpu.cu.IWB, 11); cpu 1175 src/dps8/dps8_eis.c e -> MF3 = getbits36_7 (cpu.cu.IWB, 2); cpu 1206 src/dps8/dps8_eis.c cpu 1207 src/dps8/dps8_eis.c cpu 1230 src/dps8/dps8_eis.c PNL (cpu.du.Dk_PTR_W[k-1] = address); cpu 1232 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[k-1] = address; cpu 1264 src/dps8/dps8_eis.c address = (cpu.AR [n].WORDNO + SIGNEXT15_18 (offset)) & AMASK; cpu 1266 src/dps8/dps8_eis.c PNL (cpu.du.Dk_PTR_W[k-1] = address); cpu 1268 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[k-1] = address; cpu 1272 src/dps8/dps8_eis.c cpu.cu.TSN_PRNO[k-1] = n; cpu 1273 src/dps8/dps8_eis.c cpu.cu.TSN_VALID[k-1] = 1; cpu 1274 src/dps8/dps8_eis.c e -> addr [k - 1].SNR = cpu.PR [n].SNR; cpu 1275 src/dps8/dps8_eis.c e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu 1276 src/dps8/dps8_eis.c cpu.TPR.TRR, cpu 1277 src/dps8/dps8_eis.c cpu.PPR.PRR); cpu 1298 src/dps8/dps8_eis.c PNL (cpu.du.Dk_PTR_W[k-1] = address); cpu 1301 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[k-1] = address; cpu 1319 src/dps8/dps8_eis.c PNL (cpu.du.POP = 0); cpu 1320 src/dps8/dps8_eis.c PNL (cpu.du.POL = 0); cpu 1325 src/dps8/dps8_eis.c if (i < cpu.currentInstruction.info -> ndes) cpu 1335 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 1345 src/dps8/dps8_eis.c PNL (cpu.du.POP = 1); cpu 1356 src/dps8/dps8_eis.c cpu.du.TAk[k-1] = cpu.du.TAk[useTA-1]; cpu 1358 src/dps8/dps8_eis.c cpu.du.TAk[k-1] = getbits36_2 (opDesc, 21); // type alphanumeric cpu 1372 src/dps8/dps8_eis.c cpu.dataMode = 0102; // 9 bit an cpu 1373 src/dps8/dps8_eis.c cpu.ou.opsz = is_9 >> 12; cpu 1376 src/dps8/dps8_eis.c cpu.dataMode = 0042; // 6 bit an cpu 1377 src/dps8/dps8_eis.c cpu.ou.opsz = is_6 >> 12; cpu 1380 src/dps8/dps8_eis.c cpu.dataMode = 0022; // 4 bit an cpu 1381 src/dps8/dps8_eis.c cpu.ou.opsz = is_4 >> 12; cpu 1417 src/dps8/dps8_eis.c address = (cpu.AR [n].WORDNO + offset) & AMASK; cpu 1422 src/dps8/dps8_eis.c cpu.cu.TSN_PRNO[k-1] = n; cpu 1423 src/dps8/dps8_eis.c cpu.cu.TSN_VALID[k-1] = 1; cpu 1424 src/dps8/dps8_eis.c e -> addr [k - 1].SNR = cpu.PR [n].SNR; cpu 1425 src/dps8/dps8_eis.c e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); cpu 1431 src/dps8/dps8_eis.c PNL (cpu.du.POL = 1); cpu 1443 src/dps8/dps8_eis.c switch (cpu.du.TAk[k-1]) cpu 1489 src/dps8/dps8_eis.c switch (cpu.du.TAk[k-1]) cpu 1576 src/dps8/dps8_eis.c PNL (cpu.du.Dk_PTR_W[k-1] = effWORDNO); cpu 1578 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[k-1] = effWORDNO; cpu 1600 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 1612 src/dps8/dps8_eis.c PNL (cpu.du.POP = 1); cpu 1622 src/dps8/dps8_eis.c y = (cpu.AR [n].WORDNO + SIGNEXT15_18 (offset)) & AMASK; cpu 1627 src/dps8/dps8_eis.c cpu.cu.TSN_PRNO[k-1] = n; cpu 1628 src/dps8/dps8_eis.c cpu.cu.TSN_VALID[k-1] = 1; cpu 1629 src/dps8/dps8_eis.c e -> addr [k - 1].SNR = cpu.PR[n].SNR; cpu 1630 src/dps8/dps8_eis.c e -> addr [k - 1].RNR = max3 (cpu.PR [n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); cpu 1637 src/dps8/dps8_eis.c PNL (cpu.du.Dk_PTR_W[k-1] = y); cpu 1640 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[k-1] = y; cpu 1655 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 1658 src/dps8/dps8_eis.c PNL (cpu.du.POP = 1); cpu 1674 src/dps8/dps8_eis.c address = (cpu.AR[n].WORDNO + SIGNEXT15_18(offset)) & AMASK; cpu 1679 src/dps8/dps8_eis.c cpu.cu.TSN_PRNO[k-1] = n; cpu 1680 src/dps8/dps8_eis.c cpu.cu.TSN_VALID[k-1] = 1; cpu 1681 src/dps8/dps8_eis.c e->addr[k-1].SNR = cpu.PR[n].SNR; cpu 1682 src/dps8/dps8_eis.c e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); cpu 1687 src/dps8/dps8_eis.c PNL (cpu.du.POL = 1); cpu 1696 src/dps8/dps8_eis.c cpu.dataMode = 0021; // 4 bit numeric cpu 1698 src/dps8/dps8_eis.c cpu.dataMode = 0101; // 9 bit numeric cpu 1796 src/dps8/dps8_eis.c sim_printf ("parseNumericOperandDescriptor(ta=%d) How'd we get here 2?\n", cpu.du.TAk[k-1]); cpu 1804 src/dps8/dps8_eis.c PNL (cpu.du.Dk_PTR_W[k-1] = effWORDNO); cpu 1806 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[k-1] = effWORDNO; cpu 1817 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(): address:%06o cPos:%d bPos:%d N%u %u\n", cpu.du.Dk_PTR_W[k-1], a->cPos, a->bPos, k, e->N[k-1]); cpu 1833 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 1839 src/dps8/dps8_eis.c cpu.dataMode = 0010; // 1 bit not alpha, not alpha numeric cpu 1844 src/dps8/dps8_eis.c PNL (cpu.du.POP = 1); cpu 1855 src/dps8/dps8_eis.c address = (cpu.AR[n].WORDNO + SIGNEXT15_18(offset)) & AMASK; cpu 1861 src/dps8/dps8_eis.c cpu.cu.TSN_PRNO[k-1] = n; cpu 1862 src/dps8/dps8_eis.c cpu.cu.TSN_VALID[k-1] = 1; cpu 1863 src/dps8/dps8_eis.c e->addr[k-1].SNR = cpu.PR[n].SNR; cpu 1864 src/dps8/dps8_eis.c e->addr[k-1].RNR = max3(cpu.PR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); cpu 1867 src/dps8/dps8_eis.c PNL (cpu.du.POL = 1); cpu 1915 src/dps8/dps8_eis.c PNL (cpu.du.Dk_PTR_W[k-1] = effWORDNO); cpu 1917 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[k-1] = effWORDNO; cpu 1927 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 1959 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cpu 1961 src/dps8/dps8_eis.c int32_t address = SIGNEXT15_32 (GET_OFFSET (cpu.cu.IWB)); cpu 1965 src/dps8/dps8_eis.c word4 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except cpu 1974 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cpu 1983 src/dps8/dps8_eis.c augend = cpu.AR[ARn].WORDNO * 8u + GET_AR_CHAR (ARn) * 2u; cpu 2009 src/dps8/dps8_eis.c cpu.AR[ARn].WORDNO = (word18) (sum / 8) & AMASK; cpu 2041 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cpu 2043 src/dps8/dps8_eis.c int32_t address = SIGNEXT15_32 (GET_OFFSET (cpu.cu.IWB)); cpu 2044 src/dps8/dps8_eis.c word4 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except cpu 2051 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cpu 2054 src/dps8/dps8_eis.c minuend = cpu.AR [ARn].WORDNO * 32 + cntFromBit [GET_AR_CHAR (ARn) * 9 + GET_AR_BITNO (ARn)]; cpu 2066 src/dps8/dps8_eis.c cpu.AR [ARn].WORDNO = (word18) (difference / 32) & AMASK; cpu 2088 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cpu 2090 src/dps8/dps8_eis.c int32_t address = SIGNEXT15_32 (GET_OFFSET (cpu.cu.IWB)); cpu 2091 src/dps8/dps8_eis.c word6 reg = GET_TD (cpu.cu.IWB); // 4-bit register modification (None except cpu 2111 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cpu 2113 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn)); cpu 2114 src/dps8/dps8_eis.c augend = cpu.AR[ARn].WORDNO * 36u + GET_AR_CHAR (ARn) * 9u + GET_AR_BITNO (ARn); cpu 2119 src/dps8/dps8_eis.c if (sz == 9 || GET_A (cpu.cu.IWB)) cpu 2143 src/dps8/dps8_eis.c cpu.AR [ARn].WORDNO = (word18) (sum / 36) & AMASK; cpu 2157 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cpu 2160 src/dps8/dps8_eis.c word18 address = SIGNEXT15_18 (GET_OFFSET (cpu.cu.IWB)); cpu 2163 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); cpu 2176 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cpu 2184 src/dps8/dps8_eis.c cpu.AR[ARn].WORDNO = (cpu.AR[ARn].WORDNO + address + cpu 2198 src/dps8/dps8_eis.c cpu.AR[ARn].WORDNO = (address + r / 36) & MASK18; cpu 2216 src/dps8/dps8_eis.c cpu 2218 src/dps8/dps8_eis.c cpu 2225 src/dps8/dps8_eis.c cpu 2245 src/dps8/dps8_eis.c cpu 2249 src/dps8/dps8_eis.c cpu 2250 src/dps8/dps8_eis.c cpu 2255 src/dps8/dps8_eis.c cpu 2258 src/dps8/dps8_eis.c cpu 2266 src/dps8/dps8_eis.c cpu 2300 src/dps8/dps8_eis.c cpu 2310 src/dps8/dps8_eis.c cpu 2334 src/dps8/dps8_eis.c cpu 2353 src/dps8/dps8_eis.c cpu 2359 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cpu 2361 src/dps8/dps8_eis.c int32_t address = SIGNEXT15_32 (GET_OFFSET (cpu.cu.IWB)); cpu 2364 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); cpu 2374 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cpu 2376 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "awd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn)); cpu 2379 src/dps8/dps8_eis.c augend = cpu.AR [ARn].WORDNO; cpu 2389 src/dps8/dps8_eis.c cpu.AR[ARn].WORDNO = (word18) sum & AMASK; cpu 2398 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cpu 2400 src/dps8/dps8_eis.c word18 address = SIGNEXT15_18 (GET_OFFSET (cpu.cu.IWB)); cpu 2401 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); cpu 2407 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cpu 2410 src/dps8/dps8_eis.c cpu.AR[ARn].WORDNO = (cpu.AR[ARn].WORDNO - cpu 2420 src/dps8/dps8_eis.c cpu.AR[ARn].WORDNO = (- (address + r / 36)) & MASK18; cpu 2434 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cpu 2436 src/dps8/dps8_eis.c int32_t address = SIGNEXT15_32 (GET_OFFSET (cpu.cu.IWB)); cpu 2439 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); cpu 2448 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cpu 2450 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn)); cpu 2453 src/dps8/dps8_eis.c minued = cpu.AR [ARn].WORDNO; cpu 2463 src/dps8/dps8_eis.c cpu.AR [ARn].WORDNO = (word18) difference & AMASK; cpu 2472 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cpu 2474 src/dps8/dps8_eis.c word18 address = SIGNEXT15_18 (GET_OFFSET (cpu.cu.IWB)); cpu 2477 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); cpu 2486 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cpu 2491 src/dps8/dps8_eis.c cpu.AR[ARn].WORDNO = (cpu.AR[ARn].WORDNO - cpu 2503 src/dps8/dps8_eis.c cpu.AR[ARn].WORDNO = (- (address + (r + 3) / 4)) & MASK18; cpu 2756 src/dps8/dps8_eis.c uint ARn = GET_ARN (cpu.cu.IWB); cpu 2757 src/dps8/dps8_eis.c uint address = SIGNEXT15_18 (GET_OFFSET (cpu.cu.IWB)); cpu 2758 src/dps8/dps8_eis.c word4 reg = (word4) GET_TD (cpu.cu.IWB); // 4-bit register modification (None except cpu 2792 src/dps8/dps8_eis.c if (GET_A (cpu.cu.IWB)) cpu 2797 src/dps8/dps8_eis.c augend = cpu.AR[ARn].WORDNO * 36u; cpu 2816 src/dps8/dps8_eis.c augend = cpu.AR[ARn].WORDNO * 36u + map [charno * 16 + bitno]; cpu 2876 src/dps8/dps8_eis.c cpu.AR [ARn].WORDNO = (word18) (sum / 36u) & AMASK; cpu 2953 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 3028 src/dps8/dps8_eis.c word9 fill = getbits36_9 (cpu.cu.IWB, 0); cpu 3036 src/dps8/dps8_eis.c for (; cpu.du.CHTALLY < min (e->N1, e->N2); cpu.du.CHTALLY ++) cpu 3038 src/dps8/dps8_eis.c word9 c1 = EISget469 (1, cpu.du.CHTALLY); // get Y-char1n cpu 3039 src/dps8/dps8_eis.c word9 c2 = EISget469 (2, cpu.du.CHTALLY); // get Y-char2n cpu 3040 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpc tally %d c1 %03o c2 %03o\n", cpu.du.CHTALLY, c1, c2); cpu 3053 src/dps8/dps8_eis.c for( ; cpu.du.CHTALLY < e->N2; cpu.du.CHTALLY ++) cpu 3056 src/dps8/dps8_eis.c word9 c2 = EISget469 (2, cpu.du.CHTALLY); // get Y-char2n cpu 3070 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < e->N1; cpu.du.CHTALLY ++) cpu 3072 src/dps8/dps8_eis.c word9 c1 = EISget469 (1, cpu.du.CHTALLY); // get Y-char1n cpu 3096 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 3185 src/dps8/dps8_eis.c c1 = (cpu.du.D2_PTR_W >> 13) & 017; cpu 3186 src/dps8/dps8_eis.c c2 = (cpu.du.D2_PTR_W >> 9) & 017; cpu 3195 src/dps8/dps8_eis.c c1 = (cpu.du.D2_PTR_W >> 12) & 077; cpu 3196 src/dps8/dps8_eis.c c2 = (cpu.du.D2_PTR_W >> 6) & 077; cpu 3205 src/dps8/dps8_eis.c c1 = (cpu.du.D2_PTR_W >> 9) & 0777; cpu 3206 src/dps8/dps8_eis.c c2 = (cpu.du.D2_PTR_W ) & 0777; cpu 3250 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < limit; cpu.du.CHTALLY ++) cpu 3252 src/dps8/dps8_eis.c yCharn11 = EISget469 (1, cpu.du.CHTALLY); cpu 3253 src/dps8/dps8_eis.c yCharn12 = EISget469 (1, cpu.du.CHTALLY + 1); cpu 3257 src/dps8/dps8_eis.c SC_I_TALLY (cpu.du.CHTALLY == limit); cpu 3265 src/dps8/dps8_eis.c word36 CY3 = setbits36_24 (0, 12, cpu.du.CHTALLY); cpu 3279 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 3368 src/dps8/dps8_eis.c c1 = (cpu.du.D2_PTR_W >> 13) & 017; cpu 3369 src/dps8/dps8_eis.c c2 = (cpu.du.D2_PTR_W >> 9) & 017; cpu 3378 src/dps8/dps8_eis.c c1 = (cpu.du.D2_PTR_W >> 12) & 077; cpu 3379 src/dps8/dps8_eis.c c2 = (cpu.du.D2_PTR_W >> 6) & 077; cpu 3388 src/dps8/dps8_eis.c c1 = (cpu.du.D2_PTR_W >> 9) & 0777; cpu 3389 src/dps8/dps8_eis.c c2 = (cpu.du.D2_PTR_W ) & 0777; cpu 3435 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < limit; cpu.du.CHTALLY ++) cpu 3437 src/dps8/dps8_eis.c yCharn11 = EISget469 (1, limit - cpu.du.CHTALLY - 1); cpu 3438 src/dps8/dps8_eis.c yCharn12 = EISget469 (1, limit - cpu.du.CHTALLY); cpu 3443 src/dps8/dps8_eis.c SC_I_TALLY (cpu.du.CHTALLY == limit); cpu 3451 src/dps8/dps8_eis.c word36 CY3 = setbits36_24 (0, 12, cpu.du.CHTALLY); cpu 3465 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 3548 src/dps8/dps8_eis.c uint mask = (uint) getbits36_9 (cpu.cu.IWB, 0); cpu 3604 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < limit; cpu.du.CHTALLY ++) cpu 3606 src/dps8/dps8_eis.c word9 yCharn1 = EISget469 (1, cpu.du.CHTALLY); cpu 3617 src/dps8/dps8_eis.c word36 CY3 = setbits36_24 (0, 12, cpu.du.CHTALLY); cpu 3619 src/dps8/dps8_eis.c SC_I_TALLY (cpu.du.CHTALLY == limit); cpu 3633 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 3720 src/dps8/dps8_eis.c uint mask = (uint) getbits36_9 (cpu.cu.IWB, 0); cpu 3775 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < limit; cpu.du.CHTALLY ++) cpu 3777 src/dps8/dps8_eis.c word9 yCharn1 = EISget469 (1, limit - cpu.du.CHTALLY - 1); cpu 3788 src/dps8/dps8_eis.c word36 CY3 = setbits36_24 (0, 12, cpu.du.CHTALLY); cpu 3790 src/dps8/dps8_eis.c SC_I_TALLY (cpu.du.CHTALLY == limit); cpu 3845 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 3990 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < e -> N1; cpu.du.CHTALLY ++) cpu 3992 src/dps8/dps8_eis.c word9 c = EISget469 (1, cpu.du.CHTALLY); // get src char cpu 4024 src/dps8/dps8_eis.c SC_I_TALLY (cpu.du.CHTALLY == e -> N1); cpu 4027 src/dps8/dps8_eis.c putbits36_24 (& CY3, 12, cpu.du.CHTALLY); cpu 4037 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 4186 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < limit; cpu.du.CHTALLY ++) cpu 4188 src/dps8/dps8_eis.c word9 c = EISget469 (1, limit - cpu.du.CHTALLY - 1); // get src char cpu 4220 src/dps8/dps8_eis.c SC_I_TALLY (cpu.du.CHTALLY == e -> N1); cpu 4223 src/dps8/dps8_eis.c putbits36_24 (& CY3, 12, cpu.du.CHTALLY); cpu 4295 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 4382 src/dps8/dps8_eis.c word1 T = getbits36_1 (cpu.cu.IWB, 9); cpu 4384 src/dps8/dps8_eis.c word9 fill = getbits36_9 (cpu.cu.IWB, 0); cpu 4436 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, TA1, TA2, e -> N1, e -> N2, e -> CN1, e -> CN2); cpu 4438 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, e -> TA1, e -> TA2, e -> N1, e -> N2, e -> CN1, e -> CN2); cpu 4453 src/dps8/dps8_eis.c if ((cpu.du.CHTALLY % PGSZ) == 0 && cpu 4466 src/dps8/dps8_eis.c (cpu.du.D1_PTR_W & PGMK) == 0 && cpu 4467 src/dps8/dps8_eis.c (cpu.du.D2_PTR_W & PGMK) == 0) cpu 4474 src/dps8/dps8_eis.c while (cpu.du.CHTALLY < e -> N1) cpu 4477 src/dps8/dps8_eis.c EISReadPage (& e -> ADDR1, cpu.du.CHTALLY / 4, pg); cpu 4478 src/dps8/dps8_eis.c EISWritePage (& e -> ADDR2, cpu.du.CHTALLY / 4, pg); cpu 4479 src/dps8/dps8_eis.c cpu.du.CHTALLY += PGSZ * 4; cpu 4493 src/dps8/dps8_eis.c if ((cpu.du.CHTALLY % PGSZ) == 0 && cpu 4506 src/dps8/dps8_eis.c (cpu.du.D1_PTR_W & PGMK) == 0 && cpu 4507 src/dps8/dps8_eis.c (cpu.du.D2_PTR_W& PGMK) == 0) cpu 4525 src/dps8/dps8_eis.c while (cpu.du.CHTALLY < e -> N2) cpu 4527 src/dps8/dps8_eis.c EISWritePage (& e -> ADDR2, cpu.du.CHTALLY / 4, pg); cpu 4528 src/dps8/dps8_eis.c cpu.du.CHTALLY += PGSZ * 4; cpu 4554 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < e -> N2; cpu.du.CHTALLY += 4) cpu 4556 src/dps8/dps8_eis.c uint n = cpu.du.CHTALLY / 4; cpu 4585 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < e -> N2; cpu.du.CHTALLY += 4) cpu 4587 src/dps8/dps8_eis.c uint n = cpu.du.CHTALLY / 4; cpu 4598 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < min (e->N1, e->N2); cpu.du.CHTALLY ++) cpu 4600 src/dps8/dps8_eis.c word9 c = EISget469 (1, cpu.du.CHTALLY); // get src char cpu 4608 src/dps8/dps8_eis.c EISput469 (2, cpu.du.CHTALLY, c); cpu 4646 src/dps8/dps8_eis.c if (ovp && (cpu.du.CHTALLY == e -> N1 - 1)) cpu 4652 src/dps8/dps8_eis.c EISput469 (2, cpu.du.CHTALLY, cout); cpu 4664 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < e -> N2 ; cpu.du.CHTALLY ++) cpu 4667 src/dps8/dps8_eis.c if (ovp && (cpu.du.CHTALLY == e -> N2 - 1)) cpu 4670 src/dps8/dps8_eis.c EISput469 (2, cpu.du.CHTALLY, 015); // 015 is decimal - cpu 4672 src/dps8/dps8_eis.c EISput469 (2, cpu.du.CHTALLY, 014); // 014 is decimal + cpu 4675 src/dps8/dps8_eis.c EISput469 (2, cpu.du.CHTALLY, fillT); cpu 4693 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 4780 src/dps8/dps8_eis.c word1 T = getbits36_1 (cpu.cu.IWB, 9); cpu 4782 src/dps8/dps8_eis.c word9 fill = getbits36_9 (cpu.cu.IWB, 0); cpu 4850 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < limit; cpu.du.CHTALLY += 4) cpu 4852 src/dps8/dps8_eis.c uint n = (limit - cpu.du.CHTALLY - 1) / 4; cpu 4885 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < e -> N2; cpu.du.CHTALLY += 4) cpu 4887 src/dps8/dps8_eis.c uint n = (limit - cpu.du.CHTALLY - 1) / 4; cpu 4898 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < min (e -> N1, e -> N2); cpu.du.CHTALLY ++) cpu 4900 src/dps8/dps8_eis.c word9 c = EISget469 (1, e -> N1 - cpu.du.CHTALLY - 1); // get src char cpu 4908 src/dps8/dps8_eis.c EISput469 (2, e -> N2 - cpu.du.CHTALLY - 1, c); cpu 4947 src/dps8/dps8_eis.c if (ovp && (cpu.du.CHTALLY == 0)) cpu 4952 src/dps8/dps8_eis.c EISput469 (2, e -> N2 - cpu.du.CHTALLY - 1, cout); cpu 4964 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < e -> N2 ; cpu.du.CHTALLY ++) cpu 4967 src/dps8/dps8_eis.c if (ovp && (cpu.du.CHTALLY == e -> N2 - 1)) cpu 4970 src/dps8/dps8_eis.c EISput469 (2, e -> N2 - cpu.du.CHTALLY - 1, 015); // 015 is decimal - cpu 4972 src/dps8/dps8_eis.c EISput469 (2, e -> N2 - cpu.du.CHTALLY - 1, 014); // 014 is decimal + cpu 4976 src/dps8/dps8_eis.c EISput469 (2, e -> N2 - cpu.du.CHTALLY - 1, fillT); cpu 5021 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5182 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5204 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5215 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5334 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5378 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5424 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5458 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5589 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5665 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5696 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5765 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5823 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5886 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 5992 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 6094 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 6136 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 6193 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 6256 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 6322 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 6383 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 6448 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 6472 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[KMOP] = (cpu.du.Dk_PTR_W[KMOP] + 1) & AMASK; // bump source to next address cpu 6475 src/dps8/dps8_eis.c PNL (cpu.du.Dk_PTR_W[1] = (cpu.du.Dk_PTR_W[1] + 1) & AMASK); // bump source to next address cpu 6478 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[1] = (cpu.du.Dk_PTR_W[1] + 1) & AMASK; // bump source to next address cpu 6514 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 6651 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 6778 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 7000 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 7164 src/dps8/dps8_eis.c word1 T = getbits36_1 (cpu.cu.IWB, 9); cpu 7166 src/dps8/dps8_eis.c word9 fill = getbits36_9 (cpu.cu.IWB, 0); cpu 7187 src/dps8/dps8_eis.c for ( ; cpu.du.CHTALLY < min(e->N1, e->N2); cpu.du.CHTALLY ++) cpu 7189 src/dps8/dps8_eis.c word9 c = EISget469(1, cpu.du.CHTALLY); // get src char cpu 7197 src/dps8/dps8_eis.c EISput469(2, cpu.du.CHTALLY, xlate (&e->ADDR3, dstTA, c)); cpu 7240 src/dps8/dps8_eis.c EISput469 (2, cpu.du.CHTALLY, cout); cpu 7276 src/dps8/dps8_eis.c for( ; cpu.du.CHTALLY < e->N2 ; cpu.du.CHTALLY ++) cpu 7277 src/dps8/dps8_eis.c EISput469 (2, cpu.du.CHTALLY, cfill); cpu 7300 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 7474 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[eisaddr_idx] = (cpu.du.Dk_PTR_W[eisaddr_idx] + 1) & AMASK; // bump source to next address cpu 7537 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[eisaddr_idx] = (cpu.du.Dk_PTR_W[eisaddr_idx] + 1) & AMASK; // bump source to next address cpu 7607 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 7645 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character cpu 7647 src/dps8/dps8_eis.c word1 T = getbits36_1 (cpu.cu.IWB, 9); cpu 7648 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cpu 7925 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 8018 src/dps8/dps8_eis.c bool F = getbits36_1 (cpu.cu.IWB, 0) != 0; // fill bit cpu 8019 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // T (enablefault) bit cpu 8021 src/dps8/dps8_eis.c uint BOLR = getbits36_4 (cpu.cu.IWB, 5); // T (enablefault) bit cpu 8050 src/dps8/dps8_eis.c for( ; cpu.du.CHTALLY < min(e->N1, e->N2); cpu.du.CHTALLY += 1) cpu 8061 src/dps8/dps8_eis.c cpu.du.Z = 0; cpu 8074 src/dps8/dps8_eis.c for(; cpu.du.CHTALLY < e->N2; cpu.du.CHTALLY += 1) cpu 8086 src/dps8/dps8_eis.c cpu.du.Z = 0; cpu 8103 src/dps8/dps8_eis.c SC_I_ZERO (cpu.du.Z); cpu 8153 src/dps8/dps8_eis.c baseBitPosn -= (int) cpu.du.CHTALLY; cpu 8175 src/dps8/dps8_eis.c word18 saveAddr = cpu.du.Dk_PTR_W[eisaddr_idx]; cpu 8176 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[eisaddr_idx] += (word18) woff; cpu 8177 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[eisaddr_idx] &= AMASK; cpu 8202 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[eisaddr_idx] = saveAddr; cpu 8211 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 8290 src/dps8/dps8_eis.c PNL (cpu.du.D1_PTR_W += (word18) numWords1); cpu 8291 src/dps8/dps8_eis.c PNL (cpu.du.D1_PTR_W &= AMASK); cpu 8293 src/dps8/dps8_eis.c cpu.du.D1_PTR_W += (word18) numWords1; cpu 8294 src/dps8/dps8_eis.c cpu.du.D1_PTR_W &= AMASK; cpu 8306 src/dps8/dps8_eis.c PNL (cpu.du.D2_PTR_W += (word18) numWords1); cpu 8307 src/dps8/dps8_eis.c PNL (cpu.du.D2_PTR_W &= AMASK); cpu 8309 src/dps8/dps8_eis.c cpu.du.D2_PTR_W += (word18) numWords1; cpu 8310 src/dps8/dps8_eis.c cpu.du.D2_PTR_W &= AMASK; cpu 8315 src/dps8/dps8_eis.c bool F = getbits36_1 (cpu.cu.IWB, 0) != 0; // fill bit cpu 8316 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // T (enablefault) bit cpu 8318 src/dps8/dps8_eis.c uint BOLR = getbits36_4 (cpu.cu.IWB, 5); // T (enablefault) bit cpu 8333 src/dps8/dps8_eis.c for( ; cpu.du.CHTALLY < min(e->N1, e->N2); cpu.du.CHTALLY += 1) cpu 8343 src/dps8/dps8_eis.c cpu.du.Z = 0; cpu 8355 src/dps8/dps8_eis.c for(; cpu.du.CHTALLY < e->N2; cpu.du.CHTALLY += 1) cpu 8367 src/dps8/dps8_eis.c cpu.du.Z = 0; cpu 8384 src/dps8/dps8_eis.c SC_I_ZERO (cpu.du.Z); cpu 8410 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 8503 src/dps8/dps8_eis.c bool F = getbits36_1 (cpu.cu.IWB, 0) != 0; // fill bit cpu 8504 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // T (enablefault) bit cpu 8506 src/dps8/dps8_eis.c uint BOLR = getbits36_4 (cpu.cu.IWB, 5); // T (enablefault) bit cpu 8536 src/dps8/dps8_eis.c for( ; cpu.du.CHTALLY < min (e->N1, e->N2); cpu.du.CHTALLY += 1) cpu 8546 src/dps8/dps8_eis.c cpu.du.Z = 0; cpu 8553 src/dps8/dps8_eis.c for (; cpu.du.CHTALLY < e->N2; cpu.du.CHTALLY += 1) cpu 8563 src/dps8/dps8_eis.c cpu.du.Z = 0; cpu 8572 src/dps8/dps8_eis.c SC_I_ZERO (cpu.du.Z); cpu 8598 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 8677 src/dps8/dps8_eis.c PNL (cpu.du.D1_PTR_W += (word18) numWords1); cpu 8678 src/dps8/dps8_eis.c PNL (cpu.du.D1_PTR_W &= AMASK); cpu 8680 src/dps8/dps8_eis.c cpu.du.D1_PTR_W += (word18) numWords1; cpu 8681 src/dps8/dps8_eis.c cpu.du.D1_PTR_W &= AMASK; cpu 8693 src/dps8/dps8_eis.c PNL (cpu.du.D2_PTR_W += (word18) numWords1); cpu 8694 src/dps8/dps8_eis.c PNL (cpu.du.D2_PTR_W &= AMASK); cpu 8696 src/dps8/dps8_eis.c cpu.du.D2_PTR_W += (word18) numWords1; cpu 8697 src/dps8/dps8_eis.c cpu.du.D2_PTR_W &= AMASK; cpu 8702 src/dps8/dps8_eis.c bool F = getbits36_1 (cpu.cu.IWB, 0) != 0; // fill bit cpu 8703 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // T (enablefault) bit cpu 8705 src/dps8/dps8_eis.c uint BOLR = getbits36_4 (cpu.cu.IWB, 5); // T (enablefault) bit cpu 8720 src/dps8/dps8_eis.c for( ; cpu.du.CHTALLY < min(e->N1, e->N2); cpu.du.CHTALLY += 1) cpu 8731 src/dps8/dps8_eis.c cpu.du.Z = 0; cpu 8739 src/dps8/dps8_eis.c for(; cpu.du.CHTALLY < e->N2; cpu.du.CHTALLY += 1) cpu 8751 src/dps8/dps8_eis.c cpu.du.Z = 0; cpu 8761 src/dps8/dps8_eis.c SC_I_ZERO (cpu.du.Z); cpu 8810 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[eisaddr_idx] += 1; cpu 8811 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[eisaddr_idx] &= AMASK; cpu 8832 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 8885 src/dps8/dps8_eis.c bool F = getbits36_1 (cpu.cu.IWB, 0) != 0; // fill bit cpu 8993 src/dps8/dps8_eis.c cpu 9058 src/dps8/dps8_eis.c cpu 9099 src/dps8/dps8_eis.c cpu 9160 src/dps8/dps8_eis.c cpu 9161 src/dps8/dps8_eis.c cpu 9163 src/dps8/dps8_eis.c cpu 9164 src/dps8/dps8_eis.c cpu 9261 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 9287 src/dps8/dps8_eis.c cpu.du.Dk_PTR_W[eisaddr_idx] = (cpu.du.Dk_PTR_W[eisaddr_idx] + 1) & AMASK; // bump source to next address cpu 9314 src/dps8/dps8_eis.c cpu 9358 src/dps8/dps8_eis.c cpu 9429 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 9532 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cpu 9707 src/dps8/dps8_eis.c cpu 9728 src/dps8/dps8_eis.c cpu 9855 src/dps8/dps8_eis.c cpu 9880 src/dps8/dps8_eis.c cpu 9881 src/dps8/dps8_eis.c cpu 9908 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 10103 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 10140 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cpu 10141 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // truncation bit cpu 10142 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cpu 10452 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 10491 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cpu 10492 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // truncation bit cpu 10493 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cpu 10794 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 10834 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cpu 10835 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // truncation bit cpu 10836 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cpu 11106 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 11144 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cpu 11145 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // truncation bit cpu 11146 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cpu 11436 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 11473 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cpu 11474 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // truncation bit cpu 11475 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cpu 11705 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 11743 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cpu 11744 src/dps8/dps8_eis.c bool T = getbits36_1 (cpu.cu.IWB, 9) != 0; // truncation bit cpu 11745 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cpu 12758 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 12796 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cpu 12798 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cpu 13148 src/dps8/dps8_eis.c EISstruct * e = & cpu.currentEISinstruction; cpu 13187 src/dps8/dps8_eis.c e->P = getbits36_1 (cpu.cu.IWB, 0) != 0; // 4-bit data sign character control cpu 13189 src/dps8/dps8_eis.c bool R = getbits36_1 (cpu.cu.IWB, 10) != 0; // rounding bit cpu 50 src/dps8/dps8_faults.c #define DBG_CTR cpu.cycleCnt cpu 261 src/dps8/dps8_faults.c sim_printf (" fault number %d (%o)\n", cpu . faultNumber, cpu . faultNumber); cpu 262 src/dps8/dps8_faults.c sim_printf (" subfault number %llu (%llo)\n", (unsigned long long) cpu.subFault.bits, cpu 263 src/dps8/dps8_faults.c (unsigned long long)cpu.subFault.bits); cpu 271 src/dps8/dps8_faults.c cpu . bTroubleFaultCycle = false; cpu 381 src/dps8/dps8_faults.c sim_printf (" TRO PSR:IC %05o:%06o\r\n", cpu.PPR.PSR, cpu.PPR.IC); cpu 386 src/dps8/dps8_faults.c sim_printf (" ACV %012llo PSR:IC %05o:%06o\r\n", subFault.bits, cpu.PPR.PSR, cpu.PPR.IC); cpu 398 src/dps8/dps8_faults.c cpu . bTroubleFaultCycle ? 'Y' : 'N', faultMsg); cpu 403 src/dps8/dps8_faults.c __atomic_add_fetch (& cpu.faults[faultNumber], 1u, __ATOMIC_ACQUIRE); cpu 413 src/dps8/dps8_faults.c PNL (cpu.DACVpDF = faultNumber >= FAULT_DF0 && faultNumber <= FAULT_ACV;) cpu 417 src/dps8/dps8_faults.c fault_psr = cpu . PPR.PSR; cpu 418 src/dps8/dps8_faults.c fault_ic = cpu . PPR.IC; cpu 432 src/dps8/dps8_faults.c cpu.faultNumber = faultNumber; cpu 433 src/dps8/dps8_faults.c cpu.subFault = subFault; cpu 434 src/dps8/dps8_faults.c cpu.faultCnt [faultNumber] ++; cpu 438 src/dps8/dps8_faults.c cpu.CMR.csh_reg = 0; cpu 442 src/dps8/dps8_faults.c word3 FCT = cpu.cu.APUCycleBits & MASK3; cpu 444 src/dps8/dps8_faults.c cpu.cu.APUCycleBits = (word12) ((cpu.cu.APUCycleBits & 07770) | FCT); cpu 453 src/dps8/dps8_faults.c cpu 455 src/dps8/dps8_faults.c cpu 457 src/dps8/dps8_faults.c cpu 459 src/dps8/dps8_faults.c cpu 461 src/dps8/dps8_faults.c cpu . faultRegister [0] |= subFault.bits; cpu 466 src/dps8/dps8_faults.c cpu . faultRegister [0] |= FR_NEM; cpu 471 src/dps8/dps8_faults.c cpu . faultRegister [0] |= FR_OOB; cpu 482 src/dps8/dps8_faults.c cpu . faultRegister [0] |= FR_CON_A; cpu 485 src/dps8/dps8_faults.c cpu . faultRegister [0] |= FR_CON_B; cpu 488 src/dps8/dps8_faults.c cpu . faultRegister [0] |= FR_CON_C; cpu 491 src/dps8/dps8_faults.c cpu . faultRegister [0] |= FR_CON_D; cpu 501 src/dps8/dps8_faults.c cpu . cu . IRO_ISN = 0; cpu 502 src/dps8/dps8_faults.c cpu . cu . OEB_IOC = 0; cpu 503 src/dps8/dps8_faults.c cpu . cu . EOFF_IAIM = 0; cpu 504 src/dps8/dps8_faults.c cpu . cu . ORB_ISP = 0; cpu 505 src/dps8/dps8_faults.c cpu . cu . ROFF_IPR = 0; cpu 506 src/dps8/dps8_faults.c cpu . cu . OWB_NEA = 0; cpu 507 src/dps8/dps8_faults.c cpu . cu . WOFF_OOB = 0; cpu 508 src/dps8/dps8_faults.c cpu . cu . NO_GA = 0; cpu 509 src/dps8/dps8_faults.c cpu . cu . OCB = 0; cpu 510 src/dps8/dps8_faults.c cpu . cu . OCALL = 0; cpu 511 src/dps8/dps8_faults.c cpu . cu . BOC = 0; cpu 512 src/dps8/dps8_faults.c DPS8M_ (cpu . cu . PTWAM_ER = 0;) cpu 513 src/dps8/dps8_faults.c cpu . cu . CRT = 0; cpu 514 src/dps8/dps8_faults.c cpu . cu . RALR = 0; cpu 515 src/dps8/dps8_faults.c cpu . cu . SDWAM_ER = 0; cpu 516 src/dps8/dps8_faults.c cpu . cu . OOSB = 0; cpu 517 src/dps8/dps8_faults.c cpu . cu . PARU = 0; cpu 518 src/dps8/dps8_faults.c cpu . cu . PARL = 0; cpu 519 src/dps8/dps8_faults.c cpu . cu . ONC1 = 0; cpu 520 src/dps8/dps8_faults.c cpu . cu . ONC2 = 0; cpu 521 src/dps8/dps8_faults.c cpu . cu . IA = 0; cpu 522 src/dps8/dps8_faults.c cpu . cu . IACHN = 0; cpu 523 src/dps8/dps8_faults.c cpu . cu . CNCHN = (faultNumber == FAULT_CON) ? subFault.fault_con_subtype & MASK3 : 0; cpu 526 src/dps8/dps8_faults.c cpu . cu . FIF = cpu . cycle == FETCH_cycle ? 1 : 0; cpu 527 src/dps8/dps8_faults.c cpu . cu . FI_ADDR = (word5) faultNumber; cpu 533 src/dps8/dps8_faults.c cpu . cu . rfi = 0; cpu 541 src/dps8/dps8_faults.c SC_I_MIF (cpu.cycle == EXEC_cycle && cpu 542 src/dps8/dps8_faults.c (cpu.currentInstruction.info->ndes > 0 || cpu 544 src/dps8/dps8_faults.c cpu.currentInstruction.opcodeX && cpu 545 src/dps8/dps8_faults.c (cpu.currentInstruction.opcode & 0410) == 0))); cpu 548 src/dps8/dps8_faults.c cpu 549 src/dps8/dps8_faults.c cpu 550 src/dps8/dps8_faults.c cpu 552 src/dps8/dps8_faults.c cpu 553 src/dps8/dps8_faults.c cpu 567 src/dps8/dps8_faults.c cpu . cu . IRO_ISN = 1; cpu 569 src/dps8/dps8_faults.c cpu . cu . OEB_IOC = 1; cpu 571 src/dps8/dps8_faults.c cpu . cu . EOFF_IAIM = 1; cpu 573 src/dps8/dps8_faults.c cpu . cu . ORB_ISP = 1; cpu 575 src/dps8/dps8_faults.c cpu . cu . ROFF_IPR = 1; cpu 577 src/dps8/dps8_faults.c cpu . cu . OWB_NEA = 1; cpu 579 src/dps8/dps8_faults.c cpu . cu . WOFF_OOB = 1; cpu 581 src/dps8/dps8_faults.c cpu . cu . NO_GA = 1; cpu 583 src/dps8/dps8_faults.c cpu . cu . OCB = 1; cpu 585 src/dps8/dps8_faults.c cpu . cu . OCALL = 1; cpu 587 src/dps8/dps8_faults.c cpu . cu . BOC = 1; cpu 589 src/dps8/dps8_faults.c cpu . cu . PTWAM_ER = 1; cpu 591 src/dps8/dps8_faults.c cpu . cu . CRT = 1; cpu 593 src/dps8/dps8_faults.c cpu . cu . RALR = 1; cpu 595 src/dps8/dps8_faults.c cpu . cu . SDWAM_ER = 1; cpu 597 src/dps8/dps8_faults.c cpu . cu . OOSB = 1; cpu 602 src/dps8/dps8_faults.c cpu . cu . WOFF_OOB = 1; cpu 606 src/dps8/dps8_faults.c cpu . cu . OWB_NEA = 1; cpu 611 src/dps8/dps8_faults.c cpu . cu . OEB_IOC = 1; cpu 613 src/dps8/dps8_faults.c cpu . cu . EOFF_IAIM = 1; cpu 615 src/dps8/dps8_faults.c cpu . cu . ORB_ISP = 1; cpu 617 src/dps8/dps8_faults.c cpu . cu . ROFF_IPR = 1; cpu 622 src/dps8/dps8_faults.c cpu . cu . IA = 0; cpu 624 src/dps8/dps8_faults.c cpu . cu . IA = 010; cpu 634 src/dps8/dps8_faults.c if (cpu.MR.emr && cpu.MR.ihrrs) cpu 636 src/dps8/dps8_faults.c cpu.MR.ihr = 0; cpu 650 src/dps8/dps8_faults.c if (cpu.MR.emr && cpu.MR.ihrrs) cpu 659 src/dps8/dps8_faults.c cpu.MR.ihr = 0; cpu 666 src/dps8/dps8_faults.c cpu.MR.ihr = 0; cpu 672 src/dps8/dps8_faults.c if (cpu.cycle == FAULT_EXEC_cycle) cpu 676 src/dps8/dps8_faults.c cpu.faultNumber = FAULT_TRB; cpu 677 src/dps8/dps8_faults.c cpu.cu.FI_ADDR = FAULT_TRB; cpu 678 src/dps8/dps8_faults.c cpu.subFault.bits = 0; // XXX ??? cpu 679 src/dps8/dps8_faults.c if (cpu . bTroubleFaultCycle) cpu 690 src/dps8/dps8_faults.c cpu . PPR.IC); cpu 691 src/dps8/dps8_faults.c sim_printf("\nCycles = %"PRId64"\n", cpu.cycleCnt); cpu 692 src/dps8/dps8_faults.c sim_printf("\nInstructions = %"PRId64"\n", cpu.instrCnt); cpu 694 src/dps8/dps8_faults.c longjmp (cpu.jmpMain, JMP_STOP); cpu 703 src/dps8/dps8_faults.c cpu . bTroubleFaultCycle = true; cpu 708 src/dps8/dps8_faults.c cpu . bTroubleFaultCycle = false; cpu 713 src/dps8/dps8_faults.c if (cpu . cycle == EXEC_cycle) cpu 714 src/dps8/dps8_faults.c cpu.instrCnt ++; cpu 716 src/dps8/dps8_faults.c cpu . cycle = FAULT_cycle; cpu 718 src/dps8/dps8_faults.c longjmp (cpu.jmpMain, JMP_REENTRY); cpu 740 src/dps8/dps8_faults.c cpu.FFV_fault_number = fault_number; cpu 741 src/dps8/dps8_faults.c cpu.faultNumber = fault_number; cpu 746 src/dps8/dps8_faults.c cpu.CMR.csh_reg = 0; cpu 750 src/dps8/dps8_faults.c word3 FCT = cpu.cu.APUCycleBits & MASK3; cpu 752 src/dps8/dps8_faults.c cpu.cu.APUCycleBits = (word12) ((cpu.cu.APUCycleBits & 07770) | FCT); cpu 756 src/dps8/dps8_faults.c cpu.faultRegister [0] = 0; cpu 760 src/dps8/dps8_faults.c cpu.cu.IRO_ISN = 0; cpu 761 src/dps8/dps8_faults.c cpu.cu.OEB_IOC = 0; cpu 762 src/dps8/dps8_faults.c cpu.cu.EOFF_IAIM = 0; cpu 763 src/dps8/dps8_faults.c cpu.cu.ORB_ISP = 0; cpu 764 src/dps8/dps8_faults.c cpu.cu.ROFF_IPR = 0; cpu 765 src/dps8/dps8_faults.c cpu.cu.OWB_NEA = 0; cpu 766 src/dps8/dps8_faults.c cpu.cu.WOFF_OOB = 0; cpu 767 src/dps8/dps8_faults.c cpu.cu.NO_GA = 0; cpu 768 src/dps8/dps8_faults.c cpu.cu.OCB = 0; cpu 769 src/dps8/dps8_faults.c cpu.cu.OCALL = 0; cpu 770 src/dps8/dps8_faults.c cpu.cu.BOC = 0; cpu 775 src/dps8/dps8_faults.c cpu.cu.CRT = 0; cpu 776 src/dps8/dps8_faults.c cpu.cu.RALR = 0; cpu 777 src/dps8/dps8_faults.c cpu.cu.SDWAM_ER = 0; cpu 778 src/dps8/dps8_faults.c cpu.cu.OOSB = 0; cpu 779 src/dps8/dps8_faults.c cpu.cu.PARU = 0; cpu 780 src/dps8/dps8_faults.c cpu.cu.PARL = 0; cpu 781 src/dps8/dps8_faults.c cpu.cu.ONC1 = 0; cpu 782 src/dps8/dps8_faults.c cpu.cu.ONC2 = 0; cpu 783 src/dps8/dps8_faults.c cpu.cu.IA = 0; cpu 784 src/dps8/dps8_faults.c cpu.cu.IACHN = 0; cpu 785 src/dps8/dps8_faults.c cpu.cu.CNCHN = 0; cpu 788 src/dps8/dps8_faults.c cpu.cu.FIF = 0; cpu 789 src/dps8/dps8_faults.c cpu.cu.FI_ADDR = (word5) fault_number & MASK5; cpu 795 src/dps8/dps8_faults.c cpu.cu.rfi = 0; cpu 802 src/dps8/dps8_faults.c SC_I_MIF (cpu.cycle == EXEC_cycle && cpu 803 src/dps8/dps8_faults.c cpu.currentInstruction.info->ndes > 0); cpu 813 src/dps8/dps8_faults.c if (cpu.MR.emr && cpu.MR.ihrrs) cpu 815 src/dps8/dps8_faults.c cpu.MR.ihr = 0; cpu 818 src/dps8/dps8_faults.c if (cpu.cycle == FAULT_EXEC_cycle) cpu 820 src/dps8/dps8_faults.c cpu.faultNumber = FAULT_TRB; cpu 821 src/dps8/dps8_faults.c cpu.cu.FI_ADDR = FAULT_TRB; cpu 822 src/dps8/dps8_faults.c cpu.subFault.bits = 0; // XXX ??? cpu 823 src/dps8/dps8_faults.c if (cpu.bTroubleFaultCycle) cpu 834 src/dps8/dps8_faults.c cpu.PPR.IC); cpu 835 src/dps8/dps8_faults.c sim_printf("\nCycles = %"PRId64"\n", cpu.cycleCnt); cpu 836 src/dps8/dps8_faults.c sim_printf("\nInstructions = %"PRId64"\n", cpu.instrCnt); cpu 837 src/dps8/dps8_faults.c longjmp (cpu.jmpMain, JMP_STOP); cpu 845 src/dps8/dps8_faults.c cpu.bTroubleFaultCycle = true; cpu 847 src/dps8/dps8_faults.c cpu.cycle = FAULT_cycle; cpu 849 src/dps8/dps8_faults.c longjmp (cpu.jmpMain, JMP_REENTRY); cpu 851 src/dps8/dps8_faults.c cpu.bTroubleFaultCycle = false; cpu 855 src/dps8/dps8_faults.c if (cpu . cycle == EXEC_cycle) cpu 856 src/dps8/dps8_faults.c cpu.instrCnt ++; cpu 858 src/dps8/dps8_faults.c cpu.is_FFV = true; cpu 859 src/dps8/dps8_faults.c cpu.cycle = FAULT_cycle; cpu 860 src/dps8/dps8_faults.c longjmp (cpu.jmpMain, JMP_REENTRY); cpu 866 src/dps8/dps8_faults.c cpu.dlyFlt = true; cpu 867 src/dps8/dps8_faults.c cpu.dlyFltNum = faultNumber; cpu 868 src/dps8/dps8_faults.c cpu.dlySubFltNum = subFault; cpu 869 src/dps8/dps8_faults.c cpu.dlyCtx = faultMsg; cpu 881 src/dps8/dps8_faults.c if (cpu.tweaks.l68_mode) cpu 882 src/dps8/dps8_faults.c return cpu.g7Faults != 0 || cpu.FFV_faults != 0; // L68 cpu 884 src/dps8/dps8_faults.c return cpu.g7Faults != 0; // DPS8M cpu 889 src/dps8/dps8_faults.c if (cpu.tweaks.l68_mode) cpu 890 src/dps8/dps8_faults.c return (cpu.g7Faults & (~ (1u << FAULT_TRO))) != 0 || cpu.FFV_faults != 0; // L68 cpu 892 src/dps8/dps8_faults.c return (cpu.g7Faults & (~ (1u << FAULT_TRO))) != 0; // DPS8M cpu 912 src/dps8/dps8_faults.c cpu.FFV_faults_preset |= 1u << ((f_fault_no / 2) - 1); cpu 917 src/dps8/dps8_faults.c cpu . g7Faults &= ~(1u << FAULT_TRO); cpu 932 src/dps8/dps8_faults.c if (cpu.g7Faults & (1u << FAULT_CON)) cpu 934 src/dps8/dps8_faults.c cpu.g7Faults &= ~(1u << FAULT_CON); cpu 939 src/dps8/dps8_faults.c doFault (FAULT_CON, cpu.g7SubFaults [FAULT_CON], "Connect"); cpu 942 src/dps8/dps8_faults.c if (allowTR && (cpu.g7Faults & (1u << FAULT_TRO))) cpu 944 src/dps8/dps8_faults.c cpu . g7Faults &= ~(1u << FAULT_TRO); cpu 956 src/dps8/dps8_faults.c if (cpu . g7Faults & (1u << FAULT_EXF)) cpu 958 src/dps8/dps8_faults.c cpu . g7Faults &= ~(1u << FAULT_EXF); cpu 966 src/dps8/dps8_faults.c if (cpu.tweaks.l68_mode) { // L68 cpu 967 src/dps8/dps8_faults.c if (cpu.FFV_faults & 1u) // FFV + 2 OC TRAP cpu 969 src/dps8/dps8_faults.c cpu.FFV_faults &= ~1u; cpu 975 src/dps8/dps8_faults.c if (cpu.FFV_faults & 2u) // FFV + 4 CU HISTORY OVERFLOW TRAP cpu 977 src/dps8/dps8_faults.c cpu.FFV_faults &= ~2u; cpu 983 src/dps8/dps8_faults.c if (cpu.FFV_faults & 4u) // FFV + 6 ADR TRAP cpu 985 src/dps8/dps8_faults.c cpu.FFV_faults &= ~4u; cpu 995 src/dps8/dps8_faults.c doFault (FAULT_TRB, (_fault_subtype) {.bits=cpu.g7Faults}, "Dazed and confused in doG7Fault"); cpu 1003 src/dps8/dps8_faults.c cpu.g7Faults |= cpu.g7FaultsPreset; cpu 1004 src/dps8/dps8_faults.c cpu.g7FaultsPreset = 0; cpu 1007 src/dps8/dps8_faults.c cpu.FFV_faults |= cpu.FFV_faults_preset; cpu 1008 src/dps8/dps8_faults.c cpu.FFV_faults_preset = 0; cpu 584 src/dps8/dps8_hw_consts.h # define CLR_I_ABS CLRF (cpu.cu.IR, I_ABS) cpu 585 src/dps8/dps8_hw_consts.h # define CLR_I_MIF CLRF (cpu.cu.IR, I_MIF) cpu 586 src/dps8/dps8_hw_consts.h # define CLR_I_TRUNC CLRF (cpu.cu.IR, I_TRUNC) cpu 587 src/dps8/dps8_hw_consts.h # define CLR_I_NBAR CLRF (cpu.cu.IR, I_NBAR) cpu 588 src/dps8/dps8_hw_consts.h # define CLR_I_TALLY CLRF (cpu.cu.IR, I_TALLY) cpu 589 src/dps8/dps8_hw_consts.h # define CLR_I_PMASK CLRF (cpu.cu.IR, I_PMASK) cpu 590 src/dps8/dps8_hw_consts.h # define CLR_I_EOFL CLRF (cpu.cu.IR, I_EOFL) cpu 591 src/dps8/dps8_hw_consts.h # define CLR_I_EUFL CLRF (cpu.cu.IR, I_EUFL) cpu 592 src/dps8/dps8_hw_consts.h # define CLR_I_OFLOW CLRF (cpu.cu.IR, I_OFLOW) cpu 593 src/dps8/dps8_hw_consts.h # define CLR_I_CARRY CLRF (cpu.cu.IR, I_CARRY) cpu 594 src/dps8/dps8_hw_consts.h # define CLR_I_NEG CLRF (cpu.cu.IR, I_NEG) cpu 595 src/dps8/dps8_hw_consts.h # define CLR_I_ZERO CLRF (cpu.cu.IR, I_ZERO) cpu 597 src/dps8/dps8_hw_consts.h # define SET_I_ABS SETF (cpu.cu.IR, I_ABS) cpu 598 src/dps8/dps8_hw_consts.h # define SET_I_NBAR SETF (cpu.cu.IR, I_NBAR) cpu 599 src/dps8/dps8_hw_consts.h # define SET_I_TRUNC SETF (cpu.cu.IR, I_TRUNC) cpu 600 src/dps8/dps8_hw_consts.h # define SET_I_TALLY SETF (cpu.cu.IR, I_TALLY) cpu 601 src/dps8/dps8_hw_consts.h # define SET_I_EOFL SETF (cpu.cu.IR, I_EOFL) cpu 602 src/dps8/dps8_hw_consts.h # define SET_I_EUFL SETF (cpu.cu.IR, I_EUFL) cpu 603 src/dps8/dps8_hw_consts.h # define SET_I_OFLOW SETF (cpu.cu.IR, I_OFLOW) cpu 604 src/dps8/dps8_hw_consts.h # define SET_I_CARRY SETF (cpu.cu.IR, I_CARRY) cpu 605 src/dps8/dps8_hw_consts.h # define SET_I_NEG SETF (cpu.cu.IR, I_NEG) cpu 606 src/dps8/dps8_hw_consts.h # define SET_I_ZERO SETF (cpu.cu.IR, I_ZERO) cpu 608 src/dps8/dps8_hw_consts.h # define TST_I_ABS TSTF (cpu.cu.IR, I_ABS) cpu 609 src/dps8/dps8_hw_consts.h # define TST_I_MIF TSTF (cpu.cu.IR, I_MIF) cpu 610 src/dps8/dps8_hw_consts.h # define TST_I_NBAR TSTF (cpu.cu.IR, I_NBAR) cpu 611 src/dps8/dps8_hw_consts.h # define TST_I_PMASK TSTF (cpu.cu.IR, I_PMASK) cpu 612 src/dps8/dps8_hw_consts.h # define TST_I_TRUNC TSTF (cpu.cu.IR, I_TRUNC) cpu 613 src/dps8/dps8_hw_consts.h # define TST_I_TALLY TSTF (cpu.cu.IR, I_TALLY) cpu 614 src/dps8/dps8_hw_consts.h # define TST_I_OMASK TSTF (cpu.cu.IR, I_OMASK) cpu 615 src/dps8/dps8_hw_consts.h # define TST_I_EUFL TSTF (cpu.cu.IR, I_EUFL ) cpu 616 src/dps8/dps8_hw_consts.h # define TST_I_EOFL TSTF (cpu.cu.IR, I_EOFL ) cpu 617 src/dps8/dps8_hw_consts.h # define TST_I_OFLOW TSTF (cpu.cu.IR, I_OFLOW) cpu 618 src/dps8/dps8_hw_consts.h # define TST_I_CARRY TSTF (cpu.cu.IR, I_CARRY) cpu 619 src/dps8/dps8_hw_consts.h # define TST_I_NEG TSTF (cpu.cu.IR, I_NEG) cpu 620 src/dps8/dps8_hw_consts.h # define TST_I_ZERO TSTF (cpu.cu.IR, I_ZERO) cpu 621 src/dps8/dps8_hw_consts.h # define TST_I_HEX TSTF (cpu.cu.IR, I_HEX) cpu 623 src/dps8/dps8_hw_consts.h # define SC_I_HEX(v) SCF (v, cpu.cu.IR, I_HEX) // DPS8M only cpu 624 src/dps8/dps8_hw_consts.h # define SC_I_MIF(v) SCF (v, cpu.cu.IR, I_MIF) cpu 625 src/dps8/dps8_hw_consts.h # define SC_I_TALLY(v) SCF (v, cpu.cu.IR, I_TALLY) cpu 626 src/dps8/dps8_hw_consts.h # define SC_I_NEG(v) SCF (v, cpu.cu.IR, I_NEG) cpu 627 src/dps8/dps8_hw_consts.h # define SC_I_ZERO(v) SCF (v, cpu.cu.IR, I_ZERO) cpu 628 src/dps8/dps8_hw_consts.h # define SC_I_CARRY(v) SCF (v, cpu.cu.IR, I_CARRY); cpu 629 src/dps8/dps8_hw_consts.h # define SC_I_OFLOW(v) SCF (v, cpu.cu.IR, I_OFLOW); cpu 630 src/dps8/dps8_hw_consts.h # define SC_I_EOFL(v) SCF (v, cpu.cu.IR, I_EOFL); cpu 631 src/dps8/dps8_hw_consts.h # define SC_I_EUFL(v) SCF (v, cpu.cu.IR, I_EUFL); cpu 632 src/dps8/dps8_hw_consts.h # define SC_I_OMASK(v) SCF (v, cpu.cu.IR, I_OMASK); cpu 633 src/dps8/dps8_hw_consts.h # define SC_I_PERR(v) SCF (v, cpu.cu.IR, I_PERR); cpu 634 src/dps8/dps8_hw_consts.h # define SC_I_PMASK(v) SCF (v, cpu.cu.IR, I_PMASK); cpu 635 src/dps8/dps8_hw_consts.h # define SC_I_TRUNC(v) SCF (v, cpu.cu.IR, I_TRUNC); cpu 1474 src/dps8/dps8_hw_consts.h # define N_MODEL_HIST_SIZE (cpu.tweaks.l68_mode ? N_L68_HIST_SIZE : N_DPS8M_HIST_SIZE) cpu 49 src/dps8/dps8_iefp.c #define DBG_CTR cpu.cycleCnt cpu 56 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 60 src/dps8/dps8_iefp.c if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29)) cpu 72 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 76 src/dps8/dps8_iefp.c core_read_lock (cpu.iefpFinalAddress, result, __func__); cpu 78 src/dps8/dps8_iefp.c core_read (cpu.iefpFinalAddress, result, __func__); cpu 80 src/dps8/dps8_iefp.c core_read (cpu.iefpFinalAddress, result, __func__); cpu 87 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "Read ABS BAR"); cpu 119 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 120 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 121 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 122 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = do_append_cycle (cyctyp, result, 1); cpu 126 src/dps8/dps8_iefp.c cpu.iefpFinalAddress, * result); cpu 128 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read BAR"); cpu 129 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read BAR"); cpu 136 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = do_append_cycle (cyctyp, result, 1); cpu 138 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) cpu 143 src/dps8/dps8_iefp.c cpu.iefpFinalAddress, * result); cpu 145 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read"); cpu 146 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read"); cpu 159 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 162 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cpu 169 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 171 src/dps8/dps8_iefp.c core_read (cpu.iefpFinalAddress, result, __func__); cpu 175 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "ReadAPUDataRead ABS BAR"); cpu 194 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 195 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 196 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 197 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataRead (result, 1); cpu 198 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu 200 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRead BAR"); cpu 201 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead BAR"); cpu 205 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataRead (result, 1); cpu 207 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { cpu 208 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu 210 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRead"); cpu 211 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRead"); cpu 221 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 224 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cpu 231 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 233 src/dps8/dps8_iefp.c core_read (cpu.iefpFinalAddress, result, __func__); cpu 237 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "readOperandRead ABS BAR"); cpu 256 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 257 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 258 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 259 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleOperandRead (result, 1); cpu 260 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu 262 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "readOperandRead BAR"); cpu 263 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead BAR"); cpu 268 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleOperandRead (result, 1); cpu 270 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { cpu 271 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu 273 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "readOperandRead"); cpu 274 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "readOperandRead"); cpu 285 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 288 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cpu 295 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 297 src/dps8/dps8_iefp.c core_read_lock (cpu.iefpFinalAddress, result, __func__); cpu 301 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "ReadOperandRMW ABS BAR"); cpu 320 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 321 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 322 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 323 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleOperandRMW (result, 1); cpu 324 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu 326 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadOperandRMW BAR"); cpu 327 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW BAR"); cpu 331 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleOperandRMW (result, 1); cpu 333 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { cpu 334 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu 336 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadOperandRMW"); cpu 337 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadOperandRMW"); cpu 347 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 350 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cpu 357 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 359 src/dps8/dps8_iefp.c core_read_lock (cpu.iefpFinalAddress, result, __func__); cpu 363 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "ReadAPUDataRMW ABS BAR"); cpu 382 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 383 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 384 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 385 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataRMW (result, 1); cpu 386 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu 388 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadAPUDataRMW BAR"); cpu 389 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW BAR"); cpu 393 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataRMW (result, 1); cpu 395 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { cpu 396 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu 398 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadAPUDataRMW"); cpu 399 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadAPUDataRMW"); cpu 411 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 414 src/dps8/dps8_iefp.c if (cpu.cu.XSF) cpu 421 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 423 src/dps8/dps8_iefp.c core_read (cpu.iefpFinalAddress, result, __func__); cpu 427 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "ReadInstructionFetch ABS BAR"); cpu 446 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 447 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 448 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 449 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleInstructionFetch (result, 1); cpu 450 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu 452 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadInstructionFetch BAR"); cpu 453 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch BAR"); cpu 457 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleInstructionFetch (result, 1); cpu 459 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { cpu 460 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu 462 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadInstructionFetch"); cpu 463 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadInstructionFetch"); cpu 473 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 476 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cpu 483 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 485 src/dps8/dps8_iefp.c core_read (cpu.iefpFinalAddress, result, __func__); cpu 489 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch ABS BAR"); cpu 508 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 509 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 510 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 511 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (result, 1); cpu 512 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read: bar iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu 514 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch BAR"); cpu 515 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch BAR"); cpu 519 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (result, 1); cpu 521 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { cpu 522 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read: iefpFinalAddress=%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result); cpu 524 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadIndirectWordFetch"); cpu 525 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "ReadIndirectWordFetch"); cpu 537 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 541 src/dps8/dps8_iefp.c if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29) || cyctyp == RTCD_OPERAND_FETCH) // ISOLTS-886 cpu 549 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 552 src/dps8/dps8_iefp.c core_read2 (cpu.iefpFinalAddress, result + 0, result + 1, __func__); cpu 559 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "Read2 ABBR evn"); cpu 560 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2 ABBR odd"); cpu 573 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "Read2 AB evn"); cpu 574 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2 AB odd"); cpu 583 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 584 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 585 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 586 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = do_append_cycle (cyctyp, result, 2); cpu 589 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 592 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR"); cpu 593 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn"); cpu 594 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd"); cpu 598 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = do_append_cycle (cyctyp, result, 2); cpu 601 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 606 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2 (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 610 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2"); cpu 611 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn"); cpu 612 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd"); cpu 623 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 627 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cpu 634 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 637 src/dps8/dps8_iefp.c core_read2 (cpu.iefpFinalAddress, result + 0, result + 1, __func__); cpu 644 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRead ABBR evn"); cpu 645 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRead ABBR odd"); cpu 658 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRead AB evn"); cpu 659 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRead AB odd"); cpu 668 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 669 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 670 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 671 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleOperandRead (result, 2); cpu 674 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 677 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRead BR"); cpu 678 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead BR evn"); cpu 679 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead BR odd"); cpu 683 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleOperandRead (result, 2); cpu 686 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 690 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 693 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRead"); cpu 694 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRead evn"); cpu 695 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRead odd"); cpu 705 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 709 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cpu 716 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 719 src/dps8/dps8_iefp.c core_read2 (cpu.iefpFinalAddress, result + 0, result + 1, __func__); cpu 726 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRMW ABBR evn"); cpu 727 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRMW ABBR odd"); cpu 740 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "Read2OperandRMW AB evn"); cpu 741 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2OperandRMW AB odd"); cpu 750 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 751 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 752 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 753 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleOperandRMW (result, 2); cpu 756 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 759 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2OperandRMW BR"); cpu 760 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW BR evn"); cpu 761 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW BR odd"); cpu 765 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleOperandRMW (result, 2); cpu 768 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 771 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2OperandRMW"); cpu 772 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2OperandRMW evn"); cpu 773 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2OperandRMW odd"); cpu 783 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 787 src/dps8/dps8_iefp.c if (cpu.cu.XSF) cpu 794 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 797 src/dps8/dps8_iefp.c core_read2 (cpu.iefpFinalAddress, result + 0, result + 1, __func__); cpu 804 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "Read2InstructionFetch ABBR evn"); cpu 805 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2InstructionFetch ABBR odd"); cpu 818 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "Read2InstructionFetch AB evn"); cpu 819 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2InstructionFetch AB odd"); cpu 828 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 829 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 830 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 831 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleInstructionFetch (result, 2); cpu 834 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 837 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2InstructionFetch BR"); cpu 838 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch BR evn"); cpu 839 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch BR odd"); cpu 843 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleInstructionFetch (result, 2); cpu 846 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 849 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2InstructionFetch"); cpu 850 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2InstructionFetch evn"); cpu 851 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2InstructionFetch odd"); cpu 860 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 865 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 866 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 867 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 868 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleRTCDOperandFetch (result, 2); cpu 871 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 874 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR"); cpu 875 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn"); cpu 876 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd"); cpu 880 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleRTCDOperandFetch (result, 2); cpu 883 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 886 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2"); cpu 887 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn"); cpu 888 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd"); cpu 895 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 899 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cpu 906 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 909 src/dps8/dps8_iefp.c core_read2 (cpu.iefpFinalAddress, result + 0, result + 1, __func__); cpu 916 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch ABBR evn"); cpu 917 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2IndirectWordFetch ABBR odd"); cpu 930 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch AB evn"); cpu 931 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2IndirectWordFetch AB odd"); cpu 940 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 941 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 942 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 943 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (result, 2); cpu 946 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read: bar iefpFinalAddress=" "%08o readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 949 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch BR"); cpu 950 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch BR evn"); cpu 951 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch BR odd"); cpu 955 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleIndirectWordFetch (result, 2); cpu 958 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read: iefpFinalAddress=%08o" " readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]); cpu 961 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2IndirectWordFetch"); cpu 962 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2IndirectWordFetch evn"); cpu 963 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2IndirectWordFetch odd"); cpu 974 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 978 src/dps8/dps8_iefp.c if (isAR || cpu.cu.XSF /*get_went_appending ()*/) cpu 990 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 993 src/dps8/dps8_iefp.c core_readN (cpu.iefpFinalAddress, result, 8, __func__); cpu 1005 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress + i, result [i], "Read8 ABBR"); cpu 1036 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 1037 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 1038 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1040 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataRead (result, 8); cpu 1047 src/dps8/dps8_iefp.c cpu.iefpFinalAddress + i, result [i]); cpu 1050 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read8 BAR"); cpu 1052 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result[i], "Read8 BAR"); cpu 1059 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataRead (result, 8); cpu 1061 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) cpu 1069 src/dps8/dps8_iefp.c cpu.iefpFinalAddress + i, result [i]); cpu 1072 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read8"); cpu 1074 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "Read8"); cpu 1086 src/dps8/dps8_iefp.c Read8 (address, result, cpu.currentInstruction.b29); cpu 1087 src/dps8/dps8_iefp.c Read8 (address + 8, result + 8, cpu.currentInstruction.b29); cpu 1098 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 1102 src/dps8/dps8_iefp.c if (isAR || cpu.cu.XSF /*get_went_appending ()*/) cpu 1114 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 1117 src/dps8/dps8_iefp.c core_readN (cpu.iefpFinalAddress, result, PGSZ, __func__); cpu 1129 src/dps8/dps8_iefp.c HDBGMRead (cpu.iefpFinalAddress + i, result [i], "ReadPage AB"); cpu 1160 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 1161 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 1162 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1164 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataRead (result, PGSZ); cpu 1171 src/dps8/dps8_iefp.c cpu.iefpFinalAddress + i, result [i]); cpu 1174 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadPage B"); cpu 1176 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage B"); cpu 1184 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataRead (result, PGSZ); cpu 1186 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) cpu 1194 src/dps8/dps8_iefp.c cpu.iefpFinalAddress + i, result [i]); cpu 1197 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadPage"); cpu 1199 src/dps8/dps8_iefp.c HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage"); cpu 1210 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 1214 src/dps8/dps8_iefp.c if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29)) cpu 1220 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 1223 src/dps8/dps8_iefp.c if (cyctyp == OPERAND_STORE && cpu.useZone) cpu 1224 src/dps8/dps8_iefp.c core_write_zone (cpu.iefpFinalAddress, data, __func__); cpu 1226 src/dps8/dps8_iefp.c core_write (cpu.iefpFinalAddress, data, __func__); cpu 1230 src/dps8/dps8_iefp.c HDBGMWrite (cpu.iefpFinalAddress, data, "Write ABBR"); cpu 1236 src/dps8/dps8_iefp.c if (cyctyp == OPERAND_STORE && cpu.useZone) cpu 1252 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 1253 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 1254 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1255 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = do_append_cycle (cyctyp, & data, 1); cpu 1256 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data); cpu 1258 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write BR"); cpu 1259 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write BR"); cpu 1263 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = do_append_cycle (cyctyp, & data, 1); cpu 1264 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data); cpu 1266 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write"); cpu 1267 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write"); cpu 1278 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 1282 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cpu 1288 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 1291 src/dps8/dps8_iefp.c core_write (cpu.iefpFinalAddress, data, __func__); cpu 1295 src/dps8/dps8_iefp.c HDBGMWrite (cpu.iefpFinalAddress, data, "WriteAPUDataStore ABBR"); cpu 1314 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 1315 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 1316 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1317 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataStore (& data, 1); cpu 1318 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data); cpu 1320 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteAPUDataStore BR"); cpu 1321 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore BR"); cpu 1325 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataStore (& data, 1); cpu 1326 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data); cpu 1328 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteAPUDataStore"); cpu 1329 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteAPUDataStore"); cpu 1338 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 1342 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cpu 1348 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 1351 src/dps8/dps8_iefp.c if (cpu.useZone) cpu 1352 src/dps8/dps8_iefp.c core_write_zone (cpu.iefpFinalAddress, data, __func__); cpu 1354 src/dps8/dps8_iefp.c core_write (cpu.iefpFinalAddress, data, __func__); cpu 1358 src/dps8/dps8_iefp.c HDBGMWrite (cpu.iefpFinalAddress, data, "WriteOperandStore ABBR"); cpu 1364 src/dps8/dps8_iefp.c if (cpu.useZone) cpu 1380 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 1381 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 1382 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1383 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleOperandStore (& data, 1); cpu 1384 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data); cpu 1386 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WriteOperandStore BR"); cpu 1387 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore BR"); cpu 1391 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleOperandStore (& data, 1); cpu 1392 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data); cpu 1394 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WriteOperandStore"); cpu 1395 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "WriteOperandStore"); cpu 1407 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 1410 src/dps8/dps8_iefp.c if (cpu.cu.XSF /*get_went_appending ()*/ || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29)) cpu 1419 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 1422 src/dps8/dps8_iefp.c core_write2 (cpu.iefpFinalAddress, data [0], data [1], cpu 1426 src/dps8/dps8_iefp.c HDBGMWrite (cpu.iefpFinalAddress, data [0], "Write2 ABBR evn"); cpu 1427 src/dps8/dps8_iefp.c HDBGMWrite (cpu.iefpFinalAddress+1, data [1], "Write2 ABBR odd"); cpu 1458 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 1459 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 1460 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1461 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = do_append_cycle (cyctyp, data, 2); cpu 1467 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2 BR"); cpu 1468 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 BR evn"); cpu 1469 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 BR odd"); cpu 1475 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = do_append_cycle (cyctyp, data, 2); cpu 1481 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2"); cpu 1482 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 evn"); cpu 1483 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 odd"); cpu 1494 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 1497 src/dps8/dps8_iefp.c if (cpu.cu.XSF || cpu.currentInstruction.b29) cpu 1503 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 1506 src/dps8/dps8_iefp.c core_write2 (cpu.iefpFinalAddress, data [0], data [1], __func__); cpu 1509 src/dps8/dps8_iefp.c HDBGMWrite (cpu.iefpFinalAddress, data [0], "Write2OperandStore ABBR evn"); cpu 1510 src/dps8/dps8_iefp.c HDBGMWrite (cpu.iefpFinalAddress+1, data [1], "Write2OperandStore ABBR odd"); cpu 1531 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 1532 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 1533 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1534 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleOperandStore (data, 2); cpu 1537 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2OperandStore BR"); cpu 1538 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore BR evn"); cpu 1539 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore BR odd"); cpu 1543 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleOperandStore (data, 2); cpu 1546 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2OperandStore"); cpu 1547 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2OperandStore evn"); cpu 1548 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2OperandStore odd"); cpu 1559 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 1561 src/dps8/dps8_iefp.c if (isAR || cpu.cu.XSF /*get_went_appending ()*/) cpu 1569 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 1572 src/dps8/dps8_iefp.c core_write (cpu.iefpFinalAddress, data, __func__); cpu 1579 src/dps8/dps8_iefp.c HDBGMWrite (cpu.iefpFinalAddress, data, "Write1 ABBR"); cpu 1605 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 1606 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 1607 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1609 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataStore (& data, 1); cpu 1613 src/dps8/dps8_iefp.c cpu.iefpFinalAddress, data); cpu 1615 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write1 BR"); cpu 1616 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1 BR"); cpu 1623 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataStore (& data, 1); cpu 1627 src/dps8/dps8_iefp.c cpu.iefpFinalAddress, data); cpu 1629 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write1"); cpu 1630 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1"); cpu 1641 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 1645 src/dps8/dps8_iefp.c if (isAR || cpu.cu.XSF /*get_went_appending ()*/) cpu 1654 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 1657 src/dps8/dps8_iefp.c core_writeN (cpu.iefpFinalAddress, data, 8, __func__); cpu 1669 src/dps8/dps8_iefp.c HDBGMWrite (cpu.iefpFinalAddress + i, data [i], "Write8 ABBR"); cpu 1700 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 1701 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 1702 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1704 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataStore (data, 8); cpu 1711 src/dps8/dps8_iefp.c cpu.iefpFinalAddress + i, data [i]); cpu 1714 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write8 BR"); cpu 1716 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8 BR"); cpu 1724 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataStore (data, 8); cpu 1731 src/dps8/dps8_iefp.c cpu.iefpFinalAddress + i, data [i]); cpu 1734 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write8"); cpu 1736 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8"); cpu 1748 src/dps8/dps8_iefp.c Write8 (address, data, cpu.currentInstruction.b29); cpu 1749 src/dps8/dps8_iefp.c Write8 (address + 8, data + 8, cpu.currentInstruction.b29); cpu 1757 src/dps8/dps8_iefp.c Write8 (address, data, cpu.currentInstruction.b29); cpu 1758 src/dps8/dps8_iefp.c Write8 (address + 8, data + 8, cpu.currentInstruction.b29); cpu 1759 src/dps8/dps8_iefp.c Write8 (address + 16, data + 16, cpu.currentInstruction.b29); cpu 1760 src/dps8/dps8_iefp.c Write8 (address + 24, data + 24, cpu.currentInstruction.b29); cpu 1770 src/dps8/dps8_iefp.c cpu.TPR.CA = cpu.iefpFinalAddress = address; cpu 1774 src/dps8/dps8_iefp.c if (isAR || cpu.cu.XSF /*get_went_appending ()*/) cpu 1783 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = get_BAR_address (address); cpu 1786 src/dps8/dps8_iefp.c core_writeN (cpu.iefpFinalAddress, data, PGSZ, __func__); cpu 1798 src/dps8/dps8_iefp.c HDBGMWrite (cpu.iefpFinalAddress + i, data [i], "WritePage ABBR"); cpu 1829 src/dps8/dps8_iefp.c cpu.TPR.CA = get_BAR_address (address); cpu 1830 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 1831 src/dps8/dps8_iefp.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1833 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataStore (data, PGSZ); cpu 1841 src/dps8/dps8_iefp.c cpu.iefpFinalAddress + i, data [i]); cpu 1844 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WritePage BR"); cpu 1846 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage BR"); cpu 1853 src/dps8/dps8_iefp.c cpu.iefpFinalAddress = doAppendCycleAPUDataStore (data, PGSZ); cpu 1860 src/dps8/dps8_iefp.c cpu.iefpFinalAddress + i, data [i]); cpu 1863 src/dps8/dps8_iefp.c HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WritePage"); cpu 1865 src/dps8/dps8_iefp.c HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage"); cpu 1876 src/dps8/dps8_iefp.c if (cpu.TPR.CA & 1) // is odd? cpu 1878 src/dps8/dps8_iefp.c ReadIndirectWordFetch (cpu.TPR.CA, cpu.itxPair); cpu 1879 src/dps8/dps8_iefp.c cpu.itxPair[1] = MASK36; // fill with ones for debugging cpu 1883 src/dps8/dps8_iefp.c Read2IndirectWordFetch (cpu.TPR.CA, cpu.itxPair); cpu 60 src/dps8/dps8_ins.c #define DBG_CTR cpu.cycleCnt cpu 91 src/dps8/dps8_ins.c DCDstruct * i = & cpu.currentInstruction; cpu 97 src/dps8/dps8_ins.c PNL (cpu.prepare_state |= ps_RAW); cpu 101 src/dps8/dps8_ins.c rTAG = GET_TAG (cpu.cu.IWB); cpu 117 src/dps8/dps8_ins.c core_read(cpu.char_word_address, &tmpdata, __func__); cpu 118 src/dps8/dps8_ins.c if (tmpdata != cpu.ou.character_data) cpu 120 src/dps8/dps8_ins.c (long long unsigned int)cpu.ou.character_data, cpu 121 src/dps8/dps8_ins.c (long long unsigned int)tmpdata, cpu.char_word_address); cpu 124 src/dps8/dps8_ins.c switch (cpu.ou.characterOperandSize) cpu 127 src/dps8/dps8_ins.c putChar (& cpu.ou.character_data, cpu.CY & 077, cpu.ou.characterOperandOffset); cpu 131 src/dps8/dps8_ins.c putByte (& cpu.ou.character_data, cpu.CY & 0777, cpu.ou.characterOperandOffset); cpu 139 src/dps8/dps8_ins.c PNL (cpu.prepare_state |= ps_SAW); cpu 143 src/dps8/dps8_ins.c core_write_unlock (cpu.char_word_address, cpu.ou.character_data, __func__); cpu 145 src/dps8/dps8_ins.c WriteOperandStore (cpu.ou.character_address, cpu.ou.character_data); cpu 151 src/dps8/dps8_ins.c __func__, cpu.ou.character_data, cpu.ou.character_address, cpu 152 src/dps8/dps8_ins.c cpu.ou.characterOperandSize, cpu.ou.characterOperandOffset); cpu 156 src/dps8/dps8_ins.c cpu.TPR.CA = cpu.ou.character_address; cpu 160 src/dps8/dps8_ins.c write_operand (cpu.TPR.CA, OPERAND_STORE); cpu 170 src/dps8/dps8_ins.c DCDstruct * i = & cpu.currentInstruction; cpu 176 src/dps8/dps8_ins.c "%s a %d address %08o\n", __func__, i->b29, cpu.TPR.CA); cpu 178 src/dps8/dps8_ins.c PNL (cpu.prepare_state |= ps_POA); cpu 182 src/dps8/dps8_ins.c rTAG = GET_TAG (cpu.cu.IWB); cpu 192 src/dps8/dps8_ins.c cpu.CY = 0; cpu 193 src/dps8/dps8_ins.c SETHI (cpu.CY, cpu.TPR.CA); cpu 195 src/dps8/dps8_ins.c "%s DU CY=%012"PRIo64"\n", __func__, cpu.CY); cpu 205 src/dps8/dps8_ins.c cpu.CY = 0; cpu 206 src/dps8/dps8_ins.c SETLO (cpu.CY, cpu.TPR.CA); cpu 208 src/dps8/dps8_ins.c "%s DL CY=%012"PRIo64"\n", __func__, cpu.CY); cpu 222 src/dps8/dps8_ins.c switch (cpu.ou.characterOperandSize) cpu 225 src/dps8/dps8_ins.c cpu.CY = GETCHAR (cpu.ou.character_data, cpu.ou.characterOperandOffset); cpu 229 src/dps8/dps8_ins.c cpu.CY = GETBYTE (cpu.ou.character_data, cpu.ou.characterOperandOffset); cpu 236 src/dps8/dps8_ins.c __func__, cpu.ou.character_data, cpu.ou.character_address, cpu.CY); cpu 239 src/dps8/dps8_ins.c cpu.TPR.CA = cpu.ou.character_address; cpu 245 src/dps8/dps8_ins.c readOperandRMW (cpu.TPR.CA); cpu 247 src/dps8/dps8_ins.c readOperandRead (cpu.TPR.CA); cpu 249 src/dps8/dps8_ins.c readOperandRead (cpu.TPR.CA); cpu 257 src/dps8/dps8_ins.c if (cpu.TPR.CA & 1) cpu 258 src/dps8/dps8_ins.c ReadOperandRead (cpu.TPR.CA, &cpu.CY); cpu 260 src/dps8/dps8_ins.c Read2OperandRead (cpu.TPR.CA, cpu.Ypair); cpu 261 src/dps8/dps8_ins.c if (! (get_addr_mode () == APPEND_mode || cpu.cu.TSN_VALID [0] || cpu 262 src/dps8/dps8_ins.c cpu.cu.XSF || cpu.currentInstruction.b29 /*get_went_appending ()*/)) cpu 264 src/dps8/dps8_ins.c if (cpu.currentInstruction.info->flags & TSPN_INS) cpu 267 src/dps8/dps8_ins.c if (cpu.currentInstruction.opcode <= 0273) //-V536 cpu 268 src/dps8/dps8_ins.c n = (cpu.currentInstruction.opcode & 3); cpu 270 src/dps8/dps8_ins.c n = (cpu.currentInstruction.opcode & 3) + 4; cpu 276 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.PPR.PRR; cpu 280 src/dps8/dps8_ins.c cpu.PR[n].SNR = cpu.PPR.PSR; cpu 281 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; cpu 287 src/dps8/dps8_ins.c cpu.PPR.IC = cpu.TPR.CA; cpu 292 src/dps8/dps8_ins.c __func__, cpu.PPR.PSR, cpu.PPR.IC); cpu 293 src/dps8/dps8_ins.c if (cpu.PPR.IC & 1) cpu 295 src/dps8/dps8_ins.c cpu.cu.IWB = cpu.CY; cpu 296 src/dps8/dps8_ins.c cpu.cu.IRODD = cpu.CY; cpu 300 src/dps8/dps8_ins.c cpu.cu.IWB = cpu.Ypair[0]; cpu 301 src/dps8/dps8_ins.c cpu.cu.IRODD = cpu.Ypair[1]; cpu 326 src/dps8/dps8_ins.c putbits36_3 (& words[0], 0, cpu.PPR.PRR); cpu 327 src/dps8/dps8_ins.c putbits36_15 (& words[0], 3, cpu.PPR.PSR); cpu 328 src/dps8/dps8_ins.c putbits36_1 (& words[0], 18, cpu.PPR.P); cpu 329 src/dps8/dps8_ins.c putbits36_1 (& words[0], 19, cpu.cu.XSF); cpu 331 src/dps8/dps8_ins.c putbits36_1 (& words[0], 21, cpu.cu.SD_ON); cpu 333 src/dps8/dps8_ins.c putbits36_1 (& words[0], 23, cpu.cu.PT_ON); cpu 335 src/dps8/dps8_ins.c cpu 336 src/dps8/dps8_ins.c cpu 337 src/dps8/dps8_ins.c cpu 338 src/dps8/dps8_ins.c cpu 339 src/dps8/dps8_ins.c cpu 340 src/dps8/dps8_ins.c cpu 341 src/dps8/dps8_ins.c cpu 342 src/dps8/dps8_ins.c cpu 343 src/dps8/dps8_ins.c cpu 350 src/dps8/dps8_ins.c putbits36_12 (& words[0], 24, cpu.cu.APUCycleBits); cpu 355 src/dps8/dps8_ins.c putbits36_1 (& words[1], 0, cpu.cu.IRO_ISN); cpu 356 src/dps8/dps8_ins.c putbits36_1 (& words[1], 1, cpu.cu.OEB_IOC); cpu 357 src/dps8/dps8_ins.c putbits36_1 (& words[1], 2, cpu.cu.EOFF_IAIM); cpu 358 src/dps8/dps8_ins.c putbits36_1 (& words[1], 3, cpu.cu.ORB_ISP); cpu 359 src/dps8/dps8_ins.c putbits36_1 (& words[1], 4, cpu.cu.ROFF_IPR); cpu 360 src/dps8/dps8_ins.c putbits36_1 (& words[1], 5, cpu.cu.OWB_NEA); cpu 361 src/dps8/dps8_ins.c putbits36_1 (& words[1], 6, cpu.cu.WOFF_OOB); cpu 362 src/dps8/dps8_ins.c putbits36_1 (& words[1], 7, cpu.cu.NO_GA); cpu 363 src/dps8/dps8_ins.c putbits36_1 (& words[1], 8, cpu.cu.OCB); cpu 364 src/dps8/dps8_ins.c putbits36_1 (& words[1], 9, cpu.cu.OCALL); cpu 365 src/dps8/dps8_ins.c putbits36_1 (& words[1], 10, cpu.cu.BOC); cpu 366 src/dps8/dps8_ins.c putbits36_1 (& words[1], 11, cpu.cu.PTWAM_ER); cpu 367 src/dps8/dps8_ins.c putbits36_1 (& words[1], 12, cpu.cu.CRT); cpu 368 src/dps8/dps8_ins.c putbits36_1 (& words[1], 13, cpu.cu.RALR); cpu 369 src/dps8/dps8_ins.c putbits36_1 (& words[1], 14, cpu.cu.SDWAM_ER); cpu 370 src/dps8/dps8_ins.c putbits36_1 (& words[1], 15, cpu.cu.OOSB); cpu 371 src/dps8/dps8_ins.c putbits36_1 (& words[1], 16, cpu.cu.PARU); cpu 372 src/dps8/dps8_ins.c putbits36_1 (& words[1], 17, cpu.cu.PARL); cpu 373 src/dps8/dps8_ins.c putbits36_1 (& words[1], 18, cpu.cu.ONC1); cpu 374 src/dps8/dps8_ins.c putbits36_1 (& words[1], 19, cpu.cu.ONC2); cpu 375 src/dps8/dps8_ins.c putbits36_4 (& words[1], 20, cpu.cu.IA); cpu 376 src/dps8/dps8_ins.c putbits36_3 (& words[1], 24, cpu.cu.IACHN); cpu 377 src/dps8/dps8_ins.c putbits36_3 (& words[1], 27, cpu.cu.CNCHN); cpu 378 src/dps8/dps8_ins.c putbits36_5 (& words[1], 30, cpu.cu.FI_ADDR); cpu 379 src/dps8/dps8_ins.c putbits36_1 (& words[1], 35, cpu.cycle == INTERRUPT_cycle ? 0 : 1); cpu 383 src/dps8/dps8_ins.c putbits36_3 (& words[2], 0, cpu.TPR.TRR); cpu 384 src/dps8/dps8_ins.c putbits36_15 (& words[2], 3, cpu.TPR.TSR); cpu 388 src/dps8/dps8_ins.c putbits36_3 (& words[2], 27, (word3) cpu.switches.cpu_num); cpu 389 src/dps8/dps8_ins.c putbits36_6 (& words[2], 30, cpu.cu.delta); cpu 393 src/dps8/dps8_ins.c putbits36_3 (& words[3], 18, cpu.cu.TSN_VALID[0] ? cpu.cu.TSN_PRNO[0] : 0); cpu 394 src/dps8/dps8_ins.c putbits36_1 (& words[3], 21, cpu.cu.TSN_VALID[0]); cpu 395 src/dps8/dps8_ins.c putbits36_3 (& words[3], 22, cpu.cu.TSN_VALID[1] ? cpu.cu.TSN_PRNO[1] : 0); cpu 396 src/dps8/dps8_ins.c putbits36_1 (& words[3], 25, cpu.cu.TSN_VALID[1]); cpu 397 src/dps8/dps8_ins.c putbits36_3 (& words[3], 26, cpu.cu.TSN_VALID[2] ? cpu.cu.TSN_PRNO[2] : 0); cpu 398 src/dps8/dps8_ins.c putbits36_1 (& words[3], 29, cpu.cu.TSN_VALID[2]); cpu 399 src/dps8/dps8_ins.c putbits36_6 (& words[3], 30, cpu.TPR.TBR); cpu 403 src/dps8/dps8_ins.c putbits36_18 (& words[4], 0, cpu.PPR.IC); cpu 407 src/dps8/dps8_ins.c putbits36_18 (& words[4], 18, cpu.cu.IR); cpu 444 src/dps8/dps8_ins.c putbits36 (& words[5], 0, 18, cpu.TPR.CA); cpu 445 src/dps8/dps8_ins.c putbits36 (& words[5], 18, 1, cpu.cu.repeat_first); cpu 446 src/dps8/dps8_ins.c putbits36 (& words[5], 19, 1, cpu.cu.rpt); cpu 447 src/dps8/dps8_ins.c putbits36 (& words[5], 20, 1, cpu.cu.rd); cpu 448 src/dps8/dps8_ins.c putbits36 (& words[5], 21, 1, cpu.cu.rl); cpu 449 src/dps8/dps8_ins.c putbits36 (& words[5], 22, 1, cpu.cu.pot); cpu 451 src/dps8/dps8_ins.c putbits36_1 (& words[5], 24, cpu.cu.xde); cpu 452 src/dps8/dps8_ins.c putbits36_1 (& words[5], 25, cpu.cu.xdo); cpu 453 src/dps8/dps8_ins.c putbits36_1 (& words[5], 26, cpu.cu.itp); cpu 454 src/dps8/dps8_ins.c putbits36_1 (& words[5], 27, cpu.cu.rfi); cpu 455 src/dps8/dps8_ins.c putbits36_1 (& words[5], 28, cpu.cu.its); cpu 456 src/dps8/dps8_ins.c putbits36_1 (& words[5], 29, cpu.cu.FIF); cpu 457 src/dps8/dps8_ins.c putbits36_6 (& words[5], 30, cpu.cu.CT_HOLD); cpu 461 src/dps8/dps8_ins.c words[6] = cpu.cu.IWB; cpu 465 src/dps8/dps8_ins.c words[7] = cpu.cu.IRODD; cpu 471 src/dps8/dps8_ins.c if (cpu.tweaks.isolts_mode) cpu 545 src/dps8/dps8_ins.c scu2words (cpu.scu_data); cpu 547 src/dps8/dps8_ins.c cpu.cu_data.PSR = cpu.PPR.PSR; cpu 548 src/dps8/dps8_ins.c cpu.cu_data.PRR = cpu.PPR.PRR; cpu 549 src/dps8/dps8_ins.c cpu.cu_data.IC = cpu.PPR.IC; cpu 561 src/dps8/dps8_ins.c cpu.cu.delta = 0; cpu 562 src/dps8/dps8_ins.c cpu.cu.repeat_first = false; cpu 563 src/dps8/dps8_ins.c cpu.cu.rpt = false; cpu 564 src/dps8/dps8_ins.c cpu.cu.rd = false; cpu 565 src/dps8/dps8_ins.c cpu.cu.rl = false; cpu 566 src/dps8/dps8_ins.c cpu.cu.pot = false; cpu 567 src/dps8/dps8_ins.c cpu.cu.itp = false; cpu 568 src/dps8/dps8_ins.c cpu.cu.its = false; cpu 569 src/dps8/dps8_ins.c cpu.cu.xde = false; cpu 570 src/dps8/dps8_ins.c cpu.cu.xdo = false; cpu 580 src/dps8/dps8_ins.c cpu.PPR.PRR = getbits36_3 (words[0], 0); cpu 581 src/dps8/dps8_ins.c cpu.PPR.PSR = getbits36_15 (words[0], 3); cpu 582 src/dps8/dps8_ins.c cpu.PPR.P = getbits36_1 (words[0], 18); cpu 583 src/dps8/dps8_ins.c cpu.cu.XSF = getbits36_1 (words[0], 19); cpu 584 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s sets XSF to %o\n", __func__, cpu.cu.XSF); cpu 603 src/dps8/dps8_ins.c cpu.cu.APUCycleBits = (word12) ((cpu.cu.APUCycleBits & 07770) | (word12) getbits36_3 (words[0], 33)); cpu 608 src/dps8/dps8_ins.c cpu 609 src/dps8/dps8_ins.c cpu 610 src/dps8/dps8_ins.c cpu 611 src/dps8/dps8_ins.c cpu 612 src/dps8/dps8_ins.c cpu 613 src/dps8/dps8_ins.c cpu 614 src/dps8/dps8_ins.c cpu 615 src/dps8/dps8_ins.c cpu 616 src/dps8/dps8_ins.c cpu 617 src/dps8/dps8_ins.c cpu 618 src/dps8/dps8_ins.c cpu 619 src/dps8/dps8_ins.c cpu 620 src/dps8/dps8_ins.c cpu 621 src/dps8/dps8_ins.c cpu 622 src/dps8/dps8_ins.c cpu 623 src/dps8/dps8_ins.c cpu 624 src/dps8/dps8_ins.c cpu 625 src/dps8/dps8_ins.c cpu 626 src/dps8/dps8_ins.c cpu 627 src/dps8/dps8_ins.c cpu 628 src/dps8/dps8_ins.c cpu 629 src/dps8/dps8_ins.c cpu 630 src/dps8/dps8_ins.c cpu 631 src/dps8/dps8_ins.c cpu 632 src/dps8/dps8_ins.c cpu 637 src/dps8/dps8_ins.c cpu.TPR.TRR = getbits36_3 (words[2], 0); cpu 638 src/dps8/dps8_ins.c cpu.TPR.TSR = getbits36_15 (words[2], 3); cpu 643 src/dps8/dps8_ins.c cpu.cu.delta = getbits36_6 (words[2], 30); cpu 649 src/dps8/dps8_ins.c cpu.cu.TSN_PRNO[0] = getbits36_3 (words[3], 18); cpu 650 src/dps8/dps8_ins.c cpu.cu.TSN_VALID[0] = getbits36_1 (words[3], 21); cpu 651 src/dps8/dps8_ins.c cpu.cu.TSN_PRNO[1] = getbits36_3 (words[3], 22); cpu 652 src/dps8/dps8_ins.c cpu.cu.TSN_VALID[1] = getbits36_1 (words[3], 25); cpu 653 src/dps8/dps8_ins.c cpu.cu.TSN_PRNO[2] = getbits36_3 (words[3], 26); cpu 654 src/dps8/dps8_ins.c cpu.cu.TSN_VALID[2] = getbits36_1 (words[3], 29); cpu 655 src/dps8/dps8_ins.c cpu.TPR.TBR = getbits36_6 (words[3], 30); cpu 659 src/dps8/dps8_ins.c cpu.cu.IR = getbits36_18 (words[4], 18); // HWR cpu 660 src/dps8/dps8_ins.c cpu.PPR.IC = getbits36_18 (words[4], 0); cpu 666 src/dps8/dps8_ins.c cpu.cu.repeat_first = getbits36_1 (words[5], 18); cpu 667 src/dps8/dps8_ins.c cpu.cu.rpt = getbits36_1 (words[5], 19); cpu 668 src/dps8/dps8_ins.c cpu.cu.rd = getbits36_1 (words[5], 20); cpu 669 src/dps8/dps8_ins.c cpu.cu.rl = getbits36_1 (words[5], 21); cpu 670 src/dps8/dps8_ins.c cpu.cu.pot = getbits36_1 (words[5], 22); cpu 672 src/dps8/dps8_ins.c cpu.cu.xde = getbits36_1 (words[5], 24); cpu 673 src/dps8/dps8_ins.c cpu.cu.xdo = getbits36_1 (words[5], 25); cpu 674 src/dps8/dps8_ins.c cpu.cu.itp = getbits36_1 (words[5], 26); cpu 675 src/dps8/dps8_ins.c cpu.cu.rfi = getbits36_1 (words[5], 27); cpu 676 src/dps8/dps8_ins.c cpu.cu.its = getbits36_1 (words[5], 28); cpu 677 src/dps8/dps8_ins.c cpu.cu.FIF = getbits36_1 (words[5], 29); cpu 678 src/dps8/dps8_ins.c cpu.cu.CT_HOLD = getbits36_6 (words[5], 30); cpu 682 src/dps8/dps8_ins.c cpu.cu.IWB = words[6]; cpu 686 src/dps8/dps8_ins.c cpu.cu.IRODD = words[7]; cpu 691 src/dps8/dps8_ins.c words2scu (cpu.scu_data); cpu 692 src/dps8/dps8_ins.c decode_instruction (IWB_IRODD, & cpu.currentInstruction); cpu 699 src/dps8/dps8_ins.c if (cpu.tweaks.isolts_mode) cpu 703 src/dps8/dps8_ins.c words[i] = cpu.du.image[i]; cpu 713 src/dps8/dps8_ins.c putbits36_1 (& words[0], 9, cpu.du.Z); cpu 714 src/dps8/dps8_ins.c putbits36_1 (& words[0], 10, cpu.du.NOP); cpu 715 src/dps8/dps8_ins.c putbits36_24 (& words[0], 12, cpu.du.CHTALLY); cpu 719 src/dps8/dps8_ins.c if (cpu.tweaks.isolts_mode) cpu 724 src/dps8/dps8_ins.c putbits36_18 (& words[2], 0, cpu.du.D1_PTR_W); cpu 725 src/dps8/dps8_ins.c putbits36_6 (& words[2], 18, cpu.du.D1_PTR_B); cpu 726 src/dps8/dps8_ins.c putbits36_2 (& words[2], 25, cpu.du.TAk[0]); cpu 727 src/dps8/dps8_ins.c putbits36_1 (& words[2], 31, cpu.du.F1); cpu 728 src/dps8/dps8_ins.c putbits36_1 (& words[2], 32, cpu.du.Ak[0]); cpu 732 src/dps8/dps8_ins.c putbits36_10 (& words[3], 0, cpu.du.LEVEL1); cpu 733 src/dps8/dps8_ins.c putbits36_24 (& words[3], 12, cpu.du.D1_RES); cpu 737 src/dps8/dps8_ins.c putbits36_18 (& words[4], 0, cpu.du.D2_PTR_W); cpu 738 src/dps8/dps8_ins.c putbits36_6 (& words[4], 18, cpu.du.D2_PTR_B); cpu 739 src/dps8/dps8_ins.c putbits36_2 (& words[4], 25, cpu.du.TAk[1]); cpu 740 src/dps8/dps8_ins.c putbits36_1 (& words[4], 30, cpu.du.R); cpu 741 src/dps8/dps8_ins.c putbits36_1 (& words[4], 31, cpu.du.F2); cpu 742 src/dps8/dps8_ins.c putbits36_1 (& words[4], 32, cpu.du.Ak[1]); cpu 746 src/dps8/dps8_ins.c putbits36_10 (& words[5], 0, cpu.du.LEVEL2); cpu 747 src/dps8/dps8_ins.c putbits36_24 (& words[5], 12, cpu.du.D2_RES); cpu 751 src/dps8/dps8_ins.c putbits36_18 (& words[6], 0, cpu.du.D3_PTR_W); cpu 752 src/dps8/dps8_ins.c putbits36_6 (& words[6], 18, cpu.du.D3_PTR_B); cpu 753 src/dps8/dps8_ins.c putbits36_2 (& words[6], 25, cpu.du.TAk[2]); cpu 754 src/dps8/dps8_ins.c putbits36_1 (& words[6], 31, cpu.du.F3); cpu 755 src/dps8/dps8_ins.c putbits36_1 (& words[6], 32, cpu.du.Ak[2]); cpu 756 src/dps8/dps8_ins.c putbits36_3 (& words[6], 33, cpu.du.JMP); cpu 760 src/dps8/dps8_ins.c putbits36_24 (& words[7], 12, cpu.du.D3_RES); cpu 769 src/dps8/dps8_ins.c cpu.du.Z = getbits36_1 (words[0], 9); cpu 770 src/dps8/dps8_ins.c cpu.du.NOP = getbits36_1 (words[0], 10); cpu 771 src/dps8/dps8_ins.c cpu.du.CHTALLY = getbits36_24 (words[0], 12); cpu 776 src/dps8/dps8_ins.c cpu.du.D1_PTR_W = getbits36_18 (words[2], 0); cpu 777 src/dps8/dps8_ins.c cpu.du.D1_PTR_B = getbits36_6 (words[2], 18); cpu 778 src/dps8/dps8_ins.c cpu.du.TAk[0] = getbits36_2 (words[2], 25); cpu 779 src/dps8/dps8_ins.c cpu.du.F1 = getbits36_1 (words[2], 31); cpu 780 src/dps8/dps8_ins.c cpu.du.Ak[0] = getbits36_1 (words[2], 32); cpu 784 src/dps8/dps8_ins.c cpu.du.LEVEL1 = getbits36_10 (words[3], 0); cpu 785 src/dps8/dps8_ins.c cpu.du.D1_RES = getbits36_24 (words[3], 12); cpu 789 src/dps8/dps8_ins.c cpu.du.D2_PTR_W = getbits36_18 (words[4], 0); cpu 790 src/dps8/dps8_ins.c cpu.du.D2_PTR_B = getbits36_6 (words[4], 18); cpu 791 src/dps8/dps8_ins.c cpu.du.TAk[1] = getbits36_2 (words[4], 25); cpu 792 src/dps8/dps8_ins.c cpu.du.F2 = getbits36_1 (words[4], 31); cpu 793 src/dps8/dps8_ins.c cpu.du.Ak[1] = getbits36_1 (words[4], 32); cpu 797 src/dps8/dps8_ins.c cpu.du.LEVEL2 = getbits36_1 (words[5], 9); cpu 798 src/dps8/dps8_ins.c cpu.du.D2_RES = getbits36_24 (words[5], 12); cpu 802 src/dps8/dps8_ins.c cpu.du.D3_PTR_W = getbits36_18 (words[6], 0); cpu 803 src/dps8/dps8_ins.c cpu.du.D3_PTR_B = getbits36_6 (words[6], 18); cpu 804 src/dps8/dps8_ins.c cpu.du.TAk[2] = getbits36_2 (words[6], 25); cpu 805 src/dps8/dps8_ins.c cpu.du.F3 = getbits36_1 (words[6], 31); cpu 806 src/dps8/dps8_ins.c cpu.du.Ak[2] = getbits36_1 (words[6], 32); cpu 807 src/dps8/dps8_ins.c cpu.du.JMP = getbits36_3 (words[6], 33); cpu 811 src/dps8/dps8_ins.c cpu.du.D3_RES = getbits36_24 (words[7], 12); cpu 813 src/dps8/dps8_ins.c if (cpu.tweaks.isolts_mode) cpu 817 src/dps8/dps8_ins.c cpu.du.image[i] = words[i]; cpu 1097 src/dps8/dps8_ins.c cpu.TPR.TRR = 0; cpu 1098 src/dps8/dps8_ins.c cpu.RSDWH_R1 = 0; cpu 1102 src/dps8/dps8_ins.c if (cpu.cu.rd && ((cpu.PPR.IC & 1) != 0)) cpu 1104 src/dps8/dps8_ins.c if (cpu.cu.repeat_first) cpu 1110 src/dps8/dps8_ins.c else if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) cpu 1112 src/dps8/dps8_ins.c if (cpu.cu.repeat_first) cpu 1116 src/dps8/dps8_ins.c ReadInstructionFetch (addr, & cpu.cu.IWB); cpu 1123 src/dps8/dps8_ins.c cpu.cu.IWB = tmp[0]; cpu 1124 src/dps8/dps8_ins.c cpu.cu.IRODD = tmp[1]; cpu 1138 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) // Even cpu 1144 src/dps8/dps8_ins.c cpu.cu.IWB = tmp[0]; cpu 1145 src/dps8/dps8_ins.c cpu.cu.IRODD = tmp[1]; cpu 1149 src/dps8/dps8_ins.c ReadInstructionFetch (addr, & cpu.cu.IWB); cpu 1150 src/dps8/dps8_ins.c cpu.cu.IRODD = cpu.cu.IWB; cpu 1165 src/dps8/dps8_ins.c char * where = lookup_address (cpu.PPR.PSR, cpu.PPR.IC, & compname, cpu 1175 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); cpu 1179 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o %s\n", cpu.PPR.IC, where); cpu 1187 src/dps8/dps8_ins.c cpu.PPR.PSR, cpu 1188 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); cpu 1193 src/dps8/dps8_ins.c cpu.PPR.PSR, cpu.PPR.IC, where); cpu 1206 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu 1207 src/dps8/dps8_ins.c cpu.PPR.IC, cpu 1210 src/dps8/dps8_ins.c cpu.currentInstruction.address, cpu 1211 src/dps8/dps8_ins.c cpu.currentInstruction.opcode, cpu 1212 src/dps8/dps8_ins.c cpu.currentInstruction.opcodeX, cpu 1213 src/dps8/dps8_ins.c cpu.currentInstruction.b29, cpu 1214 src/dps8/dps8_ins.c cpu.currentInstruction.i, cpu 1215 src/dps8/dps8_ins.c GET_TM (cpu.currentInstruction.tag) >> 4, cpu 1216 src/dps8/dps8_ins.c GET_TD (cpu.currentInstruction.tag) & 017); cpu 1224 src/dps8/dps8_ins.c cpu.PPR.IC, cpu 1227 src/dps8/dps8_ins.c cpu.currentInstruction.address, cpu 1228 src/dps8/dps8_ins.c cpu.currentInstruction.opcode, cpu 1229 src/dps8/dps8_ins.c cpu.currentInstruction.opcodeX, cpu 1230 src/dps8/dps8_ins.c cpu.currentInstruction.b29, cpu 1231 src/dps8/dps8_ins.c cpu.currentInstruction.i, cpu 1232 src/dps8/dps8_ins.c GET_TM (cpu.currentInstruction.tag) >> 4, cpu 1233 src/dps8/dps8_ins.c GET_TD (cpu.currentInstruction.tag) & 017); cpu 1244 src/dps8/dps8_ins.c cpu.PPR.PSR, cpu 1245 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu 1246 src/dps8/dps8_ins.c cpu.PPR.IC, cpu 1247 src/dps8/dps8_ins.c cpu.PPR.PRR, cpu 1250 src/dps8/dps8_ins.c cpu.currentInstruction.address, cpu 1251 src/dps8/dps8_ins.c cpu.currentInstruction.opcode, cpu 1252 src/dps8/dps8_ins.c cpu.currentInstruction.opcodeX, cpu 1253 src/dps8/dps8_ins.c cpu.currentInstruction.b29, cpu.currentInstruction.i, cpu 1254 src/dps8/dps8_ins.c GET_TM (cpu.currentInstruction.tag) >> 4, cpu 1255 src/dps8/dps8_ins.c GET_TD (cpu.currentInstruction.tag) & 017); cpu 1263 src/dps8/dps8_ins.c cpu.PPR.PSR, cpu 1264 src/dps8/dps8_ins.c cpu.PPR.IC, cpu 1265 src/dps8/dps8_ins.c cpu.PPR.PRR, cpu 1268 src/dps8/dps8_ins.c cpu.currentInstruction.address, cpu 1269 src/dps8/dps8_ins.c cpu.currentInstruction.opcode, cpu 1270 src/dps8/dps8_ins.c cpu.currentInstruction.opcodeX, cpu 1271 src/dps8/dps8_ins.c cpu.currentInstruction.b29, cpu 1272 src/dps8/dps8_ins.c cpu.currentInstruction.i, cpu 1273 src/dps8/dps8_ins.c GET_TM (cpu.currentInstruction.tag) >> 4, cpu 1274 src/dps8/dps8_ins.c GET_TD (cpu.currentInstruction.tag) & 017); cpu 1284 src/dps8/dps8_ins.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) cpu 1288 src/dps8/dps8_ins.c if ((cpu.rX[0] & 00001) == 0) cpu 1300 src/dps8/dps8_ins.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) cpu 1304 src/dps8/dps8_ins.c if ((cpu.rX[0] & 00001) == 0) cpu 1316 src/dps8/dps8_ins.c trk (cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IWB_IRODD); cpu 1373 src/dps8/dps8_ins.c DCDstruct * ci = & cpu.currentInstruction; cpu 1380 src/dps8/dps8_ins.c const bool restart = cpu.cu.rfi; // instruction is to be restarted cpu 1381 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cpu 1411 src/dps8/dps8_ins.c if (unlikely (cpu.MR.emr && cpu.MR.OC_TRAP)) { cpu 1412 src/dps8/dps8_ins.c if (cpu.MR.OPCODE == opcode && cpu.MR.OPCODEX == opcodeX) { cpu 1413 src/dps8/dps8_ins.c if (cpu.MR.ihrrs) { cpu 1414 src/dps8/dps8_ins.c cpu.MR.ihr = 0; cpu 1428 src/dps8/dps8_ins.c cpu.cu.TSN_VALID[0] = 0; cpu 1429 src/dps8/dps8_ins.c cpu.cu.TSN_VALID[1] = 0; cpu 1430 src/dps8/dps8_ins.c cpu.cu.TSN_VALID[2] = 0; cpu 1431 src/dps8/dps8_ins.c cpu.cu.TSN_PRNO[0] = 0; cpu 1432 src/dps8/dps8_ins.c cpu.cu.TSN_PRNO[1] = 0; cpu 1433 src/dps8/dps8_ins.c cpu.cu.TSN_PRNO[2] = 0; cpu 1443 src/dps8/dps8_ins.c cpu.cu.XSF = 0; cpu 1445 src/dps8/dps8_ins.c cpu.cu.pot = 0; cpu 1446 src/dps8/dps8_ins.c cpu.cu.its = 0; cpu 1447 src/dps8/dps8_ins.c cpu.cu.itp = 0; cpu 1451 src/dps8/dps8_ins.c PNL (L68_ (cpu.AR_F_E = false;)) cpu 1454 src/dps8/dps8_ins.c cpu.cu.APUCycleBits &= 07770; cpu 1461 src/dps8/dps8_ins.c if (unlikely (cpu.isXED)) { cpu 1466 src/dps8/dps8_ins.c if (opcode == 0717 && !opcodeX && cpu.cu.xde && cpu.cu.xdo /* even instruction being executed */) cpu 1472 src/dps8/dps8_ins.c if (cpu.cu.xde && cpu.cu.xdo /* even instr being executed */) cpu 1476 src/dps8/dps8_ins.c if (!cpu.cu.xde && cpu.cu.xdo /* odd instr being executed */ && !(cpu.PPR.IC & 1)) cpu 1479 src/dps8/dps8_ins.c } else if (unlikely (cpu.isExec)) { cpu 1482 src/dps8/dps8_ins.c if (opcode == 0560 && !opcodeX && cpu.cu.xde && !(cpu.PPR.IC & 1)) cpu 1492 src/dps8/dps8_ins.c if (unlikely (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) { cpu 1499 src/dps8/dps8_ins.c if (cpu.cu.rl) cpu 1525 src/dps8/dps8_ins.c if (unlikely (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) { cpu 1530 src/dps8/dps8_ins.c if (unlikely (cpu.cu.rl)) { cpu 1672 src/dps8/dps8_ins.c if (n_dbgevents && (dbgevt = (dbgevent_lookup (cpu.PPR.PSR, cpu.PPR.IC))) >= 0) { cpu 1697 src/dps8/dps8_ins.c cpu.du.JMP = (word3) ndes; cpu 1698 src/dps8/dps8_ins.c cpu.dlyFlt = false; cpu 1704 src/dps8/dps8_ins.c if (unlikely (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl)) { cpu 1763 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD first %d rpt %d rd %d e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], !! (cpu.rX[0] & 01000), !! (cpu.rX[0] & 0400)); cpu 1764 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD CA %06o\n", cpu.TPR.CA); cpu 1768 src/dps8/dps8_ins.c if (cpu.cu.repeat_first) { cpu 1773 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); cpu 1777 src/dps8/dps8_ins.c if (cpu.cu.rpt || (cpu.cu.rd && icOdd) || cpu.cu.rl) cpu 1778 src/dps8/dps8_ins.c cpu.cu.repeat_first = false; cpu 1783 src/dps8/dps8_ins.c if (cpu.cu.rpt || // rpt cpu 1784 src/dps8/dps8_ins.c (cpu.cu.rd && icEven) || // rpd & even cpu 1785 src/dps8/dps8_ins.c (cpu.cu.rd && icOdd) || // rpd & odd cpu 1786 src/dps8/dps8_ins.c cpu.cu.rl) { // rl cpu 1794 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d was %06o\n", Xn, cpu.rX[Xn]); cpu 1796 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + offset) & AMASK; cpu 1797 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; cpu 1801 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu 1821 src/dps8/dps8_ins.c cpu.du.CHTALLY = 0; cpu 1822 src/dps8/dps8_ins.c cpu.du.Z = 1; cpu 1834 src/dps8/dps8_ins.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1835 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 1844 src/dps8/dps8_ins.c word18 saveIC = cpu.PPR.IC; cpu 1846 src/dps8/dps8_ins.c ReadInstructionFetch (cpu.PPR.IC + 1 + n, & cpu.currentEISinstruction.op[n]); cpu 1847 src/dps8/dps8_ins.c cpu.PPR.IC = saveIC; cpu 1851 src/dps8/dps8_ins.c PNL (cpu.IWRAddr = cpu.currentEISinstruction.op[0]); cpu 1875 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, "doPtrReg: PR[%o] SNR=%05o RNR=%o WORDNO=%06o " "BITNO=%02o\n", n, cpu.PAR[n].SNR, cpu.PAR[n].RNR, cpu.PAR[n].WORDNO, GET_PR_BITNO (n)); cpu 1882 src/dps8/dps8_ins.c cpu.TPR.TBR = GET_PR_BITNO (n); cpu 1884 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PAR[n].SNR; cpu 1886 src/dps8/dps8_ins.c cpu.TPR.TRR = max (cpu.PAR[n].RNR, cpu.PPR.PRR); cpu 1888 src/dps8/dps8_ins.c cpu.TPR.TRR = max3 (cpu.PAR[n].RNR, cpu.TPR.TRR, cpu.PPR.PRR); cpu 1890 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, "doPtrReg: n=%o offset=%05o TPR.CA=%06o " "TPR.TBR=%o TPR.TSR=%05o TPR.TRR=%o\n", n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR); cpu 1904 src/dps8/dps8_ins.c cpu.cu.TSN_VALID [0] = 0; cpu 1905 src/dps8/dps8_ins.c cpu.TPR.TBR = 0; cpu 1907 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 1908 src/dps8/dps8_ins.c cpu.TPR.TRR = 0; cpu 1909 src/dps8/dps8_ins.c cpu.RSDWH_R1 = 0; cpu 1916 src/dps8/dps8_ins.c cpu.cu.CT_HOLD = 0; // Clear interrupted IR mode flag cpu 1919 src/dps8/dps8_ins.c cpu.ou.directOperandFlag = false; cpu 1920 src/dps8/dps8_ins.c cpu.ou.directOperand = 0; cpu 1921 src/dps8/dps8_ins.c cpu.ou.characterOperandSize = 0; cpu 1922 src/dps8/dps8_ins.c cpu.ou.characterOperandOffset = 0; cpu 1923 src/dps8/dps8_ins.c cpu.ou.crflag = false; cpu 1928 src/dps8/dps8_ins.c PNL (L68_ (cpu.AR_F_E = true;)) cpu 1929 src/dps8/dps8_ins.c cpu.iefpFinalAddress = cpu.TPR.CA; cpu 1936 src/dps8/dps8_ins.c cpu.rmw_address = cpu.iefpFinalAddress; cpu 1938 src/dps8/dps8_ins.c if (cpu.cu.rl) { cpu 1941 src/dps8/dps8_ins.c cpu.lnk = GETHI36 (cpu.CY); cpu 1942 src/dps8/dps8_ins.c cpu.CY &= MASK18; cpu 1946 src/dps8/dps8_ins.c cpu.lnk = GETHI36 (cpu.Ypair[0]); cpu 1947 src/dps8/dps8_ins.c cpu.Ypair[0] &= MASK18; cpu 1955 src/dps8/dps8_ins.c PNL (cpu.IWRAddr = 0); cpu 1960 src/dps8/dps8_ins.c cpu.useZone = false; cpu 1961 src/dps8/dps8_ins.c cpu.zone = MASK36; cpu 1973 src/dps8/dps8_ins.c cpu.last_write = 0; cpu 1976 src/dps8/dps8_ins.c cpu.last_write = cpu.TPR.CA; cpu 1981 src/dps8/dps8_ins.c if (cpu.iefpFinalAddress != cpu.rmw_address) cpu 1982 src/dps8/dps8_ins.c sim_warn("executeInstruction: write addr changed %o %d\n", cpu.iefpFinalAddress, cpu.rmw_address); cpu 1983 src/dps8/dps8_ins.c core_write_unlock (cpu.iefpFinalAddress, cpu.CY, __func__); cpu 1985 src/dps8/dps8_ins.c HDBGMWrite (cpu.iefpFinalAddress, cpu.CY, "Write RMW"); cpu 1998 src/dps8/dps8_ins.c cpu.TPR.TRR = cpu.PPR.PRR; cpu 1999 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; cpu 2000 src/dps8/dps8_ins.c cpu.TPR.TBR = 0; cpu 2010 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); cpu 2019 src/dps8/dps8_ins.c bool rf = cpu.cu.repeat_first; cpu 2020 src/dps8/dps8_ins.c if (rf && cpu.cu.rd && icEven) cpu 2023 src/dps8/dps8_ins.c if (unlikely ((! rf) && (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl))) { cpu 2029 src/dps8/dps8_ins.c if (cpu.cu.rpt || cpu.cu.rd) { cpu 2032 src/dps8/dps8_ins.c bool rptA = !! (cpu.rX[0] & 01000); cpu 2033 src/dps8/dps8_ins.c bool rptB = !! (cpu.rX[0] & 00400); cpu 2035 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta first %d rf %d rpt %d rd %d " "e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, rf, cpu.cu.rpt, cpu.cu.rd, icOdd, cpu.rX[0], rptA, rptB); cpu 2037 src/dps8/dps8_ins.c if (cpu.cu.rpt) { // rpt cpu 2039 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IWB, 36 - 3); cpu 2040 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; cpu 2041 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; cpu 2045 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu 2052 src/dps8/dps8_ins.c if (cpu.cu.rd && icOdd && rptA) { // rpd, even instruction cpu 2055 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IWB, 36 - 3); cpu 2056 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; cpu 2057 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; cpu 2061 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu 2064 src/dps8/dps8_ins.c if (cpu.cu.rd && icOdd && rptB) { // rpdb, odd instruction cpu 2067 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IRODD, 36 - 3); cpu 2068 src/dps8/dps8_ins.c cpu.TPR.CA = (cpu.rX[Xn] + cpu.cu.delta) & AMASK; cpu 2069 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.TPR.CA; cpu 2073 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu 2091 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode) cpu 2092 src/dps8/dps8_ins.c flt = (cpu.cu.rl || cpu.cu.rpt || cpu.cu.rd) && cpu.dlyFlt; // L68 cpu 2094 src/dps8/dps8_ins.c flt = cpu.cu.rl && cpu.dlyFlt; cpu 2097 src/dps8/dps8_ins.c doFault (cpu.dlyFltNum, cpu.dlySubFltNum, cpu.dlyCtx); cpu 2104 src/dps8/dps8_ins.c if (cpu.cu.rpt || (cpu.cu.rd && icOdd) || cpu.cu.rl) { cpu 2111 src/dps8/dps8_ins.c uint x = (uint) getbits18 (cpu.rX[0], 0, 8); cpu 2116 src/dps8/dps8_ins.c putbits18 (& cpu.rX[0], 0, 8, x); cpu 2138 src/dps8/dps8_ins.c if (TST_I_ZERO && (cpu.rX[0] & 0100)) { cpu 2143 src/dps8/dps8_ins.c if (!TST_I_ZERO && (cpu.rX[0] & 040)) { cpu 2148 src/dps8/dps8_ins.c if (TST_I_NEG && (cpu.rX[0] & 020)) { cpu 2153 src/dps8/dps8_ins.c if (!TST_I_NEG && (cpu.rX[0] & 010)) { cpu 2158 src/dps8/dps8_ins.c if (TST_I_CARRY && (cpu.rX[0] & 04)) { cpu 2163 src/dps8/dps8_ins.c if (!TST_I_CARRY && (cpu.rX[0] & 02)) { cpu 2168 src/dps8/dps8_ins.c if (TST_I_OFLOW && (cpu.rX[0] & 01)) { cpu 2178 src/dps8/dps8_ins.c cpu.cu.rpt = false; cpu 2179 src/dps8/dps8_ins.c cpu.cu.rd = false; cpu 2180 src/dps8/dps8_ins.c cpu.cu.rl = false; cpu 2186 src/dps8/dps8_ins.c if (cpu.cu.rl) { cpu 2188 src/dps8/dps8_ins.c if (cpu.lnk == 0) { cpu 2190 src/dps8/dps8_ins.c cpu.cu.rpt = false; cpu 2191 src/dps8/dps8_ins.c cpu.cu.rd = false; cpu 2192 src/dps8/dps8_ins.c cpu.cu.rl = false; cpu 2196 src/dps8/dps8_ins.c uint Xn = (uint) getbits36_3 (cpu.cu.IWB, 36 - 3); cpu 2199 src/dps8/dps8_ins.c cpu.rX[Xn] = cpu.lnk; cpu 2207 src/dps8/dps8_ins.c if (unlikely (cpu.dlyFlt)) { cpu 2209 src/dps8/dps8_ins.c doFault (cpu.dlyFltNum, cpu.dlySubFltNum, cpu.dlyCtx); cpu 2216 src/dps8/dps8_ins.c cpu.instrCnt ++; cpu 2220 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPAQI, &cpu_dev, "A=%012"PRIo64" Q=%012"PRIo64" IR:%s\n", cpu.rA, cpu.rQ, dump_flags (buf, cpu.cu.IR)); cpu 2222 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPFLT, &cpu_dev, "E=%03o A=%012"PRIo64" Q=%012"PRIo64" %.10Lg\n", cpu.rE, cpu.rA, cpu.rQ, EAQToIEEElongdouble ()); cpu 2224 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPFLT, &cpu_dev, "E=%03o A=%012"PRIo64" Q=%012"PRIo64" %.10g\n", cpu.rE, cpu.rA, cpu.rQ, EAQToIEEEdouble ()); cpu 2226 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPIDX, &cpu_dev, "X[0]=%06o X[1]=%06o X[2]=%06o X[3]=%06o\n", cpu.rX[0], cpu.rX[1], cpu.rX[2], cpu.rX[3]); cpu 2227 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPIDX, &cpu_dev, "X[4]=%06o X[5]=%06o X[6]=%06o X[7]=%06o\n", cpu.rX[4], cpu.rX[5], cpu.rX[6], cpu.rX[7]); cpu 2229 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPPR, &cpu_dev, "PR%d/%s: SNR=%05o RNR=%o WORDNO=%06o BITNO:%02o ARCHAR:%o ARBITNO:%02o\n", n, PRalias[n], cpu.PR[n].SNR, cpu.PR[n].RNR, cpu.PR[n].WORDNO, GET_PR_BITNO (n), GET_AR_CHAR (n), GET_AR_BITNO (n)); cpu 2231 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPPPR, &cpu_dev, "PRR:%o PSR:%05o P:%o IC:%06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu 2232 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPDSBR, &cpu_dev, "ADDR:%08o BND:%05o U:%o STACK:%04o\n", cpu.DSBR.ADDR, cpu.DSBR.BND, cpu.DSBR.U, cpu.DSBR.STACK); cpu 2258 src/dps8/dps8_ins.c if (cpu.cu.rpt || cpu.cu.rd || cpu.cu.rl) cpu 2291 src/dps8/dps8_ins.c DCDstruct * i = & cpu.currentInstruction; cpu 2300 src/dps8/dps8_ins.c cpu.ou.eac = 0; cpu 2301 src/dps8/dps8_ins.c cpu.ou.RB1_FULL = 0; cpu 2302 src/dps8/dps8_ins.c cpu.ou.RP_FULL = 0; cpu 2303 src/dps8/dps8_ins.c cpu.ou.RS_FULL = 0; cpu 2304 src/dps8/dps8_ins.c cpu.ou.STR_OP = 0; cpu 2305 src/dps8/dps8_ins.c cpu.ou.cycle = 0; cpu 2307 src/dps8/dps8_ins.c PNL (cpu.ou.RS = (word9) i->opcode); cpu 2309 src/dps8/dps8_ins.c cpu.skip_cu_hist = false; cpu 2310 src/dps8/dps8_ins.c memcpy (& cpu.MR_cache, & cpu.MR, sizeof (cpu.MR_cache)); cpu 2330 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode) { // L68 cpu 2335 src/dps8/dps8_ins.c cpu.ou.RB1_FULL = cpu.ou.RP_FULL = cpu.ou.RS_FULL = 1; cpu 2336 src/dps8/dps8_ins.c cpu.ou.cycle |= ou_GIN; cpu 2337 src/dps8/dps8_ins.c cpu.ou.opsz = (opcodes10[i->opcode10].reg_use >> 12) & 037; cpu 2339 src/dps8/dps8_ins.c cpu.ou.reguse = reguse; cpu 2630 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.TPR.TRR; cpu 2631 src/dps8/dps8_ins.c cpu.PR[n].SNR = cpu.TPR.TSR; cpu 2632 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = cpu.TPR.CA; cpu 2633 src/dps8/dps8_ins.c SET_PR_BITNO (n, cpu.TPR.TBR); cpu 2674 src/dps8/dps8_ins.c cpu.Ypair[0] = 043; cpu 2675 src/dps8/dps8_ins.c cpu.Ypair[0] |= ((word36) cpu.PR[n].SNR) << 18; cpu 2676 src/dps8/dps8_ins.c cpu.Ypair[0] |= ((word36) cpu.PR[n].RNR) << 15; cpu 2678 src/dps8/dps8_ins.c cpu.Ypair[1] = (word36) cpu.PR[n].WORDNO << 18; cpu 2679 src/dps8/dps8_ins.c cpu.Ypair[1] |= (word36) GET_PR_BITNO (n) << 9; cpu 2684 src/dps8/dps8_ins.c cpu.rA = cpu.CY; cpu 2688 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); cpu 2689 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 2700 src/dps8/dps8_ins.c cpu.rQ = cpu.CY; cpu 2704 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rQ == 0); cpu 2705 src/dps8/dps8_ins.c SC_I_NEG (cpu.rQ & SIGN36); cpu 2734 src/dps8/dps8_ins.c cpu.CY = cpu.rQ; cpu 2742 src/dps8/dps8_ins.c cmp36 (cpu.rQ, cpu.CY, &cpu.cu.IR); cpu 2751 src/dps8/dps8_ins.c word72 tmp72 = YPAIRTO72 (cpu.Ypair); cpu 2752 src/dps8/dps8_ins.c word72 trAQ = convert_to_word72 (cpu.rA, cpu.rQ); cpu 2770 src/dps8/dps8_ins.c convert_to_word36 (trAQ, &cpu.rA, &cpu.rQ); cpu 2779 src/dps8/dps8_ins.c cpu.CY = cpu.rA; cpu 2808 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.TPR.TRR; cpu 2814 src/dps8/dps8_ins.c if (((cpu.CY >> 34) & 3) != 3) cpu 2816 src/dps8/dps8_ins.c word6 bitno = (cpu.CY >> 30) & 077; cpu 2845 src/dps8/dps8_ins.c word12 oSNR = getbits36_12 (cpu.CY, 6); cpu 2848 src/dps8/dps8_ins.c cpu.PR[n].SNR = 077777; cpu 2850 src/dps8/dps8_ins.c cpu.PR[n].SNR = oSNR; // unsigned word will 0-extend. cpu 2852 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = GETLO (cpu.CY); cpu 2857 src/dps8/dps8_ins.c n, cpu.CY, cpu.PR[n].RNR, GET_PR_BITNO (n), cpu 2858 src/dps8/dps8_ins.c cpu.PR[n].SNR, cpu.PR[n].WORDNO); cpu 2876 src/dps8/dps8_ins.c cpu.rX[n] = cpu.TPR.CA; cpu 2881 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); cpu 2882 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); cpu 2902 src/dps8/dps8_ins.c word18 ret = (cpu.PPR.IC + 1) & MASK18; cpu 2905 src/dps8/dps8_ins.c cpu.rX[opcode10 & 07] = ret; cpu 2913 src/dps8/dps8_ins.c cpu.CY = 0; cpu 2942 src/dps8/dps8_ins.c cpu.PR[n].RNR = cpu.TPR.TRR; cpu 2943 src/dps8/dps8_ins.c cpu.PR[n].SNR = cpu.TPR.TSR; cpu 2944 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = 0; cpu 2954 src/dps8/dps8_ins.c cmp36 (cpu.rA, cpu.CY, &cpu.cu.IR); cpu 2964 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 2966 src/dps8/dps8_ins.c cpu.CY = Add36b (cpu.CY, 1, 0, I_ZNOC, cpu 2967 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); cpu 2978 src/dps8/dps8_ins.c word36 trZ = cpu.rA & cpu.CY; cpu 2987 src/dps8/dps8_ins.c cpu.rA = cpu.Ypair[0]; cpu 2991 src/dps8/dps8_ins.c cpu.rQ = cpu.Ypair[1]; cpu 2995 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0 && cpu.rQ == 0) cpu 2996 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 3003 src/dps8/dps8_ins.c if (! (cpu.cu.IR & I_NEG) && ! (cpu.cu.IR & I_ZERO)) cpu 3022 src/dps8/dps8_ins.c cpu.rX[n] = GETLO (cpu.CY); cpu 3026 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rX[n] == 0); cpu 3027 src/dps8/dps8_ins.c SC_I_NEG (cpu.rX[n] & SIGN18); cpu 3032 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu.rA; cpu 3033 src/dps8/dps8_ins.c cpu.Ypair[1] = cpu.rQ; cpu 3073 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 cpu 3075 src/dps8/dps8_ins.c word36 tmpSign = cpu.rA & SIGN36; cpu 3080 src/dps8/dps8_ins.c cpu.rA <<= 1; cpu 3081 src/dps8/dps8_ins.c if (tmpSign != (cpu.rA & SIGN36)) cpu 3084 src/dps8/dps8_ins.c cpu.rA &= DMASK; // keep to 36-bits cpu 3089 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); cpu 3090 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 3099 src/dps8/dps8_ins.c Read2RTCDOperandFetch (cpu.TPR.CA, cpu.Ypair); cpu 3129 src/dps8/dps8_ins.c cpu.CY = ((word36) cpu.rX[n]) << 18; cpu 3130 src/dps8/dps8_ins.c cpu.zone = 0777777000000; cpu 3131 src/dps8/dps8_ins.c cpu.useZone = true; cpu 3161 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode) cpu 3162 src/dps8/dps8_ins.c tmp18 = GETLO (cpu.CY) & 0777760; // L68 cpu 3164 src/dps8/dps8_ins.c tmp18 = GETLO (cpu.CY) & 0777770; // DPS8M cpu 3204 src/dps8/dps8_ins.c word72 tmp72 = YPAIRTO72 (cpu.Ypair); cpu 3205 src/dps8/dps8_ins.c word72 trAQ = convert_to_word72 (cpu.rA, cpu.rQ); cpu 3220 src/dps8/dps8_ins.c convert_to_word36 (trAQ, &cpu.rA, &cpu.rQ); cpu 3233 src/dps8/dps8_ins.c cpu.rA = cpu.rA | cpu.CY; cpu 3234 src/dps8/dps8_ins.c cpu.rA &= DMASK; cpu 3239 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); cpu 3240 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 3245 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 3250 src/dps8/dps8_ins.c cpu.rQ = Add36b (cpu.rQ, cpu.CY, 0, I_ZNOC, cpu 3251 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); cpu 3263 src/dps8/dps8_ins.c if (cpu.cu.IR & (I_NEG | I_ZERO)) cpu 3297 src/dps8/dps8_ins.c cpu.Ypair[0] = 043; cpu 3298 src/dps8/dps8_ins.c cpu.Ypair[0] |= ((word36) cpu.PR[n].SNR) << 18; cpu 3299 src/dps8/dps8_ins.c cpu.Ypair[0] |= ((word36) cpu.PR[n].RNR) << 15; cpu 3300 src/dps8/dps8_ins.c cpu.Ypair[1] = 0; cpu 3309 src/dps8/dps8_ins.c cpu.rA = cpu.rA & cpu.CY; cpu 3310 src/dps8/dps8_ins.c cpu.rA &= DMASK; cpu 3314 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); cpu 3315 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 3326 src/dps8/dps8_ins.c cpu.CY &= DMASK; cpu 3327 src/dps8/dps8_ins.c cpu.rE = (cpu.CY >> 28) & 0377; cpu 3328 src/dps8/dps8_ins.c cpu.rA = (cpu.CY & FLOAT36MASK) << 8; cpu 3332 src/dps8/dps8_ins.c cpu.rQ = 0; cpu 3337 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0 && cpu.rQ == 0); cpu 3338 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 3351 src/dps8/dps8_ins.c cpu.rA = cpu.TPR.TRR & MASK3; cpu 3352 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.TPR.TSR & MASK15) << 18; cpu 3357 src/dps8/dps8_ins.c cpu.rQ = cpu.TPR.TBR & MASK6; cpu 3358 src/dps8/dps8_ins.c cpu.rQ |= (word36) (cpu.TPR.CA & MASK18) << 18; cpu 3363 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0 && cpu.rQ == 0); cpu 3374 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 cpu 3375 src/dps8/dps8_ins.c word36 tmpSign = cpu.rQ & SIGN36; cpu 3380 src/dps8/dps8_ins.c cpu.rQ <<= 1; cpu 3381 src/dps8/dps8_ins.c if (tmpSign != (cpu.rQ & SIGN36)) cpu 3384 src/dps8/dps8_ins.c cpu.rQ &= DMASK; // keep to 36-bits cpu 3389 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rQ == 0); cpu 3390 src/dps8/dps8_ins.c SC_I_NEG (cpu.rQ & SIGN36); cpu 3410 src/dps8/dps8_ins.c DPS8M_ (cpu.CY = cpu.cu.IR & 0000000777770LL; ) cpu 3412 src/dps8/dps8_ins.c L68_ (cpu.CY = cpu.cu.IR & 0000000777760LL;) cpu 3414 src/dps8/dps8_ins.c if (cpu.switches.procMode == procModeGCOS) cpu 3415 src/dps8/dps8_ins.c cpu.CY = cpu.cu.IR & 0000000777600LL; cpu 3416 src/dps8/dps8_ins.c cpu.zone = 0000000777777; cpu 3417 src/dps8/dps8_ins.c cpu.useZone = true; cpu 3418 src/dps8/dps8_ins.c SCF (i->stiTally, cpu.CY, I_TALLY); cpu 3426 src/dps8/dps8_ins.c cpu.rA = 0; cpu 3427 src/dps8/dps8_ins.c SETHI (cpu.rA, cpu.TPR.CA); cpu 3431 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); cpu 3432 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); cpu 3437 src/dps8/dps8_ins.c cpu.rQ = 0; cpu 3438 src/dps8/dps8_ins.c SETHI (cpu.rQ, cpu.TPR.CA); cpu 3443 src/dps8/dps8_ins.c SC_I_ZERO (cpu.TPR.CA == 0); cpu 3444 src/dps8/dps8_ins.c SC_I_NEG (cpu.TPR.CA & SIGN18); cpu 3461 src/dps8/dps8_ins.c cpu.rA = compl36 (cpu.CY, & cpu.cu.IR, & ovf); cpu 3472 src/dps8/dps8_ins.c cpu.rQ = compl36 (cpu.CY, & cpu.cu.IR, & ovf); cpu 3492 src/dps8/dps8_ins.c cpu.rX[n] = compl18 (GETHI (cpu.CY), & cpu.cu.IR, & ovf); cpu 3508 src/dps8/dps8_ins.c if (cpu.Ypair[0] == 0400000000000LL && cpu.Ypair[1] == 0) cpu 3510 src/dps8/dps8_ins.c cpu.rA = cpu.Ypair[0]; cpu 3514 src/dps8/dps8_ins.c cpu.rQ = cpu.Ypair[1]; cpu 3522 src/dps8/dps8_ins.c else if (cpu.Ypair[0] == 0 && cpu.Ypair[1] == 0) cpu 3524 src/dps8/dps8_ins.c cpu.rA = 0; cpu 3528 src/dps8/dps8_ins.c cpu.rQ = 0; cpu 3538 src/dps8/dps8_ins.c word72 tmp72 = convert_to_word72 (cpu.Ypair[0], cpu.Ypair[1]); cpu 3544 src/dps8/dps8_ins.c convert_to_word36 (tmp72, & cpu.rA, & cpu.rQ); cpu 3550 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0 && cpu.rQ == 0); cpu 3551 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 3560 src/dps8/dps8_ins.c cpu.rA = cpu.CY; cpu 3564 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); cpu 3565 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 3566 src/dps8/dps8_ins.c cpu.CY = 0; cpu 3579 src/dps8/dps8_ins.c cpu.rQ = cpu.CY; cpu 3583 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rQ == 0); cpu 3584 src/dps8/dps8_ins.c SC_I_NEG (cpu.rQ & SIGN36); cpu 3585 src/dps8/dps8_ins.c cpu.CY = 0; cpu 3599 src/dps8/dps8_ins.c cpu.rX[n] = GETHI (cpu.CY); cpu 3603 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rX[n] == 0); cpu 3604 src/dps8/dps8_ins.c SC_I_NEG (cpu.rX[n] & SIGN18); cpu 3610 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 3611 src/dps8/dps8_ins.c L68_ (cpu.ou.eac = 0;) cpu 3612 src/dps8/dps8_ins.c cpu.rX[0] = GETHI (cpu.Yblock8[0]); cpu 3616 src/dps8/dps8_ins.c cpu.rX[1] = GETLO (cpu.Yblock8[0]); cpu 3620 src/dps8/dps8_ins.c L68_ (cpu.ou.eac ++;) cpu 3621 src/dps8/dps8_ins.c cpu.rX[2] = GETHI (cpu.Yblock8[1]); cpu 3625 src/dps8/dps8_ins.c cpu.rX[3] = GETLO (cpu.Yblock8[1]); cpu 3629 src/dps8/dps8_ins.c L68_ (cpu.ou.eac ++;) cpu 3630 src/dps8/dps8_ins.c cpu.rX[4] = GETHI (cpu.Yblock8[2]); cpu 3634 src/dps8/dps8_ins.c cpu.rX[5] = GETLO (cpu.Yblock8[2]); cpu 3638 src/dps8/dps8_ins.c L68_ (cpu.ou.eac ++;) cpu 3639 src/dps8/dps8_ins.c cpu.rX[6] = GETHI (cpu.Yblock8[3]); cpu 3643 src/dps8/dps8_ins.c cpu.rX[7] = GETLO (cpu.Yblock8[3]); cpu 3647 src/dps8/dps8_ins.c L68_ (cpu.ou.eac ++;) cpu 3648 src/dps8/dps8_ins.c cpu.rA = cpu.Yblock8[4]; cpu 3652 src/dps8/dps8_ins.c cpu.rQ = cpu.Yblock8[5]; cpu 3656 src/dps8/dps8_ins.c cpu.rE = (GETHI (cpu.Yblock8[6]) >> 10) & 0377; // need checking cpu 3677 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 3678 src/dps8/dps8_ins.c L68_ (cpu.ou.eac = 0;) cpu 3679 src/dps8/dps8_ins.c SETHI (cpu.Yblock8[0], cpu.rX[0]); cpu 3680 src/dps8/dps8_ins.c SETLO (cpu.Yblock8[0], cpu.rX[1]); cpu 3681 src/dps8/dps8_ins.c L68_ (cpu.ou.eac ++;) cpu 3682 src/dps8/dps8_ins.c SETHI (cpu.Yblock8[1], cpu.rX[2]); cpu 3683 src/dps8/dps8_ins.c SETLO (cpu.Yblock8[1], cpu.rX[3]); cpu 3684 src/dps8/dps8_ins.c L68_ (cpu.ou.eac ++;) cpu 3685 src/dps8/dps8_ins.c SETHI (cpu.Yblock8[2], cpu.rX[4]); cpu 3686 src/dps8/dps8_ins.c SETLO (cpu.Yblock8[2], cpu.rX[5]); cpu 3687 src/dps8/dps8_ins.c L68_ (cpu.ou.eac ++;) cpu 3688 src/dps8/dps8_ins.c SETHI (cpu.Yblock8[3], cpu.rX[6]); cpu 3689 src/dps8/dps8_ins.c SETLO (cpu.Yblock8[3], cpu.rX[7]); cpu 3690 src/dps8/dps8_ins.c L68_ (cpu.ou.eac ++;) cpu 3691 src/dps8/dps8_ins.c cpu.Yblock8[4] = cpu.rA; cpu 3692 src/dps8/dps8_ins.c cpu.Yblock8[5] = cpu.rQ; cpu 3693 src/dps8/dps8_ins.c cpu.Yblock8[6] = ((word36)(cpu.rE & MASK8)) << 28; cpu 3694 src/dps8/dps8_ins.c if (cpu.tweaks.isolts_mode) cpu 3695 src/dps8/dps8_ins.c cpu.Yblock8[7] = (((-- cpu.shadowTR) & MASK27) << 9) | (cpu.rRALR & 07); cpu 3697 src/dps8/dps8_ins.c cpu.Yblock8[7] = ((cpu.rTR & MASK27) << 9) | (cpu.rRALR & 07); cpu 3716 src/dps8/dps8_ins.c if (cpu.CY == 0) cpu 3722 src/dps8/dps8_ins.c cpu.CY = cpu.rA; cpu 3732 src/dps8/dps8_ins.c if (cpu.CY == cpu.rQ) cpu 3737 src/dps8/dps8_ins.c cpu.CY = cpu.rA; cpu 3754 src/dps8/dps8_ins.c cpu.CY = cpu.rA; cpu 3755 src/dps8/dps8_ins.c cpu.zone = cpu 3761 src/dps8/dps8_ins.c cpu.useZone = true; cpu 3762 src/dps8/dps8_ins.c cpu.ou.crflag = true; cpu 3772 src/dps8/dps8_ins.c cpu.CY = cpu.rQ; cpu 3773 src/dps8/dps8_ins.c cpu.zone = cpu 3779 src/dps8/dps8_ins.c cpu.useZone = true; cpu 3780 src/dps8/dps8_ins.c cpu.ou.crflag = true; cpu 3786 src/dps8/dps8_ins.c SETHI (cpu.CY, (cpu.PPR.IC + 1) & MASK18); cpu 3789 src/dps8/dps8_ins.c DPS8M_ (SETLO (cpu.CY, cpu.cu.IR & 0777770);) cpu 3790 src/dps8/dps8_ins.c L68_ (SETLO (cpu.CY, cpu.cu.IR & 0777760);) cpu 3791 src/dps8/dps8_ins.c SCF (i->stiTally, cpu.CY, I_TALLY); cpu 3799 src/dps8/dps8_ins.c cpu.CY = ((word36) ((cpu.PPR.IC + 2) & MASK18)) << 18; cpu 3800 src/dps8/dps8_ins.c cpu.zone = 0777777000000; cpu 3801 src/dps8/dps8_ins.c cpu.useZone = true; cpu 3812 src/dps8/dps8_ins.c cpu.CY = cpu.rA; cpu 3813 src/dps8/dps8_ins.c cpu.zone = cpu 3821 src/dps8/dps8_ins.c cpu.useZone = true; cpu 3822 src/dps8/dps8_ins.c cpu.ou.crflag = true; cpu 3832 src/dps8/dps8_ins.c cpu.CY = cpu.rQ; cpu 3833 src/dps8/dps8_ins.c cpu.zone = cpu 3841 src/dps8/dps8_ins.c cpu.useZone = true; cpu 3842 src/dps8/dps8_ins.c cpu.ou.crflag = true; cpu 3862 src/dps8/dps8_ins.c if (cpu.cycle == EXEC_cycle) cpu 3864 src/dps8/dps8_ins.c cpu.Ypair[0] = 0; cpu 3865 src/dps8/dps8_ins.c putbits36_15 (& cpu.Ypair[0], 3, cpu.PPR.PSR); cpu 3866 src/dps8/dps8_ins.c putbits36_3 (& cpu.Ypair[0], 18, cpu.PPR.PRR); cpu 3867 src/dps8/dps8_ins.c putbits36_6 (& cpu.Ypair[0], 30, 043); cpu 3869 src/dps8/dps8_ins.c cpu.Ypair[1] = 0; cpu 3870 src/dps8/dps8_ins.c putbits36_18 (& cpu.Ypair[1], 0, cpu.PPR.IC + 2); cpu 3874 src/dps8/dps8_ins.c cpu.Ypair[0] = 0; cpu 3875 src/dps8/dps8_ins.c putbits36_15 (& cpu.Ypair[0], 3, cpu.cu_data.PSR); cpu 3876 src/dps8/dps8_ins.c putbits36_3 (& cpu.Ypair[0], 18, cpu.cu_data.PRR); cpu 3879 src/dps8/dps8_ins.c cpu.Ypair[1] = 0; cpu 3880 src/dps8/dps8_ins.c putbits36_18 (& cpu.Ypair[1], 0, cpu.cu_data.IC + 2); cpu 3892 src/dps8/dps8_ins.c if (cpu.tweaks.isolts_mode) cpu 3895 src/dps8/dps8_ins.c cpu.CY = (((uint) (((int) cpu.shadowTR) - 1)) & MASK27) << 9; cpu 3897 src/dps8/dps8_ins.c cpu.CY = (cpu.rTR & MASK27) << 9; cpu 3924 src/dps8/dps8_ins.c cpu.CY = cpu.rX[opcode10 & 07]; cpu 3925 src/dps8/dps8_ins.c cpu.zone = 0000000777777; cpu 3926 src/dps8/dps8_ins.c cpu.useZone = true; cpu 3936 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 cpu 3939 src/dps8/dps8_ins.c bool a0 = cpu.rA & SIGN36; // A0 cpu 3940 src/dps8/dps8_ins.c cpu.rA <<= 1; // shift left 1 cpu 3942 src/dps8/dps8_ins.c cpu.rA |= 1; cpu 3944 src/dps8/dps8_ins.c cpu.rA &= DMASK; // keep to 36-bits cpu 3949 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); cpu 3950 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 3964 src/dps8/dps8_ins.c cpu.rA &= DMASK; // Make sure the shifted in bits are 0 cpu 3965 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 cpu 3967 src/dps8/dps8_ins.c cpu.rA >>= tmp36; cpu 3968 src/dps8/dps8_ins.c cpu.rA &= DMASK; // keep to 36-bits cpu 3973 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); cpu 3974 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 3986 src/dps8/dps8_ins.c cpu.rA &= DMASK; // Make sure the shifted in bits are 0 cpu 3987 src/dps8/dps8_ins.c word18 tmp18 = cpu.TPR.CA & 0177; // CY bits 11-17 cpu 3989 src/dps8/dps8_ins.c bool a0 = cpu.rA & SIGN36; // A0 cpu 3992 src/dps8/dps8_ins.c cpu.rA >>= 1; // shift right 1 cpu 3994 src/dps8/dps8_ins.c cpu.rA |= SIGN36; cpu 3996 src/dps8/dps8_ins.c cpu.rA &= DMASK; // keep to 36-bits cpu 4001 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); cpu 4002 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 4015 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 cpu 4018 src/dps8/dps8_ins.c bool a0 = cpu.rA & SIGN36; // A0 cpu 4020 src/dps8/dps8_ins.c cpu.rA <<= 1; // shift left 1 cpu 4022 src/dps8/dps8_ins.c bool b0 = cpu.rQ & SIGN36; // Q0 cpu 4024 src/dps8/dps8_ins.c cpu.rA |= 1; // Q0 => A35 cpu 4026 src/dps8/dps8_ins.c cpu.rQ <<= 1; // shift left 1 cpu 4029 src/dps8/dps8_ins.c cpu.rQ |= 1; cpu 4032 src/dps8/dps8_ins.c cpu.rA &= DMASK; // keep to 36-bits cpu 4033 src/dps8/dps8_ins.c cpu.rQ &= DMASK; cpu 4039 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0 && cpu.rQ == 0); cpu 4040 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 4055 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 cpu 4056 src/dps8/dps8_ins.c word36 tmpSign = cpu.rA & SIGN36; cpu 4059 src/dps8/dps8_ins.c cpu.rA <<= 1; // shift left 1 cpu 4061 src/dps8/dps8_ins.c if (tmpSign != (cpu.rA & SIGN36)) cpu 4064 src/dps8/dps8_ins.c bool b0 = cpu.rQ & SIGN36; // Q0 cpu 4066 src/dps8/dps8_ins.c cpu.rA |= 1; // Q0 => A35 cpu 4068 src/dps8/dps8_ins.c cpu.rQ <<= 1; // shift left 1 cpu 4071 src/dps8/dps8_ins.c cpu.rA &= DMASK; // keep to 36-bits cpu 4072 src/dps8/dps8_ins.c cpu.rQ &= DMASK; cpu 4078 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0 && cpu.rQ == 0); cpu 4079 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 4091 src/dps8/dps8_ins.c cpu.rA &= DMASK; // Make sure the shifted in bits are 0 cpu 4092 src/dps8/dps8_ins.c cpu.rQ &= DMASK; // Make sure the shifted in bits are 0 cpu 4093 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 cpu 4096 src/dps8/dps8_ins.c bool a35 = cpu.rA & 1; // A35 cpu 4097 src/dps8/dps8_ins.c cpu.rA >>= 1; // shift right 1 cpu 4099 src/dps8/dps8_ins.c cpu.rQ >>= 1; // shift right 1 cpu 4102 src/dps8/dps8_ins.c cpu.rQ |= SIGN36; cpu 4104 src/dps8/dps8_ins.c cpu.rA &= DMASK; // keep to 36-bits cpu 4105 src/dps8/dps8_ins.c cpu.rQ &= DMASK; cpu 4111 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0 && cpu.rQ == 0); cpu 4112 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 4125 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 cpu 4126 src/dps8/dps8_ins.c cpu.rA &= DMASK; // Make sure the shifted in bits are 0 cpu 4127 src/dps8/dps8_ins.c cpu.rQ &= DMASK; // Make sure the shifted in bits are 0 cpu 4128 src/dps8/dps8_ins.c bool a0 = cpu.rA & SIGN36; // A0 cpu 4132 src/dps8/dps8_ins.c bool a35 = cpu.rA & 1; // A35 cpu 4134 src/dps8/dps8_ins.c cpu.rA >>= 1; // shift right 1 cpu 4136 src/dps8/dps8_ins.c cpu.rA |= SIGN36; cpu 4138 src/dps8/dps8_ins.c cpu.rQ >>= 1; // shift right 1 cpu 4140 src/dps8/dps8_ins.c cpu.rQ |= SIGN36; cpu 4142 src/dps8/dps8_ins.c cpu.rA &= DMASK; // keep to 36-bits (probably ain't necessary) cpu 4143 src/dps8/dps8_ins.c cpu.rQ &= DMASK; cpu 4149 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0 && cpu.rQ == 0); cpu 4150 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 4161 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 cpu 4164 src/dps8/dps8_ins.c bool q0 = cpu.rQ & SIGN36; // Q0 cpu 4165 src/dps8/dps8_ins.c cpu.rQ <<= 1; // shift left 1 cpu 4167 src/dps8/dps8_ins.c cpu.rQ |= 1; cpu 4169 src/dps8/dps8_ins.c cpu.rQ &= DMASK; // keep to 36-bits cpu 4174 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rQ == 0); cpu 4175 src/dps8/dps8_ins.c SC_I_NEG (cpu.rQ & SIGN36); cpu 4189 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 cpu 4191 src/dps8/dps8_ins.c cpu.rQ &= DMASK; // Make sure the shifted in bits are 0 cpu 4192 src/dps8/dps8_ins.c cpu.rQ >>= tmp36; cpu 4193 src/dps8/dps8_ins.c cpu.rQ &= DMASK; // keep to 36-bits cpu 4198 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rQ == 0); cpu 4199 src/dps8/dps8_ins.c SC_I_NEG (cpu.rQ & SIGN36); cpu 4212 src/dps8/dps8_ins.c cpu.rQ &= DMASK; // Make sure the shifted in bits are 0 cpu 4213 src/dps8/dps8_ins.c word36 tmp36 = cpu.TPR.CA & 0177; // CY bits 11-17 cpu 4214 src/dps8/dps8_ins.c bool q0 = cpu.rQ & SIGN36; // Q0 cpu 4217 src/dps8/dps8_ins.c cpu.rQ >>= 1; // shift right 1 cpu 4219 src/dps8/dps8_ins.c cpu.rQ |= SIGN36; cpu 4221 src/dps8/dps8_ins.c cpu.rQ &= DMASK; // keep to 36-bits cpu 4226 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rQ == 0); cpu 4227 src/dps8/dps8_ins.c SC_I_NEG (cpu.rQ & SIGN36); cpu 4244 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4249 src/dps8/dps8_ins.c cpu.rA = Add36b (cpu.rA, cpu.CY, 0, I_ZNOC, & cpu.cu.IR, & ovf); cpu 4260 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4266 src/dps8/dps8_ins.c word72 tmp72 = YPAIRTO72 (cpu.Ypair); cpu 4267 src/dps8/dps8_ins.c tmp72 = Add72b (convert_to_word72 (cpu.rA, cpu.rQ), cpu 4268 src/dps8/dps8_ins.c tmp72, 0, I_ZNOC, & cpu.cu.IR, & ovf); cpu 4269 src/dps8/dps8_ins.c convert_to_word36 (tmp72, & cpu.rA, & cpu.rQ); cpu 4281 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4287 src/dps8/dps8_ins.c word72 tmp72 = SIGNEXT36_72 (cpu.CY); // sign extend Cy cpu 4288 src/dps8/dps8_ins.c tmp72 = Add72b (convert_to_word72 (cpu.rA, cpu.rQ), cpu 4289 src/dps8/dps8_ins.c tmp72, 0, I_ZNOC, & cpu.cu.IR, & ovf); cpu 4290 src/dps8/dps8_ins.c convert_to_word36 (tmp72, & cpu.rA, & cpu.rQ); cpu 4305 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4311 src/dps8/dps8_ins.c word72 tmp72 = YPAIRTO72 (cpu.Ypair); cpu 4313 src/dps8/dps8_ins.c tmp72 = Add72b (convert_to_word72 (cpu.rA, cpu.rQ), cpu 4314 src/dps8/dps8_ins.c tmp72, 0, I_ZNC, & cpu.cu.IR, & ovf); cpu 4315 src/dps8/dps8_ins.c convert_to_word36 (tmp72, & cpu.rA, & cpu.rQ); cpu 4325 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4335 src/dps8/dps8_ins.c cpu.rA = Add36b (cpu.rA, cpu.CY, 0, I_ZNC, & cpu.cu.IR, & ovf); cpu 4349 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4354 src/dps8/dps8_ins.c cpu.rQ = Add36b (cpu.rQ, cpu.CY, 0, I_ZNC, & cpu.cu.IR, & ovf); cpu 4371 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4377 src/dps8/dps8_ins.c cpu.rX[n] = Add18b (cpu.rX[n], GETHI (cpu.CY), 0, I_ZNC, cpu 4378 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); cpu 4398 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4404 src/dps8/dps8_ins.c cpu.rX[n] = Add18b (cpu.rX[n], GETHI (cpu.CY), 0, cpu 4406 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); cpu 4421 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4426 src/dps8/dps8_ins.c cpu.CY = Add36b (cpu.rA, cpu.CY, 0, I_ZNOC, cpu 4427 src/dps8/dps8_ins.c & cpu.cu.IR, & ovf); cpu 4435 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4440 src/dps8/dps8_ins.c cpu.CY = Add36b (cpu.rQ, cpu.CY, 0, I_ZNOC, & cpu.cu.IR, & ovf); cpu 4457 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4463 src/dps8/dps8_ins.c word18 tmp18 = Add18b (cpu.rX[n], GETHI (cpu.CY), 0, cpu 4464 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cpu 4465 src/dps8/dps8_ins.c SETHI (cpu.CY, tmp18); cpu 4475 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4480 src/dps8/dps8_ins.c cpu.rA = Add36b (cpu.rA, cpu.CY, TST_I_CARRY ? 1 : 0, cpu 4481 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cpu 4494 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4499 src/dps8/dps8_ins.c cpu.rQ = Add36b (cpu.rQ, cpu.CY, TST_I_CARRY ? 1 : 0, cpu 4500 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cpu 4514 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4519 src/dps8/dps8_ins.c cpu.rA = Sub36b (cpu.rA, cpu.CY, 1, I_ZNOC, & cpu.cu.IR, & ovf); cpu 4530 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4536 src/dps8/dps8_ins.c word72 tmp72 = YPAIRTO72 (cpu.Ypair); cpu 4537 src/dps8/dps8_ins.c tmp72 = Sub72b (convert_to_word72 (cpu.rA, cpu.rQ), tmp72, 1, cpu 4538 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, cpu 4540 src/dps8/dps8_ins.c convert_to_word36 (tmp72, & cpu.rA, & cpu.rQ); cpu 4553 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4558 src/dps8/dps8_ins.c cpu.rA = Sub36b (cpu.rA, cpu.CY, 1, I_ZNC, & cpu.cu.IR, & ovf); cpu 4573 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4579 src/dps8/dps8_ins.c word72 tmp72 = YPAIRTO72 (cpu.Ypair); cpu 4581 src/dps8/dps8_ins.c tmp72 = Sub72b (convert_to_word72 (cpu.rA, cpu.rQ), tmp72, 1, cpu 4582 src/dps8/dps8_ins.c I_ZNC, & cpu.cu.IR, & ovf); cpu 4583 src/dps8/dps8_ins.c convert_to_word36 (tmp72, & cpu.rA, & cpu.rQ); cpu 4594 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4599 src/dps8/dps8_ins.c cpu.rQ = Sub36b (cpu.rQ, cpu.CY, 1, I_ZNC, & cpu.cu.IR, & ovf); cpu 4619 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4625 src/dps8/dps8_ins.c cpu.rX[n] = Sub18b (cpu.rX[n], GETHI (cpu.CY), 1, cpu 4626 src/dps8/dps8_ins.c I_ZNC, & cpu.cu.IR, & ovf); cpu 4636 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4641 src/dps8/dps8_ins.c cpu.rQ = Sub36b (cpu.rQ, cpu.CY, 1, I_ZNOC, & cpu.cu.IR, & ovf); cpu 4662 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4668 src/dps8/dps8_ins.c cpu.rX[n] = Sub18b (cpu.rX[n], GETHI (cpu.CY), 1, cpu 4669 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cpu 4681 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4686 src/dps8/dps8_ins.c cpu.CY = Sub36b (cpu.rA, cpu.CY, 1, I_ZNOC, & cpu.cu.IR, & ovf); cpu 4695 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4700 src/dps8/dps8_ins.c cpu.CY = Sub36b (cpu.rQ, cpu.CY, 1, I_ZNOC, & cpu.cu.IR, & ovf); cpu 4718 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4724 src/dps8/dps8_ins.c word18 tmp18 = Sub18b (cpu.rX[n], GETHI (cpu.CY), 1, cpu 4725 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cpu 4726 src/dps8/dps8_ins.c SETHI (cpu.CY, tmp18); cpu 4736 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4741 src/dps8/dps8_ins.c cpu.rA = Sub36b (cpu.rA, cpu.CY, TST_I_CARRY ? 1 : 0, cpu 4742 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cpu 4755 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4760 src/dps8/dps8_ins.c cpu.rQ = Sub36b (cpu.rQ, cpu.CY, TST_I_CARRY ? 1 : 0, cpu 4761 src/dps8/dps8_ins.c I_ZNOC, & cpu.cu.IR, & ovf); cpu 4782 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GD1;) cpu 4788 src/dps8/dps8_ins.c word72 tmp72 = multiply_128 (SIGNEXT36_72 (cpu.rA), SIGNEXT36_72 (cpu.CY)); cpu 4794 src/dps8/dps8_ins.c word72 tmp72 = (word72) (((word72s) SIGNEXT36_72 (cpu.rA)) * ((word72s) SIGNEXT36_72 (cpu.CY))); cpu 4798 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GD2;) cpu 4801 src/dps8/dps8_ins.c if (cpu.rA == MAXNEG && cpu.CY == MAXNEG) cpu 4808 src/dps8/dps8_ins.c convert_to_word36 (tmp72, &cpu.rA, &cpu.rQ); cpu 4813 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0 && cpu.rQ == 0); cpu 4814 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 4822 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 4828 src/dps8/dps8_ins.c SIGNEXT36_128 (cpu.rQ & DMASK), cpu 4829 src/dps8/dps8_ins.c SIGNEXT36_128 (cpu.CY & DMASK)); cpu 4830 src/dps8/dps8_ins.c convert_to_word36 (cast_128 (prod), &cpu.rA, &cpu.rQ); cpu 4832 src/dps8/dps8_ins.c int64_t t0 = SIGNEXT36_64 (cpu.rQ & DMASK); cpu 4833 src/dps8/dps8_ins.c int64_t t1 = SIGNEXT36_64 (cpu.CY & DMASK); cpu 4837 src/dps8/dps8_ins.c convert_to_word36 ((word72)prod, &cpu.rA, &cpu.rQ); cpu 4844 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0 && cpu.rQ == 0); cpu 4845 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 4867 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GD1;) cpu 4874 src/dps8/dps8_ins.c if ((cpu.rQ == MAXNEG && (cpu.CY == 1 || cpu.CY == NEG136)) || cpu 4875 src/dps8/dps8_ins.c (cpu.CY == 0)) cpu 4881 src/dps8/dps8_ins.c cpu.rA = (cpu.rQ & SIGN36) ? 0 : SIGN36; // works for case 1,2 cpu 4887 src/dps8/dps8_ins.c SC_I_ZERO (cpu.CY == 0); cpu 4888 src/dps8/dps8_ins.c SC_I_NEG (cpu.rQ & SIGN36); cpu 4890 src/dps8/dps8_ins.c if (cpu.rQ & SIGN36) cpu 4894 src/dps8/dps8_ins.c cpu.rQ = ((word36) (- (word36s) cpu.rQ)) & MASK36; cpu 4906 src/dps8/dps8_ins.c t_int64 dividend = (t_int64) (SIGNEXT36_64 (cpu.rQ)); cpu 4907 src/dps8/dps8_ins.c t_int64 divisor = (t_int64) (SIGNEXT36_64 (cpu.CY)); cpu 4913 src/dps8/dps8_ins.c dividend, cpu.rQ); cpu 4916 src/dps8/dps8_ins.c divisor, cpu.CY); cpu 4921 src/dps8/dps8_ins.c L68_ (cpu.ou.cycle |= ou_GD2;) cpu 4969 src/dps8/dps8_ins.c " rQ %012"PRIo64" CY %012"PRIo64"\n", cpu.rQ, cpu.CY); cpu 4972 src/dps8/dps8_ins.c cpu.rA = (word36) remainder & DMASK; cpu 4973 src/dps8/dps8_ins.c cpu.rQ = (word36) quotient & DMASK; cpu 4979 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "rA (rem) %012"PRIo64"\n", cpu.rA); cpu 4980 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "rQ (quot) %012"PRIo64"\n", cpu.rQ); cpu 4984 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rQ == 0); cpu 4985 src/dps8/dps8_ins.c SC_I_NEG (cpu.rQ & SIGN36); cpu 5019 src/dps8/dps8_ins.c cpu.rA &= DMASK; cpu 5020 src/dps8/dps8_ins.c if (cpu.rA == 0400000000000ULL) cpu 5029 src/dps8/dps8_ins.c cpu.rA = (word36) (- (word36s) cpu.rA); cpu 5031 src/dps8/dps8_ins.c cpu.rA &= DMASK; // keep to 36-bits cpu 5036 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); cpu 5037 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 5048 src/dps8/dps8_ins.c cpu.rA &= DMASK; cpu 5049 src/dps8/dps8_ins.c cpu.rQ &= DMASK; cpu 5051 src/dps8/dps8_ins.c if (cpu.rA == 0400000000000ULL && cpu.rQ == 0) cpu 5058 src/dps8/dps8_ins.c word72 tmp72 = convert_to_word72 (cpu.rA, cpu.rQ); cpu 5073 src/dps8/dps8_ins.c convert_to_word36 (tmp72, &cpu.rA, &cpu.rQ); cpu 5096 src/dps8/dps8_ins.c t_int64 a = SIGNEXT36_64 (cpu.rA); cpu 5099 src/dps8/dps8_ins.c t_int64 y = SIGNEXT36_64 (cpu.CY); cpu 5133 src/dps8/dps8_ins.c word36 Z = ~cpu.rQ & (cpu.rA ^ cpu.CY); cpu 5165 src/dps8/dps8_ins.c word72 tmp72 = YPAIRTO72 (cpu.Ypair); cpu 5166 src/dps8/dps8_ins.c word72 trAQ = convert_to_word72 (cpu.rA, cpu.rQ); cpu 5172 src/dps8/dps8_ins.c cmp72 (trAQ, tmp72, &cpu.cu.IR); cpu 5195 src/dps8/dps8_ins.c cmp18 (cpu.rX[n], GETHI (cpu.CY), &cpu.cu.IR); cpu 5211 src/dps8/dps8_ins.c cmp36wl (cpu.rA, cpu.CY, cpu.rQ, &cpu.cu.IR); cpu 5218 src/dps8/dps8_ins.c cpu.CY &= DMASK; cpu 5219 src/dps8/dps8_ins.c SC_I_ZERO (cpu.CY == 0); cpu 5220 src/dps8/dps8_ins.c SC_I_NEG (cpu.CY & SIGN36); cpu 5225 src/dps8/dps8_ins.c cpu.CY &= DMASK; cpu 5226 src/dps8/dps8_ins.c SC_I_ZERO (cpu.CY == 0); cpu 5227 src/dps8/dps8_ins.c SC_I_NEG (cpu.CY & SIGN36); cpu 5229 src/dps8/dps8_ins.c cpu.CY = 0; cpu 5247 src/dps8/dps8_ins.c cpu.rQ = cpu.rQ & cpu.CY; cpu 5248 src/dps8/dps8_ins.c cpu.rQ &= DMASK; cpu 5253 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rQ == 0); cpu 5254 src/dps8/dps8_ins.c SC_I_NEG (cpu.rQ & SIGN36); cpu 5263 src/dps8/dps8_ins.c cpu.CY = cpu.rA & cpu.CY; cpu 5264 src/dps8/dps8_ins.c cpu.CY &= DMASK; cpu 5266 src/dps8/dps8_ins.c SC_I_ZERO (cpu.CY == 0); cpu 5267 src/dps8/dps8_ins.c SC_I_NEG (cpu.CY & SIGN36); cpu 5277 src/dps8/dps8_ins.c cpu.CY = cpu.rQ & cpu.CY; cpu 5278 src/dps8/dps8_ins.c cpu.CY &= DMASK; cpu 5280 src/dps8/dps8_ins.c SC_I_ZERO (cpu.CY == 0); cpu 5281 src/dps8/dps8_ins.c SC_I_NEG (cpu.CY & SIGN36); cpu 5301 src/dps8/dps8_ins.c word18 tmp18 = cpu.rX[n] & GETHI (cpu.CY); cpu 5307 src/dps8/dps8_ins.c SETHI (cpu.CY, tmp18); cpu 5328 src/dps8/dps8_ins.c cpu.rX[n] &= GETHI (cpu.CY); cpu 5329 src/dps8/dps8_ins.c cpu.rX[n] &= MASK18; cpu 5334 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rX[n] == 0); cpu 5335 src/dps8/dps8_ins.c SC_I_NEG (cpu.rX[n] & SIGN18); cpu 5351 src/dps8/dps8_ins.c word72 tmp72 = YPAIRTO72 (cpu.Ypair); cpu 5352 src/dps8/dps8_ins.c word72 trAQ = convert_to_word72 (cpu.rA, cpu.rQ); cpu 5366 src/dps8/dps8_ins.c convert_to_word36 (trAQ, &cpu.rA, &cpu.rQ); cpu 5379 src/dps8/dps8_ins.c cpu.rQ = cpu.rQ | cpu.CY; cpu 5380 src/dps8/dps8_ins.c cpu.rQ &= DMASK; cpu 5385 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rQ == 0); cpu 5386 src/dps8/dps8_ins.c SC_I_NEG (cpu.rQ & SIGN36); cpu 5395 src/dps8/dps8_ins.c cpu.CY = cpu.rA | cpu.CY; cpu 5396 src/dps8/dps8_ins.c cpu.CY &= DMASK; cpu 5398 src/dps8/dps8_ins.c SC_I_ZERO (cpu.CY == 0); cpu 5399 src/dps8/dps8_ins.c SC_I_NEG (cpu.CY & SIGN36); cpu 5407 src/dps8/dps8_ins.c cpu.CY = cpu.rQ | cpu.CY; cpu 5408 src/dps8/dps8_ins.c cpu.CY &= DMASK; cpu 5410 src/dps8/dps8_ins.c SC_I_ZERO (cpu.CY == 0); cpu 5411 src/dps8/dps8_ins.c SC_I_NEG (cpu.CY & SIGN36); cpu 5428 src/dps8/dps8_ins.c word18 tmp18 = cpu.rX[n] | GETHI (cpu.CY); cpu 5434 src/dps8/dps8_ins.c SETHI (cpu.CY, tmp18); cpu 5454 src/dps8/dps8_ins.c cpu.rX[n] |= GETHI (cpu.CY); cpu 5455 src/dps8/dps8_ins.c cpu.rX[n] &= MASK18; cpu 5460 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rX[n] == 0); cpu 5461 src/dps8/dps8_ins.c SC_I_NEG (cpu.rX[n] & SIGN18); cpu 5472 src/dps8/dps8_ins.c cpu.rA = cpu.rA ^ cpu.CY; cpu 5473 src/dps8/dps8_ins.c cpu.rA &= DMASK; cpu 5478 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); cpu 5479 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 5491 src/dps8/dps8_ins.c cpu.rQ = cpu.rQ ^ cpu.CY; cpu 5492 src/dps8/dps8_ins.c cpu.rQ &= DMASK; cpu 5496 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rQ == 0); cpu 5497 src/dps8/dps8_ins.c SC_I_NEG (cpu.rQ & SIGN36); cpu 5505 src/dps8/dps8_ins.c cpu.CY = cpu.rA ^ cpu.CY; cpu 5506 src/dps8/dps8_ins.c cpu.CY &= DMASK; cpu 5508 src/dps8/dps8_ins.c SC_I_ZERO (cpu.CY == 0); cpu 5509 src/dps8/dps8_ins.c SC_I_NEG (cpu.CY & SIGN36); cpu 5517 src/dps8/dps8_ins.c cpu.CY = cpu.rQ ^ cpu.CY; cpu 5518 src/dps8/dps8_ins.c cpu.CY &= DMASK; cpu 5520 src/dps8/dps8_ins.c SC_I_ZERO (cpu.CY == 0); cpu 5521 src/dps8/dps8_ins.c SC_I_NEG (cpu.CY & SIGN36); cpu 5542 src/dps8/dps8_ins.c word18 tmp18 = cpu.rX[n] ^ GETHI (cpu.CY); cpu 5548 src/dps8/dps8_ins.c SETHI (cpu.CY, tmp18); cpu 5568 src/dps8/dps8_ins.c cpu.rX[n] ^= GETHI (cpu.CY); cpu 5569 src/dps8/dps8_ins.c cpu.rX[n] &= MASK18; cpu 5574 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rX[n] == 0); cpu 5575 src/dps8/dps8_ins.c SC_I_NEG (cpu.rX[n] & SIGN18); cpu 5591 src/dps8/dps8_ins.c word72 tmp72 = YPAIRTO72 (cpu.Ypair); cpu 5592 src/dps8/dps8_ins.c word72 trAQ = convert_to_word72 (cpu.rA, cpu.rQ); cpu 5615 src/dps8/dps8_ins.c word36 trZ = cpu.rQ & cpu.CY; cpu 5639 src/dps8/dps8_ins.c word18 tmp18 = cpu.rX[n] & GETHI (cpu.CY); cpu 5643 src/dps8/dps8_ins.c n, cpu.rX[n], (word18) (GETHI (cpu.CY) & MASK18), cpu 5659 src/dps8/dps8_ins.c word36 trZ = cpu.rA & ~cpu.CY; cpu 5674 src/dps8/dps8_ins.c word72 tmp72 = YPAIRTO72 (cpu.Ypair); cpu 5676 src/dps8/dps8_ins.c word72 trAQ = convert_to_word72 (cpu.rA, cpu.rQ); cpu 5699 src/dps8/dps8_ins.c word36 trZ = cpu.rQ & ~cpu.CY; cpu 5721 src/dps8/dps8_ins.c word18 tmp18 = cpu.rX[n] & ~GETHI (cpu.CY); cpu 5741 src/dps8/dps8_ins.c cpu.rE = (cpu.Ypair[0] >> 28) & MASK8; cpu 5743 src/dps8/dps8_ins.c cpu.rA = (cpu.Ypair[0] & FLOAT36MASK) << 8; cpu 5744 src/dps8/dps8_ins.c cpu.rA |= (cpu.Ypair[1] >> 28) & MASK8; cpu 5746 src/dps8/dps8_ins.c cpu.rQ = (cpu.Ypair[1] & FLOAT36MASK) << 8; cpu 5753 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0 && cpu.rQ == 0); cpu 5754 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 5771 src/dps8/dps8_ins.c cpu.Ypair[0] = ((word36)cpu.rE << 28) | cpu 5772 src/dps8/dps8_ins.c ((cpu.rA & 0777777777400LLU) >> 8); cpu 5773 src/dps8/dps8_ins.c cpu.Ypair[1] = ((cpu.rA & 0377) << 28) | cpu 5774 src/dps8/dps8_ins.c ((cpu.rQ & 0777777777400LLU) >> 8); cpu 5780 src/dps8/dps8_ins.c dfstr (cpu.Ypair); cpu 5790 src/dps8/dps8_ins.c cpu.rE &= MASK8; cpu 5791 src/dps8/dps8_ins.c cpu.rA &= DMASK; cpu 5792 src/dps8/dps8_ins.c cpu.CY = ((word36)cpu.rE << 28) | (((cpu.rA >> 8) & 01777777777LL)); cpu 5819 src/dps8/dps8_ins.c fstr (&cpu.CY); cpu 6001 src/dps8/dps8_ins.c fno (& cpu.rE, & cpu.rA, & cpu.rQ); cpu 6060 src/dps8/dps8_ins.c int y = SIGNEXT8_int ((cpu.CY >> 28) & 0377); cpu 6061 src/dps8/dps8_ins.c int e = SIGNEXT8_int (cpu.rE); cpu 6064 src/dps8/dps8_ins.c cpu.rE = e & 0377; cpu 6089 src/dps8/dps8_ins.c SC_I_ZERO ((cpu.CY & 001777777777LL) == 0); cpu 6090 src/dps8/dps8_ins.c SC_I_NEG (cpu.CY & 001000000000LL); cpu 6098 src/dps8/dps8_ins.c cpu.rE = (cpu.CY >> 28) & 0377; cpu 6110 src/dps8/dps8_ins.c cpu.CY = ((word36) (cpu.rE & 0377)) << 28; cpu 6111 src/dps8/dps8_ins.c cpu.zone = 0777777000000; cpu 6112 src/dps8/dps8_ins.c cpu.useZone = true; cpu 6124 src/dps8/dps8_ins.c "call6 PRR %o PSR %o\n", cpu.PPR.PRR, cpu.PPR.PSR); cpu 6141 src/dps8/dps8_ins.c ReadOperandRead (cpu.TPR.CA, & cpu.CY); cpu 6143 src/dps8/dps8_ins.c cpu.PPR.IC = GETHI (cpu.CY); cpu 6144 src/dps8/dps8_ins.c word18 tempIR = GETLO (cpu.CY) & 0777770; cpu 6184 src/dps8/dps8_ins.c cpu.cu.IR = tempIR; cpu 6325 src/dps8/dps8_ins.c cpu.TPR.CA = get_BAR_address (cpu.TPR.CA); cpu 6380 src/dps8/dps8_ins.c cpu.PR[0].SNR = cpu.TPR.CA & MASK15; cpu 6389 src/dps8/dps8_ins.c cpu.PR[1].SNR = cpu.TPR.CA & MASK15; cpu 6398 src/dps8/dps8_ins.c cpu.PR[2].SNR = cpu.TPR.CA & MASK15; cpu 6407 src/dps8/dps8_ins.c cpu.PR[3].SNR = cpu.TPR.CA & MASK15; cpu 6416 src/dps8/dps8_ins.c cpu.PR[4].SNR = cpu.TPR.CA & MASK15; cpu 6425 src/dps8/dps8_ins.c cpu.PR[5].SNR = cpu.TPR.CA & MASK15; cpu 6434 src/dps8/dps8_ins.c cpu.PR[6].SNR = cpu.TPR.CA & MASK15; cpu 6443 src/dps8/dps8_ins.c cpu.PR[7].SNR = cpu.TPR.CA & MASK15; cpu 6456 src/dps8/dps8_ins.c cpu.PR[0].WORDNO = cpu.TPR.CA; cpu 6457 src/dps8/dps8_ins.c SET_PR_BITNO (0, cpu.TPR.TBR); cpu 6468 src/dps8/dps8_ins.c cpu.PR[1].WORDNO = cpu.TPR.CA; cpu 6469 src/dps8/dps8_ins.c SET_PR_BITNO (1, cpu.TPR.TBR); cpu 6480 src/dps8/dps8_ins.c cpu.PR[2].WORDNO = cpu.TPR.CA; cpu 6481 src/dps8/dps8_ins.c SET_PR_BITNO (2, cpu.TPR.TBR); cpu 6492 src/dps8/dps8_ins.c cpu.PR[3].WORDNO = cpu.TPR.CA; cpu 6493 src/dps8/dps8_ins.c SET_PR_BITNO (3, cpu.TPR.TBR); cpu 6504 src/dps8/dps8_ins.c cpu.PR[4].WORDNO = cpu.TPR.CA; cpu 6505 src/dps8/dps8_ins.c SET_PR_BITNO (4, cpu.TPR.TBR); cpu 6516 src/dps8/dps8_ins.c cpu.PR[5].WORDNO = cpu.TPR.CA; cpu 6517 src/dps8/dps8_ins.c SET_PR_BITNO (5, cpu.TPR.TBR); cpu 6528 src/dps8/dps8_ins.c cpu.PR[6].WORDNO = cpu.TPR.CA; cpu 6529 src/dps8/dps8_ins.c SET_PR_BITNO (6, cpu.TPR.TBR); cpu 6540 src/dps8/dps8_ins.c cpu.PR[7].WORDNO = cpu.TPR.CA; cpu 6541 src/dps8/dps8_ins.c SET_PR_BITNO (7, cpu.TPR.TBR); cpu 6579 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu.Yblock16[n * 2 + 0]; cpu 6581 src/dps8/dps8_ins.c cpu.Ypair[1] = cpu.Yblock16[n * 2 + 1]; cpu 6584 src/dps8/dps8_ins.c word3 Crr = (GETLO (cpu.Ypair[0]) >> 15) & 07; cpu 6586 src/dps8/dps8_ins.c cpu.PR[n].RNR = max3 (Crr, cpu.SDW->R1, cpu.TPR.TRR); cpu 6588 src/dps8/dps8_ins.c cpu.PR[n].RNR = Crr; cpu 6589 src/dps8/dps8_ins.c cpu.PR[n].SNR = (cpu.Ypair[0] >> 18) & MASK15; cpu 6590 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = GETHI (cpu.Ypair[1]); cpu 6591 src/dps8/dps8_ins.c word6 bitno = (GETLO (cpu.Ypair[1]) >> 9) & 077; cpu 6648 src/dps8/dps8_ins.c cpu.Yblock16[2 * n] = 043; cpu 6649 src/dps8/dps8_ins.c cpu.Yblock16[2 * n] |= ((word36) cpu.PR[n].SNR) << 18; cpu 6650 src/dps8/dps8_ins.c cpu.Yblock16[2 * n] |= ((word36) cpu.PR[n].RNR) << 15; cpu 6652 src/dps8/dps8_ins.c cpu.Yblock16[2 * n + 1] = (word36) cpu.PR[n].WORDNO << 18; cpu 6653 src/dps8/dps8_ins.c cpu.Yblock16[2 * n + 1] |= (word36) GET_PR_BITNO(n) << 9; cpu 6689 src/dps8/dps8_ins.c if ((cpu.PR[n].SNR & 070000) != 0 && cpu.PR[n].SNR != MASK15) cpu 6692 src/dps8/dps8_ins.c cpu.CY = ((word36) (GET_PR_BITNO(n) & 077)) << 30; cpu 6694 src/dps8/dps8_ins.c cpu.CY |= ((word36) (cpu.PR[n].SNR & 07777)) << 18; cpu 6695 src/dps8/dps8_ins.c cpu.CY |= cpu.PR[n].WORDNO & PAMASK; cpu 6696 src/dps8/dps8_ins.c cpu.CY &= DMASK; // keep to 36-bits cpu 6713 src/dps8/dps8_ins.c cpu.PR[n].WORDNO += GETHI (cpu.CY); cpu 6714 src/dps8/dps8_ins.c cpu.PR[n].WORDNO &= MASK18; cpu 6732 src/dps8/dps8_ins.c cpu.PR[n].WORDNO += GETHI (cpu.CY); cpu 6733 src/dps8/dps8_ins.c cpu.PR[n].WORDNO &= MASK18; cpu 6757 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode) cpu 6758 src/dps8/dps8_ins.c cpu_port_num = (cpu.TPR.CA >> 15) & 07; cpu 6760 src/dps8/dps8_ins.c cpu_port_num = (cpu.TPR.CA >> 15) & 03; cpu 6770 src/dps8/dps8_ins.c 040, & cpu.rA, & cpu.rQ); cpu 6789 src/dps8/dps8_ins.c word72 big = convert_to_word72 (cpu.rA, cpu.rQ); cpu 6820 src/dps8/dps8_ins.c if (cpu.tweaks.drl_fatal) cpu 6828 src/dps8/dps8_ins.c cpu.cu.xde = 1; cpu 6829 src/dps8/dps8_ins.c cpu.cu.xdo = 0; cpu 6833 src/dps8/dps8_ins.c cpu.cu.IWB = cpu.CY; cpu 6872 src/dps8/dps8_ins.c cpu.cu.xde = 1; cpu 6873 src/dps8/dps8_ins.c cpu.cu.xdo = 1; cpu 6877 src/dps8/dps8_ins.c cpu.cu.IWB = cpu.Ypair[0]; cpu 6878 src/dps8/dps8_ins.c cpu.cu.IRODD = cpu.Ypair[1]; cpu 6930 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) cpu 6932 src/dps8/dps8_ins.c cpu.cu.delta = i->tag; cpu 6937 src/dps8/dps8_ins.c cpu.rX[0] = i->address; // Entire 18 bits cpu 6942 src/dps8/dps8_ins.c cpu.cu.rd = 1; cpu 6943 src/dps8/dps8_ins.c cpu.cu.repeat_first = 1; cpu 6950 src/dps8/dps8_ins.c cpu.cu.delta = i->tag; cpu 6953 src/dps8/dps8_ins.c cpu.rX[0] = i->address; // Entire 18 bits cpu 6958 src/dps8/dps8_ins.c cpu.cu.rl = 1; cpu 6959 src/dps8/dps8_ins.c cpu.cu.repeat_first = 1; cpu 6966 src/dps8/dps8_ins.c cpu.cu.delta = i->tag; cpu 6969 src/dps8/dps8_ins.c cpu.rX[0] = i->address; // Entire 18 bits cpu 6974 src/dps8/dps8_ins.c cpu.cu.rpt = 1; cpu 6975 src/dps8/dps8_ins.c cpu.cu.repeat_first = 1; cpu 6986 src/dps8/dps8_ins.c cpu.CY = (word36)cpu.rRALR; cpu 6996 src/dps8/dps8_ins.c cpu.CY = ((((word36) cpu.BAR.BASE) << 9) | cpu.BAR.BOUND) << 18; cpu 6997 src/dps8/dps8_ins.c cpu.zone = 0777777000000; cpu 6998 src/dps8/dps8_ins.c cpu.useZone = true; cpu 7012 src/dps8/dps8_ins.c word36 tmp1 = cpu.rA & SIGN36; // A0 cpu 7013 src/dps8/dps8_ins.c word36 tmp36 = (cpu.rA << 3) & DMASK; cpu 7014 src/dps8/dps8_ins.c word36 tmp36q = tmp36 / cpu.CY; // this may be more than 4 bits, keep it for remainder calculation cpu 7017 src/dps8/dps8_ins.c tmp36r = tmp36 - tmp36q * cpu.CY; cpu 7026 src/dps8/dps8_ins.c tmp36r = tmp36 + tmp36q * cpu.CY; cpu 7029 src/dps8/dps8_ins.c cpu.rQ <<= 6; // Shift C(Q) left six positions cpu 7030 src/dps8/dps8_ins.c cpu.rQ &= DMASK; cpu 7033 src/dps8/dps8_ins.c cpu.rQ |= (tmp36q & 017); cpu 7038 src/dps8/dps8_ins.c cpu.rA = tmp36r & DMASK; // remainder -> C(A) cpu 7043 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); // If C(A) = 0, then ON; cpu 7054 src/dps8/dps8_ins.c word36 tmp = cpu.rA & MASK36; cpu 7062 src/dps8/dps8_ins.c cpu.rA = tmp; cpu 7067 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); // If C(A) = 0, then ON; cpu 7069 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); // If C(A)0 = 1, then ON; cpu 7080 src/dps8/dps8_ins.c cpu.BAR.BASE = (GETHI (cpu.CY) >> 9) & 0777; cpu 7082 src/dps8/dps8_ins.c cpu.BAR.BOUND = GETHI (cpu.CY) & 0777; cpu 7107 src/dps8/dps8_ins.c uint csh1_on = getbits36_1 (cpu.CY, 54 - 36); cpu 7108 src/dps8/dps8_ins.c uint csh2_on = getbits36_1 (cpu.CY, 55 - 36); cpu 7111 src/dps8/dps8_ins.c cpu.CMR.csh1_on = (word1) csh1_on; cpu 7112 src/dps8/dps8_ins.c cpu.CMR.csh2_on = (word1) csh2_on; cpu 7116 src/dps8/dps8_ins.c L68_ (cpu.CMR.opnd_on = getbits36_1 (cpu.CY, 56 - 36);) cpu 7117 src/dps8/dps8_ins.c cpu.CMR.inst_on = getbits36_1 (cpu.CY, 57 - 36); cpu 7118 src/dps8/dps8_ins.c cpu.CMR.csh_reg = getbits36_1 (cpu.CY, 59 - 36); cpu 7119 src/dps8/dps8_ins.c if (cpu.CMR.csh_reg) cpu 7124 src/dps8/dps8_ins.c DPS8M_ (cpu.CMR.bypass_cache = getbits36_1 (cpu.CY, 68 - 36);) cpu 7125 src/dps8/dps8_ins.c cpu.CMR.luf = getbits36_2 (cpu.CY, 70 - 36); cpu 7132 src/dps8/dps8_ins.c cpu.MR.r = cpu.CY; cpu 7134 src/dps8/dps8_ins.c putbits36_1 (& cpu.MR.r, 32, 0); cpu 7136 src/dps8/dps8_ins.c putbits36_2 (& cpu.MR.r, 33, 0); cpu 7138 src/dps8/dps8_ins.c cpu.MR.FFV = getbits36_15 (cpu.CY, 0); cpu 7139 src/dps8/dps8_ins.c cpu.MR.OC_TRAP = getbits36_1 (cpu.CY, 16); cpu 7140 src/dps8/dps8_ins.c cpu.MR.ADR_TRAP = getbits36_1 (cpu.CY, 17); cpu 7141 src/dps8/dps8_ins.c cpu.MR.OPCODE = getbits36_9 (cpu.CY, 18); cpu 7142 src/dps8/dps8_ins.c cpu.MR.OPCODEX = getbits36_1 (cpu.CY, 27); cpu 7144 src/dps8/dps8_ins.c cpu.MR.sdpap = getbits36_1 (cpu.CY, 20); cpu 7145 src/dps8/dps8_ins.c cpu.MR.separ = getbits36_1 (cpu.CY, 21); cpu 7146 src/dps8/dps8_ins.c cpu.MR.hrhlt = getbits36_1 (cpu.CY, 28); cpu 7147 src/dps8/dps8_ins.c DPS8M_ (cpu.MR.hrxfr = getbits36_1 (cpu.CY, 29);) cpu 7148 src/dps8/dps8_ins.c cpu.MR.ihr = getbits36_1 (cpu.CY, 30); cpu 7149 src/dps8/dps8_ins.c cpu.MR.ihrrs = getbits36_1 (cpu.CY, 31); cpu 7150 src/dps8/dps8_ins.c cpu.MR.emr = getbits36_1 (cpu.CY, 35); cpu 7151 src/dps8/dps8_ins.c if (! cpu.tweaks.l68_mode) // DPS8M cpu 7152 src/dps8/dps8_ins.c cpu.MR.hexfp = getbits36_1 (cpu.CY, 33); cpu 7154 src/dps8/dps8_ins.c cpu.MR.hexfp = 0; cpu 7160 src/dps8/dps8_ins.c if (cpu.MR.hrhlt) cpu 7163 src/dps8/dps8_ins.c cpu.history_cyclic[hset] = 0; cpu 7167 src/dps8/dps8_ins.c cpu 7172 src/dps8/dps8_ins.c cpu 7189 src/dps8/dps8_ins.c cpu.skip_cu_hist = true; cpu 7203 src/dps8/dps8_ins.c cpu.skip_cu_hist = true; cpu 7216 src/dps8/dps8_ins.c do_ldbr (cpu.Ypair); cpu 7222 src/dps8/dps8_ins.c cpu.rTR = (cpu.CY >> 9) & MASK27; cpu 7223 src/dps8/dps8_ins.c cpu.rTRticks = 0; cpu 7224 src/dps8/dps8_ins.c if (cpu.tweaks.isolts_mode) cpu 7226 src/dps8/dps8_ins.c cpu.shadowTR = cpu.TR0 = cpu.rTR; cpu 7227 src/dps8/dps8_ins.c cpu.rTRlsb = 0; cpu 7230 src/dps8/dps8_ins.c cpu.rTR, cpu.rTR); cpu 7233 src/dps8/dps8_ins.c sim_printf (" ldt %d PSR:IC %05o:%06o\r\n", cpu.rTR, cpu.PPR.PSR, cpu.PPR.IC); cpu 7244 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode) { cpu 7253 src/dps8/dps8_ins.c word4 m = cpu.PTWAM[i].USE; cpu 7254 src/dps8/dps8_ins.c cpu.PTWAM[m].POINTER = getbits36_15 (cpu.Yblock16[i], 0); cpu 7255 src/dps8/dps8_ins.c cpu.PTWAM[m].PAGENO = getbits36_12 (cpu.Yblock16[i], 15); cpu 7256 src/dps8/dps8_ins.c cpu.PTWAM[m].FE = getbits36_1 (cpu.Yblock16[i], 27); cpu 7262 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode) { cpu 7269 src/dps8/dps8_ins.c word4 m = cpu.PTWAM[i].USE; cpu 7270 src/dps8/dps8_ins.c cpu.PTWAM[m].ADDR = getbits36_18 (cpu.Yblock16[i], 0); cpu 7271 src/dps8/dps8_ins.c cpu.PTWAM[m].M = getbits36_1 (cpu.Yblock16[i], 29); cpu 7278 src/dps8/dps8_ins.c cpu.rRALR = cpu.CY & MASK3; cpu 7279 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RALR set to %o\n", cpu.rRALR); cpu 7284 src/dps8/dps8_ins.c sim_printf (" RALR set to %o PSR:IC %05o:%06o\r\n", cpu.rRALR, cpu.PPR.PSR, cpu.PPR.IC); cpu 7290 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode) { cpu 7297 src/dps8/dps8_ins.c word4 m = cpu.SDWAM[i].USE; cpu 7298 src/dps8/dps8_ins.c cpu.SDWAM[m].POINTER = getbits36_15 (cpu.Yblock16[i], 0); cpu 7299 src/dps8/dps8_ins.c cpu.SDWAM[m].FE = getbits36_1 (cpu.Yblock16[i], 27); cpu 7305 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode) { cpu 7315 src/dps8/dps8_ins.c word4 m = cpu.SDWAM[i].USE; cpu 7317 src/dps8/dps8_ins.c cpu.SDWAM[m].ADDR = getbits36_24 (cpu.Yblock32[j], 0); cpu 7318 src/dps8/dps8_ins.c cpu.SDWAM[m].R1 = getbits36_3 (cpu.Yblock32[j], 24); cpu 7319 src/dps8/dps8_ins.c cpu.SDWAM[m].R2 = getbits36_3 (cpu.Yblock32[j], 27); cpu 7320 src/dps8/dps8_ins.c cpu.SDWAM[m].R3 = getbits36_3 (cpu.Yblock32[j], 30); cpu 7322 src/dps8/dps8_ins.c cpu.SDWAM[m].BOUND = getbits36_14 (cpu.Yblock32[j + 1], 37 - 36); cpu 7323 src/dps8/dps8_ins.c cpu.SDWAM[m].R = getbits36_1 (cpu.Yblock32[j + 1], 51 - 36); cpu 7324 src/dps8/dps8_ins.c cpu.SDWAM[m].E = getbits36_1 (cpu.Yblock32[j + 1], 52 - 36); cpu 7325 src/dps8/dps8_ins.c cpu.SDWAM[m].W = getbits36_1 (cpu.Yblock32[j + 1], 53 - 36); cpu 7326 src/dps8/dps8_ins.c cpu.SDWAM[m].P = getbits36_1 (cpu.Yblock32[j + 1], 54 - 36); cpu 7327 src/dps8/dps8_ins.c cpu.SDWAM[m].U = getbits36_1 (cpu.Yblock32[j + 1], 55 - 36); cpu 7328 src/dps8/dps8_ins.c cpu.SDWAM[m].G = getbits36_1 (cpu.Yblock32[j + 1], 56 - 36); cpu 7329 src/dps8/dps8_ins.c cpu.SDWAM[m].C = getbits36_1 (cpu.Yblock32[j + 1], 57 - 36); cpu 7330 src/dps8/dps8_ins.c cpu.SDWAM[m].EB = getbits36_14 (cpu.Yblock32[j + 1], 58 - 36); cpu 7348 src/dps8/dps8_ins.c uint reg = cpu.tweaks.l68_mode ? L68_APU_HIST_REG : DPS8M_APU_HIST_REG; cpu 7349 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0]; cpu 7350 src/dps8/dps8_ins.c cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1]; cpu 7351 src/dps8/dps8_ins.c cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE; cpu 7359 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu.faultRegister[0]; cpu 7360 src/dps8/dps8_ins.c cpu.Ypair[1] = cpu.faultRegister[1]; cpu 7361 src/dps8/dps8_ins.c cpu.faultRegister[0] = 0; cpu 7362 src/dps8/dps8_ins.c cpu.faultRegister[1] = 0; cpu 7370 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu.MR.r; cpu 7371 src/dps8/dps8_ins.c putbits36_1 (& cpu.Ypair[0], 20, cpu.MR.sdpap); cpu 7372 src/dps8/dps8_ins.c putbits36_1 (& cpu.Ypair[0], 21, cpu.MR.separ); cpu 7373 src/dps8/dps8_ins.c putbits36_1 (& cpu.Ypair[0], 30, cpu.MR.ihr); cpu 7374 src/dps8/dps8_ins.c DPS8M_ (putbits36_1 (& cpu.Ypair[0], 33, cpu.MR.hexfp);) cpu 7376 src/dps8/dps8_ins.c cpu.Ypair[1] = 0; cpu 7377 src/dps8/dps8_ins.c putbits36_15 (& cpu.Ypair[1], 36 - 36, cpu 7378 src/dps8/dps8_ins.c cpu.CMR.cache_dir_address); cpu 7379 src/dps8/dps8_ins.c putbits36_1 (& cpu.Ypair[1], 51 - 36, cpu.CMR.par_bit); cpu 7380 src/dps8/dps8_ins.c putbits36_1 (& cpu.Ypair[1], 52 - 36, cpu.CMR.lev_ful); cpu 7381 src/dps8/dps8_ins.c putbits36_1 (& cpu.Ypair[1], 54 - 36, cpu.CMR.csh1_on); cpu 7382 src/dps8/dps8_ins.c putbits36_1 (& cpu.Ypair[1], 55 - 36, cpu.CMR.csh2_on); cpu 7383 src/dps8/dps8_ins.c L68_ (putbits36_1 (& cpu.Ypair[1], 56 - 36, cpu.CMR.opnd_on);) cpu 7384 src/dps8/dps8_ins.c putbits36_1 (& cpu.Ypair[1], 57 - 36, cpu.CMR.inst_on); cpu 7385 src/dps8/dps8_ins.c putbits36_1 (& cpu.Ypair[1], 59 - 36, cpu.CMR.csh_reg); cpu 7386 src/dps8/dps8_ins.c putbits36_1 (& cpu.Ypair[1], 60 - 36, cpu.CMR.str_asd); cpu 7387 src/dps8/dps8_ins.c putbits36_1 (& cpu.Ypair[1], 61 - 36, cpu.CMR.col_ful); cpu 7388 src/dps8/dps8_ins.c putbits36_2 (& cpu.Ypair[1], 62 - 36, cpu.CMR.rro_AB); cpu 7389 src/dps8/dps8_ins.c DPS8M_ (putbits36_1 (& cpu.Ypair[1], 68 - 36, cpu.CMR.bypass_cache);) cpu 7390 src/dps8/dps8_ins.c putbits36_2 (& cpu.Ypair[1], 70 - 36, cpu.CMR.luf); cpu 7396 src/dps8/dps8_ins.c uint reg = cpu.tweaks.l68_mode ? L68_DU_HIST_REG : DPS8M_EAPU_HIST_REG; cpu 7397 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0]; cpu 7398 src/dps8/dps8_ins.c cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1]; cpu 7399 src/dps8/dps8_ins.c cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE; cpu 7405 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu 7406 src/dps8/dps8_ins.c cpu.history[CU_HIST_REG] cpu 7407 src/dps8/dps8_ins.c [cpu.history_cyclic[CU_HIST_REG]][0]; cpu 7408 src/dps8/dps8_ins.c cpu.Ypair[1] = cpu 7409 src/dps8/dps8_ins.c cpu.history[CU_HIST_REG] cpu 7410 src/dps8/dps8_ins.c [cpu.history_cyclic[CU_HIST_REG]][1]; cpu 7411 src/dps8/dps8_ins.c cpu.history_cyclic[CU_HIST_REG] = cpu 7412 src/dps8/dps8_ins.c (cpu.history_cyclic[CU_HIST_REG] + 1) % N_MODEL_HIST_SIZE; cpu 7418 src/dps8/dps8_ins.c uint reg = cpu.tweaks.l68_mode ? L68_OU_HIST_REG : DPS8M_DU_OU_HIST_REG; cpu 7419 src/dps8/dps8_ins.c cpu.Ypair[0] = cpu.history[reg] [cpu.history_cyclic[reg]][0]; cpu 7420 src/dps8/dps8_ins.c cpu.Ypair[1] = cpu.history[reg] [cpu.history_cyclic[reg]][1]; cpu 7421 src/dps8/dps8_ins.c cpu.history_cyclic[reg] = (cpu.history_cyclic[reg] + 1) % N_MODEL_HIST_SIZE; cpu 7441 src/dps8/dps8_ins.c if (cpu.cycle == EXEC_cycle) cpu 7449 src/dps8/dps8_ins.c scu2words (cpu.Yblock8); cpu 7455 src/dps8/dps8_ins.c cpu.Yblock8[j] = cpu.scu_data[j]; cpu 7464 src/dps8/dps8_ins.c cpu.Ypair[0] = ((word36) (cpu.DSBR.ADDR & PAMASK)) << (35 - 23); cpu 7471 src/dps8/dps8_ins.c cpu.Ypair[1] = ((word36) (cpu.DSBR.BND & 037777)) << (71 - 50) | cpu 7472 src/dps8/dps8_ins.c ((word36) (cpu.DSBR.U & 1)) << (71 - 55) | cpu 7473 src/dps8/dps8_ins.c ((word36) (cpu.DSBR.STACK & 07777)) << (71 - 71); cpu 7484 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) cpu 7488 src/dps8/dps8_ins.c cpu.Yblock16[j] = 0; cpu 7489 src/dps8/dps8_ins.c putbits36_15 (& cpu.Yblock16[j], 0, cpu 7490 src/dps8/dps8_ins.c cpu.PTWAM[toffset + j].POINTER); cpu 7492 src/dps8/dps8_ins.c putbits36_12 (& cpu.Yblock16[j], 15, cpu.PTWAM[toffset + j].PAGENO & 07760); cpu 7495 src/dps8/dps8_ins.c if (cpu.PTWAM[toffset + j].FE) { cpu 7498 src/dps8/dps8_ins.c parity = ((uint) cpu.PTWAM[toffset + j].POINTER << 4) | (cpu.PTWAM[toffset + j].PAGENO >> 8); cpu 7504 src/dps8/dps8_ins.c putbits36_1 (& cpu.Yblock16[j], 23, (word1) (parity & 1)); cpu 7506 src/dps8/dps8_ins.c L68_ (putbits36_12 (& cpu.Yblock16[j], 15, cpu.PTWAM[toffset + j].PAGENO); ) cpu 7507 src/dps8/dps8_ins.c putbits36_1 (& cpu.Yblock16[j], 27, cpu 7508 src/dps8/dps8_ins.c cpu.PTWAM[toffset + j].FE); cpu 7509 src/dps8/dps8_ins.c DPS8M_ (putbits36_6 (& cpu.Yblock16[j], 30, cpu.PTWAM[toffset + j].USE);) cpu 7510 src/dps8/dps8_ins.c L68_ (putbits36_4 (& cpu.Yblock16[j], 32, cpu.PTWAM[toffset + j].USE);) cpu 7522 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) cpu 7527 src/dps8/dps8_ins.c cpu.Yblock16[j] = 0; cpu 7528 src/dps8/dps8_ins.c DPS8M_ (putbits36_18 (& cpu.Yblock16[j], 0, cpu.PTWAM[toffset + j].ADDR & 0777760);) cpu 7529 src/dps8/dps8_ins.c L68_ (putbits36_18 (& cpu.Yblock16[j], 0, cpu.PTWAM[toffset + j].ADDR);) cpu 7530 src/dps8/dps8_ins.c putbits36_1 (& cpu.Yblock16[j], 29, cpu 7531 src/dps8/dps8_ins.c cpu.PTWAM[toffset + j].M); cpu 7542 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 4) & 03;) cpu 7547 src/dps8/dps8_ins.c cpu.Yblock16[j] = 0; cpu 7548 src/dps8/dps8_ins.c putbits36_15 (& cpu.Yblock16[j], 0, cpu 7549 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].POINTER); cpu 7550 src/dps8/dps8_ins.c putbits36_1 (& cpu.Yblock16[j], 27, cpu 7551 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].FE); cpu 7554 src/dps8/dps8_ins.c if (cpu.SDWAM[toffset + j].FE) { cpu 7557 src/dps8/dps8_ins.c parity = cpu.SDWAM[toffset + j].POINTER >> 4; cpu 7563 src/dps8/dps8_ins.c putbits36_1 (& cpu.Yblock16[j], 15, (word1) (parity & 1)); cpu 7565 src/dps8/dps8_ins.c putbits36_6 (& cpu.Yblock16[j], 30, cpu.SDWAM[toffset + j].USE); cpu 7567 src/dps8/dps8_ins.c L68_ (putbits36_4 (& cpu.Yblock16[j], 32, cpu.SDWAM[toffset + j].USE);) cpu 7580 src/dps8/dps8_ins.c DPS8M_ (level = (cpu.TPR.CA >> 5) & 03;) cpu 7585 src/dps8/dps8_ins.c cpu.Yblock32[j * 2] = 0; cpu 7586 src/dps8/dps8_ins.c putbits36_24 (& cpu.Yblock32[j * 2], 0, cpu 7587 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].ADDR); cpu 7588 src/dps8/dps8_ins.c putbits36_3 (& cpu.Yblock32[j * 2], 24, cpu 7589 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].R1); cpu 7590 src/dps8/dps8_ins.c putbits36_3 (& cpu.Yblock32[j * 2], 27, cpu 7591 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].R2); cpu 7592 src/dps8/dps8_ins.c putbits36_3 (& cpu.Yblock32[j * 2], 30, cpu 7593 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].R3); cpu 7594 src/dps8/dps8_ins.c cpu.Yblock32[j * 2 + 1] = 0; cpu 7596 src/dps8/dps8_ins.c putbits36_14 (& cpu.Yblock32[j * 2 + 1], 37 - 36, cpu 7597 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].BOUND); cpu 7598 src/dps8/dps8_ins.c putbits36_1 (& cpu.Yblock32[j * 2 + 1], 51 - 36, cpu 7599 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].R); cpu 7600 src/dps8/dps8_ins.c putbits36_1 (& cpu.Yblock32[j * 2 + 1], 52 - 36, cpu 7601 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].E); cpu 7602 src/dps8/dps8_ins.c putbits36_1 (& cpu.Yblock32[j * 2 + 1], 53 - 36, cpu 7603 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].W); cpu 7604 src/dps8/dps8_ins.c putbits36_1 (& cpu.Yblock32[j * 2 + 1], 54 - 36, cpu 7605 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].P); cpu 7606 src/dps8/dps8_ins.c putbits36_1 (& cpu.Yblock32[j * 2 + 1], 55 - 36, cpu 7607 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].U); cpu 7608 src/dps8/dps8_ins.c putbits36_1 (& cpu.Yblock32[j * 2 + 1], 56 - 36, cpu 7609 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].G); cpu 7610 src/dps8/dps8_ins.c putbits36_1 (& cpu.Yblock32[j * 2 + 1], 57 - 36, cpu 7611 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].C); cpu 7612 src/dps8/dps8_ins.c putbits36_14 (& cpu.Yblock32[j * 2 + 1], 58 - 36, cpu 7613 src/dps8/dps8_ins.c cpu.SDWAM[toffset + j].EB); cpu 7627 src/dps8/dps8_ins.c if (cpu.tweaks.enable_wam) cpu 7629 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode || cpu.cu.PT_ON) // only clear when enabled cpu 7632 src/dps8/dps8_ins.c cpu.PTWAM[i].FE = 0; cpu 7633 src/dps8/dps8_ins.c L68_ (cpu.PTWAM[i].USE = (word4) i;) cpu 7634 src/dps8/dps8_ins.c DPS8M_ (cpu.PTWAM[i].USE = 0;) cpu 7648 src/dps8/dps8_ins.c DPS8M_ (if (cpu.TPR.CA != 0000002 && (cpu.TPR.CA & 3) != 0) cpu 7649 src/dps8/dps8_ins.c sim_warn ("CAMP ignores enable/disable %06o\n", cpu.TPR.CA);) cpu 7650 src/dps8/dps8_ins.c if ((cpu.TPR.CA & 3) == 02) cpu 7651 src/dps8/dps8_ins.c cpu.cu.PT_ON = 1; cpu 7652 src/dps8/dps8_ins.c else if ((cpu.TPR.CA & 3) == 01) cpu 7653 src/dps8/dps8_ins.c cpu.cu.PT_ON = 0; cpu 7657 src/dps8/dps8_ins.c cpu.PTW0.FE = 0; cpu 7658 src/dps8/dps8_ins.c cpu.PTW0.USE = 0; cpu 7673 src/dps8/dps8_ins.c if (cpu.tweaks.enable_wam) cpu 7675 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode || cpu.cu.SD_ON) // only clear when enabled cpu 7678 src/dps8/dps8_ins.c cpu.SDWAM[i].FE = 0; cpu 7679 src/dps8/dps8_ins.c L68_ (cpu.SDWAM[i].USE = (word4) i;) cpu 7680 src/dps8/dps8_ins.c DPS8M_ (cpu.SDWAM[i].USE = 0;) cpu 7693 src/dps8/dps8_ins.c DPS8M_ (if (cpu.TPR.CA != 0000006 && (cpu.TPR.CA & 3) != 0) cpu 7694 src/dps8/dps8_ins.c sim_warn ("CAMS ignores enable/disable %06o\n", cpu.TPR.CA);) cpu 7695 src/dps8/dps8_ins.c if ((cpu.TPR.CA & 3) == 02) cpu 7696 src/dps8/dps8_ins.c cpu.cu.SD_ON = 1; cpu 7697 src/dps8/dps8_ins.c else if ((cpu.TPR.CA & 3) == 01) cpu 7698 src/dps8/dps8_ins.c cpu.cu.SD_ON = 0; cpu 7702 src/dps8/dps8_ins.c cpu.SDW0.FE = 0; cpu 7703 src/dps8/dps8_ins.c cpu.SDW0.USE = 0; cpu 7717 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) cpu 7718 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) cpu 7729 src/dps8/dps8_ins.c & cpu.rA, & cpu.rQ); cpu 7736 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); cpu 7737 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 7776 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 10) & 03;) cpu 7777 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 10) & 07;) cpu 7787 src/dps8/dps8_ins.c putbits36 (& cpu.faultRegister[0], 16, 4, 010); cpu 7789 src/dps8/dps8_ins.c putbits36 (& cpu.faultRegister[0], 20, 4, 010); cpu 7791 src/dps8/dps8_ins.c putbits36 (& cpu.faultRegister[0], 24, 4, 010); cpu 7793 src/dps8/dps8_ins.c putbits36 (& cpu.faultRegister[0], 28, 4, 010); cpu 7800 src/dps8/dps8_ins.c uint function = (cpu.iefpFinalAddress >> 3) & 07; cpu 7805 src/dps8/dps8_ins.c cpu.iefpFinalAddress & MASK15, cpu 7806 src/dps8/dps8_ins.c & cpu.rA, & cpu.rQ); cpu 7818 src/dps8/dps8_ins.c if (! cpu.tweaks.l68_mode) { cpu 7826 src/dps8/dps8_ins.c cpu.rA = PROM[cpu.TPR.CA & 1023]; cpu 7830 src/dps8/dps8_ins.c uint select = cpu.TPR.CA & 0x7; cpu 7834 src/dps8/dps8_ins.c cpu.rA = cpu.switches.data_switches; cpu 7864 src/dps8/dps8_ins.c cpu.rA = 0; cpu 7865 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [0] & 07LL) cpu 7867 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [0] & 01LL) cpu 7869 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [0] & 01LL) cpu 7871 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [0] ? 1LL:0LL) cpu 7873 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [0] & 07LL) cpu 7876 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [1] & 07LL) cpu 7878 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [1] & 01LL) cpu 7880 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [1] & 01LL) cpu 7882 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [1] ? 1LL:0LL) cpu 7884 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [1] & 07LL) cpu 7887 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [2] & 07LL) cpu 7889 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [2] & 01LL) cpu 7891 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [2] & 01LL) cpu 7893 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [2] ? 1LL:0LL) cpu 7895 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [2] & 07LL) cpu 7898 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [3] & 07LL) cpu 7900 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [3] & 01LL) cpu 7902 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [3] & 01LL) cpu 7904 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [3] ? 1LL:0LL) cpu 7906 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [3] & 07LL) cpu 7977 src/dps8/dps8_ins.c cpu.rA = 0; cpu 7979 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[0] == 2 ? cpu 7981 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[1] == 2 ? cpu 7983 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[2] == 2 ? cpu 7985 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.interlace[3] == 2 ? cpu 7989 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode) cpu 7995 src/dps8/dps8_ins.c cpu.rA |= (word36) ((01L) /* 0b01 DPS8M */ cpu 7997 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.FLT_BASE & 0177LL) cpu 7999 src/dps8/dps8_ins.c DPS8M_ (cpu.rA |= (word36) ((01L) /* 0b1 ID_PROM installed */ cpu 8010 src/dps8/dps8_ins.c if (cpu.tweaks.l68_mode) cpu 8016 src/dps8/dps8_ins.c cpu.rA |= (word36) ((01L) // 0b1 L68/DPS option: DPS cpu 8022 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.enable_cache ? 1 : 0) cpu 8027 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.procMode) /* 0b1 DPS8M */ cpu 8029 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.procMode & 1U) cpu 8037 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.options.proc_speed & 017LL) cpu 8048 src/dps8/dps8_ins.c cpu.rA |= (word36) ((016L) // 0b1110 CPU ID cpu 8051 src/dps8/dps8_ins.c cpu.rA |= (word36) ((cpu.switches.cpu_num & 07LL) cpu 8056 src/dps8/dps8_ins.c if (!cpu.tweaks.l68_mode) { // DPS8M cpu 8057 src/dps8/dps8_ins.c cpu.rA = 0; cpu 8087 src/dps8/dps8_ins.c cpu.rA = 0; cpu 8088 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [4] & 07LL) cpu 8090 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [4] & 01LL) cpu 8092 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [4] & 01LL) cpu 8094 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [4] ? 1LL:0LL) cpu 8096 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [4] & 07LL) cpu 8099 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [5] & 07LL) cpu 8101 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [5] & 01LL) cpu 8103 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [5] & 01LL) cpu 8105 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [5] ? 1LL:0LL) cpu 8107 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [5] & 07LL) cpu 8110 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [6] & 07LL) cpu 8112 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [6] & 01LL) cpu 8114 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [6] & 01LL) cpu 8116 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [6] ? 1LL:0LL) cpu 8118 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [6] & 07LL) cpu 8121 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.assignment [7] & 07LL) cpu 8123 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.enable [7] & 01LL) cpu 8125 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.init_enable [7] & 01LL) cpu 8127 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [7] ? 1LL:0LL) cpu 8129 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.store_size [7] & 07LL) cpu 8149 src/dps8/dps8_ins.c cpu.rA = 0; cpu 8150 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [0] == 2 ? cpu 8152 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [1] == 2 ? cpu 8154 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [2] == 2 ? cpu 8156 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [3] == 2 ? cpu 8159 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [4] == 2 ? cpu 8161 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [5] == 2 ? cpu 8163 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [6] == 2 ? cpu 8165 src/dps8/dps8_ins.c cpu.rA |= (word36) (cpu.switches.interlace [7] == 2 ? cpu 8179 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); cpu 8180 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 8191 src/dps8/dps8_ins.c int cpu_port_num = lookup_cpu_mem_map (cpu.iefpFinalAddress); cpu 8215 src/dps8/dps8_ins.c word8 sub_mask = getbits36_8 (cpu.CY, 0); cpu 8216 src/dps8/dps8_ins.c word3 expander_command = getbits36_3 (cpu.CY, 21); cpu 8217 src/dps8/dps8_ins.c uint scu_port_num = (uint) getbits36_3 (cpu.CY, 33); cpu 8229 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) cpu 8230 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) cpu 8240 src/dps8/dps8_ins.c current_running_cpu_idx, cpu.rA, cpu.rQ); cpu 8257 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 15) & 03;) cpu 8258 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 15) & 07;) cpu 8265 src/dps8/dps8_ins.c putbits36_4 (& cpu.faultRegister[0], 16, 010); cpu 8267 src/dps8/dps8_ins.c putbits36_4 (& cpu.faultRegister[0], 20, 010); cpu 8269 src/dps8/dps8_ins.c putbits36_4 (& cpu.faultRegister[0], 24, 010); cpu 8271 src/dps8/dps8_ins.c putbits36 (& cpu.faultRegister[0], 28, 4, 010); cpu 8277 src/dps8/dps8_ins.c cpu_port_num, cpu.rA); cpu 8288 src/dps8/dps8_ins.c DPS8M_ (cpu_port_num = (cpu.TPR.CA >> 10) & 03;) cpu 8289 src/dps8/dps8_ins.c L68_ (cpu_port_num = (cpu.TPR.CA >> 10) & 07;) cpu 8294 src/dps8/dps8_ins.c putbits36_4 (& cpu.faultRegister[0], 16, 010); cpu 8296 src/dps8/dps8_ins.c putbits36_4 (& cpu.faultRegister[0], 20, 010); cpu 8298 src/dps8/dps8_ins.c putbits36_4 (& cpu.faultRegister[0], 24, 010); cpu 8300 src/dps8/dps8_ins.c putbits36 (& cpu.faultRegister[0], 28, 4, 010); cpu 8305 src/dps8/dps8_ins.c cpu_port_num, cpu.iefpFinalAddress & MASK15, cpu 8306 src/dps8/dps8_ins.c cpu.rA, cpu.rQ); cpu 8321 src/dps8/dps8_ins.c cpu.rA = result; cpu 8325 src/dps8/dps8_ins.c SC_I_ZERO (cpu.rA == 0); cpu 8326 src/dps8/dps8_ins.c SC_I_NEG (cpu.rA & SIGN36); cpu 8332 src/dps8/dps8_ins.c if (! cpu.tweaks.dis_enable) cpu 8344 src/dps8/dps8_ins.c if ((! cpu.tweaks.tro_enable) && cpu 8350 src/dps8/dps8_ins.c " no events in queue\n", cpu.PPR.IC); cpu 8356 src/dps8/dps8_ins.c (unsigned long long)cpu.cycleCnt); cpu 8362 src/dps8/dps8_ins.c (unsigned long long)cpu.cycleCnt); cpu 8363 src/dps8/dps8_ins.c longjmp (cpu.jmpMain, JMP_STOP); cpu 8367 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 0430 && cpu.PPR.IC == 012) cpu 8374 src/dps8/dps8_ins.c longjmp (cpu.jmpMain, JMP_STOP); cpu 8387 src/dps8/dps8_ins.c cpu 8389 src/dps8/dps8_ins.c cpu 8391 src/dps8/dps8_ins.c cpu 8397 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 034 && cpu.PPR.IC == 03535) cpu 8399 src/dps8/dps8_ins.c sim_printf ("[%lld] sys_trouble$die DIS causes CPU halt\n", cpu.cycleCnt); cpu 8402 src/dps8/dps8_ins.c cpu.isRunning = false; cpu 8433 src/dps8/dps8_ins.c cpu.interrupt_flag = true; cpu 8439 src/dps8/dps8_ins.c if (GET_I (cpu.cu.IWB) ? bG7PendingNoTRO () : bG7Pending ()) cpu 8445 src/dps8/dps8_ins.c cpu 8450 src/dps8/dps8_ins.c cpu.g7_flag = true; cpu 8457 src/dps8/dps8_ins.c if (cpu.tweaks.isolts_mode) cpu 8460 src/dps8/dps8_ins.c cpu.isRunning = false; cpu 8489 src/dps8/dps8_ins.c if (getbits36_1 (cpu.CY, 23) != 0) cpu 8498 src/dps8/dps8_ins.c cpu.AR[n].WORDNO = GETHI (cpu.CY); cpu 8500 src/dps8/dps8_ins.c uint TA = getbits36_2 (cpu.CY, 21); cpu 8501 src/dps8/dps8_ins.c uint CN = getbits36_3 (cpu.CY, 18); cpu 8541 src/dps8/dps8_ins.c cpu.AR[n].WORDNO = 0; cpu 8564 src/dps8/dps8_ins.c cpu.AR[n].WORDNO = 0; cpu 8594 src/dps8/dps8_ins.c cpu.AR[n].WORDNO = GETHI (cpu.CY); cpu 8596 src/dps8/dps8_ins.c SET_AR_CHAR_BITNO (n, getbits36_2 (cpu.CY, 18), cpu 8597 src/dps8/dps8_ins.c getbits36_4 (cpu.CY, 20)); cpu 8612 src/dps8/dps8_ins.c word36 tmp36 = cpu.Yblock8[n]; cpu 8613 src/dps8/dps8_ins.c cpu.AR[n].WORDNO = getbits36_18 (tmp36, 0); cpu 8626 src/dps8/dps8_ins.c words2du (cpu.Yblock8); cpu 8647 src/dps8/dps8_ins.c cpu.AR[n].WORDNO = GETHI (cpu.CY); cpu 8649 src/dps8/dps8_ins.c uint TN = getbits36_1 (cpu.CY, 21); // C(Y) 21 cpu 8650 src/dps8/dps8_ins.c uint CN = getbits36_3 (cpu.CY, 18); // C(Y) 18-20 cpu 8722 src/dps8/dps8_ins.c uint TA = getbits36_2 (cpu.CY, 21); cpu 8730 src/dps8/dps8_ins.c if (getbits36_1 (cpu.CY, 23) != 0) { cpu 8740 src/dps8/dps8_ins.c putbits36_18 (& cpu.CY, 0, cpu.AR[n].WORDNO & MASK18); cpu 8754 src/dps8/dps8_ins.c putbits36_3 (& cpu.CY, 18, (word3) CN & MASK3); cpu 8761 src/dps8/dps8_ins.c putbits36_3 (& cpu.CY, 18, (word3) CN & MASK3); cpu 8768 src/dps8/dps8_ins.c putbits36_3 (& cpu.CY, 18, cpu 8772 src/dps8/dps8_ins.c cpu.zone = 0777777700000; cpu 8773 src/dps8/dps8_ins.c cpu.useZone = true; cpu 8796 src/dps8/dps8_ins.c uint TN = getbits36_1 (cpu.CY, 21); // C(Y) 21 cpu 8800 src/dps8/dps8_ins.c putbits36_18 (& cpu.CY, 0, cpu.AR[n].WORDNO & MASK18); cpu 8811 src/dps8/dps8_ins.c putbits36_3 (& cpu.CY, 18, CN & MASK3); cpu 8818 src/dps8/dps8_ins.c putbits36_3 (& cpu.CY, 18, cpu 8822 src/dps8/dps8_ins.c cpu.zone = 0777777700000; cpu 8823 src/dps8/dps8_ins.c cpu.useZone = true; cpu 8845 src/dps8/dps8_ins.c putbits36 (& cpu.CY, 0, 18, cpu.PR[n].WORDNO); cpu 8847 src/dps8/dps8_ins.c putbits36 (& cpu.CY, 18, 2, GET_AR_CHAR (n)); cpu 8848 src/dps8/dps8_ins.c putbits36 (& cpu.CY, 20, 4, GET_AR_BITNO (n)); cpu 8850 src/dps8/dps8_ins.c cpu.zone = 0777777770000; cpu 8851 src/dps8/dps8_ins.c cpu.useZone = true; cpu 8861 src/dps8/dps8_ins.c memset (cpu.Yblock8, 0, sizeof (cpu.Yblock8)); cpu 8866 src/dps8/dps8_ins.c putbits36 (& arx, 0, 18, cpu.PR[n].WORDNO); cpu 8869 src/dps8/dps8_ins.c cpu.Yblock8[n] = arx; cpu 8877 src/dps8/dps8_ins.c du2words (cpu.Yblock8); cpu 9090 src/dps8/dps8_ins.c if (cpu.tweaks.enable_emcall) { cpu 9101 src/dps8/dps8_ins.c if (cpu.tweaks.halt_on_unimp) cpu 9108 src/dps8/dps8_ins.c cpu.ou.STR_OP = (is_ou && (i->info->flags & (STORE_OPERAND | STORE_YPAIR))) ? 1 : 0; cpu 9109 src/dps8/dps8_ins.c cpu.ou.cycle |= ou_GOF; cpu 9110 src/dps8/dps8_ins.c if (cpu.MR_cache.emr && cpu.MR_cache.ihr && is_ou) cpu 9112 src/dps8/dps8_ins.c if (cpu.MR_cache.emr && cpu.MR_cache.ihr && is_du) cpu 9132 src/dps8/dps8_ins.c DCDstruct * i = & cpu.currentInstruction; cpu 9156 src/dps8/dps8_ins.c startInstrCnt = cpu.instrCnt; cpu 9177 src/dps8/dps8_ins.c unsigned long long nInsts = cpu.instrCnt - startInstrCnt; cpu 9209 src/dps8/dps8_ins.c cpu 9212 src/dps8/dps8_ins.c cpu 9219 src/dps8/dps8_ins.c cpu 9228 src/dps8/dps8_ins.c cpu 9240 src/dps8/dps8_ins.c cpu 9246 src/dps8/dps8_ins.c cpu 9251 src/dps8/dps8_ins.c cpu 9269 src/dps8/dps8_ins.c cpu 9270 src/dps8/dps8_ins.c cpu 9278 src/dps8/dps8_ins.c cpu 9279 src/dps8/dps8_ins.c cpu 9283 src/dps8/dps8_ins.c cpu 9292 src/dps8/dps8_ins.c cpu 9298 src/dps8/dps8_ins.c cpu 9303 src/dps8/dps8_ins.c cpu 9318 src/dps8/dps8_ins.c cpu 9320 src/dps8/dps8_ins.c cpu 9377 src/dps8/dps8_ins.c cpu 9379 src/dps8/dps8_ins.c cpu 9401 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, & cpu_dev, "absa CA:%08o\n", cpu.TPR.CA); cpu 9405 src/dps8/dps8_ins.c if (get_addr_mode () == ABSOLUTE_mode && ! (cpu.cu.XSF || cpu.currentInstruction.b29)) // ISOLTS-860 cpu 9407 src/dps8/dps8_ins.c * result = ((word36) (cpu.TPR.CA & MASK18)) << 12; // 24:12 format cpu 9429 src/dps8/dps8_ins.c sim_printf (" rcu to %05o:%06o PSR:IC %05o:%06o\r\n", (cpu.Yblock8[0]>>18)&MASK15, (cpu.Yblock8[4]>>18)&MASK18, cpu.PPR.PSR, cpu.PPR.IC); cpu 9434 src/dps8/dps8_ins.c dump_words(cpu.Yblock8); cpu 9442 src/dps8/dps8_ins.c words2scu (cpu.Yblock8); cpu 9443 src/dps8/dps8_ins.c decode_instruction (IWB_IRODD, & cpu.currentInstruction); cpu 9447 src/dps8/dps8_ins.c word1 saveP = cpu.PPR.P; // ISOLTS-870 02m cpu 9452 src/dps8/dps8_ins.c cpu.PPR.P = saveP; cpu 9454 src/dps8/dps8_ins.c if (getbits36_1 (cpu.Yblock8[1], 35) == 0) // cpu.cu.FLT_INT is interrupt, not fault cpu 9457 src/dps8/dps8_ins.c longjmp (cpu.jmpMain, JMP_REFETCH); cpu 9525 src/dps8/dps8_ins.c if (cpu.cu.FIF) // fault occurred during instruction fetch cpu 9533 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cpu 9535 src/dps8/dps8_ins.c longjmp (cpu.jmpMain, JMP_REFETCH); cpu 9539 src/dps8/dps8_ins.c if (cpu.cu.rfi) cpu 9546 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cpu 9547 src/dps8/dps8_ins.c longjmp (cpu.jmpMain, JMP_REFETCH); cpu 9553 src/dps8/dps8_ins.c word5 fi_addr = getbits36_5 (cpu.Yblock8[1], 30); cpu 9563 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cpu 9564 src/dps8/dps8_ins.c longjmp (cpu.jmpMain, JMP_RESTART); cpu 9567 src/dps8/dps8_ins.c if (cpu.cu.rfi || // S/W asked for the instruction to be started cpu 9568 src/dps8/dps8_ins.c cpu.cu.FIF) // fault occurred during instruction fetch cpu 9577 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cpu 9579 src/dps8/dps8_ins.c longjmp (cpu.jmpMain, JMP_REFETCH); cpu 9590 src/dps8/dps8_ins.c cpu.cu.rfi = 1; cpu 9591 src/dps8/dps8_ins.c longjmp (cpu.jmpMain, JMP_RESTART); cpu 9621 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cpu 9622 src/dps8/dps8_ins.c longjmp (cpu.jmpMain, JMP_SYNC_FAULT_RETURN); cpu 9635 src/dps8/dps8_ins.c cpu.cu.rfi = 0; cpu 9636 src/dps8/dps8_ins.c longjmp (cpu.jmpMain, JMP_SYNC_FAULT_RETURN); cpu 9643 src/dps8/dps8_ins.c cpu.cu.rfi = 1; cpu 9645 src/dps8/dps8_ins.c longjmp (cpu.jmpMain, JMP_RESTART); cpu 9660 src/dps8/dps8_ins.c cpu.cu.rfi = 1; cpu 9662 src/dps8/dps8_ins.c longjmp (cpu.jmpMain, JMP_RESTART); cpu 3311 src/dps8/dps8_iom.c sim_printf ("// CIOC %lld\r\n", cpu.cycleCnt); cpu 3472 src/dps8/dps8_iom.c __func__, iomChar (iom_unit_idx), cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC); cpu 50 src/dps8/dps8_math.c #define DBG_CTR cpu.cycleCnt cpu 76 src/dps8/dps8_math.c word72 Mant = convert_to_word72 (cpu.rA, cpu.rQ); cpu 92 src/dps8/dps8_math.c int e = SIGNEXT8_int (cpu . rE & MASK8); // make signed cpu 128 src/dps8/dps8_math.c word72 Mant = convert_to_word72 (cpu.rA, cpu.rQ); cpu 144 src/dps8/dps8_math.c int e = SIGNEXT8_int (cpu . rE & MASK8); // make signed cpu 291 src/dps8/dps8_math.c cpu . rA = 0; cpu 295 src/dps8/dps8_math.c cpu . rQ = 0; cpu 296 src/dps8/dps8_math.c cpu . rE = 0200U; /*-128*/ cpu 332 src/dps8/dps8_math.c cpu . rE = exp & MASK8; cpu 333 src/dps8/dps8_math.c cpu . rA = (result >> 36) & MASK36; cpu 337 src/dps8/dps8_math.c cpu . rQ = result & MASK36; cpu 450 src/dps8/dps8_math.c return (! cpu.tweaks.l68_mode) && (!! cpu.options.hex_mode_installed) && (!! cpu.MR.hexfp) && (!! TST_I_HEX); cpu 480 src/dps8/dps8_math.c word72 m1 = convert_to_word72 (cpu.rA, cpu.rQ); cpu 483 src/dps8/dps8_math.c word72 m2 = lshift_128 (construct_128 (0, (uint64_t) getbits36_28 (cpu.CY, 8)), 44u); // 28-bit mantissa (incl sign) cpu 485 src/dps8/dps8_math.c word72 m2 = ((word72) getbits36_28 (cpu.CY, 8)) << 44; // 28-bit mantissa (incl sign) cpu 488 src/dps8/dps8_math.c int e1 = SIGNEXT8_int (cpu.rE & MASK8); cpu 489 src/dps8/dps8_math.c int e2 = SIGNEXT8_int (getbits36_8 (cpu.CY, 0)); cpu 524 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GOE;) cpu 601 src/dps8/dps8_math.c m3 = Add72b (m1, m2, 0, I_CARRY, & cpu.cu.IR, & ovf); cpu 673 src/dps8/dps8_math.c convert_to_word36 (m3, & cpu.rA, & cpu.rQ); cpu 677 src/dps8/dps8_math.c cpu.rE = e3 & 0377; cpu 679 src/dps8/dps8_math.c SC_I_NEG (cpu.rA & SIGN36); // Do this here instead of in Add72b because cpu 681 src/dps8/dps8_math.c if (cpu.rA == 0 && cpu.rQ == 0) { cpu 683 src/dps8/dps8_math.c cpu.rE = 0200U; /*-128*/ cpu 689 src/dps8/dps8_math.c fno_ext (& e3, & cpu.rE, & cpu.rA, & cpu.rQ); cpu 735 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GON;) cpu 1078 src/dps8/dps8_math.c word72 m = convert_to_word72 (cpu.rA, cpu.rQ); cpu 1093 src/dps8/dps8_math.c if (cpu.rE == 127) { cpu 1098 src/dps8/dps8_math.c cpu.rE ++; cpu 1099 src/dps8/dps8_math.c cpu.rE &= MASK8; cpu 1110 src/dps8/dps8_math.c convert_to_word36 (m, & cpu.rA, & cpu.rQ); cpu 1111 src/dps8/dps8_math.c fno (& cpu.rE, & cpu.rA, & cpu.rQ); // normalize cpu 1131 src/dps8/dps8_math.c word72 m1 = convert_to_word72 (cpu.rA, cpu.rQ); cpu 1132 src/dps8/dps8_math.c int e1 = SIGNEXT8_int (cpu.rE & MASK8); cpu 1134 src/dps8/dps8_math.c word72 m2 = lshift_128 (construct_128 (0, (uint64_t) getbits36_28 (cpu.CY, 8)), 44u); // 28-bit mantissa (incl sign) cpu 1136 src/dps8/dps8_math.c word72 m2 = ((word72) getbits36_28 (cpu.CY, 8)) << 44; ///< 28-bit mantissa (incl sign) cpu 1138 src/dps8/dps8_math.c int e2 = SIGNEXT8_int (getbits36_8 (cpu.CY, 0)); cpu 1144 src/dps8/dps8_math.c cpu.rE = 0200U; /*-128*/ cpu 1145 src/dps8/dps8_math.c cpu.rA = 0; cpu 1149 src/dps8/dps8_math.c cpu.rQ = 0; cpu 1209 src/dps8/dps8_math.c convert_to_word36 (m3a, & cpu.rA, & cpu.rQ); cpu 1213 src/dps8/dps8_math.c cpu.rE = (word8) e3 & MASK8; cpu 1214 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "fmp A %012"PRIo64" Q %012"PRIo64" E %03o\n", cpu.rA, cpu.rQ, cpu.rE); cpu 1215 src/dps8/dps8_math.c SC_I_NEG (cpu.rA & SIGN36); cpu 1217 src/dps8/dps8_math.c if (cpu.rA == 0 && cpu.rQ == 0) { cpu 1219 src/dps8/dps8_math.c cpu.rE = 0200U; /*-128*/ cpu 1225 src/dps8/dps8_math.c fno_ext (& e3, & cpu.rE, & cpu.rA, & cpu.rQ); cpu 1272 src/dps8/dps8_math.c m1 = convert_to_word72 (cpu.rA, cpu.rQ); cpu 1273 src/dps8/dps8_math.c e1 = SIGNEXT8_int (cpu.rE & MASK8); cpu 1276 src/dps8/dps8_math.c m2 = lshift_128 (construct_128 (0, (uint64_t) getbits36_28 (cpu.CY, 8)), 44u); // 28-bit mantissa (incl sign) cpu 1278 src/dps8/dps8_math.c m2 = ((word72) getbits36_28 (cpu.CY, 8)) << 44; ///< 28-bit mantissa (incl sign) cpu 1280 src/dps8/dps8_math.c e2 = SIGNEXT8_int (getbits36_8 (cpu.CY, 0)); cpu 1284 src/dps8/dps8_math.c m2 = convert_to_word72 (cpu.rA, cpu.rQ); cpu 1285 src/dps8/dps8_math.c e2 = SIGNEXT8_int (cpu.rE & MASK8); cpu 1299 src/dps8/dps8_math.c m1 = lshift_128 (construct_128 (0, getbits36_28 (cpu.CY, 8)), 44); ///< 28-bit mantissa (incl sign) cpu 1300 src/dps8/dps8_math.c e1 = SIGNEXT8_int (getbits36_8 (cpu.CY, 0)); cpu 1309 src/dps8/dps8_math.c m1 = ((word72) getbits36_28 (cpu.CY, 8)) << 44; ///< 28-bit mantissa (incl sign) cpu 1310 src/dps8/dps8_math.c e1 = SIGNEXT8_int (getbits36_8 (cpu.CY, 0)); cpu 1318 src/dps8/dps8_math.c cpu.rE = 0200U; /*-128*/ cpu 1319 src/dps8/dps8_math.c cpu.rA = 0; cpu 1323 src/dps8/dps8_math.c cpu.rQ = 0; cpu 1391 src/dps8/dps8_math.c convert_to_word36 (m1, & cpu.rA, & cpu.rQ); cpu 1455 src/dps8/dps8_math.c cpu.rE = (word8) e3 & MASK8; cpu 1457 src/dps8/dps8_math.c cpu.rA = rshift_128 (m3, 36u).l & MASK36; cpu 1459 src/dps8/dps8_math.c cpu.rA = (m3 >> 36) & MASK36; cpu 1464 src/dps8/dps8_math.c cpu.rQ = 0; cpu 1466 src/dps8/dps8_math.c SC_I_ZERO (cpu . rA == 0); cpu 1467 src/dps8/dps8_math.c SC_I_NEG (cpu . rA & SIGN36); cpu 1469 src/dps8/dps8_math.c if (cpu.rA == 0) // set to normalized 0 cpu 1470 src/dps8/dps8_math.c cpu.rE = 0200U; /*-128*/ cpu 1547 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 1549 src/dps8/dps8_math.c word72 m = convert_to_word72 (cpu.rA, cpu.rQ); cpu 1551 src/dps8/dps8_math.c cpu.rE = 0200U; /*-128*/ cpu 1590 src/dps8/dps8_math.c convert_to_word36 (m, & cpu.rA, & cpu.rQ); cpu 1592 src/dps8/dps8_math.c fno (& cpu.rE, & cpu.rA, & cpu.rQ); cpu 1607 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 1608 src/dps8/dps8_math.c word36 A = cpu . rA, Q = cpu . rQ; cpu 1609 src/dps8/dps8_math.c word8 E = cpu . rE; cpu 1687 src/dps8/dps8_math.c word72 m1= lshift_128 (construct_128 (0, cpu.rA & 0777777777400), 36); cpu 1689 src/dps8/dps8_math.c word72 m1 = ((word72)cpu.rA & 0777777777400LL) << 36; cpu 1691 src/dps8/dps8_math.c int e1 = SIGNEXT8_int (cpu.rE & MASK8); cpu 1695 src/dps8/dps8_math.c word72 m2 = lshift_128 (construct_128 (0, getbits36_28 (cpu.CY, 8)), 44); cpu 1697 src/dps8/dps8_math.c word72 m2 = ((word72) getbits36_28 (cpu.CY, 8)) << 44; cpu 1699 src/dps8/dps8_math.c int e2 = SIGNEXT8_int (getbits36_8 (cpu.CY, 0)); cpu 1703 src/dps8/dps8_math.c L68_ (cpu.ou.cycle = ou_GOE;) cpu 1715 src/dps8/dps8_math.c L68_ (cpu.ou.cycle = ou_GOA;) cpu 1748 src/dps8/dps8_math.c L68_ (cpu.ou.cycle = ou_GOA;) cpu 1818 src/dps8/dps8_math.c L68_ (cpu.ou.cycle = ou_GOS;) cpu 1826 src/dps8/dps8_math.c word72 m1 = lshift_128 (construct_128 (0, cpu.rA & 0777777777400), 36); cpu 1828 src/dps8/dps8_math.c word72 m1 = ((word72)cpu.rA & 0777777777400LL) << 36; cpu 1830 src/dps8/dps8_math.c int e1 = SIGNEXT8_int (cpu.rE & MASK8); cpu 1835 src/dps8/dps8_math.c word72 m2 = lshift_128 (construct_128 (0, getbits36_28 (cpu.CY, 8)), 44); cpu 1837 src/dps8/dps8_math.c word72 m2 = ((word72) getbits36_28 (cpu.CY, 8)) << 44; cpu 1839 src/dps8/dps8_math.c int e2 = SIGNEXT8_int (getbits36_8 (cpu.CY, 0)); cpu 1843 src/dps8/dps8_math.c L68_ (cpu.ou.cycle = ou_GOE;) cpu 1850 src/dps8/dps8_math.c L68_ (cpu.ou.cycle = ou_GOA;) cpu 1883 src/dps8/dps8_math.c L68_ (cpu.ou.cycle = ou_GOA;) cpu 1985 src/dps8/dps8_math.c L68_ (cpu.ou.cycle = ou_GOS;) cpu 1992 src/dps8/dps8_math.c word72 m1 = convert_to_word72 (cpu.rA, cpu.rQ); cpu 1993 src/dps8/dps8_math.c int e1 = SIGNEXT8_int (cpu.rE & MASK8); cpu 1997 src/dps8/dps8_math.c word72 m2 = lshift_128 (construct_128 (0, (uint64_t) getbits36_28 (cpu.Ypair[0], 8)), 44u); // 28-bit mantissa (incl sign) cpu 1998 src/dps8/dps8_math.c m2 = or_128 (m2, lshift_128 (construct_128 (0, cpu.Ypair[1]), 8u)); cpu 2000 src/dps8/dps8_math.c word72 m2 = ((word72) getbits36_28 (cpu.Ypair[0], 8)) << 44; cpu 2001 src/dps8/dps8_math.c m2 |= (word72) cpu.Ypair[1] << 8; cpu 2004 src/dps8/dps8_math.c int e2 = SIGNEXT8_int (getbits36_8 (cpu.Ypair[0], 0)); cpu 2047 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GOE;) cpu 2055 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GOA;) cpu 2089 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GOA;) cpu 2124 src/dps8/dps8_math.c word72 m3 = Add72b (m1, m2, 0, I_CARRY, & cpu.cu.IR, & ovf); cpu 2189 src/dps8/dps8_math.c convert_to_word36 (m3, & cpu.rA, & cpu.rQ); cpu 2193 src/dps8/dps8_math.c cpu.rE = e3 & 0377; cpu 2195 src/dps8/dps8_math.c SC_I_NEG (cpu.rA & SIGN36); // Do this here instead of in Add72b because cpu 2197 src/dps8/dps8_math.c if (cpu.rA == 0 && cpu.rQ == 0) { cpu 2199 src/dps8/dps8_math.c cpu.rE = 0200U; /*-128*/ cpu 2205 src/dps8/dps8_math.c fno_ext (& e3, & cpu.rE, & cpu.rA, & cpu.rQ); cpu 2242 src/dps8/dps8_math.c cpu 2271 src/dps8/dps8_math.c cpu 2278 src/dps8/dps8_math.c cpu 2303 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 2304 src/dps8/dps8_math.c word72 m1 = convert_to_word72 (cpu.rA, cpu.rQ); cpu 2305 src/dps8/dps8_math.c int e1 = SIGNEXT8_int (cpu . rE & MASK8); cpu 2312 src/dps8/dps8_math.c word72 m2 = lshift_128 (construct_128 (0, (uint64_t) getbits36_28 (cpu.Ypair[0], 8)), 44u); // 28-bit mantissa (incl sign) cpu 2313 src/dps8/dps8_math.c m2 = or_128 (m2, lshift_128 (construct_128 (0, cpu.Ypair[1]), 8u)); cpu 2315 src/dps8/dps8_math.c word72 m2 = ((word72) getbits36_28 (cpu.Ypair[0], 8)) << 44; cpu 2316 src/dps8/dps8_math.c m2 |= (word72) cpu.Ypair[1] << 8; cpu 2320 src/dps8/dps8_math.c int e2 = SIGNEXT8_int (getbits36_8 (cpu.Ypair[0], 0)); cpu 2330 src/dps8/dps8_math.c cpu.rE = 0200U; /*-128*/ cpu 2331 src/dps8/dps8_math.c cpu.rA = 0; cpu 2335 src/dps8/dps8_math.c cpu.rQ = 0; cpu 2413 src/dps8/dps8_math.c convert_to_word36 (m3a, & cpu.rA, & cpu.rQ); cpu 2417 src/dps8/dps8_math.c cpu.rE = (word8) e3 & MASK8; cpu 2419 src/dps8/dps8_math.c SC_I_NEG (cpu.rA & SIGN36); cpu 2421 src/dps8/dps8_math.c if (cpu.rA == 0 && cpu.rQ == 0) { cpu 2423 src/dps8/dps8_math.c cpu . rE = 0200U; /*-128*/ cpu 2429 src/dps8/dps8_math.c fno_ext (& e3, & cpu.rE, & cpu.rA, & cpu.rQ); cpu 2462 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 2477 src/dps8/dps8_math.c m1 = convert_to_word72 (cpu.rA, cpu.rQ); cpu 2478 src/dps8/dps8_math.c e1 = SIGNEXT8_int (cpu.rE & MASK8); cpu 2482 src/dps8/dps8_math.c m2 = lshift_128 (construct_128 (0, (uint64_t) getbits36_28 (cpu.Ypair[0], 8)), 44u); // 28-bit mantissa (incl sign) cpu 2483 src/dps8/dps8_math.c m2 = or_128 (m2, lshift_128 (construct_128 (0, cpu.Ypair[1]), 8u)); cpu 2485 src/dps8/dps8_math.c m2 = ((word72) getbits36_28 (cpu.Ypair[0], 8)) << 44; cpu 2486 src/dps8/dps8_math.c m2 |= (word72) cpu.Ypair[1] << 8; cpu 2489 src/dps8/dps8_math.c e2 = SIGNEXT8_int (getbits36_8 (cpu.Ypair[0], 0)); cpu 2491 src/dps8/dps8_math.c m2 = convert_to_word72 (cpu.rA, cpu.rQ); cpu 2492 src/dps8/dps8_math.c e2 = SIGNEXT8_int (cpu.rE & MASK8); cpu 2521 src/dps8/dps8_math.c m1 = lshift_128 (construct_128 (0, (uint64_t) getbits36_28 (cpu.Ypair[0], 8)), 44u); // 28-bit mantissa (incl sign) cpu 2522 src/dps8/dps8_math.c m1 = or_128 (m1, lshift_128 (construct_128 (0, cpu.Ypair[1]), 8u)); cpu 2524 src/dps8/dps8_math.c m1 = ((word72) getbits36_28 (cpu.Ypair[0], 8)) << 44; cpu 2525 src/dps8/dps8_math.c m1 |= (word72) cpu.Ypair[1] << 8; cpu 2528 src/dps8/dps8_math.c e1 = SIGNEXT8_int (getbits36_8 (cpu.Ypair[0], 0)); cpu 2535 src/dps8/dps8_math.c cpu.rE = 0200U; /*-128*/ cpu 2536 src/dps8/dps8_math.c cpu.rA = 0; cpu 2540 src/dps8/dps8_math.c cpu.rQ = 0; cpu 2607 src/dps8/dps8_math.c convert_to_word36 (m1, & cpu.rA, & cpu.rQ); cpu 2615 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GOA;) cpu 2639 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GD1;) cpu 2649 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GD2;) cpu 2661 src/dps8/dps8_math.c convert_to_word36 (m3, & cpu.rA, & cpu.rQ); cpu 2665 src/dps8/dps8_math.c cpu.rE = (word8) e3 & MASK8; cpu 2667 src/dps8/dps8_math.c SC_I_ZERO (cpu.rA == 0 && cpu . rQ == 0); cpu 2668 src/dps8/dps8_math.c SC_I_NEG (cpu.rA & SIGN36); cpu 2670 src/dps8/dps8_math.c if (cpu.rA == 0 && cpu.rQ == 0) // set to normalized 0 cpu 2671 src/dps8/dps8_math.c cpu.rE = 0200U; /*-128*/ cpu 2790 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GD1;) cpu 2792 src/dps8/dps8_math.c bool dividendNegative = (getbits36_1 (cpu.rA, 0) != 0); cpu 2793 src/dps8/dps8_math.c bool divisorNegative = (getbits36_1 (cpu.CY, 0) != 0); cpu 2800 src/dps8/dps8_math.c uint128 zFrac = (((uint128) (cpu.rA & MASK35)) << 35) | ((cpu.rQ >> 1) & MASK35); cpu 2817 src/dps8/dps8_math.c cpu 2825 src/dps8/dps8_math.c uint128 dFrac = cpu.CY & MASK35; cpu 2838 src/dps8/dps8_math.c cpu.rA = (zFrac >> 35) & MASK35; cpu 2839 src/dps8/dps8_math.c cpu.rQ = (zFrac & MASK35) << 1; cpu 2841 src/dps8/dps8_math.c SC_I_ZERO (cpu.CY == 0); cpu 2842 src/dps8/dps8_math.c SC_I_NEG (cpu.rA & SIGN36); cpu 2851 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GD2;) cpu 2877 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GD2;) cpu 2883 src/dps8/dps8_math.c SC_I_ZERO (cpu.rA == 0); cpu 2884 src/dps8/dps8_math.c SC_I_NEG (cpu.rA & SIGN36); cpu 2888 src/dps8/dps8_math.c cpu.rA = quot & MASK36; cpu 2892 src/dps8/dps8_math.c cpu.rQ = remainder & MASK36; cpu 2900 src/dps8/dps8_math.c cpu 2904 src/dps8/dps8_math.c cpu 2906 src/dps8/dps8_math.c cpu 2907 src/dps8/dps8_math.c cpu 2919 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GD1;) cpu 2921 src/dps8/dps8_math.c bool dividendNegative = (getbits36_1 (cpu . rA, 0) != 0); cpu 2922 src/dps8/dps8_math.c bool divisorNegative = (getbits36_1 (cpu.CY, 0) != 0); cpu 2930 src/dps8/dps8_math.c uint128 zFrac = lshift_128 (construct_128 (0, cpu.rA & MASK35), 35); cpu 2931 src/dps8/dps8_math.c zFrac = or_128 (zFrac, construct_128 (0, (cpu.rQ >> 1) & MASK35)); cpu 2934 src/dps8/dps8_math.c uint128 zFrac = ((uint128) (cpu . rA & MASK35) << 35) | ((cpu . rQ >> 1) & MASK35); cpu 2971 src/dps8/dps8_math.c uint128 dFrac = convert_to_word72 (0, cpu.CY & MASK35); cpu 3015 src/dps8/dps8_math.c cpu.rQ = cpu.rQ & (MASK35 << 1); cpu 3019 src/dps8/dps8_math.c SC_I_ZERO (cpu.CY == 0); cpu 3020 src/dps8/dps8_math.c SC_I_NEG (cpu.rA & SIGN36); cpu 3028 src/dps8/dps8_math.c L68_ (cpu.ou.cycle |= ou_GD2;) cpu 3057 src/dps8/dps8_math.c bool Aneg = (cpu.rA & SIGN36) != 0; // blood type cpu 3058 src/dps8/dps8_math.c bool AQzero = cpu.rA == 0 && cpu.rQ == 0; cpu 3059 src/dps8/dps8_math.c if (cpu.rA & SIGN36) cpu 3061 src/dps8/dps8_math.c cpu.rA = (~cpu.rA) & MASK36; cpu 3062 src/dps8/dps8_math.c cpu.rQ = (~cpu.rQ) & MASK36; cpu 3063 src/dps8/dps8_math.c cpu.rQ += 1; cpu 3064 src/dps8/dps8_math.c if (cpu.rQ & BIT37) // overflow? cpu 3066 src/dps8/dps8_math.c cpu.rQ &= MASK36; cpu 3067 src/dps8/dps8_math.c cpu.rA = (cpu.rA + 1) & MASK36; cpu 3071 src/dps8/dps8_math.c cpu 3073 src/dps8/dps8_math.c cpu 3074 src/dps8/dps8_math.c cpu 3084 src/dps8/dps8_math.c cpu.rQ = cpu.rQ & (MASK35 << 1); cpu 3113 src/dps8/dps8_math.c cpu.rA = quot.l & MASK36; cpu 3114 src/dps8/dps8_math.c cpu.rQ = remainder.l & MASK36; cpu 3116 src/dps8/dps8_math.c cpu . rA = quot & MASK36; cpu 3117 src/dps8/dps8_math.c cpu . rQ = remainder & MASK36; cpu 3126 src/dps8/dps8_math.c SC_I_ZERO (cpu . rA == 0 && cpu . rQ == 0); cpu 3127 src/dps8/dps8_math.c SC_I_NEG (cpu . rA & SIGN36); cpu 3153 src/dps8/dps8_math.c float72 m = convert_to_word72 (cpu.rA, cpu.rQ); cpu 3155 src/dps8/dps8_math.c cpu.rE = 0200U; /*-128*/ cpu 3194 src/dps8/dps8_math.c convert_to_word36 (m, & cpu.rA, & cpu.rQ); cpu 3196 src/dps8/dps8_math.c fno (& cpu.rE, & cpu.rA, & cpu.rQ); cpu 3227 src/dps8/dps8_math.c word36 A = cpu . rA, Q = cpu . rQ; cpu 3228 src/dps8/dps8_math.c word8 E = cpu . rE; cpu 3317 src/dps8/dps8_math.c word72 m1 = convert_to_word72 (cpu.rA, cpu.rQ & 0777777777400LL); cpu 3318 src/dps8/dps8_math.c int e1 = SIGNEXT8_int (cpu . rE & MASK8); cpu 3322 src/dps8/dps8_math.c word72 m2 = lshift_128 (construct_128 (0, getbits36_28 (cpu.Ypair[0], 8)), (36 + 8)); cpu 3323 src/dps8/dps8_math.c m2 = or_128 (m2, lshift_128 (construct_128 (0, cpu.Ypair[1]), 8u)); cpu 3325 src/dps8/dps8_math.c word72 m2 = (word72) getbits36_28 (cpu.Ypair[0], 8) << (36 + 8); cpu 3326 src/dps8/dps8_math.c m2 |= cpu.Ypair[1] << 8; cpu 3328 src/dps8/dps8_math.c int e2 = SIGNEXT8_int (getbits36_8 (cpu.Ypair[0], 0)); cpu 3452 src/dps8/dps8_math.c word72 m1 = convert_to_word72 (cpu.rA & MASK36, cpu.rQ & 0777777777400LL); cpu 3453 src/dps8/dps8_math.c int e1 = SIGNEXT8_int (cpu.rE & MASK8); cpu 3457 src/dps8/dps8_math.c word72 m2 = lshift_128 (construct_128 (0, getbits36_28 (cpu.Ypair[0], 8)), (36 + 8)); cpu 3458 src/dps8/dps8_math.c m2 = or_128 (m2, lshift_128 (construct_128 (0, cpu.Ypair[1]), 8u)); cpu 3460 src/dps8/dps8_math.c word72 m2 = (word72) getbits36_28 (cpu.Ypair[0], 8) << (36 + 8); cpu 3461 src/dps8/dps8_math.c m2 |= cpu.Ypair[1] << 8; cpu 3463 src/dps8/dps8_math.c int e2 = SIGNEXT8_int (getbits36_8 (cpu.Ypair[0], 0)); cpu 3466 src/dps8/dps8_math.c L68_ (cpu.ou.cycle = ou_GOE;) cpu 3473 src/dps8/dps8_math.c L68_ (cpu.ou.cycle = ou_GOA;) cpu 1182 src/dps8/dps8_scu.c uint128 big = construct_128 (0, cpu.instrCnt); cpu 1195 src/dps8/dps8_scu.c __uint128_t big = cpu.instrCnt; cpu 1826 src/dps8/dps8_scu.c word16 b0_15 = (word16) getbits36_16 (cpu.rA, 20); cpu 1827 src/dps8/dps8_scu.c word36 b16_51 = cpu.rQ; cpu 2099 src/dps8/dps8_scu.c cpu.rQ = clk & 0777777777777; // lower 36-bits of clock cpu 2100 src/dps8/dps8_scu.c cpu.rA = (clk >> 36) & 0177777; // upper 16-bits of clock cpu 32 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || (((dptr)->dctrl & (DBG_INTR | DBG_FAULT))) || (! sim_deb_segno_on) || sim_deb_segno[cpu.PPR.PSR & (DEBUG_SEGNO_LIMIT - 1)]) && \ cpu 33 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || sim_deb_ringno == NO_SUCH_RINGNO || sim_deb_ringno == cpu . PPR. PRR) && \ cpu 35 src/dps8/dps8_simh.h cpu.cycleCnt >= sim_deb_start && \ cpu 36 src/dps8/dps8_simh.h (sim_deb_stop == 0 || cpu.cycleCnt < sim_deb_stop) && \ cpu 102 src/dps8/dps8_sys.c #define DBG_CTR cpu.cycleCnt cpu 1881 src/dps8/dps8_sys.c cpu 1882 src/dps8/dps8_sys.c cpu 1883 src/dps8/dps8_sys.c cpu 1884 src/dps8/dps8_sys.c cpu 1885 src/dps8/dps8_sys.c cpu 1886 src/dps8/dps8_sys.c cpu 1887 src/dps8/dps8_sys.c cpu 1892 src/dps8/dps8_sys.c cpu.restart = true; cpu 1893 src/dps8/dps8_sys.c cpu.restart_address = (uint) n; cpu 2075 src/dps8/dps8_sys.c cpu 2077 src/dps8/dps8_sys.c cpu 2086 src/dps8/dps8_sys.c cpu 2088 src/dps8/dps8_sys.c cpu 2129 src/dps8/dps8_sys.c cpu 2145 src/dps8/dps8_sys.c cpu 2776 src/dps8/dps8_sys.c word15 icSegno = cpu.PPR.PSR; cpu 2777 src/dps8/dps8_sys.c word18 icOffset = cpu.PPR.IC; cpu 2799 src/dps8/dps8_sys.c word15 fpSegno = cpu.PR[6].SNR; cpu 2800 src/dps8/dps8_sys.c word18 fpOffset = cpu.PR[6].WORDNO; cpu 2831 src/dps8/dps8_sys.c where = lookup_address (icSegno, cpu.rX[7] - 1, cpu 2835 src/dps8/dps8_sys.c sim_msg ("%05o:%06o %s\n", icSegno, cpu.rX[7] - 1, where); cpu 3215 src/dps8/dps8_sys.c core_read2 ((cpu.DSBR.ADDR + 2u * segno) & PAMASK, & SDWeven, & SDWodd, cpu 3220 src/dps8/dps8_sys.c sdw0_s *SDW = & cpu._s; cpu 3221 src/dps8/dps8_sys.c memset (SDW, 0, sizeof (cpu._s)); cpu 3246 src/dps8/dps8_sys.c if (cpu.DSBR.U) { cpu 3247 src/dps8/dps8_sys.c for(word15 segno = 0; 2u * segno < 16u * (cpu.DSBR.BND + 1u); segno += 1) cpu 3255 src/dps8/dps8_sys.c 2u * segno < 16u * (cpu.DSBR.BND + 1u); cpu 3261 src/dps8/dps8_sys.c core_read ((cpu.DSBR.ADDR + x1) & PAMASK, & PTWx1, __func__); cpu 3433 src/dps8/dps8_sys.c if (dbgLookupAddress (cpu.PR[6].SNR, 046, & pa, & msg)) cpu 3441 src/dps8/dps8_sys.c sim_msg ("%05o:%06o\n", cpu.PR[2].SNR, cpu.rX[0]); cpu 3443 src/dps8/dps8_sys.c if (dbgLookupAddress (cpu.PR[2].SNR, cpu.rX[0], & pa, & msg)) cpu 3451 src/dps8/dps8_sys.c if (dbgLookupAddress (cpu.PR[2].SNR, cpu.PR[2].WORDNO, & pa, & msg)) cpu 3487 src/dps8/dps8_sys.c if (dbgLookupAddress (cpu.PR[6].SNR, 046, & pa, & msg)) cpu 3496 src/dps8/dps8_sys.c cpu 3498 src/dps8/dps8_sys.c cpu 3521 src/dps8/dps8_sys.c if (dbgLookupAddress (cpu.PR[2].SNR, cpu.PR[2].WORDNO, & pa, & msg)) cpu 3546 src/dps8/dps8_sys.c if (dbgLookupAddress (cpu.PR[6].SNR, 046, & pa, & msg)) cpu 3557 src/dps8/dps8_sys.c cpu 3566 src/dps8/dps8_sys.c if (dbgLookupAddress (cpu.PR[2].SNR, cpu.PR[2].WORDNO, & pa, & msg)) cpu 3590 src/dps8/dps8_sys.c if (dbgLookupAddress (cpu.PR[6].SNR, 046, & pa, & msg)) cpu 3598 src/dps8/dps8_sys.c sim_msg ("%05o:%06o\n", cpu.PR[2].SNR, cpu.rX[0]); cpu 3600 src/dps8/dps8_sys.c if (dbgLookupAddress (cpu.PR[2].SNR, cpu.rX[0], & pa, & msg)) cpu 3608 src/dps8/dps8_sys.c if (dbgLookupAddress (cpu.PR[2].SNR, cpu.PR[2].WORDNO, & pa, & msg)) cpu 4765 src/dps8/dps8_sys.c segno = cpu.PR[prt->n].SNR; cpu 4766 src/dps8/dps8_sys.c PRoffset = cpu.PR[prt->n].WORDNO; cpu 4808 src/dps8/dps8_sys.c segno = cpu.PR[prt->n].SNR; cpu 4809 src/dps8/dps8_sys.c offset = cpu.PR[prt->n].WORDNO; cpu 964 src/dps8/dps8_utils.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 1008 src/dps8/dps8_utils.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 1056 src/dps8/dps8_utils.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 1089 src/dps8/dps8_utils.c L68_ (cpu.ou.cycle |= ou_GOS;) cpu 2003 src/dps8/dps8_utils.c cpu 2018 src/dps8/dps8_utils.c cpu 2024 src/dps8/dps8_utils.c cpu 166 src/dps8/hdbg.c if (filter && hdbgSegNum >= 0 && hdbgSegNum != cpu.PPR.PSR) \ cpu 168 src/dps8/hdbg.c if (filter && hdbgSegNum > 0 && blacklist[cpu.PPR.IC]) \ cpu 175 src/dps8/hdbg.c hevents[p].time = cpu.cycleCnt; \ cpu 189 src/dps8/hdbg.c hevents[p].trace.segno = cpu.PPR.PSR; cpu 190 src/dps8/hdbg.c hevents[p].trace.ic = cpu.PPR.IC; cpu 191 src/dps8/hdbg.c hevents[p].trace.ring = cpu.PPR.PRR; cpu 248 src/dps8/hdbg.c hevents[p].time = cpu.cycleCnt; cpu 90 src/dps8/hdbg.h # define HDBGRegAR(c) hdbgRegR (hreg_A, cpu.rA, c) cpu 91 src/dps8/hdbg.h # define HDBGRegAW(c) hdbgRegW (hreg_A, cpu.rA, c) cpu 92 src/dps8/hdbg.h # define HDBGRegQR(c) hdbgRegR (hreg_Q, cpu.rQ, c) cpu 93 src/dps8/hdbg.h # define HDBGRegQW(c) hdbgRegW (hreg_Q, cpu.rQ, c) cpu 94 src/dps8/hdbg.h # define HDBGRegXR(i, c) hdbgRegR (hreg_X0+(i), (word36) cpu.rX[i], c) cpu 95 src/dps8/hdbg.h # define HDBGRegXW(i, c) hdbgRegW (hreg_X0+(i), (word36) cpu.rX[i], c) cpu 96 src/dps8/hdbg.h # define HDBGRegYR(c) hdbgRegR (hreg_Y, (word36) cpu.rY, c) cpu 97 src/dps8/hdbg.h # define HDBGRegYW(c) hdbgRegW (hreg_Y, (word36) cpu.rY, c) cpu 100 src/dps8/hdbg.h # define HDBGRegPRR(i, c) hdbgPARegR (hreg_PR0+(i), & cpu.PAR[i], c) cpu 101 src/dps8/hdbg.h # define HDBGRegPRW(i, c) hdbgPARegW (hreg_PR0+(i), & cpu.PAR[i], c) cpu 102 src/dps8/hdbg.h # define HDBGRegARR(i, c) hdbgPARegR (hreg_AR0+(i), & cpu.PAR[i], c) cpu 103 src/dps8/hdbg.h # define HDBGRegARW(i, c) hdbgPARegW (hreg_AR0+(i), & cpu.PAR[i], c) cpu 105 src/dps8/hdbg.h cpu 106 src/dps8/hdbg.h cpu 108 src/dps8/hdbg.h # define HDBGRegIR(c) hdbgRegW (hreg_IR, (word36) cpu.cu.IR, c) cpu 626 src/dps8/threadz.c sim_printf ("sleepCPU pthread_cond_timedwait rc %ld usec %ld TR %lu CPU %lu\n", (long) rc, (long) usec, (unsigned long) cpu.rTR, (unsigned long) current_running_cpu_idx); cpu 26 src/dps8/ucache.c memset (cpu.uCache.caches, 0, sizeof (cpu.uCache.caches)); cpu 34 src/dps8/ucache.c ep = & cpu.uCache.caches[ucNum][segno]; cpu 51 src/dps8/ucache.c cpu.uCache.segnoSkips ++; cpu 56 src/dps8/ucache.c ep = & cpu.uCache.caches[ucNum][segno]; cpu 112 src/dps8/ucache.c cpu.uCache.hits[ucNum] ++; cpu 117 src/dps8/ucache.c cpu.uCache.misses[ucNum] ++;