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1 /*
2 * vim: filetype=c:tabstop=4:ai:expandtab
3 * SPDX-License-Identifier: ICU
4 * SPDX-License-Identifier: Multics
5 * scspell-id: d49ab489-f62e-11ec-9ac1-80ee73e9b8e7
6 *
7 * ---------------------------------------------------------------------------
8 *
9 * Copyright (c) 2007-2013 Michael Mondy
10 * Copyright (c) 2012-2016 Harry Reed
11 * Copyright (c) 2013-2022 Charles Anthony
12 * Copyright (c) 2021-2023 The DPS8M Development Team
13 *
14 * All rights reserved.
15 *
16 * This software is made available under the terms of the ICU
17 * License, version 1.8.1 or later. For more details, see the
18 * LICENSE.md file at the top-level directory of this distribution.
19 *
20 * ---------------------------------------------------------------------------
21 *
22 * This source file may contain code comments that adapt, include, and/or
23 * incorporate Multics program code and/or documentation distributed under
24 * the Multics License. In the event of any discrepancy between code
25 * comments herein and the original Multics materials, the original Multics
26 * materials should be considered authoritative unless otherwise noted.
27 * For more details and historical background, see the LICENSE.md file at
28 * the top-level directory of this distribution.
29 *
30 * ---------------------------------------------------------------------------
31 */
32
33 //-V536
34
35 /*
36 * scu.c -- System Controller
37 *
38 * See AN70, section 8 and GB61.
39 *
40 * There were a few variations of SCs and SCUs:
41 * SCU -- Series 60 Level 66 Controller
42 * SC -- Level 68 System Controller
43 * 4MW SCU -- A later version of the Level 68 SC
44 *
45 * SCUs control access to memory.
46 * Each SCU owns a certain range of absolute memory.
47 * This emulator allows the CPU to access memory directly however.
48 * SCUs contain clocks.
49 * SCUS also contain facilities which allow CPUS and IOMs to communicate.
50 * CPUs or IOMS request access to memory via the SCU.
51 * CPUs use the CIOC instr to talk to IOMs and other CPUs via a SCU.
52 * IOMs use interrupts to ask a SCU to signal a CPU.
53 * Other Interesting instructions:
54 * read system controller reg and set system controller reg (RSCR & SSCR)
55 *
56 */
57
58 /*
59 * Physical Details & Interconnection -- AN70, section 8.
60 *
61 * SCUs have 8 ports.
62 * Active modules (CPUs and IOMs) have up to four of their ports
63 * connected to SCU ports.
64 *
65 * The 4MW SCU has eight on/off switches to enable or disable
66 * the ports. However, the associated registers allow for
67 * values of enabled, disabled, and program control.
68 *
69 * SCUs have stores (memory banks).
70 *
71 * SCUs have four sets of registers controlling interrupts. Only two
72 * of these sets, designated "A" and "B" are used. Each set has:
73 * Execute interrupt mask register -- 32 bits; enables/disables
74 * the corresponding execute interrupt cell
75 * Interrupt mask assignment register -- 9 bits total
76 * two parts: assigned bit, set of assigned ports (8 bits)
77 * In Multics, only one CPU will be assigned in either mask
78 * and no CPU appears in both. Earlier hardware versions had
79 * four 10-position rotary switches. Later hardware versions had
80 * two 9-position (0..7 and off) rotary switches.
81 *
82 * Config panel -- Level 68 6000 SCU
83 * -- from AM81
84 * store A and store B
85 * 3 position rotary switch: on line, maint, off line
86 * size: 32K, 64K, 128K, 256K
87 * exec interrupt mask assignment
88 * four 10-position rotary switches (A through D): off, 0 .. 7, M
89 * One switch for each program interrupt register
90 * Assign mask registers to system ports
91 * Normally assign one mask reg to each CPU
92 *
93 * AM81:
94 * " The EXECUTE INTERRUPT MASK ASSIGNMENT (EIMA) rotary switches
95 * determine where interrupts sent to memory are directed. The four EIMA
96 * rotary switches, one for each program interrupt register, are used to
97 * assign mask registers to system ports. The normal settings assign one
98 * mask register to each CPU configured.
99 *
100 * Each switch assigns mask registers as follows:
101 *
102 * Position
103 * OFF Unassigned
104 * 0 Assigned to port 0
105 * ...
106 * 7 Assigned to port 7
107 * M Assigned to maintenance panel
108 *
109 * Assignment of a mask register to a system port designates the
110 * port as a control port, and that port receives interrupt present
111 * signals. Up to four system ports can be designated as control
112 * ports. The normal settings assign one mask register to each CPU
113 * configured."
114 *
115 *
116 *
117 * Config panel -- Level 68 System Controller UNIT (4MW SCU)
118 * -- from AM81
119 * Store A, A1, B, B1 (online/offline)
120 * LWR Store Size
121 * PORT ENABLE
122 * Eight on/off switches
123 * Should be on for each port connected to a configured CPU
124 * mask/port assignment
125 * Two rotary switches (A & B); set to (off, 0..7)
126 * See EXEC INTERRUPT on the 6000 SCU
127 * When booting, one should be set to the port connected to
128 * the bootload CPU. The other should be off.
129 *
130 * If memory port B of CPU C goes to SCU D, then memory port B of all
131 * other CPUs *and* IOMs must go to SCU D. -- AN70, 8-4.
132 *
133 * The base address of the SCU is the actual memory size * the port
134 * assignment. -- AN70, 8-6.
135 *
136 * 43A239854 6000B Eng. Prod. Spec, 3.2.7 Interrupt Multiplex Word:
137 * "The IOM has the ability to set any of the 32 program interrupt
138 * cells located in the system controller containing the base address
139 * of the IOM. It should be noted that for any given IOM identity
140 * switch setting, the IOM can set only 8 of these program interrupt
141 * cells."
142 *
143 */
144
145 /*
146 * === Initialization and Booting -- Part 1 -- Operator's view
147 *
148 * Booting Instructions (GB61)
149 * First boot the BCE OS (Bootload command Environment). See below.
150 * A config deck is used
151 * Bootload SCU is the one with a base addr of zero.
152 * BCE is on a BCE/Multics System tape
153 * Booted from tape into the system via bootload console
154
155 */
156
157 /*
158 * 58009906 (DPS8)
159 * When CPU needs to address the SCU (for a write/read data cycle,
160 * for example), the ETMCM board int the CU of the CPU issues a $INT
161 * to the SCU. This signal is sent ... to the SCAMX active port
162 * control board in the SCU
163 */
164
165 // How? If one of the 32 interrupt cells is set in one of the SCs,
166 // our processor will have the interrupt present (XIP) line active.
167 // Perhaps faults are flagged in the same way via the SXC system
168 // controller command.
169
170 // TEMPORARY
171 // Each SCU owns a certain range of absolute memory.
172 // CPUs use the cioc instr to talk to IOMs and other CPUs via a SCU.
173 // IOMs use interrupts to ask a SCU to signal a CPU.
174 // read system controller reg and set system controller reg (rscr & sscr)
175 // Bootload SCU is the one with a base addr of zero.
176 // 58009906
177 // When CPU needs to address the SCU (for a write/read data cycle,
178 // for example), the ETMCM board int the CU of the CPU issues a $INT
179 // to the SCU. This signal is sent ... to the SCAMX active port
180 // control board in the
181 // -----------------------
182 // How? If one of the 32 interrupt cells is set in one of the SCs,
183 // our processor will have the interrupt present (XIP) line active.
184 // Perhaps faults are flagged in the same way via the SXC system
185 // controller command.
186
187 /*
188 * *** More (new) notes ***
189 *
190 * instr rmcm -- read mem controller mask register
191 * ... for the selected controller, if the processor has a mask register
192 * assigned ..
193 * instr smcm -- set mem controller mask register
194 * ... for the selected controller, if the processor has a mask register
195 * assigned, set it to C(AQ)
196 * instr smic
197 * turn on interrupt cells (any of 0..31)
198 * instr cioc -- connect i/o channel, pg 173
199 * SC addressed by Y sends a connect signal to the port specified
200 * by C(Y)33,35
201 * instr rscr & sscr -- Read/Store System Controller Register, pg 170
202 *
203 * 32 interrupt cells ... XIP
204 * mask info
205 * 8 mask registers
206 * 58009906
207 * =============
208 *
209 * AM81
210 * Every active device (CPU, IOM) must be able to access all SCUs
211 * Every SCU must have the same active device on the same SCU, so
212 * all SCUs must have the same PORT ENABLE settings
213 * Every active device must have the same SCU on the same port,
214 * so all active devices will have the same config panel settings.
215 * Ports must correspond -- port A on every CPU and IOM must either
216 * be connected to the same SCU or not connected to any SCU.
217 * IOMs should be on lower-numbered SCU ports than CPUs.
218 * Multics can have 16MW words of memory.
219 * CPUs have 8 ports, a..h.
220 * SCUs have 8 ports, 0..7.
221 *
222 *
223 * Level 68 6000 SCU Configuration Panel
224 * system control and monitor (cont&mon/mon/off)
225 * system boot control (on/off)
226 * alarm (disable/normal)
227 * maintenance panel mode (test/normal)
228 * store a
229 * mode (offline/maint/online)
230 * size (32k, 64k, 128k, 256k)
231 * store b
232 * mode (offline/maint/online)
233 * size (32k, 64k, 128k, 256k)
234 * execute interrupt mask assignment
235 * (A through D; off/0/1/2/3/4/5/6/7/m)
236 * [CAC] I interpret this as CPU [A..D] is connected to my port [0..7]
237 * address control
238 * lower store (a/b)
239 * offset (off, 16k, 32k, 64k)
240 * interlace (on/off)
241 * cycle port priority (on/off)
242 * port control (8 toggles) (enabled/prog cont/disable)
243 *
244 * The EXECUTE INTERRUPT MASK ASSIGNMENT (EIMA) rotary switches
245 * determine where interrupts sent to memory are directed. The four EIMA
246 * rotary switches, one for each program interrupt register, are used to
247 * assign mask registers to system ports. The normal settings assign one
248 * mask register to each CPU configured.
249 *
250 * Assignment of a mask register to a system port designates the port as a
251 * control port, and that port receives interrupt present signals. Up to four
252 * system ports can be designated as control ports. The normal settings
253 * assign one mask register to each cpu configured.
254 *
255 *
256 *
257 * Configuration rules for Multics:
258 *
259 * 1. Each CPU in the system must be connected to each SCU in the system
260 *
261 * 2. Each IOM in the system must be connected to each SCU in the system
262 *
263 * 3. Each SCU in the system must be connected to every CPU and IOM in the
264 * system.
265 *
266 * 4. Corresponding ports on all CPUs and IOMs must be connected to the same
267 * SCU. For example, port A on every CPU and IOM must be connected to the
268 * same SCU or not connected to any SCU.
269 *
270 * 5. Corresponding ports on all SCUs must be connected to the same active
271 * device (CPU or IOM). For example, if port 0 on any SCU is connected to
272 * IOM A, then port 0 on all SCUs must be connected to IOM A.
273 *
274 * 6. IOMs should be connected to lower-number SCU ports the CPUs.
275 *
276 * These rules are illustrated in Figure 3-5, where the port numbers for a
277 * small Multics system of 2 CPUS, 3 SCUs and 2 IOMs have been indicated
278 *
279 *
280 *
281 *
282 * ----------------- -----------------
283 * | | | |
284 * | CPU A | | CPU B |
285 * | | | |
286 * ----------------- -----------------
287 * | A | B | C | D | | A | B | C | D |
288 * ----------------- -----------------
289 * | | | | | |
290 * | | | | | -----------------
291 * | | | | | |
292 * | | -------------------------------)---)---------------- |
293 * | | | | | |
294 * -------------------- ----------------- | | | |
295 * | | | | | |
296 * | -----------------------------------)------------------- | | |
297 * | | | | | |
298 * | | | -------------------- | |
299 * | | | | | |
300 * ----------------- ----------------- -----------------
301 * | 7 | 6 | 5 | 4 | | 7 | 6 | 5 | 4 | | 7 | 6 | 5 | 4 |
302 * ----------------- ----------------- -----------------
303 * | | | | | |
304 * | SCU C | | SCU B | | SCU A |
305 * | | | | | |
306 * ----------------- ----------------- -----------------
307 * | 3 | 2 | 1 | 0 | | 3 | 2 | 1 | 0 | | 3 | 2 | 1 | 0 |
308 * ----------------- ----------------- -----------------
309 * | | | | | |
310 * | | | ----------- | |
311 * | | | | | |
312 * | -----------------------------------)--------- | | |
313 * | | | | | |
314 * ---------- -------------------------- | | | |
315 * | | | | | |
316 * | | ------------------------------)----)------------------------- |
317 * | | | | | |
318 * | | | | | ---------------------------
319 * | | | | | |
320 * ----------------- -----------------
321 * | A | B | C | D | | A | B | C | D |
322 * ----------------- -----------------
323 * | | | |
324 * | IOM A | | IOM B |
325 * | | | |
326 * ----------------- -----------------
327 *
328 *
329 *
330 *"During bootload, Multics requires a contiguous section of memory beginning at
331 * absolute address 0 and sufficiently large to contain all routines and data
332 * structures used during the first phase of Multics initialization (i.e.
333 * collection 1).
334 * The size of the section required varies among Multics release, and it also
335 * depends on the size of the SST segment, which is dependent on the parameters
336 * specified by the site on the SST config card. ... However
337 * 512 KW is adequate for all circumstances. There can be no "holes" in memory
338 * within this region. Beyond this region, "holes" can exist in memory."
339 *
340 *
341 */
342
343 /*
344 * From AN70-1 May84, pg 86 (8-6)
345 *
346 * RSCR SC_CFG bits 9-11 lower store size
347 *
348 * A DPS-8 SCU may have up to four store units attached to it. If this
349 * is the case, two store units form a pair of units. The size of a
350 * pair of units (or a single unit) is 32K * 2 ** (lower store size)
351 * above.
352 */
353
354 /*
355 * From AN70-1 May84, pg 86 (8-6)
356 *
357 * SCU ADDRESSING
358 *
359 * There are three ways in which an SCU is addressed. In the
360 * normal mode of operation (memory reading and writing), an active
361 * unit (IOM or CPU) translates an absolute address into a memory
362 * port (on it) and a relative memory address within the memory
363 * described by the memory port. The active module sends the
364 * address to the SCU on the proper memory port. If the active
365 * module is enabled by the port enable mask in the referenced SCU,
366 * the SCU will take the address given to it and provide the
367 * necessary memory access.
368 *
369 * The other two ways pertain to reading/setting control
370 * registers in the SCU itself. For each of these, it is still
371 * necessary to specify somehow the memory port on the CPU whose SCU
372 * registers are desired. For the RMCM, SMCM and SMIC instructions,
373 * this consists of providing a virtual address to the processor for
374 * which bits 1 and 2 are the memory port desired.
375 *
376 * The rscr and sscr instructions, though key off the final
377 * absolute address to determine the SCI (or SCU store unit)
378 * desired. Thus, software needs a way to translate a memory port
379 * number into an absolute address to reach the SCU. This is done
380 * with the paged segment scas, generated by int_scas (and
381 * init_scu). scas has a page corresponding to each SCU and to each
382 * store unit in each SCU. pmut$rscr and pmut$sscr use the memory
383 * port number desired to generate a virtual address into scas whose
384 * absolute address (courtesy of the ptws for sca) just happen to
385 * describe memory within that SCU.
386 *
387 * The cioc instruction (discussed below) also depends on the
388 * final absolute addres of the target operand to identify the SCU
389 * to perform the operation. In the case of the cioc instruction,
390 * though, the has no particular impact in Multics software. All
391 * target operands for the cioc instruction when referencing IOMs
392 * are in the low order SCU. When referencing CPUS, the SCU
393 * performing the connecting has no real bearing.
394 *
395 * Inter-module communication
396 *
397 * As mentioned earlier, communication between active modules
398 * (CPUs and IOMs can only be performed through SCUs.
399 *
400 * CPUs communicate to IOMs and other CPUs via the cioc
401 * (connect i/o channel) instruction. The operand of the instruction
402 * is a word in memory. The SCU containing this operand is the SCU
403 * that performs the connect function. The word fetched from memory
404 * contains in its low order bits the identity of a port on the SCU
405 * to which this connection is to be sent. This only succeeds if the
406 * target port is enabled (port enable mask) on the SCU. When the
407 * target of the connection is an IOM; this generates a connect strobe
408 * to the IOM. The IOM examines its mailbox in memory to determine
409 * its course of action. When the target of the connect is another
410 * CPU, this generates a connect fault in the target processor. The
411 * target processor determines what course to follow on the basis
412 * of information in memory analyzed by software. When a connect is
413 * sent to a process (including the processor issuing the connect),
414 * the connect is deferred until the processor stops
415 * executing inhibited code (instructions with the inhibit bit set).
416 *
417 * Signals sent from an IOM to a CPU are much more involved.
418 * The basic flow is as follows. The IOM determines an interrupt
419 * number. (The interrupt number is a five bit value, from 0 to 31.
420 * The high order bits are the interrupt level.
421 *
422 * 0 - system fault
423 * 1 - terminate
424 * 2 - marker
425 * 3 - special
426 *
427 * The low order three bits determines the IOM and IOM channel
428 * group.
429 *
430 * 0 - IOM 0 channels 32-63
431 * 1 - IOM 1 channels 32-63
432 * 2 - IOM 2 channels 32-63
433 * 3 - IOM 3 channels 32-63
434 * 4 - IOM 0 channels 0-31
435 * 5 - IOM 1 channels 0-31
436 * 6 - IOM 2 channels 0-31
437 * 7 - IOM 3 channels 0-31
438 *
439 * It also takes the channel number in the group (0-31 meaning
440 * either channels 0-31 to 32-63) and sets the <channel number>th
441 * bit in the <interrupt number>th memory location in the interrupt
442 * mask word (IMW) array in memory. It then generates a word with
443 * the <interrupt number>th bit set and sends this to the bootload
444 * SCU with the SC (set execute cells) SCU command. This sets the
445 * execute interrupt cell register in the SCU and sends an XIP
446 * (execute interrupt present) signal to various processors
447 * connected to the SCU. (The details of this are covered in the
448 * next section.) One of the processors (the first to get to it)
449 * sends an XEC (execute interrupt cells) SCU command to the SCU who
450 * generated the XIP signal. The SCU provides the interrupt number
451 * to the processor, who uses it to determine the address of a fault
452 * pair in memory for the "fault" caused by this interrupt. The
453 * processing of the XEC command acts upon the highest priority
454 * (lowest number) bit in the execute interrupt cell register, and
455 * also resets this bit in the register.
456 *
457 * Interrupts Masks and Assignment
458 *
459 * The mechanism for determining which processors are candidates
460 * for receiving an interrupt from an IOM is an involved
461 * topic. First of all, a processor will not be interrupted as long
462 * as it is executing inhibited instructions (instructions with the
463 * inhibit bit set). Beyond this, though, lies the question of
464 * interrupt masks and mask assignment.
465 *
466 * Internal to the SCU are two sets of registers (A and B),
467 * each set consisting of the execute interrupt mask register and
468 * the interrupt mask assignment register. Each execute interrupt
469 * mask register is 32 bits long, with each bit enabling the
470 * corresponding bit in the execute interrupt cell register. Each
471 * interrupt mask assignment register has two parts, an assigned bit
472 * and a set of ports to which it is assigned (8 bits). When a bit
473 * is set in the execute interrupt sells register, the SCU ANDs this
474 * bit with the corresponding bit in each of the execute interrupt
475 * mask registers. If the corresponding bit of execute interrupt
476 * mask register A, for example, is on, the SCU then looks at the A
477 * interrupt mask assignment register. If this register is not
478 * assigned (enable), no further action takes place in regards to
479 * the A registers. (The B registers are still considered) (in
480 * parallel, by the way).) If the register is assigned (enabled)
481 * then interrupts will be send to all ports (processors) whose
482 * corresponding bit is set in the interrupt mask assignment
483 * register. This, only certain interrupts are allowed to be
484 * signalled at any given time (base on the contents of the execute
485 * interrupt mask registers) and only certain processors will
486 * receive these interrupts (as controlled by the interrupt mask
487 * assignment registers).
488 *
489 * In Multics, only one processor is listed in each of the two
490 * interrupt mask assignment registers, and no processor appears in
491 * both. Thus there is a one for one correspondence between
492 * interrupt masks that are assigned (interrupt mask registers whose
493 * assigned (enabled) bit is on) and processors who have an
494 * interrupt mask (SCU port number appears in an interrupt mask
495 * register). So, at any one time only two processors
496 * are eligible to receive interrupts. Other processors need not
497 * worry about masking interrupts.
498 *
499 * The contents of the interrupt mask registers may be
500 * obtained with the SCU configuration information with the rscr
501 * instruction and set with the sscr instruction.
502 *
503 * bits meaning
504 *
505 * 00-07 ports assigned to mask A (interrupt mask assignment A)
506 * 08-08 mask A is unassigned (disabled)
507 * 36-43 ports assigned to mask B (interrupt mask assignment B)
508 * 44-44 mask B is unassigned (disabled)
509 *
510 * The contents of a execute interrupt mask register are
511 * obtained with the rmcm or the rscr instruction and set with the
512 * smcm or the sscr instruction. The rmcm and smcm instruction only
513 * work if the processor making the request has a mask register
514 * assigned to it. If not, rmcm returns zero (no interrupt are
515 * enabled to it) and a smcm is ignored (actually the port mask
516 * setting is still done). The rscr and sscr instructions allow the
517 * examining/setting of the execute interrupt mask register for any
518 * port on a SCU; these have the same effect as smcm and rmcm if the
519 * SCU port being referenced does not have a mask assigned to it.
520 * The format of the data returned by these instructions is as
521 * follows.
522 *
523 * bits meaning
524 * 00-15 execute interrupt mask register 00-15
525 * 32-35 SCU port mask 0-3
526 * 36-51 execute interrupt mask register 16-31
527 * 68-71 SCU port mask 4-7
528 *
529 */
530
531 // SCU numbering:
532 //
533 // AM81-04, pg 49: "... the ports are listed in order of increasing base
534 // address, which corresponds to the order of mem config cards."
535 // pg 97: "mem port size state ... port as a value (a through h) that
536 // corresponds to the number of the active module port to which the
537 // system controller is connected.
538 //
539 // From this, I conclude;
540 // The SCU connected to port A (0) is SCUA, 1 B, 2 C, etc.
541 // SCUA starts at address 0, and the SCUs are sorted by increasing addresses.
542 //
543
544 // ============================================================================
545
546 #include <sys/time.h>
547 #include "dps8.h"
548 #include "dps8_sys.h"
549 #include "dps8_faults.h"
550 #include "dps8_scu.h"
551 #include "dps8_iom.h"
552 #include "dps8_cable.h"
553 #include "dps8_cpu.h"
554 #include "dps8_utils.h"
555 #if defined(THREADZ) || defined(LOCKLESS)
556 # include "threadz.h"
557 #endif
558
559 #define DBG_CTR 1
560
561 scu_t scu [N_SCU_UNITS_MAX];
562
563 #define N_SCU_UNITS 1 // Default
564
565 static UNIT scu_unit [N_SCU_UNITS_MAX] = {
566 #ifdef NO_C_ELLIPSIS
567 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
568 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
569 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
570 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
571 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
572 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
573 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL },
574 { UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL }
575 #else
576 [0 ... N_SCU_UNITS_MAX-1] = {
577 UDATA (NULL, 0, 0), 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL
578 }
579 #endif
580 };
581
582 #define UNIT_NUM(uptr) ((uptr) - scu_unit)
583
584 // Hardware configuration switches
585
586 // sscr and other instructions override these settings
587
588 static struct config_switches
589 {
590 uint mode; // program or manual
591 uint port_enable [N_SCU_PORTS]; // enable/disable
592 uint mask_enable [N_ASSIGNMENTS]; // enable/disable
593 uint mask_assignment [N_ASSIGNMENTS]; // assigned port number
594 uint lower_store_size; // In K words, power of 2; 32 - 4096
595 uint cyclic; // 7 bits
596 uint nea; // 8 bits
597 uint onl; // 4 bits
598 uint interlace; // 1 bit
599 uint lwr; // 1 bit
600 } config_switches [N_SCU_UNITS_MAX];
601
602 enum { MODE_MANUAL = 0, MODE_PROGRAM = 1 };
603
604 unsigned int gtod_warned = 0;
605
606 // ============================================================================
607
608 static t_stat scu_show_nunits (UNUSED FILE * st, UNUSED UNIT * uptr,
/* ![[next]](../icons/right.png)
![[first]](../icons/n_first.png)
![[top]](../icons/top.png)
*/
609 UNUSED int val, const UNUSED void * desc)
610 {
611 sim_printf("Number of SCU units in system is %d\n", scu_dev.numunits);
612 return SCPE_OK;
613 }
614
615 static t_stat scu_set_nunits (UNUSED UNIT * uptr, UNUSED int32 value,
/* ![[previous]](../icons/left.png)
*/
616 const char * cptr, UNUSED void * desc)
617 {
618 if (! cptr)
619 return SCPE_ARG;
620 int n = atoi (cptr);
621 if (n < 1 || n > N_SCU_UNITS_MAX)
622 return SCPE_ARG;
623 scu_dev.numunits = (uint) n;
624 return SCPE_OK;
625 }
626
627 static t_stat scu_show_state (UNUSED FILE * st, UNIT *uptr, UNUSED int val,
/* */
628 UNUSED const void * desc)
629 {
630 long scu_unit_idx = UNIT_NUM (uptr);
631 if (scu_unit_idx < 0 || scu_unit_idx >= (int) scu_dev.numunits)
632 {
633 sim_debug (DBG_ERR, & scu_dev,
634 "scu_show_state: Invalid unit number %ld\n",
635 (long) scu_unit_idx);
636 sim_printf ("error: Invalid unit number %ld\n", (long) scu_unit_idx);
637 return SCPE_ARG;
638 }
639
640 sim_printf ("SCU unit number %ld\n", (long) scu_unit_idx);
641 scu_t * scup = scu + scu_unit_idx;
642 sim_printf (" Mode %s\n",
643 config_switches[scu_unit_idx].mode ? "PROGRAM" : "MANUAL");
644
645 for (int i = 0; i < N_SCU_PORTS; i ++)
646 {
647 struct ports * pp = scup -> ports + i;
648
649 sim_printf (" Port %d %s dev_idx %d dev_port %d type %s\n",
650 i, scup->port_enable[i] ? "ENABLE " : "DISABLE",
651 pp->dev_idx, pp->dev_port[XXX_TEMP_SCU_SUBPORT],
652 pp->type == ADEV_NONE ? "NONE" :
653 pp->type == ADEV_CPU ? "CPU" :
654 pp->type == ADEV_IOM ? "IOM" :
655 "<enum broken>");
656 }
657 for (int i = 0; i < N_ASSIGNMENTS; i ++)
658 {
659 //struct interrupts * ip = scup -> interrupts + i;
660
661 sim_printf (" Cell %c\n", 'A' + i);
662 sim_printf (" exec_intr_mask %012o\n",
663 scup -> exec_intr_mask [i]);
664 sim_printf (" mask_enable %s\n",
665 scup -> mask_enable [i] ? "ENABLE" : "DISABLE");
666 sim_printf (" mask_assignment %d\n",
667 scup -> mask_assignment [i]);
668 sim_printf (" cells ");
669 for (int j = 0; j < N_CELL_INTERRUPTS; j ++)
670 sim_printf("%d", scup -> cells [j]);
671 sim_printf ("\n");
672 }
673 sim_printf("Lower store size: %d\n", scup -> lower_store_size);
674 sim_printf("Cyclic: %03o\n", scup -> cyclic);
675 sim_printf("NEA: %03o\n", scup -> nea);
676 sim_printf("Online: %02o\n", scup -> onl);
677 sim_printf("Interlace: %o\n", scup -> interlace);
678 sim_printf("Lower: %o\n", scup -> lwr);
679 sim_printf("ID: %o\n", scup -> id);
680 sim_printf("mode_reg: %06o\n", scup -> mode_reg);
681 sim_printf("Elapsed days: %d\n", scup -> elapsed_days);
682 sim_printf("Steady clock: %d\n", scup -> steady_clock);
683 sim_printf("Bullet time: %d\n", scup -> bullet_time);
684 sim_printf("Y2K enabled: %d\n", scup -> y2k);
685 return SCPE_OK;
686 }
687
688 static t_stat scu_show_config (UNUSED FILE * st, UNUSED UNIT * uptr,
/* */
689 UNUSED int val, UNUSED const void * desc)
690 {
691 static const char * map [N_SCU_PORTS] =
692 {
693 "0", "1", "2", "3", "4", "5", "6", "7"
694 };
695 long scu_unit_idx = UNIT_NUM (uptr);
696 if (scu_unit_idx < 0 || scu_unit_idx >= (int) scu_dev.numunits)
697 {
698 sim_debug (DBG_ERR, & scu_dev,
699 "scu_show_config: Invalid unit number %ld\n",
700 (long) scu_unit_idx);
701 sim_printf ("error: Invalid unit number %ld\n", (long) scu_unit_idx);
702 return SCPE_ARG;
703 }
704
705 sim_printf ("SCU unit number %ld\n", (long) scu_unit_idx);
706
707 struct config_switches * sw = config_switches + scu_unit_idx;
708
709 const char * mode = "<out of range>";
710 switch (sw -> mode)
711 {
712 case MODE_PROGRAM:
713 mode = "Program";
714 break;
715 case MODE_MANUAL:
716 mode = "Manual";
717 break;
718 }
719
720 sim_printf ("Mode: %s\n", mode);
721 sim_printf ("Port Enable: ");
722 for (int i = 0; i < N_SCU_PORTS; i ++)
723 sim_printf (" %3o", sw -> port_enable [i]);
724 sim_printf ("\n");
725 for (int i = 0; i < N_ASSIGNMENTS; i ++)
726 {
727 sim_printf ("Mask %c: %s\n",
728 'A' + i,
729 sw->mask_enable[i] ? (map[sw->mask_assignment[i]]) : "Off");
730 }
731 sim_printf ("Lower Store Size: %o\n", sw -> lower_store_size);
732 sim_printf ("Cyclic: %03o\n", sw -> cyclic);
733 sim_printf ("Non-existent address: %03o\n", sw -> nea);
734
735 return SCPE_OK;
736 }
737
738 //
739 // set scu0 config=<blah> [;<blah>]
740 //
741 // blah =
742 // mode= manual | program
743 // mask[A|B] = off | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
744 // portN = enable | disable
745 // lwrstoresize = 32 | 64 | 128 | 256 | 512 | 1024 | 2048 | 4096
746 // cyclic = n
747 // nea = n
748 //
749 // o nea is not implemented; will read as "nea off"
750 // o Multics sets cyclic priority explicitly; config
751 // switches are ignored.
752 // o STORE A, A1, B, B1 ONLINE/OFFLINE not implemented;
753 // will always read online.
754 // o store size if not enforced; a full memory complement
755 // is provided.
756 // o interlace not implemented; will read as 'off'
757 // o LOWER STORE A/B not implemented.
758 // o MASK is 'MASK/PORT ASSIGNMENT' analogous to the
759 // 'EXECUTE INTERRUPT MASK ASSIGNMENT of a 6000 SCU
760
761 static config_value_list_t cfg_mode_list [] =
762 {
763 { "manual", 0 },
764 { "program", 1 },
765 { NULL, 0 }
766 };
767
768 static config_value_list_t cfg_mask_list [] =
769 {
770 { "off", -1 },
771 { NULL, 0 }
772 };
773
774 static config_value_list_t cfg_able_list [] =
775 {
776 { "disable", 0 },
777 { "enable", 1 },
778 { NULL, 0 }
779 };
780
781 static config_value_list_t cfg_size_list [] =
782 {
783 { "32", 0 },
784 { "64", 1 },
785 { "128", 2 },
786 { "256", 3 },
787 { "512", 4 },
788 { "1024", 5 },
789 { "2048", 6 },
790 { "4096", 7 },
791 { "32K", 0 },
792 { "64K", 1 },
793 { "128K", 2 },
794 { "256K", 3 },
795 { "512K", 4 },
796 { "1024K", 5 },
797 { "2048K", 6 },
798 { "4096K", 7 },
799 { "1M", 5 },
800 { "2M", 6 },
801 { "4M", 7 },
802 { NULL, 0 }
803 };
804
805 static config_value_list_t cfg_on_off [] =
806 {
807 { "off", 0 },
808 { "on", 1 },
809 { "disable", 0 },
810 { "enable", 1 },
811 { NULL, 0 }
812 };
813
814 static config_list_t scu_config_list [] =
815 {
816 /* 0 */ { "mode", 1, 0, cfg_mode_list },
817 /* 1 */ { "maska", 0, N_SCU_PORTS - 1, cfg_mask_list },
818 /* 2 */ { "maskb", 0, N_SCU_PORTS - 1, cfg_mask_list },
819 /* 3 */ { "port0", 1, 0, cfg_able_list },
820 /* 4 */ { "port1", 1, 0, cfg_able_list },
821 /* 5 */ { "port2", 1, 0, cfg_able_list },
822 /* 6 */ { "port3", 1, 0, cfg_able_list },
823 /* 7 */ { "port4", 1, 0, cfg_able_list },
824 /* 8 */ { "port5", 1, 0, cfg_able_list },
825 /* 9 */ { "port6", 1, 0, cfg_able_list },
826 /* 10 */ { "port7", 1, 0, cfg_able_list },
827 /* 11 */ { "lwrstoresize", 0, 7, cfg_size_list },
828 /* 12 */ { "cyclic", 0, 0177, NULL },
829 /* 13 */ { "nea", 0, 0377, NULL },
830 // mask: 8 a_online, 4 a1_online, 2 b_online, 1, b1_online
831 /* 14 */ { "onl", 0, 017, NULL },
832 /* 15 */ { "int", 0, 1, NULL },
833 /* 16 */ { "lwr", 0, 1, NULL },
834
835 // Hacks
836
837 /* 17 */ { "elapsed_days", 0, 20000, NULL },
838 /* 18 */ { "steady_clock", 0, 1, cfg_on_off },
839 /* 19 */ { "bullet_time", 0, 1, cfg_on_off },
840 /* 20 */ { "y2k", 0, 1, cfg_on_off },
841 { NULL, 0, 0, NULL }
842 };
843
844 static t_stat scu_set_config (UNIT * uptr, UNUSED int32 value,
/* */
845 const char * cptr, UNUSED void * desc)
846 {
847 long scu_unit_idx = UNIT_NUM (uptr);
848 if (scu_unit_idx < 0 || scu_unit_idx >= (int) scu_dev.numunits)
849 {
850 sim_debug (DBG_ERR, & scu_dev,
851 "scu_set_config: Invalid unit number %ld\n", (long) scu_unit_idx);
852 sim_printf ("error: scu_set_config: Invalid unit number %ld\n",
853 (long) scu_unit_idx);
854 return SCPE_ARG;
855 }
856
857 struct config_switches * sw = config_switches + scu_unit_idx;
858
859 config_state_t cfg_state = { NULL, NULL };
860
861 for (;;)
862 {
863 int64_t v;
864 int rc = cfg_parse ("scu_set_config", cptr, scu_config_list,
865 & cfg_state, & v);
866 if (rc == -1) // done
867 break;
868
869 if (rc == -2) // error
870 {
871 cfg_parse_done (& cfg_state);
872 return SCPE_ARG;
873 }
874
875 const char * p = scu_config_list [rc].name;
876 if (strcmp (p, "mode") == 0)
877 sw -> mode = (uint) v;
878 else if (strcmp (p, "maska") == 0)
879 {
880 if (v == -1)
881 sw -> mask_enable [0] = false;
882 else
883 {
884 sw -> mask_enable [0] = true;
885 sw -> mask_assignment [0] = (uint) v;
886 }
887 }
888 else if (strcmp (p, "maskb") == 0)
889 {
890 if (v == -1)
891 sw -> mask_enable [1] = false;
892 else
893 {
894 sw -> mask_enable [1] = true;
895 sw -> mask_assignment [1] = (uint) v;
896 }
897 }
898 else if (strcmp (p, "port0") == 0)
899 sw -> port_enable [0] = (uint) v;
900 else if (strcmp (p, "port1") == 0)
901 sw -> port_enable [1] = (uint) v;
902 else if (strcmp (p, "port2") == 0)
903 sw -> port_enable [2] = (uint) v;
904 else if (strcmp (p, "port3") == 0)
905 sw -> port_enable [3] = (uint) v;
906 else if (strcmp (p, "port4") == 0)
907 sw -> port_enable [4] = (uint) v;
908 else if (strcmp (p, "port5") == 0)
909 sw -> port_enable [5] = (uint) v;
910 else if (strcmp (p, "port6") == 0)
911 sw -> port_enable [6] = (uint) v;
912 else if (strcmp (p, "port7") == 0)
913 sw -> port_enable [7] = (uint) v;
914 else if (strcmp (p, "lwrstoresize") == 0)
915 sw -> lower_store_size = (uint) v;
916 else if (strcmp (p, "cyclic") == 0)
917 sw -> cyclic = (uint) v;
918 else if (strcmp (p, "nea") == 0)
919 sw -> nea = (uint) v;
920 else if (strcmp (p, "onl") == 0)
921 sw -> onl = (uint) v;
922 else if (strcmp (p, "int") == 0)
923 sw -> interlace = (uint) v;
924 else if (strcmp (p, "lwr") == 0)
925 sw -> lwr = (uint) v;
926 else if (strcmp (p, "elapsed_days") == 0)
927 scu [scu_unit_idx].elapsed_days = (uint) v;
928 else if (strcmp (p, "steady_clock") == 0)
929 scu [scu_unit_idx].steady_clock = (uint) v;
930 else if (strcmp (p, "bullet_time") == 0)
931 scu [scu_unit_idx].bullet_time = (uint) v;
932 else if (strcmp (p, "y2k") == 0)
933 scu [scu_unit_idx].y2k = (uint) v;
934 else
935 {
936 sim_printf ("error: scu_set_config: invalid cfg_parse rc <%d>\n",
937 rc);
938 cfg_parse_done (& cfg_state);
939 return SCPE_ARG;
940 }
941 } // process statements
942 cfg_parse_done (& cfg_state);
943 return SCPE_OK;
944 }
945
946 static MTAB scu_mod [] =
947 {
948 {
949 MTAB_XTD | MTAB_VUN | \
950 MTAB_NMO | MTAB_VALR, /* Mask */
951 0, /* Match */
952 (char *) "CONFIG", /* Print string */
953 (char *) "CONFIG", /* Match string */
954 scu_set_config, /* Validation routine */
955 scu_show_config, /* Display routine */
956 NULL, /* Value descriptor */
957 NULL /* Help */
958 },
959 {
960 MTAB_XTD | MTAB_VDV | \
961 MTAB_NMO | MTAB_VALR, /* Mask */
962 0, /* Match */
963 (char *) "NUNITS", /* Print string */
964 (char *) "NUNITS", /* Match string */
965 scu_set_nunits, /* Validation routine */
966 scu_show_nunits, /* Display routine */
967 (char *) "Number of SCU units in the system", /* Value descriptor */
968 NULL /* Help */
969 },
970 {
971 MTAB_XTD | MTAB_VUN | \
972 MTAB_NMO | MTAB_VALR, /* Mask */
973 0, /* Match */
974 (char *) "STATE", /* Print string */
975 (char *) "STATE", /* Match string */
976 NULL, /* Validation routine */
977 scu_show_state, /* Display routine */
978 (char *) "SCU unit internal state", /* Value descriptor */
979 NULL /* Help */
980 },
981 {
982 MTAB_XTD | MTAB_VUN | \
983 MTAB_NMO | MTAB_VALR, /* Mask */
984 0, /* Match */
985 (char *) "RESET", /* Print string */
986 (char *) "RESET", /* Match string */
987 scu_reset_unit, /* Validation routine */
988 NULL, /* Display routine */
989 (char *) "reset SCU unit", /* Value descriptor */
990 NULL /* Help */
991 },
992 {
993 0, 0, NULL, NULL, NULL, NULL, NULL, NULL
994 }
995 };
996
997 //static t_stat scu_reset (DEVICE *dptr);
998
999 static DEBTAB scu_dt [] =
1000 {
1001 { (char *) "TRACE", DBG_TRACE, NULL },
1002 { (char *) "NOTIFY", DBG_NOTIFY, NULL },
1003 { (char *) "INFO", DBG_INFO, NULL },
1004 { (char *) "ERR", DBG_ERR, NULL },
1005 { (char *) "WARN", DBG_WARN, NULL },
1006 { (char *) "DEBUG", DBG_DEBUG, NULL },
1007 { (char *) "INTR", DBG_INTR, NULL }, // Don't move as it messes up DBG messages
1008 { (char *) "ALL", DBG_ALL, NULL },
1009 { NULL, 0, NULL }
1010 };
1011
1012 DEVICE scu_dev =
1013 {
1014 (char *) "SCU", /* Name */
1015 scu_unit, /* Units */
1016 NULL, /* Registers */
1017 scu_mod, /* Modifiers */
1018 N_SCU_UNITS, /* #Units */
1019 10, /* Address radix */
1020 8, /* Address width */
1021 1, /* Address increment */
1022 8, /* Data radix */
1023 8, /* Data width */
1024 NULL, /* Examine routine */
1025 NULL, /* Deposit routine */
1026 & scu_reset, /* Reset routine */
1027 NULL, /* Boot routine */
1028 NULL, /* Attach routine */
1029 NULL, /* Detach routine */
1030 NULL, /* Context */
1031 DEV_DEBUG, /* Flags */
1032 0, /* Debug control flags */
1033 scu_dt, /* Debug flag names */
1034 NULL, /* Memory size change */
1035 NULL, /* Logical name */
1036 NULL, /* Help */
1037 NULL, /* Attach_help */
1038 NULL, /* Help_ctx */
1039 NULL, /* Description */
1040 NULL /* End */
1041 };
1042
1043 static void dump_intr_regs (char * ctx, uint scu_unit_idx)
/* */
1044 {
1045 scu_t * up = scu + scu_unit_idx;
1046
1047 sim_debug (DBG_DEBUG, & scu_dev,
1048 "%s A: mask %011o enable %o assignment %o\n",
1049 ctx, up -> exec_intr_mask [0], up -> mask_enable [0],
1050 up -> mask_assignment [0]);
1051 sim_debug (DBG_DEBUG, & scu_dev,
1052 "%s B: mask %011o enable %o assignment %o\n",
1053 ctx, up -> exec_intr_mask [1], up -> mask_enable [1],
1054 up -> mask_assignment [1]);
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102 }
1103
1104 void scu_unit_reset (int scu_unit_idx)
/* */
1105 {
1106 scu_t * up = scu + scu_unit_idx;
1107 struct config_switches * sw = config_switches + scu_unit_idx;
1108
1109 for (int i = 0; i < N_SCU_PORTS; i ++)
1110 {
1111 up -> port_enable [i] = sw -> port_enable [i];
1112 }
1113
1114 for (int i = 0; i < N_ASSIGNMENTS; i ++)
1115 {
1116 up -> mask_enable [i] = sw -> mask_enable [i];
1117 up -> mask_assignment [i] = sw -> mask_assignment [i];
1118 }
1119 up -> lower_store_size = sw -> lower_store_size;
1120 up -> cyclic = sw -> cyclic;
1121 up -> nea = sw -> nea;
1122 up -> onl = sw -> onl;
1123 up -> interlace = sw -> interlace;
1124 up -> lwr = sw -> lwr;
1125
1126 // This is to allow the CPU reset to update the memory map. IAC clears the
1127 // attached SCUs; they clear the attached IOMs.
1128
1129 for (uint port_num = 0; port_num < N_SCU_PORTS; port_num ++)
1130 {
1131 struct ports * portp = & scu [scu_unit_idx].ports [port_num];
1132 if (portp->type != ADEV_IOM)
1133 continue;
1134 //if (! scu [scu_unit_idx].port_enable [scu_port_num])
1135 //continue;
1136 iom_unit_reset_idx ((uint) portp->dev_idx);
1137 }
1138
1139 // CAC - These settings were reversed engineer from the code instead
1140 // of from the documentation. In case of issues, try fixing these, not the
1141 // code.
1142
1143 for (int i = 0; i < N_ASSIGNMENTS; i ++)
1144 {
1145 // XXX Hack for t4d
1146 up -> exec_intr_mask [i] = 037777777777;
1147 }
1148 }
1149
1150 t_stat scu_reset (UNUSED DEVICE * dptr)
/* */
1151 {
1152 // On reset, instantiate the config switch settings
1153
1154 for (int scu_unit_idx = 0; scu_unit_idx < N_SCU_UNITS_MAX; scu_unit_idx ++)
1155 scu_unit_reset (scu_unit_idx);
1156 return SCPE_OK;
1157 }
1158
1159 // ============================================================================
1160
1161 #if defined(THREADZ) || defined(LOCKLESS)
1162 static pthread_mutex_t clock_lock = PTHREAD_MUTEX_INITIALIZER;
1163 #endif
1164
1165 // The SCU clock is 52 bits long; fits in t_uint64
1166 static uint64 set_SCU_clock (uint scu_unit_idx)
/* */
1167 {
1168 #if defined(THREADZ) || defined(LOCKLESS)
1169 pthread_mutex_lock (& clock_lock);
1170 #endif
1171
1172 // The emulator supports two clock models: steady and real
1173 // In steady mode the time of day is coupled to the instruction clock,
1174 // allowing reproducible behavior. In real, the clock is
1175 // coupled to the actual time-of-day.
1176
1177 if (scu [0].steady_clock)
1178 {
1179 // The is a bit of code that is waiting for 5000 ms; this
1180 // fools into going faster
1181 #ifdef NEED_128
1182 uint128 big = construct_128 (0, cpu.instrCnt);
1183 // Sync up the clock and the TR; see wiki page "CAC 08-Oct-2014"
1184 //big *= 4u;
1185 big = lshift_128 (big, 2);
1186 if (scu [0].bullet_time)
1187 big = multiply_128 (big, construct_128 (0, 10000u));
1188
1189 //big += scu [0].elapsed_days * 1000000llu * 60llu * 60llu * 24llu;
1190 uint128 days = construct_128 (0, scu[0].elapsed_days);
1191 days = multiply_128 (days, construct_128 (0, 1000000));
1192 days = multiply_128 (days, construct_128 (0, 60 * 60 * 24));
1193 big = add_128 (big, days);
1194 #else
1195 __uint128_t big = cpu.instrCnt;
1196 // Sync up the clock and the TR; see wiki page "CAC 08-Oct-2014"
1197 big *= 4u;
1198 //big /= 100u;
1199 if (scu [0].bullet_time)
1200 big *= 10000;
1201
1202 big += scu [0].elapsed_days * 1000000llu * 60llu * 60llu * 24llu;
1203 #endif
1204
1205 // Boot time
1206
1207 // load_fnp is complaining that FNP core image is more than 5 years old; try
1208 // moving the 'boot time' back to MR12.3 release date. (12/89 according to
1209 // https://www.multicians.org/chrono.html
1210
1211 // date -d "1990-01-01 00:00:00 -9" +%s
1212 // 631184400
1213 // For debugging MR12.3 and earlier with steady_clock, uncomment --
1214 // uint64 UNIX_secs = 631184400;
1215
1216 // Otherwise, we'll use the current time as the steady_clock starting point --
1217 uint64 UNIX_secs = (uint64)time(NULL);
1218
1219 #ifdef NEED_128
1220 uint64 UNIX_usecs = UNIX_secs * 1000000llu + big.l;
1221 #else
1222 uint64 UNIX_usecs = UNIX_secs * 1000000llu + (uint64) big;
1223 #endif
1224 // now determine uSecs since Jan 1, 1901 ...
1225 uint64 Multics_usecs = 2177452800000000llu + UNIX_usecs;
1226
1227 // The casting to uint show be okay; both are 64 bit, so if
1228 // user_correction is <0, it will come out in the wash ok.
1229 Multics_usecs += (uint64) scu [scu_unit_idx].user_correction;
1230
1231 // The get calendar clock function is guaranteed to return
1232 // different values on successive calls.
1233
1234 if (scu [scu_unit_idx].last_time >= Multics_usecs)
1235 {
1236 sim_debug (DBG_TRACE, & scu_dev, "finagle clock\n");
1237 Multics_usecs = scu [scu_unit_idx].last_time + 1;
1238 }
1239 scu [scu_unit_idx].last_time = Multics_usecs;
1240 goto done;
1241 }
1242
1243 // The calendar clock consists of a 52-bit register which counts
1244 // microseconds and is readable as a double-precision integer by a
1245 // single instruction from any central processor. This rate is in
1246 // the same order of magnitude as the instruction processing rate of
1247 // the GE-645, so that timing of 10-instruction subroutines is
1248 // meaningful. The register is wide enough that overflow requires
1249 // several tens of years; thus it serves as a calendar containing
1250 // the number of microseconds since 0000 GMT, January 1, 1901
1251 /// Secs from Jan 1, 1901 to Jan 1, 1970 - 2 177 452 800 Seconds
1252 /// uSecs from Jan 1, 1901 to Jan 1, 1970 - 2 177 452 800 000 000 uSeconds
1253
1254 struct timeval now;
1255 gettimeofday(& now, NULL);
1256
1257 if (scu [0].y2k) // Apply clock skew when Y2K mode enabled
1258 {
1259 // Back the clock up to just after the MR12.5 release
1260 // $ date --date='30 years ago' +%s ; date +%s
1261 // 1685451324
1262 // 7738766524
1263 now.tv_sec -= (1685451324 - 738766524); // XXX(jhj): make dynamic!
1264 }
1265 uint64 UNIX_secs = (uint64) now.tv_sec;
1266 uint64 UNIX_usecs = UNIX_secs * 1000000LL + (uint64) now.tv_usec;
1267
1268 static uint64 last_UNIX_usecs = 0;
1269 if ( (!sim_quiet) && (UNIX_usecs < last_UNIX_usecs))
1270 {
1271 if (gtod_warned < 11)
1272 {
1273 sim_warn ("\rHost clock went backwards %llu uS!\r\n",
1274 (unsigned long long)(last_UNIX_usecs - UNIX_usecs));
1275 gtod_warned++;
1276 }
1277 else if (gtod_warned == 11)
1278 {
1279 sim_warn ("\rHost clock went backwards %llu uS! Suppressing further warnings.\r\n",
1280 (unsigned long long)(last_UNIX_usecs - UNIX_usecs));
1281 gtod_warned++;
1282 }
1283 }
1284 last_UNIX_usecs = UNIX_usecs;
1285
1286 // now determine uSecs since Jan 1, 1901 ...
1287 uint64 Multics_usecs = 2177452800000000LL + UNIX_usecs;
1288
1289 // Correction factor from the set time command
1290
1291 // The casting to uint show be okay; both are 64 bit, so if
1292 // user_correction is <0, it will come out in the wash ok.
1293 Multics_usecs += (uint64) scu [scu_unit_idx].user_correction;
1294
1295 if (scu [scu_unit_idx].last_time >= Multics_usecs)
1296 Multics_usecs = scu [scu_unit_idx].last_time + 1;
1297 scu [scu_unit_idx].last_time = Multics_usecs;
1298
1299 done:
1300 #if defined(THREADZ) || defined(LOCKLESS)
1301 pthread_mutex_unlock (& clock_lock);
1302 #endif
1303
1304 return scu [scu_unit_idx].last_time;
1305
1306 }
1307
1308 //static char pcellb [N_CELL_INTERRUPTS + 1];
1309 static char * pcells (uint scu_unit_idx, char * buf)
/* */
1310 {
1311 for (uint i = 0; i < N_CELL_INTERRUPTS; i ++)
1312 {
1313 if (scu [scu_unit_idx].cells [i])
1314 buf [i] = '1';
1315 else
1316 buf [i] = '0';
1317 }
1318 buf [N_CELL_INTERRUPTS] = '\0';
1319 return buf;
1320 }
1321
1322 // Either an interrupt has arrived on a port, or a mask register has
1323 // been updated. Bring the CPU up date on the interrupts.
1324
1325 // threadz notes:
1326 //
1327 // deliver_interrupts is called either from a CPU instruction or from
1328 // IOM set_general_interrupt on the IOM thread.
1329 //
1330 // potential race conditions:
1331 // CPU variables: XIP
1332 // SCU variables: cells, mask_enable, exec_intr_mask, mask assignment
1333
1334 // Always called with SCU lock set
1335
1336 static void deliver_interrupts (uint scu_unit_idx)
/* */
1337 {
1338 sim_debug (DBG_DEBUG, & scu_dev, "deliver_interrupts %o\n", scu_unit_idx);
1339 for (uint cpun = 0; cpun < cpu_dev.numunits; cpun ++)
1340 {
1341 cpus[cpun].events.XIP[scu_unit_idx] = false;
1342 }
1343
1344 // If the CIOC generates marker and terminate interrupts, they will be posted simultaneously.
1345 // Since the interrupts are recognized by priority and terminate has a higher priority then
1346 // marker, if will be delivered first. The following code will deliver marker before terminate.
1347
1348 #ifdef REORDER
1349 for (uint jnum = 0; jnum < N_CELL_INTERRUPTS; jnum ++)
1350 {
1351 static const uint reorder[N_CELL_INTERRUPTS] = {
1352 0, 1, 2, 3, 4, 5, 6, 7,
1353 16, 17, 18, 29, 20, 21, 22, 23,
1354 8, 9, 10, 11, 12, 13, 14, 15,
1355 25, 25, 26, 27, 28, 29, 30, 31 };
1356 uint inum = reorder[jnum];
1357 if (! scu [scu_unit_idx].cells [inum])
1358 continue; //
1359 sim_debug (DBG_DEBUG, & scu_dev, "trying to deliver %d\n", inum);
1360 sim_debug (DBG_INTR, & scu_dev,
1361 "scu %u trying to deliver %d\n", scu_unit_idx, inum);
1362
1363 for (uint pima = 0; pima < N_ASSIGNMENTS; pima ++) // A, B
1364 {
1365 //sim_debug (DBG_DEBUG, & scu_dev,
1366 // "trying inum %u pima %u enable %u\n"
1367 // , inum, pima, scu [scu_unit_idx].mask_enable [pima]);
1368 if (scu [scu_unit_idx].mask_enable [pima] == 0)
1369 continue;
1370 uint mask = scu [scu_unit_idx].exec_intr_mask [pima];
1371 uint port = scu [scu_unit_idx].mask_assignment [pima];
1372 //sim_debug (DBG_DEBUG, & scu_dev,
1373 // "mask %u port %u type %u cells %o\n",
1374 // mask, port, scu [scu_unit_idx].ports [port].type,
1375 // scu [scu_unit_idx].cells [inum]);
1376 if (scu [scu_unit_idx].ports [port].type != ADEV_CPU)
1377 continue;
1378 if ((mask & (1u << (31 - inum))) != 0)
1379 {
1380 uint sn = 0;
1381 if (scu[scu_unit_idx].ports[port].is_exp)
1382 {
1383 sn = (uint) scu[scu_unit_idx].ports[port].xipmaskval;
1384 if (sn >= N_SCU_SUBPORTS)
1385 {
1386 sim_warn ("XIP mask not set; defaulting to subport 0\n");
1387 sn = 0;
1388 }
1389 }
1390 if (! cables->scu_to_cpu[scu_unit_idx][port][sn].in_use)
1391 {
1392 sim_warn ("bad scu_unit_idx %u\n", scu_unit_idx);
1393 continue;
1394 }
1395 uint cpu_unit_udx = cables->scu_to_cpu[scu_unit_idx][port][sn].cpu_unit_idx;
1396 # if defined(THREADZ) || defined(LOCKLESS)
1397 cpus[cpu_unit_udx].events.XIP[scu_unit_idx] = true;
1398 # ifdef TESTING
1399 HDBGIntrSet (inum, cpu_unit_udx, scu_unit_idx, __func__);
1400 # endif
1401 createCPUThread((uint) cpu_unit_udx);
1402 # ifndef NO_TIMEWAIT
1403 wakeCPU ((uint) cpu_unit_udx);
1404 # endif
1405 sim_debug (DBG_DEBUG, & scu_dev,
1406 "interrupt set for CPU %d SCU %d\n",
1407 cpu_unit_udx, scu_unit_idx);
1408 # else // ! THREADZ
1409 //if (cpu_unit_udx && ! cpu.isRunning) sim_printf ("starting CPU %c\n", cpu_unit_udx + 'A');
1410 # ifdef ROUND_ROBIN
1411 cpus[cpu_unit_udx].isRunning = true;
1412 # endif
1413 cpus[cpu_unit_udx].events.XIP[scu_unit_idx] = true;
1414 sim_debug (DBG_DEBUG, & scu_dev, "interrupt set for CPU %d SCU %d\n", cpu_unit_udx, scu_unit_idx);
1415 sim_debug (DBG_INTR, & scu_dev,
1416 "XIP set for SCU %d\n", scu_unit_idx);
1417 # endif // ! THREADZ
1418 }
1419 }
1420 }
1421 #else // !REORDER
1422 for (uint inum = 0; inum < N_CELL_INTERRUPTS; inum ++)
1423 {
1424 if (! scu [scu_unit_idx].cells [inum])
1425 continue; //
1426 sim_debug (DBG_DEBUG, & scu_dev, "trying to deliver %d\n", inum);
1427 sim_debug (DBG_INTR, & scu_dev,
1428 "scu %u trying to deliver %d\n", scu_unit_idx, inum);
1429
1430 for (uint pima = 0; pima < N_ASSIGNMENTS; pima ++) // A, B
1431 {
1432 //sim_debug (DBG_DEBUG, & scu_dev,
1433 // "trying inum %u pima %u enable %u\n"
1434 // , inum, pima, scu [scu_unit_idx].mask_enable [pima]);
1435 if (scu [scu_unit_idx].mask_enable [pima] == 0)
1436 continue;
1437 uint mask = scu [scu_unit_idx].exec_intr_mask [pima];
1438 uint port = scu [scu_unit_idx].mask_assignment [pima];
1439 //sim_debug (DBG_DEBUG, & scu_dev,
1440 // "mask %u port %u type %u cells %o\n",
1441 // mask, port, scu [scu_unit_idx].ports [port].type,
1442 // scu [scu_unit_idx].cells [inum]);
1443 if (scu [scu_unit_idx].ports [port].type != ADEV_CPU)
1444 continue;
1445 if ((mask & (1u << (31 - inum))) != 0)
1446 {
1447 uint sn = 0;
1448 if (scu[scu_unit_idx].ports[port].is_exp)
1449 {
1450 sn = (uint) scu[scu_unit_idx].ports[port].xipmaskval;
1451 if (sn >= N_SCU_SUBPORTS)
1452 {
1453 sim_warn ("XIP mask not set; defaulting to subport 0\n");
1454 sn = 0;
1455 }
1456 }
1457 if (! cables->scu_to_cpu[scu_unit_idx][port][sn].in_use)
1458 {
1459 sim_warn ("bad scu_unit_idx %u\n", scu_unit_idx);
1460 continue;
1461 }
1462 uint cpu_unit_udx = cables->scu_to_cpu[scu_unit_idx][port][sn].cpu_unit_idx;
1463 # if defined(THREADZ) || defined(LOCKLESS)
1464 cpus[cpu_unit_udx].events.XIP[scu_unit_idx] = true;
1465 # ifdef TESTING
1466 HDBGIntrSet (inum, cpu_unit_udx, scu_unit_idx, __func__);
1467 # endif
1468 createCPUThread((uint) cpu_unit_udx);
1469 # ifndef NO_TIMEWAIT
1470 wakeCPU ((uint) cpu_unit_udx);
1471 # endif
1472 sim_debug (DBG_DEBUG, & scu_dev,
1473 "interrupt set for CPU %d SCU %d\n",
1474 cpu_unit_udx, scu_unit_idx);
1475 # else // ! THREADZ
1476 //if (cpu_unit_udx && ! cpu.isRunning) sim_printf ("starting CPU %c\n", cpu_unit_udx + 'A');
1477 # ifdef ROUND_ROBIN
1478 cpus[cpu_unit_udx].isRunning = true;
1479 # endif
1480 cpus[cpu_unit_udx].events.XIP[scu_unit_idx] = true;
1481 sim_debug (DBG_DEBUG, & scu_dev, "interrupt set for CPU %d SCU %d\n", cpu_unit_udx, scu_unit_idx);
1482 sim_debug (DBG_INTR, & scu_dev,
1483 "XIP set for SCU %d\n", scu_unit_idx);
1484 # endif // ! THREADZ
1485 }
1486 }
1487 }
1488 #endif // REORDER
1489 }
1490
1491 t_stat scu_smic (uint scu_unit_idx, uint UNUSED cpu_unit_udx,
/* */
1492 uint UNUSED cpu_port_num, word36 rega)
1493 {
1494 #if defined(THREADZ) || defined(LOCKLESS)
1495 lock_scu ();
1496 #endif
1497 // smic can set cells but not reset them...
1498
1499 if (getbits36_1 (rega, 35))
1500 {
1501 for (uint i = 0; i < 16; i ++)
1502 {
1503 if (getbits36_1 (rega, i))
1504 scu [scu_unit_idx].cells [i + 16] = 1;
1505 }
1506 char pcellb [N_CELL_INTERRUPTS + 1];
1507 sim_debug (DBG_TRACE, & scu_dev,
1508 "SMIC low: Unit %u Cells: %s\n",
1509 scu_unit_idx, pcells (scu_unit_idx, pcellb));
1510 }
1511 else
1512 {
1513 for (uint i = 0; i < 16; i ++)
1514 {
1515 if (getbits36_1 (rega, i))
1516 scu [scu_unit_idx].cells [i] = 1;
1517 }
1518 char pcellb [N_CELL_INTERRUPTS + 1];
1519 sim_debug (DBG_TRACE, & scu_dev,
1520 "SMIC high: Unit %d Cells: %s\n",
1521 scu_unit_idx, pcells (scu_unit_idx, pcellb));
1522 }
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548 dump_intr_regs ("smic", scu_unit_idx);
1549 deliver_interrupts (scu_unit_idx);
1550 #if defined(THREADZ) || defined(LOCKLESS)
1551 unlock_scu ();
1552 #endif
1553 return SCPE_OK;
1554 }
1555
1556 // system controller and the function to be performed as follows:
1557 //
1558 // Effective Function
1559 // Address
1560 // y0000x C(system controller mode register) -> C(AQ)
1561 // y0001x C(system controller configuration switches) -> C(AQ)
1562 // y0002x C(mask register assigned to port 0) -> C(AQ)
1563 // y0012x C(mask register assigned to port 1) -> C(AQ)
1564 // y0022x C(mask register assigned to port 2) -> C(AQ)
1565 // y0032x C(mask register assigned to port 3) -> C(AQ)
1566 // y0042x C(mask register assigned to port 4) -> C(AQ)
1567 // y0052x C(mask register assigned to port 5) -> C(AQ)
1568 // y0062x C(mask register assigned to port 6) -> C(AQ)
1569 // y0072x C(mask register assigned to port 7) -> C(AQ)
1570 // y0003x C(interrupt cells) -> C(AQ)
1571 //
1572 // y0004x
1573 // or C(calendar clock) -> C(AQ)
1574 // y0005x
1575 //
1576 // y0006x
1577 // or C(store unit mode register) -> C(AQ)
1578 // y0007x
1579 //
1580 // where: y = value of C(TPR.CA)0,2 (C(TPR.CA)1,2 for the DPS 8M
1581 // processor) used to select the system controller
1582 // x = any octal digit
1583 //
1584
1585 t_stat scu_sscr (uint scu_unit_idx, UNUSED uint cpu_unit_udx,
/* */
1586 UNUSED uint cpu_port_num, word18 addr,
1587 word36 rega, word36 regq)
1588 {
1589 sim_debug (DBG_DEBUG, & scu_dev, "sscr SCU unit %o\n", scu_unit_idx);
1590
1591 // Only valid for a 4MW SCU
1592
1593 if (scu_unit_idx >= scu_dev.numunits)
1594 {
1595 // XXX should this be a store fault?
1596 sim_warn ("%s: scu_unit_idx out of range %d\n",
1597 __func__, scu_unit_idx);
1598 return SCPE_OK;
1599 }
1600
1601 // BCE uses clever addressing schemes to select SCUs; it appears we need
1602 // to be more selecting in picking out the function bits;
1603 //uint function = (addr >> 3) & 07777;
1604 uint function = (addr >> 3) & 07;
1605
1606 // See scs.incl.pl1
1607
1608 if (config_switches [scu_unit_idx].mode != MODE_PROGRAM)
1609 {
1610 sim_warn ("%s: SCU mode is 'MANUAL', not 'PROGRAM' -- sscr "
1611 "not allowed to set switches.\n",
1612 __func__);
1613 // XXX [CAC] Setting an unassigned register generates a STORE FAULT;
1614 // this probably should as well
1615 return SCPE_OK;
1616 }
1617
1618 // Not used by 4MW
1619
1620 switch (function)
1621 {
1622 case 00000: // Set system controller mode register
1623 {
1624 #if defined(THREADZ) || defined(LOCKLESS)
1625 lock_scu ();
1626 #endif
1627 scu [scu_unit_idx].id = (word4) getbits36_4 (regq, 50 - 36);
1628 scu [scu_unit_idx].mode_reg = getbits36_18 (regq, 54 - 36);
1629 #if defined(THREADZ) || defined(LOCKLESS)
1630 unlock_scu ();
1631 #endif
1632 }
1633 break;
1634
1635 case 00001: // Set system controller configuration register
1636 // (4MW SCU only)
1637 {
1638 sim_debug (DBG_DEBUG, & scu_dev,
1639 "sscr 1 %d A: %012"PRIo64" Q: %012"PRIo64"\n",
1640 scu_unit_idx, rega, regq);
1641 #if defined(THREADZ) || defined(LOCKLESS)
1642 lock_scu ();
1643 #endif
1644 scu_t * up = scu + scu_unit_idx;
1645 for (int maskab = 0; maskab < 2; maskab ++)
1646 {
1647 word9 mask = ((maskab ? regq : rega) >> 27) & 0777;
1648 if (mask & 01)
1649 {
1650 up -> mask_enable [maskab] = 0;
1651 sim_debug (DBG_DEBUG, & scu_dev,
1652 "sscr %u mask disable %d\n",
1653 scu_unit_idx, maskab);
1654 }
1655 else
1656 {
1657 up -> mask_enable [maskab] = 1;
1658 sim_debug (DBG_DEBUG, & scu_dev,
1659 "sscr %u mask enable %d\n",
1660 scu_unit_idx, maskab);
1661 for (int pn = 0; pn < N_SCU_PORTS; pn ++)
1662 {
1663 if ((2 << (N_SCU_PORTS - 1 - pn)) & mask)
1664 {
1665 up -> mask_assignment [maskab] = (uint) pn;
1666 break;
1667 }
1668 }
1669
1670 }
1671 sim_debug (DBG_INTR, & scu_dev,
1672 "SCU%u SSCR1 mask %c enable set to %u assigned to "
1673 "port %u\n",
1674 scu_unit_idx, 'a' + maskab, up->mask_enable[maskab],
1675 up->mask_assignment[maskab]);
1676 }
1677 // AN87-00A, pg 2-5, 2-6 specify which fields are and are not
1678 // settable.
1679
1680 //if (up -> lower_store_size != ((rega >> 24) & 07))
1681 //sim_printf ("??? The CPU tried to change the SCU store size\n");
1682 up -> lower_store_size = (rega >> 24) & 07;
1683 up -> cyclic = (regq >> 8) & 0177;
1684 up -> nea = (rega >> 6) & 0377;
1685 up -> onl = (rega >> 20) & 017;
1686 up -> interlace = (rega >> 5) & 1;
1687 up -> lwr = (rega >> 4) & 1;
1688 up -> port_enable [0] = (rega >> 3) & 01;
1689 up -> port_enable [1] = (rega >> 2) & 01;
1690 up -> port_enable [2] = (rega >> 1) & 01;
1691 up -> port_enable [3] = (rega >> 0) & 01;
1692 up -> port_enable [4] = (regq >> 3) & 01;
1693 up -> port_enable [5] = (regq >> 2) & 01;
1694 up -> port_enable [6] = (regq >> 1) & 01;
1695 up -> port_enable [7] = (regq >> 0) & 01;
1696
1697 #if defined(THREADZ) || defined(LOCKLESS)
1698 unlock_scu ();
1699 #endif
1700 // XXX A, A1, B, B1, INT, LWR not implemented. (AG87-00A pgs 2-5,
1701 // 2-6)
1702 break;
1703 }
1704
1705 case 00002: // Set mask register port 0
1706 //case 00012: // Set mask register port 1
1707 //case 00022: // Set mask register port 2
1708 //case 00032: // Set mask register port 3
1709 //case 00042: // Set mask register port 4
1710 //case 00052: // Set mask register port 5
1711 //case 00062: // Set mask register port 6
1712 //case 00072: // Set mask register port 7
1713 {
1714 #if defined(THREADZ) || defined(LOCKLESS)
1715 lock_scu ();
1716 #endif
1717 uint port_num = (addr >> 6) & 07;
1718 sim_debug (DBG_DEBUG, & scu_dev, "Set mask register port %d to "
1719 "%012"PRIo64",%012"PRIo64"\n",
1720 port_num, rega, regq);
1721
1722 // Find mask reg assigned to specified port
1723 int mask_num = -1;
1724 uint n_masks_found = 0;
1725 for (int p = 0; p < N_ASSIGNMENTS; p ++)
1726 {
1727 //if (scup -> interrupts [p].mask_assign.unassigned)
1728 if (scu [scu_unit_idx].mask_enable [p] == 0)
1729 continue;
1730 //if (scup -> interrupts [p].mask_assign.port == port_num)
1731 if (scu [scu_unit_idx ].mask_assignment [p] == port_num)
1732 {
1733 if (n_masks_found == 0)
1734 mask_num = p;
1735 n_masks_found ++;
1736 }
1737 }
1738
1739 if (! n_masks_found)
1740 {
1741 // According to bootload_tape_label.alm, this condition is OK
1742 sim_debug (DBG_WARN, & scu_dev,
1743 "%s: No masks assigned to cpu on port %d\n",
1744 __func__, port_num);
1745 #if defined(THREADZ) || defined(LOCKLESS)
1746 unlock_scu ();
1747 #endif
1748 return SCPE_OK;
1749 }
1750
1751 if (n_masks_found > 1)
1752 {
1753 // Not legal for Multics
1754 sim_debug (DBG_WARN, & scu_dev,
1755 "%s: Multiple masks assigned to cpu on port %d\n",
1756 __func__, port_num);
1757 }
1758
1759 // See AN87
1760 //scup -> interrupts[mask_num].exec_intr_mask = 0;
1761 scu [scu_unit_idx].exec_intr_mask [mask_num] = 0;
1762 scu [scu_unit_idx].exec_intr_mask [mask_num] |=
1763 ((word32) getbits36_16(rega, 0) << 16);
1764 scu [scu_unit_idx].exec_intr_mask [mask_num] |=
1765 getbits36_16(regq, 0);
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775 sim_debug (DBG_TRACE, & scu_dev,
1776 "SSCR Set mask unit %u port %u mask_num %u "
1777 "mask 0x%08x\n",
1778 scu_unit_idx, port_num, mask_num,
1779 scu [scu_unit_idx].exec_intr_mask [mask_num]);
1780 dump_intr_regs ("sscr set mask", scu_unit_idx);
1781 scu [scu_unit_idx].mask_enable [mask_num] = 1;
1782 sim_debug (DBG_INTR, & scu_dev,
1783 "SCU%u SSCR2 exec_intr mask %c set to 0x%08x"
1784 " and enabled.\n",
1785 scu_unit_idx, 'a' + mask_num,
1786 scu[scu_unit_idx].exec_intr_mask[mask_num]);
1787
1788 deliver_interrupts (scu_unit_idx);
1789 #if defined(THREADZ) || defined(LOCKLESS)
1790 unlock_scu ();
1791 #endif
1792 }
1793 break;
1794
1795 case 00003: // Set interrupt cells
1796 {
1797 #if defined(THREADZ) || defined(LOCKLESS)
1798 lock_scu ();
1799 #endif
1800 for (uint i = 0; i < 16; i ++)
1801 {
1802 scu [scu_unit_idx].cells [i] =
1803 getbits36_1 (rega, i) ? 1 : 0;
1804 scu [scu_unit_idx].cells [i + 16] =
1805 getbits36_1 (regq, i) ? 1 : 0;
1806 }
1807 char pcellb [N_CELL_INTERRUPTS + 1];
1808 sim_debug (DBG_TRACE, & scu_dev,
1809 "SSCR Set int. cells: Unit %u Cells: %s\n",
1810 scu_unit_idx, pcells (scu_unit_idx, pcellb));
1811 sim_debug (DBG_INTR, & scu_dev,
1812 "SCU%u SSCR3 Set int. cells %s\n",
1813 scu_unit_idx, pcells (scu_unit_idx, pcellb));
1814 dump_intr_regs ("sscr set interrupt cells", scu_unit_idx);
1815 deliver_interrupts (scu_unit_idx);
1816 #if defined(THREADZ) || defined(LOCKLESS)
1817 unlock_scu ();
1818 #endif
1819 }
1820 break;
1821
1822 case 00004: // Set calendar clock (4MW SCU only)
1823 case 00005:
1824 {
1825 // AQ: 20-35 clock bits 0-15, 36-71 clock bits 16-51
1826 word16 b0_15 = (word16) getbits36_16 (cpu.rA, 20);
1827 word36 b16_51 = cpu.rQ;
1828 uint64 new_clk = (((uint64) b0_15) << 36) | b16_51;
1829 #if defined(THREADZ) || defined(LOCKLESS)
1830 lock_scu ();
1831 #endif
1832 scu [scu_unit_idx].user_correction =
1833 (int64) (new_clk - set_SCU_clock (scu_unit_idx));
1834 #if defined(THREADZ) || defined(LOCKLESS)
1835 unlock_scu ();
1836 #endif
1837 //sim_printf ("sscr %o\n", function);
1838 }
1839 break;
1840
1841 case 00006: // Set unit mode register
1842 case 00007:
1843 // XXX See notes in AL39 sscr re: store unit selection
1844 //sim_printf ("sscr %o\n", function);
1845 sim_warn ("sscr set unit mode register\n");
1846 //return STOP_UNIMP;
1847 return SCPE_OK;
1848
1849 default:
1850 sim_warn ("sscr unhandled code\n");
1851 //return STOP_UNIMP;
1852 return SCPE_OK;
1853 //sim_printf ("sscr %o\n", function);
1854 }
1855 return SCPE_OK;
1856 }
1857
1858 t_stat scu_rscr (uint scu_unit_idx, uint cpu_unit_udx, word18 addr,
/* */
1859 word36 * rega, word36 * regq)
1860 {
1861 // Only valid for a 4MW SCU
1862
1863 if (scu_unit_idx >= scu_dev.numunits)
1864 {
1865 sim_warn ("%s: scu_unit_idx out of range %d\n",
1866 __func__, scu_unit_idx);
1867 return SCPE_OK;
1868 }
1869
1870 // BCE uses clever addressing schemes to select SCUs; it appears we need
1871 // to be more selecting in picking out the function bits;
1872 //uint function = (addr >> 3) & 07777;
1873 uint function = (addr >> 3) & 07;
1874
1875 //sim_printf ("rscr %o\n", function);
1876
1877 // See scs.incl.pl1
1878
1879 switch (function)
1880 {
1881 case 00000: // Read system controller mode register
1882 {
1883 // AN-87
1884 // 0..0 -> A
1885 // 0..0 -> Q 36-49 (0-13)
1886 // ID -> Q 50-53 (14-17)
1887 // MODE REG -> Q 54-71 (18-35)
1888 //
1889 // ID: 0000 8034, 8035
1890 // 0001 Level 68 SC
1891 // 0010 Level 66 SCU
1892 // CAC: According to scr.incl.pl1. 0010 is a 4MW SCU
1893 // MODE REG: these fields are only used by T&D
1894 * rega = 0;
1895 //* regq = 0000002000000; // ID = 0010
1896 * regq = 0;
1897 #if defined(THREADZ) || defined(LOCKLESS)
1898 lock_scu ();
1899 #endif
1900 putbits36_4 (regq, 50 - 36, scu [scu_unit_idx].id);
1901 putbits36_18 (regq, 54 - 36, scu [scu_unit_idx].mode_reg);
1902 #if defined(THREADZ) || defined(LOCKLESS)
1903 unlock_scu ();
1904 #endif
1905 break;
1906 }
1907
1908 case 00001: // Read system controller configuration register
1909 {
1910 // AN-87, scr.incl.pl1
1911 //
1912 // SCU:
1913 // reg A:
1914 // MASK A | SIZE | A | A1 | B | B1 | PORT | 0 | MOD | NEA |
1915 // INT | LWR | PMR 0-3
1916 // reg Q:
1917 // MASK B | not used | CYCLIC PRIOR | not used | PMR 4-7
1918 //
1919 // MASK A/B (9 bits): EIMA switch setting for mask A/B. The
1920 // assigned port corresponds to the but position within the
1921 // field. A bit in position 9 indicates that the mask is
1922 // not assigned.
1923 // From scr.incl.pl1:
1924 // 400 => assigned to port 0
1925 // .
1926 // .
1927 // 002 => assigned to port 7
1928 // 001 => mask off */
1929
1930 //
1931 // SIZE (3 bits): Size of lower store
1932 // 000 = 32K ... 111 = 4M
1933 //
1934 // A A1 B B1 (1 bit): store unit A/A1/B/B1 online
1935 //
1936 // PORT (4 bits): Port number of the SCU port through which
1937 // the RSCR instruction was received
1938 //
1939 //struct config_switches * sw = config_switches + scu_unit_idx;
1940 sim_debug (DBG_DEBUG, & scu_dev, "rscr 1 %d\n", scu_unit_idx);
1941 #if defined(THREADZ) || defined(LOCKLESS)
1942 lock_scu ();
1943 #endif
1944 scu_t * up = scu + scu_unit_idx;
1945 word9 maskab [2];
1946 for (int i = 0; i < 2; i ++)
1947 {
1948 if (up -> mask_enable [i])
1949 {
1950 maskab [i] = (2 << (N_SCU_PORTS - 1 -
1951 up -> mask_assignment [i])) & 0777;
1952 }
1953 else
1954 maskab [i] = 0001;
1955 }
1956
1957 int scu_port_num = -1; // The port that the rscr instruction was
1958 // received on
1959
1960 for (int pn = 0; pn < N_SCU_PORTS; pn ++)
1961 {
1962 for (int sn = 0; sn < N_SCU_SUBPORTS; sn ++)
1963 {
1964 if (cables->scu_to_cpu[scu_unit_idx][pn][sn].in_use &&
1965 cables->scu_to_cpu[scu_unit_idx][pn][sn].cpu_unit_idx ==
1966 cpu_unit_udx)
1967 {
1968 scu_port_num = pn;
1969 goto gotit;
1970 }
1971 }
1972 }
1973 gotit:;
1974 if (scu_port_num < 0)
1975 {
1976 #if defined(THREADZ) || defined(LOCKLESS)
1977 unlock_scu ();
1978 #endif
1979 sim_warn ("%s: can't find cpu port in the snarl of cables; "
1980 "scu_unit_no %d, cpu_unit_udx %d\n",
1981 __func__, scu_unit_idx, cpu_unit_udx);
1982 return SCPE_OK;
1983 }
1984
1985 // AN87, pg 2-5
1986 word36 a, q;
1987
1988 a = 0;
1989 // (data, starting bit position, number of bits, value)
1990 putbits36_9 (& a, 0, maskab [0]);
1991 putbits36_3 (& a, 9, (word3) up -> lower_store_size);
1992 putbits36_4 (& a, 12, (word4) up -> onl); // A, A1, B, B1 online
1993 putbits36_4 (& a, 16, (word4) scu_port_num);
1994 putbits36_1 (& a, 21, (word1) config_switches[scu_unit_idx].mode);
1995 putbits36_8 (& a, 22, (word8) up -> nea);
1996 putbits36_1 (& a, 30, (word1) up -> interlace);
1997 putbits36_1 (& a, 31, (word1) up -> lwr);
1998 // XXX INT, LWR not implemented. (AG87-00A pgs 2-5. 2-6)
1999 // interlace <- 0
2000 // lower <- 0
2001 // Looking at scr_util.list, I *think* the port order
2002 // 0,1,2,3.
2003 putbits36_1 (& a, 32, (word1) up -> port_enable [0]);
2004 putbits36_1 (& a, 33, (word1) up -> port_enable [1]);
2005 putbits36_1 (& a, 34, (word1) up -> port_enable [2]);
2006 putbits36_1 (& a, 35, (word1) up -> port_enable [3]);
2007 * rega = a;
2008
2009 q = 0;
2010 putbits36_9 (& q, 0, maskab [1]);
2011 // cyclic prior <- 0
2012 putbits36_7 (& q, 57-36, (word7) up -> cyclic & MASK7);
2013 // Looking at scr_util.list, I *think* the port order
2014 // 0,1,2,3.
2015 putbits36_1 (& q, 32, (word1) up -> port_enable [4]);
2016 putbits36_1 (& q, 33, (word1) up -> port_enable [5]);
2017 putbits36_1 (& q, 34, (word1) up -> port_enable [6]);
2018 putbits36_1 (& q, 35, (word1) up -> port_enable [7]);
2019 * regq = q;
2020
2021 #if defined(THREADZ) || defined(LOCKLESS)
2022 unlock_scu ();
2023 #endif
2024 sim_debug (DBG_DEBUG, & scu_dev,
2025 "rscr 1 %d A: %012"PRIo64" Q: %012"PRIo64"\n",
2026 scu_unit_idx, * rega, * regq);
2027 break;
2028 }
2029
2030 case 00002: // mask register
2031 {
2032 uint port_num = (addr >> 6) & MASK3;
2033 #if defined(THREADZ) || defined(LOCKLESS)
2034 lock_scu ();
2035 #endif
2036 scu_t * up = scu + scu_unit_idx;
2037 uint mask_contents = 0;
2038 if (up -> mask_assignment [0] == port_num)
2039 {
2040 mask_contents = up -> exec_intr_mask [0];
2041 }
2042 else if (up -> mask_assignment [1] == port_num)
2043 {
2044 mask_contents = up -> exec_intr_mask [1];
2045 }
2046 mask_contents &= MASK32;
2047
2048 * rega = 0;
2049 putbits36 (rega, 0, 16, (mask_contents >> 16) & MASK16);
2050 putbits36 (rega, 32, 1, up -> port_enable [0]);
2051 putbits36 (rega, 33, 1, up -> port_enable [1]);
2052 putbits36 (rega, 34, 1, up -> port_enable [2]);
2053 putbits36 (rega, 35, 1, up -> port_enable [3]);
2054
2055 * regq = 0;
2056 putbits36 (rega, 0, 16, (mask_contents >> 0) & MASK16);
2057 putbits36 (regq, 32, 1, up -> port_enable [4]);
2058 putbits36 (regq, 33, 1, up -> port_enable [5]);
2059 putbits36 (regq, 34, 1, up -> port_enable [6]);
2060 putbits36 (regq, 35, 1, up -> port_enable [7]);
2061
2062 #if defined(THREADZ) || defined(LOCKLESS)
2063 unlock_scu ();
2064 #endif
2065 sim_debug (DBG_TRACE, & scu_dev,
2066 "RSCR mask unit %u port %u assigns %u %u mask 0x%08x\n",
2067 scu_unit_idx, port_num, up -> mask_assignment [0],
2068 up -> mask_assignment [1],
2069 mask_contents);
2070 }
2071 break;
2072
2073 case 00003: // Interrupt cells
2074 {
2075 #if defined(THREADZ) || defined(LOCKLESS)
2076 lock_scu ();
2077 #endif
2078 scu_t * up = scu + scu_unit_idx;
2079 // * rega = up -> exec_intr_mask [0];
2080 // * regq = up -> exec_intr_mask [1];
2081 for (uint i = 0; i < N_CELL_INTERRUPTS; i ++)
2082 {
2083 word1 cell = up -> cells [i] ? 1 : 0;
2084 if (i < 16)
2085 putbits36_1 (rega, i, cell);
2086 else
2087 putbits36_1 (regq, i - 16, cell);
2088 }
2089 #if defined(THREADZ) || defined(LOCKLESS)
2090 unlock_scu ();
2091 #endif
2092 }
2093 break;
2094
2095 case 00004: // Get calendar clock (4MW SCU only)
2096 case 00005:
2097 {
2098 uint64 clk = set_SCU_clock (scu_unit_idx);
2099 cpu.rQ = clk & 0777777777777; // lower 36-bits of clock
2100 cpu.rA = (clk >> 36) & 0177777; // upper 16-bits of clock
2101 #ifdef TESTING
2102 HDBGRegAW ("rscr get clock");
2103 HDBGRegQW ("rscr get clock");
2104 #endif
2105 }
2106 break;
2107
2108 case 00006: // SU Mode register
2109 case 00007: // SU Mode register
2110 {
2111 //sim_printf ("rscr SU Mode Register%o\n", function);
2112
2113 // Completely undocumented...
2114 // scr.incl.alm
2115 //" Structure scr_su
2116 //"
2117 // equ scr_su_size,2
2118 //
2119 //
2120 // equ scr_su.ZAC_line_word,1
2121 // equ scr_su.ZAC_line_shift,30
2122 // bool scr_su.ZAC_line_mask,000077
2123 // equ scr_su.syndrome_word,1
2124 // equ scr_su.syndrome_shift,22
2125 // bool scr_su.syndrome_mask,000377
2126 // equ scr_su.identification_word,1
2127 // equ scr_su.identification_shift,18
2128 // bool scr_su.identification_mask,000017
2129 // equ scr_su.EDAC_disabled_word,1
2130 // bool scr_su.EDAC_disabled,400000 " DL
2131 // equ scr_su.MINUS_5_VOLT_margin_word,1
2132 //" equ scr_su.MINUS_5_VOLT_margin_shift,11
2133 // bool scr_su.MINUS_5_VOLT_margin_mask,000003
2134 // equ scr_su.PLUS_5_VOLT_margin_word,1
2135 // equ scr_su.PLUS_5_VOLT_margin_shift,9
2136 // bool scr_su.PLUS_5_VOLT_margin_mask,000003
2137 // equ scr_su.spare_margin_word,1
2138 // equ scr_su.spare_margin_shift,7
2139 // bool scr_su.spare_margin_mask,000003
2140 // equ scr_su.PLUS_19_VOLT_margin_word,1
2141 //" equ scr_su.PLUS_19_VOLT_margin_shift,5
2142 // bool scr_su.PLUS_19_VOLT_margin_mask,000003
2143 // equ scr_su.SENSE_strobe_margin_word,1
2144 //" equ scr_su.SENSE_strobe_margin_shift,2
2145 // bool scr_su.SENSE_strobe_margin_mask,000003
2146 //" equ scr_su.maint_functions_enabled_word,1
2147 // bool scr_su.maint_functions_enabled,000001 " DL
2148
2149 // 1 1 1 2 2 2 2 3 3 3 3
2150 // 0 6 4 8 9 3 5 7 9 1 2 4 5
2151 // ------------------------------------------------------------------------------
2152 // | ZAC | synd | id | EDAC | 0 | -5 | +5 | spare | +19 | 0 | sense | 0 | maint |
2153 // ------------------------------------------------------------------------------
2154 // 6 8 4 1 4 2 2 2 2 1 2 1 1
2155
2156 // Okay, it looks safe to return 0.
2157
2158 * rega = 0;
2159 * regq = 0;
2160 }
2161 break;
2162
2163 default:
2164 sim_warn ("rscr %o\n", function);
2165 return SCPE_OK;
2166 }
2167 return SCPE_OK;
2168 }
2169
2170
2171
2172
2173
2174 int scu_cioc (uint cpu_unit_udx, uint scu_unit_idx, uint scu_port_num,
/* */
2175 uint expander_command, uint sub_mask)
2176 {
2177
2178
2179
2180 sim_debug (DBG_DEBUG, & scu_dev,
2181 "scu_cioc: Connect from %o sent to "
2182 "unit %o port %o exp %o mask %03o\n",
2183 cpu_unit_udx, scu_unit_idx, scu_port_num,
2184 expander_command, sub_mask);
2185
2186 #if defined(THREADZ) || defined(LOCKLESS)
2187 lock_scu ();
2188 #endif
2189 struct ports * portp = & scu [scu_unit_idx].ports [scu_port_num];
2190
2191 int rc = 0;
2192 if (! scu [scu_unit_idx].port_enable [scu_port_num])
2193 {
2194 sim_debug (DBG_ERR, & scu_dev,
2195 "scu_cioc: Connect sent to disabled port; dropping\n");
2196 sim_debug (DBG_ERR, & scu_dev,
2197 "scu_cioc: scu_unit_idx %u scu_port_num %u\n",
2198 scu_unit_idx, scu_port_num);
2199 rc = 1;
2200 goto done;
2201 }
2202
2203 if (expander_command == 1) // "set subport enables"
2204 {
2205 for (uint i = 0; i < N_SCU_SUBPORTS; i++)
2206 {
2207 portp->subport_enables [i] = !! (sub_mask & (0200u >> i));
2208 }
2209 goto done;
2210 }
2211
2212 if (expander_command == 2) // "set xipmask"
2213 {
2214 int cnt = 0;
2215 int val = -1;
2216 for (uint i = 0; i < N_SCU_SUBPORTS; i++)
2217 {
2218 portp->xipmask [i] = !! (sub_mask & (0200u >> i));
2219 if (portp->xipmask [i])
2220 {
2221 val = (int) i;
2222 cnt ++;
2223 }
2224 }
2225 if (cnt > 1)
2226 {
2227 sim_warn ("xip mask cnt > 1\n");
2228 val = -1;
2229 }
2230 portp->xipmaskval = val;
2231 goto done;
2232 }
2233
2234 if (portp -> type == ADEV_IOM)
2235 {
2236 int iom_unit_idx = portp->dev_idx;
2237 #if defined(THREADZ) || defined(LOCKLESS)
2238 unlock_scu ();
2239 # if !defined(IO_ASYNC_PAYLOAD_CHAN) && !defined(IO_ASYNC_PAYLOAD_CHAN_THREAD)
2240 lock_iom ();
2241 lock_libuv ();
2242 # endif
2243 iom_interrupt (scu_unit_idx, (uint) iom_unit_idx);
2244 # if !defined(IO_ASYNC_PAYLOAD_CHAN) && !defined(IO_ASYNC_PAYLOAD_CHAN_THREAD)
2245 unlock_libuv ();
2246 unlock_iom ();
2247 # endif
2248 return 0;
2249 #else // ! THREADZ
2250 if (sys_opts.iom_times.connect <= 0)
2251 {
2252 iom_interrupt (scu_unit_idx, (uint) iom_unit_idx);
2253 goto done;
2254 }
2255 else
2256 {
2257 //sim_printf ("scu_cioc: Queuing an IOM in %d cycles "
2258 //"(for the connect channel) %u %d\n",
2259 //sys_opts.iom_times.connect, scu_unit_idx, iom_unit_idx);
2260 sim_debug (DBG_INFO, & scu_dev,
2261 "scu_cioc: Queuing an IOM in %d cycles "
2262 "(for the connect channel)\n",
2263 sys_opts.iom_times.connect);
2264 // Stash the iom_interrupt call parameters
2265 iom_dev.units[iom_unit_idx].u3 = (int32) scu_unit_idx;
2266 iom_dev.units[iom_unit_idx].u4 = (int32) iom_unit_idx;
2267 int rc;
2268 if ((rc = sim_activate (& iom_dev.units [iom_unit_idx],
2269 sys_opts.iom_times.connect)) != SCPE_OK)
2270 {
2271 sim_warn ("sim_activate failed (%d)\n", rc);
2272 goto done;
2273 }
2274 goto done;
2275 }
2276 #endif // ! THREADZ
2277 }
2278 else if (portp -> type == ADEV_CPU)
2279 {
2280
2281
2282 // by subport_enables
2283 if (portp->is_exp)
2284 {
2285 for (uint sn = 0; sn < N_SCU_SUBPORTS; sn ++)
2286 {
2287 if (portp->subport_enables[sn])
2288 {
2289 if (! cables->
2290 scu_to_cpu[scu_unit_idx][scu_port_num][sn].in_use)
2291 {
2292 sim_warn ("Can't find CPU to interrupt\n");
2293 continue;
2294 }
2295 uint cpu_unit_udx = cables->
2296 scu_to_cpu[scu_unit_idx][scu_port_num][sn].cpu_unit_idx;
2297 setG7fault ((uint) cpu_unit_udx, FAULT_CON, fst_zero);
2298 }
2299 }
2300 }
2301 else
2302 {
2303 if (! cables->scu_to_cpu[scu_unit_idx][scu_port_num][0].in_use)
2304 {
2305 sim_warn ("Can't find CPU to interrupt\n");
2306 rc = 1;
2307 goto done;
2308 }
2309 uint cpu_unit_udx =
2310 cables->scu_to_cpu[scu_unit_idx][scu_port_num][0].cpu_unit_idx;
2311 setG7fault ((uint) cpu_unit_udx, FAULT_CON, fst_zero);
2312 }
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335 goto done;
2336 }
2337 else
2338 {
2339 sim_debug (DBG_ERR, & scu_dev,
2340 "scu_cioc: Connect sent to not-an-IOM or CPU; dropping\n");
2341 rc = 1;
2342 goto done;
2343 }
2344 done:
2345 #if defined(THREADZ) || defined(LOCKLESS)
2346 unlock_scu ();
2347 #endif
2348 return rc;
2349 }
2350
2351 // =============================================================================
2352
2353 // The SXC (set execute cells) SCU command.
2354
2355 // From AN70:
2356 // It then generates a word with
2357 // the <interrupt number>th bit set and sends this to the bootload
2358 // SCU with the SC (set execute cells) SCU command.
2359 //
2360
2361 int scu_set_interrupt (uint scu_unit_idx, uint inum)
/* */
2362 {
2363 const char* moi = "SCU::interrupt";
2364
2365 if (inum >= N_CELL_INTERRUPTS)
2366 {
2367 sim_debug (DBG_WARN, & scu_dev,
2368 "%s: Bad interrupt number %d\n", moi, inum);
2369 return 1;
2370 }
2371
2372 #if defined(THREADZ) || defined(LOCKLESS)
2373 lock_scu ();
2374 #endif
2375 scu [scu_unit_idx].cells [inum] = 1;
2376 dump_intr_regs ("scu_set_interrupt", scu_unit_idx);
2377 deliver_interrupts (scu_unit_idx);
2378 #if defined(THREADZ) || defined(LOCKLESS)
2379 unlock_scu ();
2380 #endif
2381 return 0;
2382 }
2383
2384 // Scan a SCU for interrupts from highest to lowest. If an interrupt is
2385 // present, clear it, update the interrupt state bits and return the fault
2386 // pair address for the interrupt (2 * interrupt number). If no interrupt
2387 // is present, return 1.
2388 //
2389
2390 uint scu_get_highest_intr (uint scu_unit_idx)
/* */
2391 {
2392 #if defined(THREADZ) || defined(LOCKLESS)
2393 lock_scu ();
2394 #endif
2395 // lower numbered cells have higher priority
2396 for (int inum = 0; inum < N_CELL_INTERRUPTS; inum ++)
2397 {
2398 for (uint pima = 0; pima < N_ASSIGNMENTS; pima ++) // A, B
2399 {
2400 if (scu [scu_unit_idx].mask_enable [pima] == 0)
2401 continue;
2402 uint mask = scu [scu_unit_idx].exec_intr_mask [pima];
2403 uint port = scu [scu_unit_idx].mask_assignment [pima];
2404 // if (scu [scu_unit_idx].ports [port].type != ADEV_CPU ||
2405 // scu [scu_unit_idx].ports [port].dev_idx != current_running_cpu_idx)
2406 if (scu[scu_unit_idx].ports[port].type != ADEV_CPU ||
2407 cpus[current_running_cpu_idx].scu_port[scu_unit_idx] != port)
2408 continue;
2409 if (scu [scu_unit_idx].cells [inum] &&
2410 (mask & (1u << (31 - inum))) != 0)
2411 {
2412 sim_debug (DBG_TRACE, & scu_dev, "scu_get_highest_intr inum %d pima %u mask 0%011o port %u cells 0%011o\n", inum, pima, mask, port, scu [scu_unit_idx].cells [inum]);
2413 scu [scu_unit_idx].cells [inum] = false;
2414 dump_intr_regs ("scu_get_highest_intr", scu_unit_idx);
2415 deliver_interrupts (scu_unit_idx);
2416 #if defined(THREADZ) || defined(LOCKLESS)
2417 unlock_scu ();
2418 #endif
2419 return (uint) inum * 2;
2420 }
2421 }
2422 }
2423 #if defined(THREADZ) || defined(LOCKLESS)
2424 unlock_scu ();
2425 #endif
2426 return 1;
2427 }
2428
2429 t_stat scu_reset_unit (UNIT * uptr, UNUSED int32 value,
/* */
2430 UNUSED const char * cptr,
2431 UNUSED void * desc)
2432 {
2433 uint scu_unit_idx = (uint) (uptr - scu_unit);
2434 scu_unit_reset ((int) scu_unit_idx);
2435 return SCPE_OK;
2436 }
2437
2438 void scu_init (void)
/* */
2439 {
2440 // One time only initializations
2441
2442 for (int u = 0; u < N_SCU_UNITS_MAX; u ++)
2443 {
2444 for (int p = 0; p < N_SCU_PORTS; p ++)
2445 {
2446 for (int s = 0; s < N_SCU_SUBPORTS; s ++)
2447 {
2448 scu[u].ports[p].dev_port[s] = -1;
2449 scu[u].ports[p].subport_enables[s] = false;
2450 scu[u].ports[p].xipmask[s] = false;
2451 // Invalid value for detecting uninitialized XIP mask.
2452 scu[u].ports[p].xipmaskval = N_SCU_SUBPORTS;
2453 }
2454 scu[u].ports[p].type = ADEV_NONE;
2455 scu[u].ports[p].is_exp = false;
2456 }
2457
2458 // ID: 0000 8034, 8035
2459 // 0001 Level 68 SC
2460 // 0010 Level 66 SCU
2461 scu [u].id = 02l; // 0b0010
2462 scu [u].mode_reg = 0; // used by T&D
2463 scu [u].elapsed_days = 0;
2464 }
2465
2466 }
2467
2468 t_stat scu_rmcm (uint scu_unit_idx, uint cpu_unit_udx, word36 * rega,
/* */
2469 word36 * regq)
2470 {
2471 scu_t * up = scu + scu_unit_idx;
2472
2473 // Assume no mask register assigned
2474 * rega = 0;
2475 * regq = 0;
2476
2477 // Which port is cpu_unit_udx connected to? (i.e. which port did the
2478 // command come in on?
2479 int scu_port_num = -1; // The port that the rscr instruction was
2480 // received on
2481
2482 for (int pn = 0; pn < N_SCU_PORTS; pn ++)
2483 {
2484 for (int sn = 0; sn < N_SCU_SUBPORTS; sn ++)
2485 {
2486 if (cables->scu_to_cpu[scu_unit_idx][pn][sn].in_use &&
2487 cables->scu_to_cpu[scu_unit_idx][pn][sn].cpu_unit_idx ==
2488 cpu_unit_udx)
2489 {
2490 scu_port_num = pn;
2491 goto gotit;
2492 }
2493 }
2494 }
2495
2496 gotit:;
2497
2498 //sim_printf ("rmcm scu_port_num %d\n", scu_port_num);
2499
2500 if (scu_port_num < 0)
2501 {
2502 sim_warn ("%s: can't find cpu port in the snarl of cables; "
2503 "scu_unit_no %d, cpu_unit_udx %d\n",
2504 __func__, scu_unit_idx, cpu_unit_udx);
2505 sim_debug (DBG_ERR, & scu_dev,
2506 "%s: can't find cpu port in the snarl of cables; "
2507 "scu_unit_no %d, cpu_unit_udx %d\n",
2508 __func__, scu_unit_idx, cpu_unit_udx);
2509 // Non 4MWs do a store fault
2510 return SCPE_OK;
2511 }
2512
2513 // A reg:
2514 // 0 15 16 31 32 35
2515 // IER 0-15 00000000 PER 0-3
2516 // Q reg:
2517 // 0 15 16 31 32 35
2518 // IER 16-32 00000000 PER 4-7
2519
2520 sim_debug (DBG_TRACE, & scu_dev, "rmcm selected scu port %u\n",
2521 scu_port_num);
2522 #if defined(THREADZ) || defined(LOCKLESS)
2523 lock_scu ();
2524 #endif
2525 uint mask_contents = 0;
2526 if (up -> mask_assignment [0] == (uint) scu_port_num)
2527 {
2528 mask_contents = up -> exec_intr_mask [0];
2529 sim_debug (DBG_TRACE, & scu_dev, "rmcm got mask %011o from pima A\n",
2530 mask_contents);
2531 }
2532 else if (up -> mask_assignment [1] == (uint) scu_port_num)
2533 {
2534 mask_contents = up -> exec_intr_mask [1];
2535 sim_debug (DBG_TRACE, & scu_dev, "rmcm got mask %011o from pima B\n",
2536 mask_contents);
2537 }
2538 mask_contents &= MASK32;
2539
2540 * rega = 0; //-V1048
2541 putbits36_16 (rega, 0, (mask_contents >> 16) & MASK16);
2542 putbits36_1 (rega, 32, (word1) up -> port_enable [0]);
2543 putbits36_1 (rega, 33, (word1) up -> port_enable [1]);
2544 putbits36_1 (rega, 34, (word1) up -> port_enable [2]);
2545 putbits36_1 (rega, 35, (word1) up -> port_enable [3]);
2546
2547 * regq = 0; //-V1048
2548 putbits36_16 (regq, 0, (mask_contents >> 0) & MASK16);
2549 putbits36_1 (regq, 32, (word1) up -> port_enable [4]);
2550 putbits36_1 (regq, 33, (word1) up -> port_enable [5]);
2551 putbits36_1 (regq, 34, (word1) up -> port_enable [6]);
2552 putbits36_1 (regq, 35, (word1) up -> port_enable [7]);
2553
2554 #if defined(THREADZ) || defined(LOCKLESS)
2555 unlock_scu ();
2556 #endif
2557 sim_debug (DBG_TRACE, & scu_dev,
2558 "RMCM returns %012"PRIo64" %012"PRIo64"\n",
2559 * rega, * regq);
2560 dump_intr_regs ("rmcm", scu_unit_idx);
2561 return SCPE_OK;
2562 }
2563
2564 t_stat scu_smcm (uint scu_unit_idx, uint cpu_unit_udx, word36 rega, word36 regq)
/* ![[last]](../icons/n_last.png)
*/
2565 {
2566 sim_debug (DBG_TRACE, & scu_dev,
2567 "SMCM SCU unit %d CPU unit %d A %012"PRIo64" Q %012"PRIo64"\n",
2568 scu_unit_idx, cpu_unit_udx, rega, regq);
2569
2570 scu_t * up = scu + scu_unit_idx;
2571
2572 // Which port is cpu_unit_udx connected to? (i.e. which port did the
2573 // command come in on?
2574 int scu_port_num = -1; // The port that the rscr instruction was
2575 // received on
2576
2577 for (int pn = 0; pn < N_SCU_PORTS; pn ++)
2578 {
2579 for (int sn = 0; sn < N_SCU_SUBPORTS; sn ++)
2580 {
2581 if (cables->scu_to_cpu[scu_unit_idx][pn][sn].in_use &&
2582 cables->scu_to_cpu[scu_unit_idx][pn][sn].cpu_unit_idx ==
2583 cpu_unit_udx)
2584 {
2585 scu_port_num = pn;
2586 goto gotit;
2587 }
2588 }
2589 }
2590 gotit:;
2591
2592 //sim_printf ("rmcm scu_port_num %d\n", scu_port_num);
2593
2594 if (scu_port_num < 0)
2595 {
2596 sim_warn ("%s: can't find cpu port in the snarl of cables; "
2597 "scu_unit_no %d, cpu_unit_udx %d\n",
2598 __func__, scu_unit_idx, cpu_unit_udx);
2599 return SCPE_OK;
2600 }
2601
2602 sim_debug (DBG_TRACE, & scu_dev, "SMCM SCU port num %d\n", scu_port_num);
2603
2604 // A reg:
2605 // 0 15 16 31 32 35
2606 // IER 0-15 00000000 PER 0-3
2607 // Q reg:
2608 // 0 15 16 31 32 35
2609 // IER 16-32 00000000 PER 4-7
2610
2611 uint imask =
2612 ((uint) getbits36_16(rega, 0) << 16) |
2613 ((uint) getbits36_16(regq, 0) << 0);
2614 #if defined(THREADZ) || defined(LOCKLESS)
2615 lock_scu ();
2616 #endif
2617 if (up -> mask_assignment [0] == (uint) scu_port_num)
2618 {
2619 up -> exec_intr_mask [0] = imask;
2620 sim_debug (DBG_TRACE, & scu_dev, "SMCM intr mask 0 set to %011o\n",
2621 imask);
2622 }
2623 else if (up -> mask_assignment [1] == (uint) scu_port_num)
2624 {
2625 up -> exec_intr_mask [1] = imask;
2626 sim_debug (DBG_TRACE, & scu_dev, "SMCM intr mask 1 set to %011o\n",
2627 imask);
2628 }
2629
2630 scu [scu_unit_idx].port_enable [0] = (uint) getbits36_1 (rega, 32);
2631 scu [scu_unit_idx].port_enable [1] = (uint) getbits36_1 (rega, 33);
2632 scu [scu_unit_idx].port_enable [2] = (uint) getbits36_1 (rega, 34);
2633 scu [scu_unit_idx].port_enable [3] = (uint) getbits36_1 (rega, 35);
2634 scu [scu_unit_idx].port_enable [4] = (uint) getbits36_1 (regq, 32);
2635 scu [scu_unit_idx].port_enable [5] = (uint) getbits36_1 (regq, 33);
2636 scu [scu_unit_idx].port_enable [6] = (uint) getbits36_1 (regq, 34);
2637 scu [scu_unit_idx].port_enable [7] = (uint) getbits36_1 (regq, 35);
2638
2639 dump_intr_regs ("smcm", scu_unit_idx);
2640 deliver_interrupts (scu_unit_idx);
2641 #if defined(THREADZ) || defined(LOCKLESS)
2642 unlock_scu ();
2643 #endif
2644
2645 return SCPE_OK;
2646 }
![[bottom]](../icons/n_bottom.png){kind=icon}
*/