src/dps8/dps8

/* */
This source file includes following definitions.
Read
Read2
Read8
Read16
ReadPage
Write
Write2
Write1
Write8
Write16
Write32
WritePage
ReadIndirect
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * SPDX-License-Identifier: Multics
   5  * scspell-id: 755f1556-f62e-11ec-8184-80ee73e9b8e7
   6  *
   7  * ---------------------------------------------------------------------------
   8  *
   9  * Copyright (c) 2007-2013 Michael Mondy
  10  * Copyright (c) 2012-2016 Harry Reed
  11  * Copyright (c) 2013-2016 Charles Anthony
  12  * Copyright (c) 2015 Eric Swenson
  13  * Copyright (c) 2017 Michal Tomek
  14  * Copyright (c) 2021-2022 The DPS8M Development Team
  15  *
  16  * All rights reserved.
  17  *
  18  * This software is made available under the terms of the ICU
  19  * License, version 1.8.1 or later.  For more details, see the
  20  * LICENSE.md file at the top-level directory of this distribution.
  21  *
  22  * ---------------------------------------------------------------------------
  23  *
  24  * This source file may contain code comments that adapt, include, and/or
  25  * incorporate Multics program code and/or documentation distributed under
  26  * the Multics License.  In the event of any discrepancy between code
  27  * comments herein and the original Multics materials, the original Multics
  28  * materials should be considered authoritative unless otherwise noted.
  29  * For more details and historical background, see the LICENSE.md file at
  30  * the top-level directory of this distribution.
  31  *
  32  * ---------------------------------------------------------------------------
  33  */
  34 
  35 //-V::536
  36 
  37 #include "dps8.h"
  38 #include "dps8_sys.h"
  39 #include "dps8_faults.h"
  40 #include "dps8_scu.h"
  41 #include "dps8_iom.h"
  42 #include "dps8_cable.h"
  43 #include "dps8_cpu.h"
  44 #include "dps8_append.h"
  45 #include "dps8_iefp.h"
  46 #include "dps8_addrmods.h"
  47 #include "dps8_utils.h"
  48 
  49 #define DBG_CTR cpu.cycleCnt
  50 
  51 // new Read/Write stuff ...
  52 
  53 void Read (word18 address, word36 * result, processor_cycle_type cyctyp)
     /*  */
  54   {
  55     cpu.TPR.CA = cpu.iefpFinalAddress = address;
  56     bool isBAR = get_bar_mode ();
  57 
  58     //if (get_went_appending () ||
  59     if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29))
  60       {
  61         goto B29;
  62       }
  63 
  64     switch (get_addr_mode ())
  65       {
  66         case ABSOLUTE_mode:
  67           {
  68             if (isBAR)
  69               {
  70                 set_apu_status (apuStatus_FABS); // XXX maybe...
  71                 cpu.iefpFinalAddress = get_BAR_address (address);
  72                 fauxDoAppendCycle (cyctyp);
  73 #ifdef LOCKLESS
  74                 if (cyctyp == OPERAND_RMW || cyctyp == APU_DATA_RMW)
  75                   core_read_lock (cpu.iefpFinalAddress, result, __func__);
  76                 else
  77                   core_read (cpu.iefpFinalAddress, result, __func__);
  78 #else
  79                 core_read (cpu.iefpFinalAddress, result, __func__);
  80 #endif
  81                 sim_debug (DBG_FINAL, & cpu_dev,
  82                            "Read (Actual) Read:       bar address=%08o  "
  83                            "readData=%012"PRIo64"\n", address, *result);
  84 #ifdef TESTING
  85                 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read ABS BAR");
  86                 HDBGMRead (cpu.iefpFinalAddress, * result, "Read ABS BAR");
  87 #endif
  88                 return;
  89               }
  90             else
  91               {
  92                 set_apu_status (apuStatus_FABS);
  93                 fauxDoAppendCycle (cyctyp);
  94 #ifdef LOCKLESS
  95                 if (cyctyp == OPERAND_RMW || cyctyp == APU_DATA_RMW)
  96                   core_read_lock (address, result, __func__);
  97                 else
  98                   core_read (address, result, __func__);
  99 #else
 100                 core_read (address, result, __func__);
 101 #endif
 102                 sim_debug (DBG_FINAL, & cpu_dev,
 103                            "Read (Actual) Read:       abs address=%08o  "
 104                            "readData=%012"PRIo64"\n", address, *result);
 105 #ifdef TESTING
 106                 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read ABS");
 107                 HDBGMRead (address, * result, "Read ABS");
 108 #endif
 109                 return;
 110               }
 111           }
 112 
 113         case APPEND_mode:
 114           {
 115 B29:;
 116             if (isBAR)
 117               {
 118                 cpu.TPR.CA = get_BAR_address (address);
 119                 cpu.TPR.TSR = cpu.PPR.PSR;
 120                 cpu.TPR.TRR = cpu.PPR.PRR;
 121                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, result, 1);
 122                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 123                            "Read (Actual) Read:  bar iefpFinalAddress=%08o  "
 124                            "readData=%012"PRIo64"\n",
 125                            cpu.iefpFinalAddress, * result);
 126 #ifdef TESTING
 127                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read BAR");
 128                 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read BAR");
 129 #endif
 130 
 131                 return;
 132               }
 133             else
 134               {
 135                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, result, 1);
 136                 // XXX Don't trace Multics idle loop
 137                 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
 138                   {
 139                     sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 140                                "Read (Actual) Read:  iefpFinalAddress=%08o  "
 141                                "readData=%012"PRIo64"\n",
 142                                cpu.iefpFinalAddress, * result);
 143 #ifdef TESTING
 144                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read");
 145                     HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read");
 146 #endif
 147                   }
 148               }
 149             return;
 150           }
 151       }
 152     return ;//SCPE_UNK;
 153   }
 154 
 155 void Read2 (word18 address, word36 * result, processor_cycle_type cyctyp)
     /*  */
 156   {
 157     cpu.TPR.CA = cpu.iefpFinalAddress = address;
 158 
 159     bool isBAR = get_bar_mode ();
 160 
 161     //if (get_went_appending () ||
 162     if (cpu.cu.XSF || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29) ||
 163         cyctyp == RTCD_OPERAND_FETCH) // ISOLTS-886
 164            // Another option would be to set_went_appending in ReadRTCDOp
 165       {
 166         goto B29;
 167       }
 168 
 169     switch (get_addr_mode ())
 170       {
 171         case ABSOLUTE_mode:
 172           {
 173             if (isBAR)
 174               {
 175                 set_apu_status (apuStatus_FABS); // XXX maybe...
 176                 cpu.iefpFinalAddress = get_BAR_address (address);
 177 
 178                 fauxDoAppendCycle (cyctyp);
 179                 core_read2 (cpu.iefpFinalAddress, result + 0, result + 1,
 180                             __func__);
 181                 if_sim_debug (DBG_FINAL, & cpu_dev)
 182                   {
 183                     for (uint i = 0; i < 2; i ++)
 184                       sim_debug (DBG_FINAL, & cpu_dev,
 185                                   "Read2 (Actual) Read:       bar address=%08o"
 186                                   "  readData=%012"PRIo64"\n",
 187                                   address + i, result [i]);
 188                   }
 189 #ifdef TESTING
 190                 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read2 ABBR");
 191                 HDBGMRead (cpu.iefpFinalAddress, * result, "Read2 ABBR evn");
 192                 HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2 ABBR odd");
 193 #endif
 194                 return;
 195               }
 196             else
 197               {
 198                 set_apu_status (apuStatus_FABS);
 199                 fauxDoAppendCycle (cyctyp);
 200                 core_read2 (address, result + 0, result + 1, __func__);
 201                 if_sim_debug (DBG_FINAL, & cpu_dev)
 202                   {
 203                     for (uint i = 0; i < 2; i ++)
 204                       sim_debug (DBG_FINAL, & cpu_dev,
 205                                  "Read2 (Actual) Read:       abs address=%08o"
 206                                  "  readData=%012"PRIo64"\n",
 207                                  address + i, result [i]);
 208                   }
 209 #ifdef TESTING
 210                 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read2 AB");
 211                 HDBGMRead (cpu.iefpFinalAddress, * result, "Read2 AB evn");
 212                 HDBGMRead (cpu.iefpFinalAddress+1, * (result+1), "Read2 AB odd");
 213 #endif
 214                 return;
 215               }
 216           }
 217 
 218         case APPEND_mode:
 219           {
 220 B29:;
 221             if (isBAR)
 222               {
 223                 cpu.TPR.CA = get_BAR_address (address);
 224                 cpu.TPR.TSR = cpu.PPR.PSR;
 225                 cpu.TPR.TRR = cpu.PPR.PRR;
 226                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, result, 2);
 227                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
 228                   {
 229                     for (uint i = 0; i < 2; i ++)
 230                      sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 231                                 "Read2 (Actual) Read:  bar iefpFinalAddress="
 232                                 "%08o  readData=%012"PRIo64"\n",
 233                                 cpu.iefpFinalAddress + i, result [i]);
 234                   }
 235 #ifdef TESTING
 236                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read2 BR");
 237                 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 BR evn");
 238                 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 BR odd");
 239 #endif
 240                 return;
 241               }
 242             else
 243               {
 244                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, result, 2);
 245                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
 246                   {
 247                     for (uint i = 0; i < 2; i ++)
 248                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 249                                  "Read2 (Actual) Read:  iefpFinalAddress=%08o"
 250                                  "  readData=%012"PRIo64"\n",
 251                                  cpu.iefpFinalAddress + i, result [i]);
 252                   }
 253                 if_sim_debug (DBG_FINAL, & cpu_dev)
 254                   {
 255                     if (cyctyp == OPERAND_READ)
 256                       {
 257                         for (uint i = 0; i < 2; i ++)
 258                           sim_debug (DBG_FINAL, & cpu_dev,
 259                                      "Read2 (Actual) Read:  iefpFinalAddress=%08o"
 260                                      "  readData=%012"PRIo64"\n",
 261                                      cpu.iefpFinalAddress + i, result [i]);
 262                       }
 263                   }
 264 #ifdef TESTING
 265                 HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read2");
 266                 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, * result, "Read2 evn");
 267                 HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, * (result+1), "Read2 odd");
 268 #endif
 269               }
 270             return;
 271           }
 272       }
 273     return ;//SCPE_UNK;
 274   }
 275 
 276 void Read8 (word18 address, word36 * result, bool isAR)
     /*  */
 277   {
 278     cpu.TPR.CA = cpu.iefpFinalAddress = address;
 279 
 280     bool isBAR = get_bar_mode ();
 281 
 282     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
 283       {
 284         goto B29;
 285       }
 286 
 287     switch (get_addr_mode ())
 288       {
 289         case ABSOLUTE_mode:
 290           {
 291             if (isBAR)
 292               {
 293                 set_apu_status (apuStatus_FABS); // XXX maybe...
 294                 cpu.iefpFinalAddress = get_BAR_address (address);
 295 
 296                 fauxDoAppendCycle (APU_DATA_READ);
 297                 core_readN (cpu.iefpFinalAddress, result, 8, __func__);
 298                 if_sim_debug (DBG_FINAL, & cpu_dev)
 299                   {
 300                     for (uint i = 0; i < 8; i ++)
 301                       sim_debug (DBG_FINAL, & cpu_dev,
 302                                  "Read8 (Actual) Read:       bar address=%08o"
 303                                  "  readData=%012"PRIo64"\n",
 304                                  address + i, result [i]);
 305                   }
 306 #ifdef TESTING
 307                 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "Read8 ABBR");
 308                 for (uint i = 0; i < 8; i ++)
 309                   HDBGMRead (cpu.iefpFinalAddress + i, result [i], "Read8 ABBR");
 310 #endif
 311                 return;
 312               }
 313             else
 314               {
 315                 set_apu_status (apuStatus_FABS);
 316                 fauxDoAppendCycle (APU_DATA_READ);
 317                 core_readN (address, result, 8, __func__);
 318                 if_sim_debug (DBG_FINAL, & cpu_dev)
 319                   {
 320                     for (uint i = 0; i < 8; i ++)
 321                       sim_debug (DBG_FINAL, & cpu_dev,
 322                                  "Read8 (Actual) Read:       abs address=%08o"
 323                                  "  readData=%012"PRIo64"\n",
 324                                  address + i, result [i]);
 325                   }
 326 #ifdef TESTING
 327                 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "Read8 ABS");
 328                 for (uint i = 0; i < 8; i ++)
 329                   HDBGMRead (address + i, result [i], "Read8 ABS");
 330 #endif
 331                 return;
 332               }
 333           }
 334 
 335         case APPEND_mode:
 336           {
 337 B29:;
 338             if (isBAR)
 339               {
 340                 cpu.TPR.CA = get_BAR_address (address);
 341                 cpu.TPR.TSR = cpu.PPR.PSR;
 342                 cpu.TPR.TRR = cpu.PPR.PRR;
 343                 cpu.iefpFinalAddress = do_append_cycle (APU_DATA_READ, result,
 344                                                         8);
 345                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
 346                   {
 347                     for (uint i = 0; i < 8; i ++)
 348                      sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 349                                 "Read8 (Actual) Read:  bar iefpFinalAddress="
 350                                 "%08o  readData=%012"PRIo64"\n",
 351                                 cpu.iefpFinalAddress + i, result [i]);
 352                   }
 353 #ifdef TESTING
 354                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "Read8 BAR");
 355                 for (uint i = 0; i < 8; i ++)
 356                   HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result[i], "Read8 BAR");
 357 #endif
 358                 return;
 359               }
 360             else
 361               {
 362                 cpu.iefpFinalAddress = do_append_cycle (APU_DATA_READ, result,
 363                                                         8);
 364                 // XXX Don't trace Multics idle loop
 365                 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
 366                   {
 367                     if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
 368                       {
 369                         for (uint i = 0; i < 8; i ++)
 370                           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 371                                      "Read8 (Actual) Read:  iefpFinalAddress="
 372                                      "%08o  readData=%012"PRIo64"\n",
 373                                      cpu.iefpFinalAddress + i, result [i]);
 374                       }
 375 #ifdef TESTING
 376                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "Read8");
 377                     for (uint i = 0; i < 8; i ++)
 378                       HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "Read8");
 379 #endif
 380                   }
 381               }
 382             return;
 383           }
 384       }
 385     return ;//SCPE_UNK;
 386   }
 387 
 388 void Read16 (word18 address, word36 * result)
     /*  */
 389   {
 390     address &= paragraphMask; // Round to 8 word boundary
 391     Read8 (address, result, cpu.currentInstruction.b29);
 392     Read8 (address + 8, result + 8, cpu.currentInstruction.b29);
 393     return;
 394   }
 395 
 396 void ReadPage (word18 address, word36 * result, bool isAR)
     /*  */
 397   {
 398     if ((address & PGMK) != 0)
 399       {
 400         sim_warn ("ReadPage not on boundary %06o\n", address);
 401       }
 402     address &= (word18) ~PGMK; // Round to page boundary
 403     cpu.TPR.CA = cpu.iefpFinalAddress = address;
 404 
 405     bool isBAR = get_bar_mode ();
 406 
 407     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
 408       {
 409         goto B29;
 410       }
 411 
 412     switch (get_addr_mode ())
 413       {
 414         case ABSOLUTE_mode:
 415           {
 416             if (isBAR)
 417               {
 418                 set_apu_status (apuStatus_FABS); // XXX maybe...
 419                 cpu.iefpFinalAddress = get_BAR_address (address);
 420 
 421                 fauxDoAppendCycle (APU_DATA_READ);
 422                 core_readN (cpu.iefpFinalAddress, result, PGSZ, __func__);
 423                 if_sim_debug (DBG_FINAL, & cpu_dev)
 424                   {
 425                     for (uint i = 0; i < PGSZ; i ++)
 426                       sim_debug (DBG_FINAL, & cpu_dev,
 427                                  "ReadPage (Actual) Read:       bar address="
 428                                  "%08o  readData=%012"PRIo64"\n",
 429                                   address + i, result [i]);
 430                   }
 431 #ifdef TESTING
 432                 HDBGIEFP (hdbgIEFP_abs_bar_read, 0, address, "ReadPage AB");
 433                 for (uint i = 0; i < PGSZ; i ++)
 434                   HDBGMRead (cpu.iefpFinalAddress + i, result [i], "ReadPage AB");
 435 #endif
 436                 return;
 437               }
 438             else
 439               {
 440                 set_apu_status (apuStatus_FABS);
 441                 fauxDoAppendCycle (APU_DATA_READ);
 442                 core_readN (address, result, PGSZ, __func__);
 443                 if_sim_debug (DBG_FINAL, & cpu_dev)
 444                   {
 445                     for (uint i = 0; i < PGSZ; i ++)
 446                       sim_debug (DBG_FINAL, & cpu_dev,
 447                                  "ReadPage (Actual) Read:       abs address="
 448                                  "%08o  readData=%012"PRIo64"\n",
 449                                  address + i, result [i]);
 450                   }
 451 #ifdef TESTING
 452                 HDBGIEFP (hdbgIEFP_abs_read, 0, address, "ReadPage ABS");
 453                 for (uint i = 0; i < PGSZ; i ++)
 454                   HDBGMRead (address + i, result [i], "ReadPage ABS");
 455 #endif
 456                 return;
 457               }
 458           }
 459 
 460         case APPEND_mode:
 461           {
 462 B29:;
 463             if (isBAR)
 464               {
 465                 cpu.TPR.CA = get_BAR_address (address);
 466                 cpu.TPR.TSR = cpu.PPR.PSR;
 467                 cpu.TPR.TRR = cpu.PPR.PRR;
 468                 cpu.iefpFinalAddress = do_append_cycle (APU_DATA_READ, result,
 469                                                         PGSZ);
 470                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
 471                   {
 472                     for (uint i = 0; i < PGSZ; i ++)
 473                      sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 474                                 "ReadPage (Actual) Read:  bar iefpFinalAddress="
 475                                 "%08o  readData=%012"PRIo64"\n",
 476                                 cpu.iefpFinalAddress + i, result [i]);
 477                   }
 478 #ifdef TESTING
 479                 HDBGIEFP (hdbgIEFP_bar_read, cpu.TPR.TSR, address, "ReadPage B");
 480                 for (uint i = 0; i < PGSZ; i ++)
 481                   HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage B");
 482 #endif
 483 
 484                 return;
 485               }
 486             else
 487               {
 488                 cpu.iefpFinalAddress = do_append_cycle (APU_DATA_READ, result,
 489                                                         PGSZ);
 490                 // XXX Don't trace Multics idle loop
 491                 if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307)
 492                   {
 493                     if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
 494                       {
 495                         for (uint i = 0; i < PGSZ; i ++)
 496                           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 497                                      "ReadPage (Actual) Read:  iefpFinalAddress"
 498                                      "=%08o  readData=%012"PRIo64"\n",
 499                                      cpu.iefpFinalAddress + i, result [i]);
 500                       }
 501 #ifdef TESTING
 502                     HDBGIEFP (hdbgIEFP_read, cpu.TPR.TSR, address, "ReadPage");
 503                     for (uint i = 0; i < PGSZ; i ++)
 504                       HDBGAPURead (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, result [i], "ReadPage");
 505 #endif
 506                   }
 507               }
 508             return;
 509           }
 510       }
 511     return ;//SCPE_UNK;
 512   }
 513 
 514 void Write (word18 address, word36 data, processor_cycle_type cyctyp)
     /*  */
 515  {
 516     cpu.TPR.CA = cpu.iefpFinalAddress = address;
 517 
 518     bool isBAR = get_bar_mode ();
 519 
 520     if (cpu.cu.XSF /*get_went_appending ()*/ || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29))
 521         goto B29;
 522 
 523     switch (get_addr_mode ())
 524       {
 525         case ABSOLUTE_mode:
 526           {
 527             if (isBAR)
 528               {
 529                 cpu.iefpFinalAddress = get_BAR_address (address);
 530                 set_apu_status (apuStatus_FABS); // XXX maybe...
 531                 fauxDoAppendCycle (cyctyp);
 532                 if (cyctyp == OPERAND_STORE && cpu.useZone)
 533                   {
 534                     core_write_zone (cpu.iefpFinalAddress, data, __func__);
 535                   }
 536                 else
 537                   {
 538                     core_write (cpu.iefpFinalAddress, data, __func__);
 539                   }
 540                 sim_debug (DBG_FINAL, & cpu_dev,
 541                            "Write(Actual) Write:      bar address=%08o "
 542                            "writeData=%012"PRIo64"\n", address, data);
 543 #ifdef TESTING
 544                 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write ABBR");
 545                 HDBGMWrite (cpu.iefpFinalAddress, data, "Write ABBR");
 546 #endif
 547                 return;
 548               }
 549             else
 550               {
 551                 set_apu_status (apuStatus_FABS);
 552                 fauxDoAppendCycle (cyctyp);
 553                 if (cyctyp == OPERAND_STORE && cpu.useZone)
 554                   {
 555                     core_write_zone (address, data, __func__);
 556                   }
 557                 else
 558                   {
 559                     core_write (address, data, __func__);
 560                   }
 561                 sim_debug (DBG_FINAL, & cpu_dev,
 562                            "Write(Actual) Write:      abs address=%08o "
 563                            "writeData=%012"PRIo64"\n",
 564                            address, data);
 565 #ifdef TESTING
 566                 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write AB");
 567                 HDBGMWrite (address, data, "Write AB");
 568 #endif
 569                 return;
 570               }
 571           }
 572 
 573         case APPEND_mode:
 574           {
 575 B29:
 576             if (isBAR)
 577               {
 578                 cpu.TPR.CA = get_BAR_address (address);
 579                 cpu.TPR.TSR = cpu.PPR.PSR;
 580                 cpu.TPR.TRR = cpu.PPR.PRR;
 581                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, & data, 1);
 582                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 583                            "Write(Actual) Write: bar iefpFinalAddress=%08o "
 584                            "writeData=%012"PRIo64"\n",
 585                            cpu.iefpFinalAddress, data);
 586 #ifdef TESTING
 587                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write BR");
 588                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write BR");
 589 #endif
 590                 return;
 591               }
 592             else
 593               {
 594                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, & data, 1);
 595                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 596                            "Write(Actual) Write: iefpFinalAddress=%08o "
 597                            "writeData=%012"PRIo64"\n",
 598                            cpu.iefpFinalAddress, data);
 599 #ifdef TESTING
 600                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write");
 601                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write");
 602 #endif
 603                 return;
 604               }
 605           }
 606       }
 607 
 608     return ;//SCPE_UNK;
 609   }
 610 
 611 void Write2 (word18 address, word36 * data, processor_cycle_type cyctyp)
     /*  */
 612   {
 613     cpu.TPR.CA = cpu.iefpFinalAddress = address;
 614     bool isBAR = get_bar_mode ();
 615 
 616     if (cpu.cu.XSF /*get_went_appending ()*/ || (cyctyp != INSTRUCTION_FETCH && cpu.currentInstruction.b29))
 617       goto B29;
 618 
 619     switch (get_addr_mode ())
 620       {
 621         case ABSOLUTE_mode:
 622           {
 623             if (isBAR)
 624               {
 625                 cpu.iefpFinalAddress = get_BAR_address (address);
 626                 set_apu_status (apuStatus_FABS); // XXX maybe...
 627                 fauxDoAppendCycle (cyctyp);
 628                 core_write2 (cpu.iefpFinalAddress, data [0], data [1],
 629                               __func__);
 630 #ifdef TESTING
 631                 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write2 ABBR");
 632                 HDBGMWrite (cpu.iefpFinalAddress, data [0], "Write2 ABBR evn");
 633                 HDBGMWrite (cpu.iefpFinalAddress+1, data [1], "Write2 ABBR odd");
 634 #endif
 635                 sim_debug (DBG_FINAL, & cpu_dev,
 636                            "Write2 (Actual) Write:      bar address=%08o "
 637                            "writeData=%012"PRIo64" %012"PRIo64"\n",
 638                            address, data [0], data [1]);
 639               }
 640             else
 641               {
 642                 set_apu_status (apuStatus_FABS);
 643                 fauxDoAppendCycle (cyctyp);
 644                 core_write2 (address, data [0], data [1], __func__);
 645                 sim_debug (DBG_FINAL, & cpu_dev,
 646                            "Write2 (Actual) Write:      abs address=%08o "
 647                            "writeData=%012"PRIo64" %012"PRIo64"\n",
 648                            address, data [0], data [1]);
 649 #ifdef TESTING
 650                 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write2 AB");
 651                 HDBGMWrite (address, data [0], "Write2 AB evn");
 652                 HDBGMWrite (address+1, data [1], "Write2 AB odd");
 653 #endif
 654               }
 655           }
 656           break;
 657 
 658         case APPEND_mode:
 659           {
 660 B29:
 661             if (isBAR)
 662               {
 663                 cpu.TPR.CA = get_BAR_address (address);
 664                 cpu.TPR.TSR = cpu.PPR.PSR;
 665                 cpu.TPR.TRR = cpu.PPR.PRR;
 666                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, data, 2);
 667                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 668                            "Write2 (Actual) Write: bar iefpFinalAddress=%08o "
 669                            "writeData=%012"PRIo64" %012"PRIo64"\n",
 670                            address, data [0], data [1]);
 671 #ifdef TESTING
 672                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write2 BR");
 673                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 BR evn");
 674                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 BR odd");
 675 #endif
 676               }
 677             else
 678               {
 679                 cpu.iefpFinalAddress = do_append_cycle (cyctyp, data, 2);
 680                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 681                            "Write2 (Actual) Write: iefpFinalAddress=%08o "
 682                            "writeData=%012"PRIo64" %012"PRIo64"\n",
 683                            address, data [0], data [1]);
 684 #ifdef TESTING
 685                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write2");
 686                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data[0], "Write2 evn");
 687                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + 1, cpu.iefpFinalAddress + 1, data[1], "Write2 odd");
 688 #endif
 689               }
 690           }
 691           break;
 692       }
 693     return ;//SCPE_UNK;
 694   }
 695 
 696 void Write1 (word18 address, word36 data, bool isAR)
     /*  */
 697   {
 698     cpu.TPR.CA = cpu.iefpFinalAddress = address;
 699     bool isBAR = get_bar_mode ();
 700     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
 701       goto B29;
 702     switch (get_addr_mode ())
 703       {
 704         case ABSOLUTE_mode:
 705           {
 706             if (isBAR)
 707              {
 708                 cpu.iefpFinalAddress = get_BAR_address (address);
 709                 set_apu_status (apuStatus_FABS); // XXX maybe...
 710                 fauxDoAppendCycle (APU_DATA_STORE);
 711                 core_write (cpu.iefpFinalAddress, data, __func__);
 712                 sim_debug (DBG_FINAL, & cpu_dev,
 713                            "Write1(Actual) Write:      bar address=%08o "
 714                            "writeData=%012"PRIo64"\n",
 715                            address, data);
 716 #ifdef TESTING
 717                 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write1 ABBR");
 718                 HDBGMWrite (cpu.iefpFinalAddress, data, "Write1 ABBR");
 719 #endif
 720                 return;
 721               }
 722             else
 723               {
 724                 set_apu_status (apuStatus_FABS);
 725                 fauxDoAppendCycle (APU_DATA_STORE);
 726                 core_write (address, data, __func__);
 727                 sim_debug (DBG_FINAL, & cpu_dev,
 728                            "Write1(Actual) Write:      abs address=%08o "
 729                            "writeData=%012"PRIo64"\n",
 730                            address, data);
 731 #ifdef TESTING
 732                 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write1 AB");
 733                 HDBGMWrite (address, data, "Write1 AB");
 734 #endif
 735                 return;
 736               }
 737           }
 738 
 739         case APPEND_mode:
 740           {
 741 B29:
 742             if (isBAR)
 743               {
 744                 cpu.TPR.CA = get_BAR_address (address);
 745                 cpu.TPR.TSR = cpu.PPR.PSR;
 746                 cpu.TPR.TRR = cpu.PPR.PRR;
 747                 cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, & data,
 748                                                         1);
 749                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 750                            "Write8(Actual) Write: bar iefpFinalAddress="
 751                            "%08o writeData=%012"PRIo64"\n",
 752                            cpu.iefpFinalAddress, data);
 753 #ifdef TESTING
 754                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write1 BR");
 755                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1 BR");
 756 #endif
 757                 return;
 758               }
 759             else
 760               {
 761                 cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, & data,
 762                                                        1);
 763                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 764                            "Write(Actual) Write: iefpFinalAddress=%08o "
 765                            "writeData=%012"PRIo64"\n",
 766                            cpu.iefpFinalAddress, data);
 767 #ifdef TESTING
 768                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write1");
 769                 HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA, cpu.iefpFinalAddress, data, "Write1");
 770 #endif
 771                 return;
 772               }
 773           }
 774       }
 775     return ;//SCPE_UNK;
 776   }
 777 
 778 void Write8 (word18 address, word36 * data, bool isAR)
     /*  */
 779   {
 780     address &= paragraphMask; // Round to 8 word boundarryt
 781     cpu.TPR.CA = cpu.iefpFinalAddress = address;
 782 
 783     bool isBAR = get_bar_mode ();
 784 
 785     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
 786       goto B29;
 787 
 788     switch (get_addr_mode ())
 789      {
 790         case ABSOLUTE_mode:
 791           {
 792             if (isBAR)
 793              {
 794                 cpu.iefpFinalAddress = get_BAR_address (address);
 795                 set_apu_status (apuStatus_FABS); // XXX maybe...
 796                 fauxDoAppendCycle (APU_DATA_STORE);
 797                 core_writeN (cpu.iefpFinalAddress, data, 8, __func__);
 798                 if_sim_debug (DBG_FINAL, & cpu_dev)
 799                   {
 800                     for (uint i = 0; i < 8; i ++)
 801                       sim_debug (DBG_FINAL, & cpu_dev,
 802                                  "Write8(Actual) Write:      bar address=%08o "
 803                                  "writeData=%012"PRIo64"\n",
 804                                  address + i, data [i]);
 805                   }
 806 #ifdef TESTING
 807                 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "Write8 ABBR");
 808                 for (uint i = 0; i < 8; i ++)
 809                   HDBGMWrite (cpu.iefpFinalAddress + i, data [i], "Write8 ABBR");
 810 #endif
 811                 return;
 812               }
 813             else
 814               {
 815                 set_apu_status (apuStatus_FABS);
 816                 fauxDoAppendCycle (APU_DATA_STORE);
 817                 core_writeN (address, data, 8, __func__);
 818                 if_sim_debug (DBG_FINAL, & cpu_dev)
 819                   {
 820                     for (uint i = 0; i < 8; i ++)
 821                       sim_debug (DBG_FINAL, & cpu_dev,
 822                                  "Write8(Actual) Write:      abs address=%08o "
 823                                  "writeData=%012"PRIo64"\n",
 824                                   address + i, data [i]);
 825                   }
 826 #ifdef TESTING
 827                 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "Write8 AB");
 828                 for (uint i = 0; i < 8; i ++)
 829                   HDBGMWrite (address + i, data [i], "Write8 AB");
 830 #endif
 831                 return;
 832               }
 833           }
 834 
 835         case APPEND_mode:
 836           {
 837 B29:
 838             if (isBAR)
 839               {
 840                 cpu.TPR.CA = get_BAR_address (address);
 841                 cpu.TPR.TSR = cpu.PPR.PSR;
 842                 cpu.TPR.TRR = cpu.PPR.PRR;
 843                 cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, data,
 844                                                         8);
 845                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
 846                   {
 847                     for (uint i = 0; i < 8; i ++)
 848                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 849                                  "Write8(Actual) Write: bar iefpFinalAddress="
 850                                  "%08o writeData=%012"PRIo64"\n",
 851                                  cpu.iefpFinalAddress + i, data [i]);
 852                   }
 853 #ifdef TESTING
 854                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "Write8 BR");
 855                 for (uint i = 0; i < 8; i ++)
 856                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8 BR");
 857 #endif
 858 
 859                 return;
 860               }
 861             else
 862               {
 863                 cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, data,
 864                                                         8);
 865                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
 866                   {
 867                     for (uint i = 0; i < 8; i ++)
 868                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 869                                  "Write8(Actual) Write: iefpFinalAddress=%08o "
 870                                  "writeData=%012"PRIo64"\n",
 871                                  cpu.iefpFinalAddress + i, data [i]);
 872                   }
 873 #ifdef TESTING
 874                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "Write8");
 875                 for (uint i = 0; i < 8; i ++)
 876                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "Write8");
 877 #endif
 878 
 879                 return;
 880               }
 881           }
 882       }
 883     return ;//SCPE_UNK;
 884   }
 885 
 886 void Write16 (word18 address, word36 * data)
     /*  */
 887   {
 888     address &= paragraphMask; // Round to 8 word boundary
 889     Write8 (address, data, cpu.currentInstruction.b29);
 890     Write8 (address + 8, data + 8, cpu.currentInstruction.b29);
 891     return;
 892   }
 893 
 894 void Write32 (word18 address, word36 * data)
     /*  */
 895   {
 896 //#define paragraphMask 077777770
 897     //address &= paragraphMask; // Round to 8 word boundary
 898     address &= 077777740; // Round to 32 word boundary
 899     Write8 (address, data, cpu.currentInstruction.b29);
 900     Write8 (address + 8, data + 8, cpu.currentInstruction.b29);
 901     Write8 (address + 16, data + 16, cpu.currentInstruction.b29);
 902     Write8 (address + 24, data + 24, cpu.currentInstruction.b29);
 903     return;
 904   }
 905 
 906 void WritePage (word18 address, word36 * data, bool isAR)
     /*  */
 907   {
 908     if ((address & PGMK) != 0)
 909       {
 910         sim_warn ("WritePage not on boundary %06o\n", address);
 911       }
 912     address &= (word18) ~PGMK; // Round to page boundary
 913     cpu.TPR.CA = cpu.iefpFinalAddress = address;
 914 
 915     bool isBAR = get_bar_mode ();
 916 
 917     if (isAR || cpu.cu.XSF /*get_went_appending ()*/)
 918       goto B29;
 919 
 920     switch (get_addr_mode ())
 921      {
 922         case ABSOLUTE_mode:
 923           {
 924             if (isBAR)
 925              {
 926                 cpu.iefpFinalAddress = get_BAR_address (address);
 927                 set_apu_status (apuStatus_FABS); // XXX maybe...
 928                 fauxDoAppendCycle (APU_DATA_STORE);
 929                 core_writeN (cpu.iefpFinalAddress, data, PGSZ, __func__);
 930                 if_sim_debug (DBG_FINAL, & cpu_dev)
 931                   {
 932                     for (uint i = 0; i < PGSZ; i ++)
 933                       sim_debug (DBG_FINAL, & cpu_dev,
 934                                  "WritePage(Actual) Write:      bar address="
 935                                  "%08o writeData=%012"PRIo64"\n",
 936                                  address + i, data [i]);
 937                   }
 938 #ifdef TESTING
 939                 HDBGIEFP (hdbgIEFP_abs_bar_write, 0, address, "WritePage ABBR");
 940                 for (uint i = 0; i < PGSZ; i ++)
 941                   HDBGMWrite (cpu.iefpFinalAddress + i, data [i], "WritePage ABBR");
 942 #endif
 943                 return;
 944               }
 945             else
 946               {
 947                 set_apu_status (apuStatus_FABS);
 948                 fauxDoAppendCycle (APU_DATA_STORE);
 949                 core_writeN (address, data, PGSZ, __func__);
 950                 if_sim_debug (DBG_FINAL, & cpu_dev)
 951                   {
 952                     for (uint i = 0; i < PGSZ; i ++)
 953                       sim_debug (DBG_FINAL, & cpu_dev,
 954                                  "WritePage(Actual) Write:      abs address="
 955                                  "%08o writeData=%012"PRIo64"\n",
 956                                  address + i, data [i]);
 957                   }
 958 #ifdef TESTING
 959                 HDBGIEFP (hdbgIEFP_abs_write, 0, address, "WritePage AB");
 960                 for (uint i = 0; i < PGSZ; i ++)
 961                   HDBGMWrite (address + i, data [i], "WritePage AB");
 962 #endif
 963                 return;
 964               }
 965           }
 966 
 967         case APPEND_mode:
 968           {
 969 B29:
 970             if (isBAR)
 971               {
 972                 cpu.TPR.CA = get_BAR_address (address);
 973                 cpu.TPR.TSR = cpu.PPR.PSR;
 974                 cpu.TPR.TRR = cpu.PPR.PRR;
 975                 cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, data,
 976                                                         PGSZ);
 977                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
 978                   {
 979                     for (uint i = 0; i < PGSZ; i ++)
 980                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
 981                                  "WritePage(Actual) Write: bar "
 982                                  "iefpFinalAddress=%08o writeData=%012"PRIo64
 983                                  "\n",
 984                                  cpu.iefpFinalAddress + i, data [i]);
 985                   }
 986 #ifdef TESTING
 987                 HDBGIEFP (hdbgIEFP_bar_write, cpu.TPR.TSR, address, "WritePage BR");
 988                 for (uint i = 0; i < PGSZ; i ++)
 989                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage BR");
 990 #endif
 991                 return;
 992               }
 993             else
 994               {
 995                 cpu.iefpFinalAddress = do_append_cycle (APU_DATA_STORE, data,
 996                                                         PGSZ);
 997                 if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev)
 998                   {
 999                     for (uint i = 0; i < PGSZ; i ++)
1000                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
1001                                  "WritePage(Actual) Write: iefpFinalAddress="
1002                                  "%08o writeData=%012"PRIo64"\n",
1003                                  cpu.iefpFinalAddress + i, data [i]);
1004                   }
1005 #ifdef TESTING
1006                 HDBGIEFP (hdbgIEFP_write, cpu.TPR.TSR, address, "WritePage");
1007                 for (uint i = 0; i < PGSZ; i ++)
1008                   HDBGAPUWrite (cpu.TPR.TSR, cpu.TPR.CA + i, cpu.iefpFinalAddress + i, data [i], "WritePage");
1009 #endif
1010 
1011                 return;
1012               }
1013           }
1014       }
1015     return ;//SCPE_UNK;
1016   }
1017 
1018 void ReadIndirect (void)
     /*  */
1019   {
1020     if (cpu.TPR.CA & 1) // is odd?
1021       {
1022         Read (cpu.TPR.CA, cpu.itxPair, INDIRECT_WORD_FETCH);
1023         cpu.itxPair[1] = MASK36; // fill with ones for debugging
1024       }
1025     else
1026       {
1027         Read2 (cpu.TPR.CA, cpu.itxPair, INDIRECT_WORD_FETCH);
1028       }
1029     return;
1030   }
/* */
root/src/dps8/dps8_iefp.c

DEFINITIONS
