src/dps8/dps8

/* */
   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: e959445f-f62e-11ec-b5eb-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2007-2013 Michael Mondy
   9  * Copyright (c) 2012-2016 Harry Reed
  10  * Copyright (c) 2013-2016 Charles Anthony
  11  * Copyright (c) 2021-2022 The DPS8M Development Team
  12  *
  13  * All rights reserved.
  14  *
  15  * This software is made available under the terms of the ICU
  16  * License, version 1.8.1 or later.  For more details, see the
  17  * LICENSE.md file at the top-level directory of this distribution.
  18  *
  19  * ---------------------------------------------------------------------------
  20  */
  21 
  22 extern DEVICE scu_dev;
  23 
  24 #ifdef SPEED
  25 # define if_sim_debug(dbits, dptr) if ((0))
  26 #else
  27 # define if_sim_debug(dbits, dptr) \
  28   if ( \
  29       sim_deb && \
  30       (((dptr)->dctrl & (dbits)) || (dbits) == 0) && \
  31       ((dptr != & cpu_dev) || ((1 << current_running_cpu_idx) & dbgCPUMask)) && \
  32       ((dptr != & cpu_dev) || (((dptr)->dctrl & (DBG_INTR | DBG_FAULT))) || (! sim_deb_segno_on) || sim_deb_segno[cpu.PPR.PSR & (DEBUG_SEGNO_LIMIT - 1)]) && \
  33       ((dptr != & cpu_dev) || sim_deb_ringno == NO_SUCH_RINGNO || sim_deb_ringno == cpu . PPR. PRR) && \
  34       ((dptr != & cpu_dev) || (! sim_deb_bar) || (! TST_I_NBAR)) && \
  35       cpu.cycleCnt >= sim_deb_start && \
  36       (sim_deb_stop == 0 || cpu.cycleCnt < sim_deb_stop) && \
  37       (sim_deb_mme_cntdwn == 0) && \
  38       ((dptr != & cpu_dev) | (((dbits) & DBG_TRACE) ? (sim_deb_skip_cnt ++ >= sim_deb_skip_limit) : (sim_deb_skip_cnt >= sim_deb_skip_limit))) \
  39     )
  40 #endif
  41 
  42 #if !defined(THREADZ) && !defined(LOCKLESS)
  43 # define dps8_sim_debug _sim_debug
  44 #endif
  45 
  46 #undef sim_debug
  47 #if defined(THREADZ) || defined(LOCKLESS)
  48 # define sim_debug(dbits, dptr, ...) \
  49   if_sim_debug((dbits), dptr) \
  50     dps8_sim_debug ((dbits), dptr, DBG_CTR, __VA_ARGS__); \
  51   else \
  52     (void) 0
  53 #else
  54 # define sim_debug(dbits, dptr, ...) \
  55   if_sim_debug((dbits), dptr) \
  56     dps8_sim_debug ((dbits), dptr, __VA_ARGS__); \
  57   else \
  58     (void) 0
  59 #endif
  60 
  61 /* scp Debug flags */
  62 
  63 #define DBG_TRACE         (1U << 0)      ///< instruction trace
  64 #define DBG_MSG           (1U << 1)      ///< misc output
  65 
  66 #define DBG_REGDUMPAQI    (1U << 2)      ///< A/Q/IR register dump
  67 #define DBG_REGDUMPIDX    (1U << 3)      ///< index register dump
  68 #define DBG_REGDUMPPR     (1U << 4)      ///< pointer registers dump
  69 //#define DBG_REGDUMPADR  (1U << 5)      ///< address registers dump
  70 #define DBG_REGDUMPPPR    (1U << 6)      ///< PPR register dump
  71 #define DBG_REGDUMPDSBR   (1U << 7)      ///< descriptor segment base register dump
  72 #define DBG_REGDUMPFLT    (1U << 8)      ///< C(EAQ) floating-point register dump
  73 
  74 //#define DBG_REGDUMP     (DBG_REGDUMPAQI | DBG_REGDUMPIDX | DBG_REGDUMPPR |
  75 //                         DBG_REGDUMPADR | DBG_REGDUMPPPR | DBG_REGDUMPDSBR | DBG_REGDUMPFLT)
  76 #define DBG_REGDUMP       (DBG_REGDUMPAQI | DBG_REGDUMPIDX | DBG_REGDUMPPR | \
  77                            DBG_REGDUMPPPR | DBG_REGDUMPDSBR | DBG_REGDUMPFLT)
  78 
  79 #define DBG_ADDRMOD       (1U << 9)      ///< follow address modifications
  80 #define DBG_APPENDING     (1U << 10)     ///< follow appending unit operations
  81 #define DBG_TRACEEXT      (1U << 11)     ///< extended instruction trace
  82 #define DBG_WARN          (1U << 12)
  83 #define DBG_DEBUG         (1U << 13)
  84 #define DBG_INFO          (1U << 14)
  85 #define DBG_NOTIFY        (1U << 15)
  86 #define DBG_SIM_USES_16   (1U << 16)
  87 #define DBG_SIM_USES_17   (1U << 17)
  88 #define DBG_SIM_USES_18   (1U << 18)
  89 #define DBG_ERR           (1U << 19)
  90 #define DBG_ALL (DBG_NOTIFY | DBG_INFO | DBG_ERR | DBG_DEBUG | DBG_WARN | \
  91                  DBG_ERR | DBG_TRACE )
  92 #define DBG_FAULT         (1U << 20)     ///< follow fault handling
  93 #define DBG_INTR          (1U << 21)     // follow interrupt handling
  94 #define DBG_CORE          (1U << 22)
  95 #define DBG_CYCLE         (1U << 23)
  96 #define DBG_CAC           (1U << 24)
  97 #define DBG_FINAL         (1U << 25)
  98 #define DBG_AVC           (1U << 26)
  99 
 100 // Abort codes, used to sort out longjmp's back to the main loop.
 101 // Codes > 0 are simulator stop codes
 102 // Codes < 0 are internal aborts
 103 // Code  = 0 stops execution for an interrupt check (XXX Don't know if I like
 104 // this or not)
 105 // XXX above is not entirely correct (anymore).
 106 
 107 //#define SCPE_OK    0
 108 #define STOP_STOP   1
 109 #define STOP_BKPT   2
 110 
 111 // not really STOP codes, but get returned from instruction loops
 112 #define CONT_TRA    -1  // encountered a transfer instruction; don't bump PPR.IC
 113 #define CONT_DIS    -2  // instruction was a DIS
 114 #define CONT_XEC    -3  // instruction was a XEC or XED
 115 #define CONT_RET    -5  // encountered a return instruction; don't bump PPR.IC,
 116                         // do instruction fetch
 117 
 118 //
 119 // mask entry flags
 120 //  MTAB_XTD extended entry
 121 //  MTAB_VDV valid for devices
 122 //  MTAB_VUN valid for units
 123 //  MTAB_VALO takes a value (optional)
 124 //  MTAB_VALR takes a value (required)
 125 //  MTAB_NMO valid only in named SHOW
 126 //  MTAB_NC do not convert option value to upper case
 127 //  MTAB_SHP SHOW parameter takes optional value
 128 
 129 // Requires a value, DEV and DEVn both work, not in "show"
 130 #define MTAB_unit_value      MTAB_XTD | MTAB_VUN | MTAB_VDV | MTAB_NMO | MTAB_VALR
 131 // Requires a value, DEVn, not in "show"
 132 #define MTAB_unitonly_value      MTAB_XTD | MTAB_VUN | MTAB_NMO | MTAB_VALR
 133 // Requires a value, DEV and DEVn both work, in "show"
 134 #define MTAB_unit_value_show MTAB_XTD | MTAB_VUN | MTAB_VDV | MTAB_VALR
 135 // Requires a value, DEV only, not in "show", uppercase value
 136 #define MTAB_dev_valr_noshow MTAB_XTD | MTAB_VDV | MTAB_NMO | MTAB_VALR
 137 // Requires a value, DEV only, not in "show", don't uppercase value
 138 #define MTAB_dev_valr_nouc MTAB_XTD | MTAB_VDV | MTAB_NMO | MTAB_VALR | MTAB_NC
 139 // Requires a value, DEV only, not in "show"
 140 #define MTAB_dev_value     MTAB_XTD | MTAB_VDV | MTAB_NMO | MTAB_VALR
 141 // No value, DEV only, in "show"
 142 #define MTAB_dev_novalue     MTAB_XTD | MTAB_VDV
 143 // Requires a value, DEVn only, in "show", don't uppercase value
 144 #define MTAB_unit_valr_nouc MTAB_XTD | MTAB_VUN | MTAB_VALR | MTAB_NC
 145 // Value optional, DEVn only, do not uppercase value
 146 #define MTAB_unit_nouc MTAB_XTD | MTAB_VUN | MTAB_NC
 147 // Value optional, DEVn only,  uppercase value
 148 #define MTAB_unit_uc MTAB_XTD | MTAB_VUN
 149 // Value required, DEV only
 150 #define MTAB_dev_valr MTAB_XTD | MTAB_VDV | MTAB_VALR
 151 // End of list marker
 152 #define MTAB_eol { 0, 0, NULL, NULL, 0, 0, NULL, NULL }
 153 
 154 extern uint32 sim_brk_summ, sim_brk_types, sim_brk_dflt;
 155 extern FILE *sim_deb;
 156 void sim_printf( const char * format, ... );    // not really simh, by my impl
 157 
 158 #if defined(THREADZ) || defined(LOCKLESS)
 159 void dps8_sim_debug (uint32 dbits, DEVICE* dptr, unsigned long long cnt, const char* fmt, ...);
 160 
 161 #endif
 162 #define sim_msg sim_printf
 163 #define sim_warn sim_printf
 164 #define sim_print sim_printf
/* */
root/src/dps8/dps8_simh.h

INCLUDED FROM
