cpu_dev 80 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 106 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 198 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 242 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 262 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 286 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 318 src/dps8/dps8_addrmods.c sim_debug (DBG_APPENDING, & cpu_dev, "do_ITS_ITP sets XSF to 1\n"); cpu_dev 328 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 337 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 377 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 380 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 416 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 439 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 473 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, "R_MOD: Cr=%06o\n", Cr); cpu_dev 477 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 507 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, "R_MOD: TPR.CA=%06o\n", cpu_dev 516 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, "RI_MOD: Td=%o\n", Td); cpu_dev 529 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 554 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 615 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 633 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 643 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 672 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 677 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 687 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 742 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 749 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 752 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 801 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 840 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 855 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 867 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 963 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 999 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1026 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1040 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1047 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1068 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1084 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1087 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1117 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1147 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1154 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1157 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1185 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1206 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1222 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1225 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1243 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1275 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1290 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1314 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1357 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1375 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1397 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1420 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1469 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1487 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1508 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 1534 src/dps8/dps8_addrmods.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 56 src/dps8/dps8_append.c # define DBGAPP(...) sim_debug (DBG_APPENDING, & cpu_dev, __VA_ARGS__) cpu_dev 1846 src/dps8/dps8_append.c sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n"); cpu_dev 671 src/dps8/dps8_cpu.c sim_msg ("Number of CPUs in system is %d\n", cpu_dev.numunits); cpu_dev 683 src/dps8/dps8_cpu.c cpu_dev.numunits = (uint32) n; cpu_dev 860 src/dps8/dps8_cpu.c sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to %s\n", cpu_dev 1546 src/dps8/dps8_cpu.c sim_debug (DBG_INFO, & cpu_dev, "CPU reset: Running\n"); cpu_dev 1619 src/dps8/dps8_cpu.c DEVICE cpu_dev = cpu_dev 1840 src/dps8/dps8_cpu.c cpu_dev 1873 src/dps8/dps8_cpu.c cpu_dev 2076 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, "set_temporary_absolute_mode bit 29 sets XSF to 0\n"); cpu_dev 2106 src/dps8/dps8_cpu.c set_cpu_idx (cpu_dev.numunits - 1); cpu_dev 2111 src/dps8/dps8_cpu.c for (c = 0; c < cpu_dev.numunits; c ++) cpu_dev 2117 src/dps8/dps8_cpu.c if (c == cpu_dev.numunits) cpu_dev 2122 src/dps8/dps8_cpu.c set_cpu_idx ((current + 1) % cpu_dev.numunits); cpu_dev 2280 src/dps8/dps8_cpu.c sim_debug (DBG_CYCLE, & cpu_dev, "Cycle is %s\n", cpu_dev 2316 src/dps8/dps8_cpu.c sim_debug (DBG_INTR, & cpu_dev, "intr_pair_addr %u flag %d\n", cpu_dev 2319 src/dps8/dps8_cpu.c if_sim_debug (DBG_INTR, & cpu_dev) cpu_dev 2500 src/dps8/dps8_cpu.c sim_debug (DBG_CYCLE, & cpu_dev, cpu_dev 2603 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, "fetchCycle bit 29 sets XSF to 0\n"); cpu_dev 2706 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 2714 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 3393 src/dps8/dps8_cpu.c sim_debug (DBG_WARN, & cpu_dev, cpu_dev 3421 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3488 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3570 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3588 src/dps8/dps8_cpu.c sim_debug (DBG_MSG, & cpu_dev, cpu_dev 3597 src/dps8/dps8_cpu.c sim_debug (DBG_WARN, & cpu_dev, cpu_dev 3625 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3634 src/dps8/dps8_cpu.c sim_debug (DBG_WARN, & cpu_dev, cpu_dev 3661 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, cpu_dev 3676 src/dps8/dps8_cpu.c sim_debug (DBG_MSG, & cpu_dev, cpu_dev 3710 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, "core_write2 %08o %012llo (%s)\n", addr - 1, cpu_dev 3736 src/dps8/dps8_cpu.c sim_debug (DBG_CORE, & cpu_dev, "core_write2 %08o %012"PRIo64" (%s)\n", addr, odd, ctx); cpu_dev 3873 src/dps8/dps8_cpu.c sim_debug (DBG_DEBUG, & cpu_dev, "APU: Setting absolute mode.\n"); cpu_dev 3882 src/dps8/dps8_cpu.c sim_debug (DBG_DEBUG, & cpu_dev, "APU: Keeping append mode.\n"); cpu_dev 3884 src/dps8/dps8_cpu.c sim_debug (DBG_DEBUG, & cpu_dev, "APU: Setting append mode.\n"); cpu_dev 3890 src/dps8/dps8_cpu.c sim_debug (DBG_ERR, & cpu_dev, cpu_dev 473 src/dps8/dps8_cpu.h extern DEVICE cpu_dev; cpu_dev 420 src/dps8/dps8_decimal.c cpu_dev 422 src/dps8/dps8_decimal.c cpu_dev 450 src/dps8/dps8_decimal.c cpu_dev 465 src/dps8/dps8_decimal.c cpu_dev 468 src/dps8/dps8_decimal.c cpu_dev 476 src/dps8/dps8_decimal.c cpu_dev 482 src/dps8/dps8_decimal.c cpu_dev 501 src/dps8/dps8_decimal.c cpu_dev 530 src/dps8/dps8_decimal.c cpu_dev 547 src/dps8/dps8_decimal.c cpu_dev 569 src/dps8/dps8_decimal.c cpu_dev 582 src/dps8/dps8_decimal.c cpu_dev 600 src/dps8/dps8_decimal.c cpu_dev 604 src/dps8/dps8_decimal.c cpu_dev 611 src/dps8/dps8_decimal.c cpu_dev 620 src/dps8/dps8_decimal.c cpu_dev 645 src/dps8/dps8_decimal.c cpu_dev 669 src/dps8/dps8_decimal.c cpu_dev 687 src/dps8/dps8_decimal.c cpu_dev 695 src/dps8/dps8_decimal.c cpu_dev 32 src/dps8/dps8_decimal.h if_sim_debug (DBG_TRACEEXT, & cpu_dev) \ cpu_dev 42 src/dps8/dps8_decimal.h if_sim_debug (DBG_TRACEEXT, & cpu_dev) \ cpu_dev 562 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteCache addr %06o\n", p->cachedAddr); cpu_dev 572 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 577 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 583 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 600 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 605 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 611 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 626 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadCache addr %06o\n", address); cpu_dev 650 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 653 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 656 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 671 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); } cpu_dev 673 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 676 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 694 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteIdx addr %06o n %u\n", cpu.du.Dk_PTR_W[eisaddr_idx], n); cpu_dev 697 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteIdx addr %06o n %u\n", p->address, n); cpu_dev 734 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadIdx addr %06o n %u\n", cpu.du.Dk_PTR_W[eisaddr_idx], n); cpu_dev 738 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadIdx %ld addr %06o n %u\n", eisaddr_idx, p->address, n); cpu_dev 764 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISRead addr %06o\n", cpu.du.Dk_PTR_W[eisaddr_idx]); cpu_dev 766 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISRead addr %06o\n", p->address); cpu_dev 777 src/dps8/dps8_eis.c cpu_dev 779 src/dps8/dps8_eis.c cpu_dev 799 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s addr %06o\n", __func__, addressN); cpu_dev 815 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 819 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 823 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 839 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 842 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 861 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s addr %06o\n", __func__, addressN); cpu_dev 877 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 881 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 885 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 901 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 904 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 966 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISGet469 : k: %u TAk %u coffset %u c %o \n", k, cpu.du.TAk[k - 1], residue, c); cpu_dev 968 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EISGet469 : k: %u TAk %u coffset %u c %o \n", k, e -> TA [k - 1], residue, c); cpu_dev 1281 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "AR n %u k %u\n", n, k - 1); cpu_dev 1286 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "No ARb %u\n", k - 1); cpu_dev 1313 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "No ARa %u\n", k - 1); cpu_dev 1429 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "AR n %u k %u\n", n, k - 1); cpu_dev 1436 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "initial CN%u %u\n", k, CN); cpu_dev 1471 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "N%u %o\n", k, e->N[k-1]); cpu_dev 1515 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA4\n", cpu_dev 1539 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA6\n", cpu_dev 1553 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 1565 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA9\n", cpu_dev 1720 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(): N%u %0o\n", k, e->N[k-1]); cpu_dev 1818 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(): address:%06o cPos:%d bPos:%d N%u %u\n", cpu.du.Dk_PTR_W[k-1], a->cPos, a->bPos, k, e->N[k-1]); cpu_dev 1820 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(): address:%06o cPos:%d bPos:%d N%u %u\n", a->address, a->cPos, a->bPos, k, e->N[k-1]); cpu_dev 1858 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d AR%d\n", k, n); cpu_dev 1878 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d RL reg %u val %"PRIo64"\n", k, reg, (word36)e->N[k-1]); cpu_dev 1885 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d opdesc %012"PRIo64"\n", k, opDesc); cpu_dev 1886 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "N%u %u\n", k, e->N[k-1]); cpu_dev 2109 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r); cpu_dev 2114 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn)); cpu_dev 2117 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd augend 0%o\n", augend); cpu_dev 2123 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd force augend 0%o\n", augend); cpu_dev 2142 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum); cpu_dev 2251 src/dps8/dps8_eis.c cpu_dev 2282 src/dps8/dps8_eis.c cpu_dev 2333 src/dps8/dps8_eis.c cpu_dev 2371 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, cpu_dev 2377 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "awd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn)); cpu_dev 2383 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "awd augend 0%o\n", augend); cpu_dev 2388 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "awd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum); cpu_dev 2446 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r); cpu_dev 2451 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn)); cpu_dev 2457 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd minued 0%o\n", minued); cpu_dev 2462 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd minued 0%o subtractend 0%o difference 0%o\n", minued, subtractend, difference); cpu_dev 2483 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd r 0%o\n", r); cpu_dev 2485 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r); cpu_dev 2769 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d r 0%"PRIo64"\n", sz, rcnt); cpu_dev 2785 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r); cpu_dev 2862 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum); cpu_dev 3041 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpc tally %d c1 %03o c2 %03o\n", cpu.du.CHTALLY, c1, c2); cpu_dev 3918 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 3921 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 3985 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4012 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4113 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4116 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4180 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4208 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 4437 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, TA1, TA2, e -> N1, e -> N2, e -> CN1, e -> CN2); cpu_dev 4439 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, e -> TA1, e -> TA2, e -> N1, e -> N2, e -> CN1, e -> CN2); cpu_dev 4474 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #3\n"); cpu_dev 4514 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #4\n"); cpu_dev 4554 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #1\n"); cpu_dev 4584 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #2\n"); cpu_dev 4849 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MRL special case #1\n"); cpu_dev 4880 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MRL special case #2\n"); cpu_dev 5043 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "src: %d: %o\n", n, c); cpu_dev 5165 src/dps8/dps8_eis.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 5167 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "inBuffer:"); cpu_dev 5169 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, " %02o", * q); cpu_dev 5170 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "\n"); cpu_dev 5843 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "LTE IT[%d]<=%d\n", e -> mopIF - 1, next); cpu_dev 5894 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC IF %d, srcTally %d, dstTally %d\n", e->mopIF, e->srcTally, e->dstTally); cpu_dev 5897 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC n %d, srcTally %d, dstTally %d\n", n, e->srcTally, e->dstTally); cpu_dev 5909 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC c %d (0%o)\n", c, c); cpu_dev 5912 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC ES off\n"); cpu_dev 5914 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC is zero\n"); cpu_dev 5921 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC is not zero\n"); cpu_dev 5935 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC ES on\n"); cpu_dev 6005 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLS n %d c %o\n", n, c); cpu_dev 6011 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is off, c is zero; edit insertion table entry 1 is moved to the receiving field in place of the character.\n"); cpu_dev 6022 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is off, c is non-zero, SN is off; edit insertion table entry 3 is moved to the receiving field; the character is also moved to the receiving field, and ES is set ON.\n"); cpu_dev 6043 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is off, c is non-zero, SN is OFF; edit insertion table entry 4 is moved to the receiving field; the character is also moved to the receiving field, and ES is set ON.\n"); cpu_dev 6057 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is ON, the character is moved to the receiving field.\n"); cpu_dev 6099 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MORS mopIF %d src %d dst %d\n", e->mopIF, e->srcTally, e->dstTally); cpu_dev 6141 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC mopIF %d\n", e->mopIF); cpu_dev 6145 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC n %d srcTally %d dstTally %d\n", n, e->srcTally, e->dstTally); cpu_dev 6153 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC write to output buffer %o\n", *e->in); cpu_dev 6162 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC done\n"); cpu_dev 6493 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MOP %s(%o) %o\n", m -> mopName, mop, e->mopIF); cpu_dev 6497 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "getMop(e->m == NULL || e->m->f == NULL): mop:%d IF:%d\n", mop, e->mopIF); cpu_dev 6545 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "mopExecutor srcTally %d dstTally %d mopTally %d\n", e->srcTally, e->dstTally, e->mopTally); cpu_dev 6549 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "mopExecutor EISgetMop forced break\n"); cpu_dev 6574 src/dps8/dps8_eis.c cpu_dev 6580 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6600 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "mop faults %o src %d dst %d mop %d\n", e->_faults, e->srcTally, e->dstTally, e->mopTally); cpu_dev 6617 src/dps8/dps8_eis.c cpu_dev 6633 src/dps8/dps8_eis.c cpu_dev 6654 src/dps8/dps8_eis.c sim_debug(DBG_TRACEEXT, & cpu_dev, "mve\n"); cpu_dev 6951 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6955 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7180 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7658 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 7661 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 7664 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 7703 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "n1 %d sc1 %d\n", n1, sc1); cpu_dev 7734 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "n2 %d\n", n2); cpu_dev 7756 src/dps8/dps8_eis.c if_sim_debug (DBG_CAC, & cpu_dev) cpu_dev 7767 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "mvn res: '%s'\n", res); cpu_dev 7889 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "is neg %o\n", decNumberIsNegative(op1)); cpu_dev 7890 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "is zero %o\n", decNumberIsZero(op1)); cpu_dev 7891 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "R %o\n", R); cpu_dev 7892 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "Trunc %o\n", Trunc); cpu_dev 7893 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "TRUNC %o\n", TST_I_TRUNC); cpu_dev 7894 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "OMASK %o\n", TST_I_OMASK); cpu_dev 7895 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "tstOVFfault %o\n", tstOVFfault ()); cpu_dev 7896 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "T %o\n", T); cpu_dev 7897 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "EOvr %o\n", EOvr); cpu_dev 7898 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "Ovr %o\n", Ovr); cpu_dev 8031 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8300 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8304 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8517 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8687 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8691 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 8891 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb N1 %d N2 %d\n", e -> N1, e -> N2); cpu_dev 8918 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(min(e->N1, e->N2)) i %d b1 %d b2 %d\n", i, b1, b2); cpu_dev 8938 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(e->N1 < e->N2) i %d b1fill %d b2 %d\n", i, b1, b2); cpu_dev 8958 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(e->N1 > e->N2) i %d b1 %d b2fill %d\n", i, b1, b2); cpu_dev 9555 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 9721 src/dps8/dps8_eis.c cpu_dev 9746 src/dps8/dps8_eis.c cpu_dev 9757 src/dps8/dps8_eis.c cpu_dev 9779 src/dps8/dps8_eis.c cpu_dev 9800 src/dps8/dps8_eis.c cpu_dev 9821 src/dps8/dps8_eis.c cpu_dev 9841 src/dps8/dps8_eis.c cpu_dev 9848 src/dps8/dps8_eis.c cpu_dev 12377 src/dps8/dps8_eis.c cpu_dev 12379 src/dps8/dps8_eis.c cpu_dev 12408 src/dps8/dps8_eis.c cpu_dev 12423 src/dps8/dps8_eis.c cpu_dev 12426 src/dps8/dps8_eis.c cpu_dev 12436 src/dps8/dps8_eis.c cpu_dev 12442 src/dps8/dps8_eis.c cpu_dev 12461 src/dps8/dps8_eis.c cpu_dev 12551 src/dps8/dps8_eis.c cpu_dev 12568 src/dps8/dps8_eis.c cpu_dev 12590 src/dps8/dps8_eis.c cpu_dev 12603 src/dps8/dps8_eis.c cpu_dev 12617 src/dps8/dps8_eis.c cpu_dev 12621 src/dps8/dps8_eis.c cpu_dev 12628 src/dps8/dps8_eis.c cpu_dev 12637 src/dps8/dps8_eis.c cpu_dev 12680 src/dps8/dps8_eis.c cpu_dev 12717 src/dps8/dps8_eis.c cpu_dev 12735 src/dps8/dps8_eis.c cpu_dev 12743 src/dps8/dps8_eis.c cpu_dev 12925 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: clz1 %d clz2 %d\n",clz1,clz2); cpu_dev 12931 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d S1 %d S2 %d N1 %d N2 %d clz1 %d clz2 %d E1 %d E2 %d SF2 %d NQ %d\n",e->S1,e->S2,e->N1,e->N2,clz1,clz2,op1->exponent,op2->exponent,e->SF2,NQ); cpu_dev 12952 src/dps8/dps8_eis.c ) { sim_debug (DBG_TRACEEXT, & cpu_dev, "oops! dv2d anomalous results"); } // divide by zero has already been checked before cpu_dev 13005 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: exp1 %d exp2 %d digits op1 %d op2 %d op1a %d op2a %d\n",op1->exponent,op2->exponent,op1->digits,op2->digits,_1a.digits,_2a.digits); cpu_dev 13016 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: addzero n2 %d %s exp %d\n",n2,res,op3->exponent); cpu_dev 13353 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: clz1 %d clz2 %d\n",clz1,clz2); cpu_dev 13359 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d S1 %d S2 %d N1 %d N2 %d clz1 %d clz2 %d E1 %d E2 %d SF3 %d NQ %d\n",e->S1,e->S2,e->N1,e->N2,clz1,clz2,op1->exponent,op2->exponent,e->SF3,NQ); cpu_dev 13380 src/dps8/dps8_eis.c ) { sim_debug (DBG_TRACEEXT, & cpu_dev, "oops! dv3d anomalous results"); } // divide by zero has already been checked before cpu_dev 13433 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: exp1 %d exp2 %d digits op1 %d op2 %d op1a %d op2a %d\n",op1->exponent,op2->exponent,op1->digits,op2->digits,_1a.digits,_2a.digits); cpu_dev 13444 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: addzero n3 %d %s exp %d\n",n3,res,op3->exponent); cpu_dev 395 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 409 src/dps8/dps8_faults.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 546 src/dps8/dps8_faults.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MIF %o\n", TST_I_MIF); cpu_dev 548 src/dps8/dps8_faults.c cpu_dev 674 src/dps8/dps8_faults.c sim_debug (DBG_CYCLE, & cpu_dev, "Changing fault number to Trouble fault\n"); cpu_dev 718 src/dps8/dps8_faults.c sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to FAULT_cycle\n"); cpu_dev 724 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, cpu_dev 728 src/dps8/dps8_faults.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 803 src/dps8/dps8_faults.c sim_debug (DBG_TRACEEXT, & cpu_dev, "MIF %o\n", TST_I_MIF); cpu_dev 848 src/dps8/dps8_faults.c sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to FAULT_cycle\n"); cpu_dev 895 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, "setG7fault CPU %d fault %d (%o) sub %"PRId64" %"PRIo64"\n", cpu_dev 907 src/dps8/dps8_faults.c sim_debug (DBG_FAULT, & cpu_dev, "set_FFV_fault CPU f_fault_no %u\n", cpu_dev 81 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 102 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 122 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 139 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 181 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 184 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 201 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 204 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 227 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 230 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 245 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 248 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 253 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 258 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 298 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 301 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 318 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 321 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 345 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 348 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 367 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 370 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 423 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 426 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 443 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 446 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 470 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 473 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 493 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 496 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 540 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 561 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 582 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 595 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 635 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 645 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 667 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 680 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 712 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 727 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 749 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 763 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 798 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 801 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 818 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 821 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 845 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 848 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 865 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 868 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 930 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 933 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 950 src/dps8/dps8_iefp.c if_sim_debug (DBG_FINAL, & cpu_dev) cpu_dev 953 src/dps8/dps8_iefp.c sim_debug (DBG_FINAL, & cpu_dev, cpu_dev 977 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 980 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 997 src/dps8/dps8_iefp.c if_sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev) cpu_dev 1000 src/dps8/dps8_iefp.c sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, cpu_dev 92 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 147 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 171 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, &cpu_dev, cpu_dev 174 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, &cpu_dev, cpu_dev 193 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 206 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 232 src/dps8/dps8_ins.c sim_debug (DBG_ADDRMOD, & cpu_dev, cpu_dev 287 src/dps8/dps8_ins.c sim_debug (DBG_TRACE, & cpu_dev, "%s %05o:%06o\n", cpu_dev 303 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "CU: P %d IR %#o PSR %0#o IC %0#o TSR %0#o\n", cpu_dev 306 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "CU: xsf %d rf %d rpt %d rd %d rl %d pot %d xde %d xdo %d itp %d rfi %d its %d fif %d hold %0#o\n", cpu_dev 311 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "CU: iwb %012"PRIo64" irodd %012"PRIo64"\n", cpu_dev 464 src/dps8/dps8_ins.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 580 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s sets XSF to %o\n", __func__, cpu.cu.XSF); cpu_dev 1150 src/dps8/dps8_ins.c if_sim_debug (flag, &cpu_dev) cpu_dev 1164 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o|%06o %s\n", cpu_dev 1169 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o %s\n", cpu.PPR.IC, where); cpu_dev 1176 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%05o:%06o|%06o %s\n", cpu_dev 1182 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%05o:%06o %s\n", cpu_dev 1192 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1210 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1230 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1249 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, cpu_dev 1753 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD first %d rpt %d rd %d e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], !! (cpu.rX[0] & 01000), !! (cpu.rX[0] & 0400)); cpu_dev 1754 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD CA %06o\n", cpu.TPR.CA); cpu_dev 1780 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; offset is %06o\n", offset); cpu_dev 1784 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d was %06o\n", Xn, cpu.rX[Xn]); cpu_dev 1791 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu_dev 1807 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, "initialize EIS descriptors\n"); cpu_dev 1855 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, "doPtrReg: PR[%o] SNR=%05o RNR=%o WORDNO=%06o " "BITNO=%02o\n", n, cpu.PAR[n].SNR, cpu.PAR[n].RNR, cpu.PAR[n].WORDNO, GET_PR_BITNO (n)); cpu_dev 1870 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, &cpu_dev, "doPtrReg: n=%o offset=%05o TPR.CA=%06o " "TPR.TBR=%o TPR.TSR=%05o TPR.TRR=%o\n", n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR); cpu_dev 2015 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta first %d rf %d rpt %d rd %d " "e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, rf, cpu.cu.rpt, cpu.cu.rd, icOdd, cpu.rX[0], rptA, rptB); cpu_dev 2025 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu_dev 2041 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu_dev 2053 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]); cpu_dev 2105 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "tally %d\n", x); cpu_dev 2107 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "tally runout\n"); cpu_dev 2111 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "not tally runout\n"); cpu_dev 2119 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is zero terminate\n"); cpu_dev 2124 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not zero terminate\n"); cpu_dev 2129 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is neg terminate\n"); cpu_dev 2134 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not neg terminate\n"); cpu_dev 2139 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is carry terminate\n"); cpu_dev 2144 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is not carry terminate\n"); cpu_dev 2149 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "is overflow terminate\n"); cpu_dev 2162 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "not terminate\n"); cpu_dev 2198 src/dps8/dps8_ins.c if_sim_debug (DBG_REGDUMP, & cpu_dev) { cpu_dev 2200 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPAQI, &cpu_dev, "A=%012"PRIo64" Q=%012"PRIo64" IR:%s\n", cpu.rA, cpu.rQ, dump_flags (buf, cpu.cu.IR)); cpu_dev 2202 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPFLT, &cpu_dev, "E=%03o A=%012"PRIo64" Q=%012"PRIo64" %.10Lg\n", cpu.rE, cpu.rA, cpu.rQ, EAQToIEEElongdouble ()); cpu_dev 2204 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPFLT, &cpu_dev, "E=%03o A=%012"PRIo64" Q=%012"PRIo64" %.10g\n", cpu.rE, cpu.rA, cpu.rQ, EAQToIEEEdouble ()); cpu_dev 2206 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPIDX, &cpu_dev, "X[0]=%06o X[1]=%06o X[2]=%06o X[3]=%06o\n", cpu.rX[0], cpu.rX[1], cpu.rX[2], cpu.rX[3]); cpu_dev 2207 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPIDX, &cpu_dev, "X[4]=%06o X[5]=%06o X[6]=%06o X[7]=%06o\n", cpu.rX[4], cpu.rX[5], cpu.rX[6], cpu.rX[7]); cpu_dev 2209 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPPR, &cpu_dev, "PR%d/%s: SNR=%05o RNR=%o WORDNO=%06o BITNO:%02o ARCHAR:%o ARBITNO:%02o\n", n, PRalias[n], cpu.PR[n].SNR, cpu.PR[n].RNR, cpu.PR[n].WORDNO, GET_PR_BITNO (n), GET_AR_CHAR (n), GET_AR_BITNO (n)); cpu_dev 2211 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPPPR, &cpu_dev, "PRR:%o PSR:%05o P:%o IC:%06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); cpu_dev 2212 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPDSBR, &cpu_dev, "ADDR:%08o BND:%05o U:%o STACK:%04o\n", cpu.DSBR.ADDR, cpu.DSBR.BND, cpu.DSBR.U, cpu.DSBR.STACK); cpu_dev 2834 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, & cpu_dev, cpu_dev 4890 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "\n"); cpu_dev 4891 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 4894 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 4905 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, ">>> quot 1 %"PRId64"\n", quotient); cpu_dev 4906 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, ">>> rem 1 %"PRId64"\n", remainder); cpu_dev 4922 src/dps8/dps8_ins.c cpu_dev 4924 src/dps8/dps8_ins.c cpu_dev 4932 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 4934 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 4939 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, cpu_dev 4947 src/dps8/dps8_ins.c sim_debug (DBG_ERR, & cpu_dev, cpu_dev 4959 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "rA (rem) %012"PRIo64"\n", cpu.rA); cpu_dev 4960 src/dps8/dps8_ins.c sim_debug (DBG_CAC, & cpu_dev, "rQ (quot) %012"PRIo64"\n", cpu.rQ); cpu_dev 5621 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6103 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6759 src/dps8/dps8_ins.c if_sim_debug (DBG_TRACEEXT, & cpu_dev) cpu_dev 6778 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 6786 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, cpu_dev 7209 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "ldt TR %d (%o)\n", cpu_dev 7259 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RALR set to %o\n", cpu.rRALR); cpu_dev 8348 src/dps8/dps8_ins.c sim_debug (DBG_MSG, & cpu_dev, "BCE DIS causes CPU halt\n"); cpu_dev 8368 src/dps8/dps8_ins.c cpu_dev 8378 src/dps8/dps8_ins.c sim_debug (DBG_MSG, & cpu_dev, "sys_trouble$die DIS causes CPU halt\n"); cpu_dev 8383 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "entered DIS_cycle\n"); cpu_dev 8410 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS sees an interrupt\n"); cpu_dev 8427 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS sees a TRO\n"); cpu_dev 8433 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS refetches\n"); cpu_dev 9379 src/dps8/dps8_ins.c sim_debug (DBG_APPENDING, & cpu_dev, "absa CA:%08o\n", cpu.TPR.CA); cpu_dev 9409 src/dps8/dps8_ins.c if_sim_debug (DBG_FAULT, & cpu_dev) cpu_dev 9433 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU interrupt return\n"); cpu_dev 9511 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU FIF REFETCH return\n"); cpu_dev 9519 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU rfi refetch return\n"); cpu_dev 9539 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU MME2 restart return\n"); cpu_dev 9555 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU rfi/FIF REFETCH return\n"); cpu_dev 9566 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU MME2 restart return\n"); cpu_dev 9597 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU sync fault return\n"); cpu_dev 9611 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU MMEx sync fault return\n"); cpu_dev 9621 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU LUF RESTART return\n"); cpu_dev 9638 src/dps8/dps8_ins.c sim_debug (DBG_FAULT, & cpu_dev, "RCU ACV RESTART return\n"); cpu_dev 1214 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "fmp A %012"PRIo64" Q %012"PRIo64" E %03o\n", cpu.rA, cpu.rQ, cpu.rE); cpu_dev 2308 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dufm e1 %d %03o m1 %012"PRIo64" %012"PRIo64"\n", e1, e1, (word36) (m1 >> 36) & MASK36, (word36) m1 & MASK36); cpu_dev 2323 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dufm e2 %d %03o m2 %012"PRIo64" %012"PRIo64"\n", e2, e2, (word36) (m2 >> 36) & MASK36, (word36) m2 & MASK36); cpu_dev 1376 src/dps8/dps8_scu.c for (uint cpun = 0; cpun < cpu_dev.numunits; cpun ++) cpu_dev 31 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || ((1 << current_running_cpu_idx) & dbgCPUMask)) && \ cpu_dev 32 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || (((dptr)->dctrl & (DBG_INTR | DBG_FAULT))) || (! sim_deb_segno_on) || sim_deb_segno[cpu.PPR.PSR & (DEBUG_SEGNO_LIMIT - 1)]) && \ cpu_dev 33 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || sim_deb_ringno == NO_SUCH_RINGNO || sim_deb_ringno == cpu . PPR. PRR) && \ cpu_dev 34 src/dps8/dps8_simh.h ((dptr != & cpu_dev) || (! sim_deb_bar) || (! TST_I_NBAR)) && \ cpu_dev 38 src/dps8/dps8_simh.h ((dptr != & cpu_dev) | (((dbits) & DBG_TRACE) ? (sim_deb_skip_cnt ++ >= sim_deb_skip_limit) : (sim_deb_skip_cnt >= sim_deb_skip_limit))) \ cpu_dev 1791 src/dps8/dps8_sys.c cpu_dev.numunits = 1; cpu_dev 2581 src/dps8/dps8_sys.c sim_debug (dflag, & cpu_dev, "%s", line); cpu_dev 2702 src/dps8/dps8_sys.c sim_debug (dflag, & cpu_dev, "%s", line); cpu_dev 2721 src/dps8/dps8_sys.c sim_debug (dflag, & cpu_dev, "%s", line); cpu_dev 4613 src/dps8/dps8_sys.c if (uptr == &cpu_dev.units[0]) cpu_dev 4817 src/dps8/dps8_sys.c & cpu_dev, // dev[0] is special to the scp interface; it is the 'default device' cpu_dev 178 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Add36b op1 %012"PRIo64" op2 %012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", op1, op2, carryin, flagsToSet, * flags); cpu_dev 249 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Add36b res %012"PRIo64" flags %06o ovf %o\n", res, * flags, * ovf); cpu_dev 615 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1 %012"PRIo64"%012"PRIo64" op2 %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", cpu_dev 618 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1 %012"PRIo64"%012"PRIo64" op2 %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", cpu_dev 659 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1e %012"PRIo64"%012"PRIo64" op2e %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", cpu_dev 662 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1e %012"PRIo64"%012"PRIo64" op2e %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", cpu_dev 673 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) (rshift_128 (res, 36).l & MASK36), (word36) (res.l & MASK36), * flags, * ovf); cpu_dev 675 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) ((res >> 36) & MASK36), (word36) (res & MASK36), * flags, * ovf); cpu_dev 753 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) (rshift_128 (res, 36).l & MASK36), (word36) (res.l & MASK36), * flags, * ovf); cpu_dev 755 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) ((res >> 36) & MASK36), (word36) (res & MASK36), * flags, * ovf); cpu_dev 1091 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1 %016"PRIx64"%016"PRIx64"\n", op1.h, op1.l); cpu_dev 1092 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2 %016"PRIx64"%016"PRIx64"\n", op2.h, op2.l); cpu_dev 1095 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\n", op1s.h, op1s.l); cpu_dev 1096 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2s %016"PRIx64"%016"PRIx64"\n", op2s.h, op2s.l); cpu_dev 1098 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1 %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op1>>64), (uint64_t) op1); cpu_dev 1099 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2 %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op2>>64), (uint64_t) op2); cpu_dev 1102 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op1s>>64), (uint64_t) op1s); cpu_dev 1103 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2s %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op2s>>64), (uint64_t) op2s);