IC 87 src/dps8/dps8_addrmods.c return cpu.PPR.IC; IC 2019 src/dps8/dps8_append.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; IC 2068 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; IC 2122 src/dps8/dps8_append.c cpu.PPR.IC = cpu.TPR.CA; IC 2168 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 900 src/dps8/dps8_cpu.c cpu.PPR.IC = 0; IC 1604 src/dps8/dps8_cpu.c { ORDATA (IC, dummy_IC, VASIZE), 0, 0, 0 }, IC 1606 src/dps8/dps8_cpu.c { ORDATA (IC, cpus[0].PPR.IC, VASIZE), 0, 0, 0 }, IC 1740 src/dps8/dps8_cpu.c sim_brk_test ((cpu.PPR.IC & 0777777) | IC 2101 src/dps8/dps8_cpu.c cpus [0].PPR.IC = dummy_IC; IC 2416 src/dps8/dps8_cpu.c get_BAR_address (cpu.PPR.IC); IC 2439 src/dps8/dps8_cpu.c (cpu.PPR.IC & 1) == 0 && IC 2456 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 1) IC 2609 src/dps8/dps8_cpu.c fetchInstruction (cpu.PPR.IC); IC 2628 src/dps8/dps8_cpu.c stall_points[i].offset && stall_points[i].offset == cpu.PPR.IC) IC 2905 src/dps8/dps8_cpu.c (cpu.cu.rd && (cpu.PPR.IC & 1)) || IC 2910 src/dps8/dps8_cpu.c -- cpu.PPR.IC; IC 2931 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 2932 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 2978 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 2980 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3003 src/dps8/dps8_cpu.c if ((cpu.PPR.IC & 1) == 0 && IC 3007 src/dps8/dps8_cpu.c (cpu.PPR.IC & ~3u) != (cpu.last_write & ~3u)) IC 3009 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3016 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3018 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3033 src/dps8/dps8_cpu.c cpu.PPR.IC += ci->info->ndes; IC 3034 src/dps8/dps8_cpu.c cpu.PPR.IC ++; IC 3192 src/dps8/dps8_cpu.c dummy_IC = cpu.PPR.IC; IC 3396 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); IC 3403 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, addr, IC 3437 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3480 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3504 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3520 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3562 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3600 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); IC 3607 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3618 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3637 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); IC 3644 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3655 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); IC 3696 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 3719 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IC 4234 src/dps8/dps8_cpu.c putbits36_18 (& w1, 54 - 36, cpu.PPR.IC); IC 101 src/dps8/dps8_cpu.h word18 IC; // The word offset from the origin of the procedure segment IC 1037 src/dps8/dps8_cpu.h #define USE_IRODD (cpu.cu.rd && ((cpu. PPR.IC & 1) != 0)) IC 1651 src/dps8/dps8_cpu.h word18 IC; IC 353 src/dps8/dps8_eis.c return cpu.PPR.IC; IC 450 src/dps8/dps8_eis.c return cpu.PPR.IC; IC 525 src/dps8/dps8_eis.c return cpu.PPR.IC; IC 381 src/dps8/dps8_faults.c sim_printf (" TRO PSR:IC %05o:%06o\r\n", cpu.PPR.PSR, cpu.PPR.IC); IC 386 src/dps8/dps8_faults.c sim_printf (" ACV %012llo PSR:IC %05o:%06o\r\n", subFault.bits, cpu.PPR.PSR, cpu.PPR.IC); IC 418 src/dps8/dps8_faults.c fault_ic = cpu . PPR.IC; IC 691 src/dps8/dps8_faults.c cpu . PPR.IC); IC 834 src/dps8/dps8_faults.c cpu.PPR.IC); IC 137 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) IC 365 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) IC 491 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) IC 277 src/dps8/dps8_ins.c cpu.PR[n].WORDNO = (cpu.PPR.IC + 1) & MASK18; IC 283 src/dps8/dps8_ins.c cpu.PPR.IC = cpu.TPR.CA; IC 288 src/dps8/dps8_ins.c __func__, cpu.PPR.PSR, cpu.PPR.IC); IC 289 src/dps8/dps8_ins.c if (cpu.PPR.IC & 1) IC 399 src/dps8/dps8_ins.c putbits36_18 (& words[4], 0, cpu.PPR.IC); IC 545 src/dps8/dps8_ins.c cpu.cu_data.IC = cpu.PPR.IC; IC 656 src/dps8/dps8_ins.c cpu.PPR.IC = getbits36_18 (words[4], 0); IC 1098 src/dps8/dps8_ins.c if (cpu.cu.rd && ((cpu.PPR.IC & 1) != 0)) IC 1130 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) // Even IC 1155 src/dps8/dps8_ins.c char * where = lookup_address (cpu.PPR.PSR, cpu.PPR.IC, & compname, IC 1165 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); IC 1169 src/dps8/dps8_ins.c sim_debug (flag, &cpu_dev, "%06o %s\n", cpu.PPR.IC, where); IC 1178 src/dps8/dps8_ins.c cpu.BAR.BASE, cpu.PPR.IC, where); IC 1183 src/dps8/dps8_ins.c cpu.PPR.PSR, cpu.PPR.IC, where); IC 1197 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1214 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1236 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1254 src/dps8/dps8_ins.c cpu.PPR.IC, IC 1306 src/dps8/dps8_ins.c trk (cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IWB_IRODD); IC 1466 src/dps8/dps8_ins.c if (!cpu.cu.xde && cpu.cu.xdo /* odd instr being executed */ && !(cpu.PPR.IC & 1)) IC 1472 src/dps8/dps8_ins.c if (opcode == 0560 && !opcodeX && cpu.cu.xde && !(cpu.PPR.IC & 1)) IC 1662 src/dps8/dps8_ins.c if (n_dbgevents && (dbgevt = (dbgevent_lookup (cpu.PPR.PSR, cpu.PPR.IC))) >= 0) { IC 1753 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD first %d rpt %d rd %d e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], !! (cpu.rX[0] & 01000), !! (cpu.rX[0] & 0400)); IC 1763 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); IC 1827 src/dps8/dps8_ins.c word18 saveIC = cpu.PPR.IC; IC 1828 src/dps8/dps8_ins.c Read (cpu.PPR.IC + 1 + n, & cpu.currentEISinstruction.op[n], INSTRUCTION_FETCH); IC 1829 src/dps8/dps8_ins.c cpu.PPR.IC = saveIC; IC 1990 src/dps8/dps8_ins.c bool icOdd = !! (cpu.PPR.IC & 1); IC 2211 src/dps8/dps8_ins.c sim_debug (DBG_REGDUMPPPR, &cpu_dev, "PRR:%o PSR:%05o P:%o IC:%06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); IC 2882 src/dps8/dps8_ins.c word18 ret = (cpu.PPR.IC + 1) & MASK18; IC 3766 src/dps8/dps8_ins.c SETHI (cpu.CY, (cpu.PPR.IC + 1) & MASK18); IC 3779 src/dps8/dps8_ins.c cpu.CY = ((word36) ((cpu.PPR.IC + 2) & MASK18)) << 18; IC 3850 src/dps8/dps8_ins.c putbits36_18 (& cpu.Ypair[1], 0, cpu.PPR.IC + 2); IC 3860 src/dps8/dps8_ins.c putbits36_18 (& cpu.Ypair[1], 0, cpu.cu_data.IC + 2); IC 6123 src/dps8/dps8_ins.c cpu.PPR.IC = GETHI (cpu.CY); IC 6911 src/dps8/dps8_ins.c if ((cpu.PPR.IC & 1) == 0) IC 7213 src/dps8/dps8_ins.c sim_printf (" ldt %d PSR:IC %05o:%06o\r\n", cpu.rTR, cpu.PPR.PSR, cpu.PPR.IC); IC 7264 src/dps8/dps8_ins.c sim_printf (" RALR set to %o PSR:IC %05o:%06o\r\n", cpu.rRALR, cpu.PPR.PSR, cpu.PPR.IC); IC 8328 src/dps8/dps8_ins.c " no events in queue\n", cpu.PPR.IC); IC 8345 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 0430 && cpu.PPR.IC == 012) IC 8375 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 034 && cpu.PPR.IC == 03535) IC 9406 src/dps8/dps8_ins.c sim_printf (" rcu to %05o:%06o PSR:IC %05o:%06o\r\n", (cpu.Yblock8[0]>>18)&MASK15, (cpu.Yblock8[4]>>18)&MASK18, cpu.PPR.PSR, cpu.PPR.IC); IC 3472 src/dps8/dps8_iom.c __func__, iomChar (iom_unit_idx), cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC); IC 2743 src/dps8/dps8_sys.c word18 icOffset = cpu.PPR.IC; IC 4084 src/dps8/dps8_sys.c { "cpus[].PPR.IC", SYM_STRUCT_OFFSET, SYM_UINT32_18, offsetof (struct ppr_s, IC) }, IC 168 src/dps8/hdbg.c if (filter && hdbgSegNum > 0 && blacklist[cpu.PPR.IC]) \ IC 190 src/dps8/hdbg.c hevents[p].trace.ic = cpu.PPR.IC;