root/src/dps8/dps8_hw_consts.h

/* */

INCLUDED FROM

DEFINITIONS

1. SIGNEXT6_int
2. SIGNEXT8_int
3. SIGNEXT15_32
4. SIGNEXT18_32
5. SIGNEXT21_32
6. SIGNEXT22_32
7. SIGNEXT24_32
8. SIGNEXT36_64
9. SIGNEXT18_64
10. SIGNEXT21_64
11. SIGNEXT22_64
12. SIGNEXT24_64
13. SIGNEXT72_128
14. SIGNEXT36_128
15. SIGNEXT15_18
16. SIGNEXT18_24
17. SIGNEXT36_72

   1 /*
   2  * vim: filetype=c:tabstop=4:ai:expandtab
   3  * SPDX-License-Identifier: ICU
   4  * scspell-id: 6effbe78-f62e-11ec-87ca-80ee73e9b8e7
   5  *
   6  * ---------------------------------------------------------------------------
   7  *
   8  * Copyright (c) 2007-2013 Michael Mondy
   9  * Copyright (c) 2012-2016 Harry Reed
  10  * Copyright (c) 2013-2016 Charles Anthony
  11  * Copyright (c) 2021-2022 The DPS8M Development Team
  12  *
  13  * All rights reserved.
  14  *
  15  * This software is made available under the terms of the ICU
  16  * License, version 1.8.1 or later.  For more details, see the
  17  * LICENSE.md file at the top-level directory of this distribution.
  18  *
  19  * ---------------------------------------------------------------------------
  20  */
  21 
  22 #ifndef DPS8_HW_CONSTS_H
  23 # define DPS8_HW_CONSTS_H
  24 
  25 # include "dps8_math128.h"
  26 
  27 /////////////////////////////////////
  28 //
  29 // SCU/Memory
  30 //
  31 
  32 # define XXX_TEMP_SCU_SUBPORT 0
  33 
  34 enum { N_SCU_PORTS       =  8 };
  35 enum { N_SCU_SUBPORTS    =  4 };
  36 enum { N_ASSIGNMENTS     =  2 };
  37 // Number of interrupts in an interrupt cell register
  38 enum { N_CELL_INTERRUPTS = 32 };
  39 
  40 # define PASIZE          24                       /* phys addr width */
  41 # define PAMASK          ((1U << PASIZE) - 1U)
  42 // Mask out low bit
  43 # define PAEVEN          (((1U << (PASIZE - 1)) - 1U) << 1)
  44 # define MEM_SIZE_MAX    (1U << PASIZE)           /* maximum memory */
  45 
  46 // The minimum allocation size of a SCU is 64K (2^16)
  47 // (2 banks of 32K). Call it an SCBANK
  48 # define SCBANK_SZ          (1U << 16)
  49 
  50 // Maximum memory size is MEM_SIZE_MAX, number of
  51 // scbanks is:
  52 # define N_SCBANKS ((MEM_SIZE_MAX) / (SCBANK_SZ))
  53 
  54 //
  55 // Memory addressing
  56 //
  57 
  58 # define VASIZE            18                     // virtual addr width
  59 # define AMASK           ((1U << VASIZE) - 1U)    // virtual addr mask
  60 # define SEGSIZE          (1U << VASIZE)          // size of segment in words
  61 
  62 /////////////////////////////////////
  63 //
  64 // Append unit memory paging
  65 //
  66 
  67 # define PGSZ 1024u
  68 # define PGMK 1023u
  69 
  70 //
  71 // IOM
  72 //
  73 
  74 enum { MAX_CHANNELS     = 64 };
  75 enum { N_IOM_PORTS      =  8 };
  76 // The number of devices that a dev_code can address (6 bit number)
  77 enum { N_DEV_CODES      = 64 };
  78 enum { IOM_CONNECT_CHAN =  2 };
  79 
  80 /////////////////////////////////////
  81 //
  82 // Words
  83 //
  84 
  85 # define MAX18           0777777U
  86 # define MAX18POS        0377777U                 //  2**17-1
  87 # define MAX18NEG        0400000U                 // -2**17
  88 # define SIGN18          0400000U
  89 // NB. these 2 use the wrong bit number convention
  90 # define BIT19           01000000U                // carry out bit from 18 bit arithmetic
  91 # define BIT20           02000000U                // carry out bit from 19 bit arithmetic
  92 # define MASK36          0777777777777LLU         // data mask
  93 # define DMASK           MASK36
  94 # define MASK10          0001777U                 // 10-bit data mask
  95 # define MASK14          0037777U                 // 14-bit data mask
  96 # define MASK16          0177777U                 // 16-bit data mask
  97 # define MASK17          0377777U                 // 17-bit data mask
  98 # define MASK18          0777777U                 // 18-bit data mask
  99 # define WMASK           MASK18                   // WORDNO mask
 100 # define MASKLO18        0000000777777LLU
 101 # define MASKHI18        0777777000000LLU
 102 # define MASK20          03777777U                // 20-bit data mask
 103 # define MASK24          077777777U               // 24-bit data mask
 104 # define MASK28          01777777777U             // 28-bit data mask
 105 # define SIGN24          040000000U
 106 # define SIGN36          0400000000000LLU         // sign bit of a 36-bit word
 107 // NB. these 3 use the wrong bit number convention
 108 # define BIT37           01000000000000LLU        // carry out bit from 36 bit arithmetic
 109 # define BIT38           02000000000000LLU        // carry out bit from 37 bit arithmetic
 110 # define BIT35           0200000000000LLU         // next to the sign bit
 111 # define MASK32          037777777777U
 112 # define MASK15          077777U
 113 # define SMASK           MASK15                   // Segment number mask
 114 # define SIGN15          040000U                  // sign mask 15-bit number
 115 # define MAGMASK         0377777777777LLU         // magnitude mask
 116 # define ONES            0777777777777LLU
 117 # define NEG136          0777777777777LLU         // -1
 118 # define MAXPOS          0377777777777LLU         //  2**35-1
 119 # define MAXNEG          0400000000000LLU         // -2**35
 120 # define MAX36           0777777777777LLU         // 2**36-1
 121 # define MAX72           (((word72)1U << 72) - 1U)  // 72 1's
 122 
 123 # define CARRY           01000000000000LLU        // carry from 2 36-bit additions/subs
 124 # define ZEROEXT         0777777777777LLU         // mask to zero extend a 36 => 64-bit int
 125 # define ZEROEXT18       0777777U                 // mask to zero extend a 18 => 32-bit int
 126 
 127 # ifdef NEED_128
 128 
 129 #  define SIGN72          (construct_128 (0200U, 0U))
 130 // NB. these use the wrong bit number convention
 131 #  define BIT68           (construct_128 (010U, 0U))
 132 #  define BIT69           (construct_128 (020U, 0U))
 133 #  define BIT70           (construct_128 (040U, 0U))
 134 #  define BIT71           (construct_128 (0100U, 0U)) // next to the sign bit
 135 #  define BIT73           (construct_128 (0400U, 0U)) // carry out bit from 72 bit arithmetic
 136 #  define BIT74           (construct_128 (01000U, 0U)) // carry out bit from 73 bit arithmetic
 137 #  define MASK63          0x7FFFFFFFFFFFFFFF
 138 #  define MASK64          0xFFFFFFFFFFFFFFFF
 139 #  define MASK68          (construct_128 (017U, MASK64)) // Hex mode mantissa normalization mask
 140 #  define MASK70          (construct_128 (0077U, MASK64))
 141 #  define MASK71          (construct_128 (0177U, MASK64))
 142 #  define MASK72          (construct_128 (0377U, MASK64))
 143 
 144 # else
 145 
 146 #  define SIGN72          ((word72)1U << 71)
 147 // NB. these use the wrong bit number convention
 148 #  define BIT68           ((word72)1U << 67)
 149 #  define BIT69           ((word72)1U << 68)
 150 #  define BIT70           ((word72)1U << 69)
 151 #  define BIT71           ((word72)1U << 70)  // next to the sign bit
 152 #  define BIT73           ((word72)1U << 72)       // carry out bit from 72 bit arithmetic
 153 #  define BIT74           ((word72)1U << 73)       // carry out bit from 73 bit arithmetic
 154 
 155 #  define MASK68          (((word72)1U << 68) - 1U) // Hex mode mantissa normalization mask
 156 #  define MASK70          (((word72)1U << 70) - 1U)
 157 #  define MASK71          (((word72)1U << 71) - 1U)
 158 #  define MASK72          (((word72)1U << 72) - 1U)
 159 #  define ZEROEXT72       (((word72)1U << 72) - 1U)  // mask to zero extend a 72 => 128 int
 160 
 161 # endif
 162 
 163 # define SIGN64          ((uint64)1U << 63)
 164 
 165 # define MASK2           03U
 166 # define MASK3           07U
 167 # define MASK4           017U
 168 # define MASK5           037U
 169 # define MASK6           077U
 170 # define MASK7           0177U
 171 
 172 # define SIGN8           0200U                    // sign mask 8-bit number
 173 # define MASK8           0377U                    // 8-bit mask
 174 # define MASK9           0777U                    // 9-bit mask
 175 
 176 # define MASK11          03777U
 177 
 178 # define SIGN12          0x800U                   // sign mask 12-bit number
 179 # define MASK12          07777U
 180 
 181 # define SIGN6           0040U                    // sign bit of 6-bit signed number (e.g. Scaling Factor)
 182 
 183 # define MASK35          0377777777777llu
 184 
 185 # define MASKBITS(x)     ( ~(~((uint64)0)<<x) )   // lower (x) bits all ones
 186 # define MASKBITS18(x)   ( ~(~((word18)0)<<x) )   // lower (x) bits all ones
 187 # define MASKBITS72(x)   ( ~(~((word72)0)<<x) )   // lower (x) bits all ones
 188 
 189 # define GETHI36(a)      ((word18) (((a) >> 18) & MASK18))
 190 # define GETLO36(a)      ((word18) ((a) & MASK18))
 191 # define SETHI36(a,b)    (((a) &= MASKLO18), ((a) |= ((((word36)(b) & MASKLO18) << 18))))
 192 # define SETLO36(a,b)    (((a) &= MASKHI18), ((a) |= ((word36)(b) & MASKLO18)))
 193 # define GETHI(a)        GETHI36((a))
 194 # define GETLO(a)        GETLO36((a))
 195 # define SETHI(a,b)      SETHI36((a),(b))
 196 # define SETLO(a,b)      SETLO36((a),(b))
 197 
 198 # define GETHI72(a)      ((word36) (((a) >> 36) & MASK36))
 199 # define GETLO72(a)      ((word36) ((a) & MASK36))
 200 # define SETHI72(a,b)    ((a) &= MASK36, (a) |= ((((word72)(b) & MASK36)) << 36))
 201 # define SETLO72(a,b)    ((a) &= MASK36 << 36, (a) |= ((word72)(b) & MASK36))
 202 
 203 # define GET24(a)        ((word24) ((a) & MASK24))
 204 # define MASK21          07777777llu
 205 # define SIGN21          04000000llu
 206 # define MASK22          017777777llu
 207 # define SIGN22          010000000llu
 208 # define MASK27          0777777777llu
 209 
 210 // Sign extend DPS8M words into host words
 211 
 212 static inline int SIGNEXT6_int (word6 w)
     /*  */
 213   {
 214     if (w & SIGN6)
 215       {
 216         return ((int) w) | (int) (((uint) -1) << 6);
 217       }
 218     return w & MASK6;
 219   }
 220 
 221 static inline int SIGNEXT8_int (word8 w)
     /*  */
 222   {
 223     if (w & SIGN8)
 224       {
 225         return ((int) w) | (int) (((uint) -1) << 8);
 226       }
 227     return w & MASK8;
 228   }
 229 
 230 static inline int32 SIGNEXT15_32 (word15 w)
     /*  */
 231   {
 232     if (w & SIGN15)
 233       {
 234         return ((int32) w) | (int32) (((uint32) -1) << 15);
 235       }
 236     return w & MASK15;
 237   }
 238 
 239 static inline int32 SIGNEXT18_32 (word18 w)
     /*  */
 240   {
 241     if (w & SIGN18)
 242       {
 243         return ((int32) w) | (int32) (((uint32) -1) << 18);
 244       }
 245     return w & MASK18;
 246   }
 247 
 248 static inline int32 SIGNEXT21_32 (word21 w)
     /*  */
 249   {
 250     if (w & SIGN21)
 251       {
 252         return ((int32) w) | (int32) (((uint32) -1) << 21);
 253       }
 254     return w & MASK21;
 255   }
 256 
 257 static inline int32 SIGNEXT22_32 (word22 w)
     /*  */
 258   {
 259     if (w & SIGN22)
 260       {
 261         return ((int32) w) | (int32) (((uint32) -1) << 22);
 262       }
 263     return w & MASK22;
 264   }
 265 
 266 static inline int32 SIGNEXT24_32 (word24 w)
     /*  */
 267   {
 268     if (w & SIGN24)
 269       {
 270         return ((int32) w) | (int32) (((uint32) -1) << 24);
 271       }
 272     return w & MASK24;
 273   }
 274 
 275 static inline t_int64 SIGNEXT36_64 (word36 w)
     /*  */
 276   {
 277     if (w & SIGN36)
 278       {
 279         return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 36);
 280       }
 281     return w & MASK36;
 282   }
 283 
 284 static inline t_int64 SIGNEXT18_64 (word36 w)
     /*  */
 285   {
 286     if (w & SIGN18)
 287       {
 288         return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 18);
 289       }
 290     return w & MASK18;
 291   }
 292 
 293 static inline t_int64 SIGNEXT21_64 (word36 w)
     /*  */
 294   {
 295     if (w & SIGN21)
 296       {
 297         return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 21);
 298       }
 299     return w & MASK21;
 300   }
 301 
 302 static inline t_int64 SIGNEXT22_64 (word36 w)
     /*  */
 303   {
 304     if (w & SIGN22)
 305       {
 306         return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 22);
 307       }
 308     return w & MASK22;
 309   }
 310 
 311 static inline t_int64 SIGNEXT24_64 (word36 w)
     /*  */
 312   {
 313     if (w & SIGN24)
 314       {
 315         return ((t_int64) w) | (t_int64) (((t_uint64) -1ll) << 24);
 316       }
 317     return w & MASK24;
 318   }
 319 
 320 static inline int128 SIGNEXT72_128 (word72 w)
     /*  */
 321   {
 322 # ifdef NEED_128
 323     if (isnonzero_128 (and_128 (w, SIGN72)))
 324       {
 325         uint128 v = or_128 (w, construct_128 (0xFFFFFFFFFFFFFF80, 0));
 326         return cast_s128 (v);
 327       }
 328     uint128 v =  and_128 (w, MASK72);
 329 #  if defined(__sun__) || defined(_AIX)
 330     return (int128) { (uint64_t)  v.h, v.l};
 331 #  elif defined(__MINGW32__)
 332     return (int128) { (int64_t)   v.h, v.l};
 333 #  else
 334     return (int128) { (__int64_t) v.h, v.l};
 335 #  endif
 336 # else
 337     if (w & SIGN72)
 338       {
 339         return ((int128) w) | (int128) (((uint128) -1ll) << 72);
 340       }
 341     return w & MASK72;
 342 # endif
 343   }
 344 
 345 # ifdef NEED_128
 346 static inline int128 SIGNEXT36_128 (word36 w)
     /*  */
 347   {
 348     if (w & SIGN36)
 349       {
 350         return construct_s128 ((int64_t) MASK64, w | 0xFFFFFFF000000000);
 351       }
 352     return construct_s128 (0, w);
 353   }
 354 # endif
 355 
 356 // Sign extend DPS8M words into DPS8M words
 357 // NB: The high order bits in the host container will
 358 // set to 0; you cannot do host math with
 359 // these results.
 360 
 361 static inline word18 SIGNEXT15_18 (word15 w)
     /*  */
 362   {
 363     if (w & SIGN15)
 364       {
 365         return (w | ((word18) -1) << 15) & MASK18;
 366       }
 367     return w & MASK15;
 368   }
 369 
 370 static inline word24 SIGNEXT18_24 (word18 w)
     /*  */
 371   {
 372     if (w & SIGN18)
 373       {
 374         return (w | ((word24) -1) << 18) & MASK24;
 375       }
 376     return w & MASK18;
 377   }
 378 
 379 static inline word72 SIGNEXT36_72 (word36 w)
     /*  */
 380   {
 381 # ifdef NEED_128
 382     if (w & SIGN36)
 383       {
 384         //return (w | ((word72) DMASK) << 36) & MASK72;
 385         return construct_128 (0377U, (w & MASK36) | 0xFFFFFFF000000000);
 386       }
 387     //return w & MASK36;
 388     return construct_128 (0, w & MASK36);
 389 # else
 390     if (w & SIGN36)
 391       {
 392         return (w | ((word72) DMASK) << 36) & MASK72;
 393       }
 394     return w & MASK36;
 395 # endif
 396   }
 397 
 398 # define SETS36(x)       ((x) | SIGN36)
 399 # define CLRS36(x)       ((x) & ~SIGN36)
 400 # define TSTS36(x)       ((x) & SIGN36)
 401 
 402 /////////////////////////////////////
 403 //
 404 // Instruction format
 405 //
 406 
 407 # define INST_V_TAG      0                        // Tag
 408 # define INST_M_TAG      077U
 409 # define INST_V_A        6                        // Indirect via pointer
 410 # define INST_M_A        1U
 411 # define INST_V_I        7                        // Interrupt Inhibit
 412 # define INST_M_I        1U
 413 # define INST_V_OP       9                        // opcode
 414 # define INST_M_OP       0777U
 415 # define INST_V_OPX      8                        // opcode extension
 416 # define INST_M_OPX      1U
 417 
 418 # define INST_V_ADDR     18                       // Address
 419 # define INST_M_ADDR     0777777U
 420 # define INST_V_OFFSET   18                       // Offset (Bit29=1)
 421 # define INST_M_OFFSET   077777U
 422 # define INST_V_PRN      33                       // n of PR[n] (Bit29=1)
 423 # define INST_M_PRN      07U
 424 # define INST_V_ARN      33                       // n of AR[n] (Bit29=1)
 425 # define INST_M_ARN      07U
 426 
 427 # define GET_TAG(x)      ((word6)  ( (x)                   & INST_M_TAG ))
 428 # define GET_A(x)        ((word1)  (((x) >> INST_V_A)      & INST_M_A   ))
 429 # define GET_I(x)        ((int32)  (((x) >> INST_V_I)      & INST_M_I   ))
 430 # define GET_OP(x)       ((word9)  (((x) >> INST_V_OP)     & INST_M_OP ))
 431 # define GET_OPX(x)      ((bool)   (((x) >> INST_V_OPX)    & INST_M_OPX))
 432 
 433 # define GET_OFFSET(x)   ((word15) (((x) >> INST_V_OFFSET) & INST_M_OFFSET))
 434 # define GET_PRN(x)      ((word3)  (((x) >> INST_V_PRN)    & INST_M_PRN))
 435 # define GET_ARN(x)      ((word3)  (((x) >> INST_V_ARN)    & INST_M_ARN))
 436 
 437 # define GET_TM(x)       (       (GET_TAG(x) & 060U))
 438 # define GET_TD(x)       (       (GET_TAG(x) & 017U))
 439 
 440 # define GET_ADDR(x)     ((uint32) (((x) >> INST_V_ADDR) & INST_M_ADDR))
 441 
 442 // tag defines ...
 443 # define TAG_R           0U
 444 # define TAG_RI          1U
 445 # define TAG_IT          2U
 446 # define TAG_IR          3U
 447 
 448 # define _TD(tag)        ((tag) & 017U)
 449 # define _TM(tag)        ((tag) & 060U)
 450 
 451 enum {
 452     TD_N        = 000U,
 453     TD_AU       = 001U,
 454     TD_QU       = 002U,
 455     TD_DU       = 003U,
 456     TD_IC       = 004U,
 457     TD_AL       = 005U,
 458     TD_QL       = 006U,
 459     TD_DL       = 007U,
 460     TD_X0       = 010U,
 461     TD_X1       = 011U,
 462     TD_X2       = 012U,
 463     TD_X3       = 013U,
 464     TD_X4       = 014U,
 465     TD_X5       = 015U,
 466     TD_X6       = 016U,
 467     TD_X7       = 017U
 468 };
 469 
 470 enum {
 471     TM_R        = 000U,
 472     TM_RI       = 020U,
 473     TM_IT       = 040U,  // HWR - next 2 had values swapped
 474     TM_IR       = 060U
 475 };
 476 
 477 /* see AL39, pp 6-13, tbl 6-3 */
 478 enum {
 479     IT_F1       = 000U,
 480     IT_SD       = 004U,
 481     IT_SCR      = 005U,
 482     IT_F2       = 006U,
 483     IT_F3       = 007U,
 484     IT_CI       = 010U,
 485     IT_I        = 011U,
 486     IT_SC       = 012U,
 487     IT_AD       = 013U,
 488     IT_DI       = 014U,
 489     IT_DIC      = 015U,
 490     IT_ID       = 016U,
 491     IT_IDC      = 017U,
 492 
 493     // not really IT, but they're in it's namespace
 494     SPEC_ITP    = 001U,
 495     SPEC_ITS    = 003U
 496 };
 497 
 498 # define GET_TB(tag)     ((tag) & 040U)
 499 # define GET_CF(tag)     ((tag) & 007U)
 500 
 501 # define _TB(tag)        GET_TB((tag))
 502 # define _CF(tag)        GET_CF((tag))
 503 
 504 # define TB6             000U // 6-bit characters
 505 # define TB9             040U // 9-bit characters
 506 
 507 /////////////////////////////////////
 508 //
 509 // ITS/ITP
 510 //
 511 
 512 # define ISITP(x)                (((x) & INST_M_TAG) == 041U)
 513 # define GET_ITP_PRNUM(Ypair)    ((word3)  (((Ypair)[0] >> 33) & 07U))
 514 # define GET_ITP_WORDNO(Ypair)   ((word18) (((Ypair)[1] >> 18) & WMASK))
 515 # define GET_ITP_BITNO(Ypair)    ((word6)  (((Ypair)[1] >>  9) & 077U))
 516 # define GET_ITP_MOD(Ypair)      (GET_TAG((Ypair)[1]))
 517 
 518 # define ISITS(x)                (((x) & INST_M_TAG) == 043U)
 519 # define GET_ITS_SEGNO(Ypair)    ((word15) (((Ypair)[0] >> 18) & SMASK))
 520 # define GET_ITS_RN(Ypair)       ((word3)  (((Ypair)[0] >> 15) & 07))
 521 # define GET_ITS_WORDNO(Ypair)   ((word18) (((Ypair)[1] >> 18) & WMASK))
 522 # define GET_ITS_BITNO(Ypair)    ((word6)  (((Ypair)[1] >>  9) & 077))
 523 # define GET_ITS_MOD(Ypair)      (GET_TAG((Ypair)[1]))
 524 
 525 /////////////////////////////////////
 526 //
 527 // Indicator register bits
 528 //
 529 
 530 # define F_V_A           17      // Zero
 531 # define F_V_B           16      // Negative
 532 # define F_V_C           15      // Carry
 533 # define F_V_D           14      // Overflow
 534 # define F_V_E           13      // Exponent Overflow
 535 # define F_V_F           12      // Exponent Underflow
 536 # define F_V_G           11      // Overflow Mask
 537 # define F_V_H           10      // Tally Runout
 538 # define F_V_I            9      // Parity Error
 539 # define F_V_J            8      // Parity Mask
 540 # define F_V_K            7      // Not BAR mode
 541 # define F_V_L            6      // Truncation
 542 # define F_V_M            5      // Mid Instruction Interrupt Fault
 543 # define F_V_N            4      // Absolute Mode
 544 # define F_V_O            3      // Hex Mode
 545 
 546 # define F_A             (1LLU << F_V_A)
 547 # define F_B             (1LLU << F_V_B)
 548 # define F_C             (1LLU << F_V_C)
 549 # define F_D             (1LLU << F_V_D)
 550 # define F_E             (1LLU << F_V_E)
 551 # define F_F             (1LLU << F_V_F)
 552 # define F_G             (1LLU << F_V_G)
 553 # define F_H             (1LLU << F_V_H)
 554 # define F_I             (1LLU << F_V_I)
 555 # define F_J             (1LLU << F_V_J)
 556 # define F_K             (1LLU << F_V_K)
 557 # define F_L             (1LLU << F_V_L)
 558 # define F_M             (1LLU << F_V_M)
 559 # define F_N             (1LLU << F_V_N)
 560 # define F_O             (1LLU << F_V_O)
 561 
 562 # define I_HEX   F_O     // base-16 exponent                 0000010  // DPS8M only
 563 # define I_ABS   F_N     // absolute mode                    0000020
 564 # define I_MIF   F_M     // mid-instruction interrupt fault  0000040
 565 # define I_TRUNC F_L     // truncation                       0000100
 566 # define I_NBAR  F_K     // not BAR mode                     0000200
 567 # define I_PMASK F_J     // parity mask                      0000400
 568 # define I_PERR  F_I     // parity error                     0001000
 569 # define I_TALLY F_H     // tally runout                     0002000
 570 # define I_OMASK F_G     // overflow mask                    0004000
 571 # define I_EUFL  F_F     // exponent underflow               0010000
 572 # define I_EOFL  F_E     // exponent overflow                0020000
 573 # define I_OFLOW F_D     // overflow                         0040000
 574 # define I_CARRY F_C     // carry                            0100000
 575 # define I_NEG   F_B     // negative                         0200000
 576 # define I_ZERO  F_A     // zero                             0400000
 577 
 578 # define I_ZNOC (I_ZERO | I_NEG | I_OFLOW | I_CARRY)
 579 # define I_ZNC  (I_ZERO | I_NEG | I_CARRY)
 580 
 581 # define CLR_I_ABS   CLRF (cpu.cu.IR, I_ABS)
 582 # define CLR_I_MIF   CLRF (cpu.cu.IR, I_MIF)
 583 # define CLR_I_TRUNC CLRF (cpu.cu.IR, I_TRUNC)
 584 # define CLR_I_NBAR  CLRF (cpu.cu.IR, I_NBAR)
 585 # define CLR_I_TALLY CLRF (cpu.cu.IR, I_TALLY)
 586 # define CLR_I_PMASK CLRF (cpu.cu.IR, I_PMASK)
 587 # define CLR_I_EOFL  CLRF (cpu.cu.IR, I_EOFL)
 588 # define CLR_I_EUFL  CLRF (cpu.cu.IR, I_EUFL)
 589 # define CLR_I_OFLOW CLRF (cpu.cu.IR, I_OFLOW)
 590 # define CLR_I_CARRY CLRF (cpu.cu.IR, I_CARRY)
 591 # define CLR_I_NEG   CLRF (cpu.cu.IR, I_NEG)
 592 # define CLR_I_ZERO  CLRF (cpu.cu.IR, I_ZERO)
 593 
 594 # define SET_I_ABS   SETF (cpu.cu.IR, I_ABS)
 595 # define SET_I_NBAR  SETF (cpu.cu.IR, I_NBAR)
 596 # define SET_I_TRUNC SETF (cpu.cu.IR, I_TRUNC)
 597 # define SET_I_TALLY SETF (cpu.cu.IR, I_TALLY)
 598 # define SET_I_EOFL  SETF (cpu.cu.IR, I_EOFL)
 599 # define SET_I_EUFL  SETF (cpu.cu.IR, I_EUFL)
 600 # define SET_I_OFLOW SETF (cpu.cu.IR, I_OFLOW)
 601 # define SET_I_CARRY SETF (cpu.cu.IR, I_CARRY)
 602 # define SET_I_NEG   SETF (cpu.cu.IR, I_NEG)
 603 # define SET_I_ZERO  SETF (cpu.cu.IR, I_ZERO)
 604 
 605 # define TST_I_ABS   TSTF (cpu.cu.IR, I_ABS)
 606 # define TST_I_MIF   TSTF (cpu.cu.IR, I_MIF)
 607 # define TST_I_NBAR  TSTF (cpu.cu.IR, I_NBAR)
 608 # define TST_I_PMASK TSTF (cpu.cu.IR, I_PMASK)
 609 # define TST_I_TRUNC TSTF (cpu.cu.IR, I_TRUNC)
 610 # define TST_I_TALLY TSTF (cpu.cu.IR, I_TALLY)
 611 # define TST_I_OMASK TSTF (cpu.cu.IR, I_OMASK)
 612 # define TST_I_EUFL  TSTF (cpu.cu.IR, I_EUFL )
 613 # define TST_I_EOFL  TSTF (cpu.cu.IR, I_EOFL )
 614 # define TST_I_OFLOW TSTF (cpu.cu.IR, I_OFLOW)
 615 # define TST_I_CARRY TSTF (cpu.cu.IR, I_CARRY)
 616 # define TST_I_NEG   TSTF (cpu.cu.IR, I_NEG)
 617 # define TST_I_ZERO  TSTF (cpu.cu.IR, I_ZERO)
 618 # define TST_I_HEX   TSTF (cpu.cu.IR, I_HEX)
 619 
 620 # define SC_I_HEX(v)   SCF (v, cpu.cu.IR, I_HEX) // DPS8M only
 621 # define SC_I_MIF(v)   SCF (v, cpu.cu.IR, I_MIF)
 622 # define SC_I_TALLY(v) SCF (v, cpu.cu.IR, I_TALLY)
 623 # define SC_I_NEG(v)   SCF (v, cpu.cu.IR, I_NEG)
 624 # define SC_I_ZERO(v)  SCF (v, cpu.cu.IR, I_ZERO)
 625 # define SC_I_CARRY(v) SCF (v, cpu.cu.IR, I_CARRY);
 626 # define SC_I_OFLOW(v) SCF (v, cpu.cu.IR, I_OFLOW);
 627 # define SC_I_EOFL(v)  SCF (v, cpu.cu.IR, I_EOFL);
 628 # define SC_I_EUFL(v)  SCF (v, cpu.cu.IR, I_EUFL);
 629 # define SC_I_OMASK(v) SCF (v, cpu.cu.IR, I_OMASK);
 630 # define SC_I_PERR(v)  SCF (v, cpu.cu.IR, I_PERR);
 631 # define SC_I_PMASK(v) SCF (v, cpu.cu.IR, I_PMASK);
 632 # define SC_I_TRUNC(v) SCF (v, cpu.cu.IR, I_TRUNC);
 633 
 634 /////////////////////////////////////
 635 //
 636 //  floating-point constants
 637 //
 638 
 639 # define FLOAT36MASK     01777777777LLU               ///< user to extract mantissa from single precision C(CEAQ)
 640 # define FLOAT72MASK     01777777777777777777777LLU   ///< use to extract mantissa from double precision C(EAQ)
 641 # define FLOAT72SIGN     (1LLU << 63)                 ///< mantissa sign mask for full precision C(EAQ)
 642 // XXX beware the 72's are not what they seem!
 643 
 644 /////////////////////////////////////
 645 //
 646 // Faults
 647 //
 648 
 649 # define N_FAULT_GROUPS 7
 650 # define N_FAULTS 32
 651 
 652 enum _fault
 653   {
 654     FAULT_SDF  =  0U, // shutdown fault
 655     FAULT_STR  =  1U, // store fault
 656     FAULT_MME  =  2U, // master mode entry
 657     FAULT_F1   =  3U, // fault tag 1
 658     FAULT_TRO  =  4U, // timer runout fault
 659     FAULT_CMD  =  5U, // command
 660     FAULT_DRL  =  6U, // derail
 661     FAULT_LUF  =  7U, // lockup
 662     FAULT_CON  =  8U, // connect
 663     FAULT_PAR  =  9U, // parity
 664     FAULT_IPR  = 10U, // illegal procedure
 665     FAULT_ONC  = 11U, // operation not complete
 666     FAULT_SUF  = 12U, // startup
 667     FAULT_OFL  = 13U, // overflow
 668     FAULT_DIV  = 14U, // divide check
 669     FAULT_EXF  = 15U, // execute
 670     FAULT_DF0  = 16U, // directed fault 0
 671     FAULT_DF1  = 17U, // directed fault 1
 672     FAULT_DF2  = 18U, // directed fault 2
 673     FAULT_DF3  = 19U, // directed fault 3
 674     FAULT_ACV  = 20U, // access violation
 675     FAULT_MME2 = 21U, // Master mode entry 2
 676     FAULT_MME3 = 22U, // Master mode entry 3
 677     FAULT_MME4 = 23U, // Master mode entry 4
 678     FAULT_F2   = 24U, // fault tag 2
 679     FAULT_F3   = 25U, // fault tag 3
 680     FAULT_UN1  = 26U, // unassigned
 681     FAULT_UN2  = 27U, // unassigned
 682     FAULT_UN3  = 28U, // unassigned
 683     FAULT_UN4  = 29U, // unassigned
 684     FAULT_UN5  = 30U, // unassigned
 685     FAULT_TRB  = 31U  // Trouble
 686   };
 687 
 688 # define FAULTBASE_MASK  07740U       ///< mask off all but top 7 msb
 689 
 690 typedef enum _fault _fault;
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 746 typedef enum fault_onc_subtype_
 747   {
 748     flt_onc_nem,        // A nonexistent main memory address has been requested.
 749     flt_onc_FORCE  = 0400000000000llu // Force enum size to 36 bits.
 750   } fault_onc_subtype_;
 751 
 752 typedef enum fault_str_subtype_
 753   {
 754     flt_str_oob,        // A BAR mode boundary violation has occurred.
 755     flt_str_ill_ptr,    // SPRPn illegal ptr.
 756     flt_str_nea,        // non-existent address
 757     flt_str_FORCE  = 0400000000000llu // Force enum size to 36 bits.
 758   } fault_str_subtype_;
 759 
 760 typedef enum fault_con_subtype_
 761   {
 762     con_a         = 0,  // A $CONNECT signal has been received through port A.
 763     con_b         = 1,  // A $CONNECT signal has been received through port B.
 764     con_c         = 2,  // A $CONNECT signal has been received through port C.
 765     con_d         = 3,  // A $CONNECT signal has been received through port D.
 766     flt_con_FORCE = 0400000000000llu // Force enum size to 36 bits.
 767   } fault_con_subtype_;
 768 
 769 typedef enum fault_acv_subtype_
 770   {
 771     ACV0          = (1U << 15),   ///< 15.Illegal ring order (ACV0=IRO)
 772     ACV1          = (1U << 14),   ///< 3. Not in execute bracket (ACV1=OEB)
 773     ACV2          = (1U << 13),   ///< 6. No execute permission (ACV2=E-OFF)
 774     ACV3          = (1U << 12),   ///< 1. Not in read bracket (ACV3=ORB)
 775     ACV4          = (1U << 11),   ///< 4. No read permission (ACV4=R-OFF)
 776     ACV5          = (1U << 10),   ///< 2. Not in write bracket (ACV5=OWB)
 777     ACV6          = (1U <<  9),   ///< 5. No write permission (ACV6=W-OFF)
 778     ACV7          = (1U <<  8),   ///< 8. Call limiter fault (ACV7=NO GA)
 779     ACV8          = (1U <<  7),   ///< 16.Out of call brackets (ACV8=OCB)
 780     ACV9          = (1U <<  6),   ///< 9. Outward call (ACV9=OCALL)
 781     ACV10         = (1U <<  5),   ///< 10.Bad outward call (ACV10=BOC)
 782     ACV11         = (1U <<  4),   ///< 11.Inward return (ACV11=INRET)
 783     ACV12         = (1U <<  3),   ///< 7. Invalid ring crossing (ACV12=CRT)
 784     ACV13         = (1U <<  2),   ///< 12.Ring alarm (ACV13=RALR)
 785     ACV14         = (1U <<  1),   ///< 13.Associative memory error
 786     ACV15         = (1U <<  0),   ///< 14.Out of segment bounds (ACV15=OOSB)
 787     flt_acv_FORCE = 0400000000000llu // Force enum size to 36 bits.
 788   } fault_acv_subtype_;
 789 
 790 # define FR_ILL_OP_CONST  0400000000000llu
 791 # define FR_ILL_MOD_CONST 0200000000000llu
 792 # define FR_ILL_SLV_CONST 0100000000000llu
 793 
 794 typedef enum fault_ipr_subtype_
 795   {
 796     FR_ILL_OP       = FR_ILL_OP_CONST,  //  0 a ILL OP
 797     FR_ILL_MOD      = FR_ILL_MOD_CONST, //  1 b ILL MOD
 798     FR_ILL_SLV      = FR_ILL_SLV_CONST, //  2 c ILL SLV
 799     FR_ILL_PROC     = 0040000000000llu, //  3 d ILL PROC
 800     FR_ILL_PROC_MOD = 0240000000000llu, //  1,3 d ILL PROC | ILL MOD
 801     FR_NEM          = 0020000000000llu, //  4 e NEM
 802     FR_OOB          = 0010000000000llu, //  5 f OOB
 803     FR_ILL_DIG      = 0004000000000llu, //  6 g ILL DIG
 804     FR_PROC_PARU    = 0002000000000llu, //  7 h PROC PARU
 805     FR_PROC_PARL    = 0001000000000llu, //  8 i PROC PARU
 806     FR_CON_A        = 0000400000000llu, //  9 j $CON A
 807     FR_CON_B        = 0000200000000llu, // 10 k $CON B
 808     FR_CON_C        = 0000100000000llu, // 11 l $CON C
 809     FR_CON_D        = 0000040000000llu, // 12 m $CON D
 810     FR_DA_ERR       = 0000020000000llu, // 13 n DA ERR
 811     FR_DA_ERR2      = 0000010000000llu  // 14 o DA ERR2
 812   } fault_ipr_subtype_;
 813 
 814 typedef enum fault_cmd_subtype_
 815   {
 816     flt_cmd_lprpn_bits,  // illegal bits in lprpn instruction
 817     flt_cmd_not_control,  // not control
 818     flt_cmd_FORCE  = 0400000000000llu // Force enum size to 36 bits.
 819   } fault_cmd_subtype_;
 820 
 821 typedef union _fault_subtype
 822   {
 823     fault_onc_subtype_ fault_onc_subtype;
 824     fault_str_subtype_ fault_str_subtype;
 825     fault_con_subtype_ fault_con_subtype;
 826     fault_acv_subtype_ fault_acv_subtype;
 827     fault_ipr_subtype_ fault_ipr_subtype;
 828     fault_cmd_subtype_ fault_cmd_subtype;
 829     word36 bits;
 830   } _fault_subtype;
 831 
 832 // Fault Register bits
 833 enum _faultRegisterBits0
 834   {
 835     FR_IA_MASK   = 017,
 836     FR_IAA_SHIFT =  16,  // 0000003600000llu,
 837     FR_IAB_SHIFT =  12,  // 0000000170000llu,
 838     FR_IAC_SHIFT =   8,  // 0000000007400llu,
 839     FR_IAD_SHIFT =   4,  // 0000000000360llu,
 840 
 841     FR_CPAR_DIR  = 0000000000010llu, // 32 p CPAR DIR
 842     FR_CPAR_STR  = 0000000000004llu, // 33 q CPAR STR
 843     FR_CPAR_IA   = 0000000000002llu, // 34 r CPAR IA
 844     FR_CPAR_BLK  = 0000000000001llu  // 35 s CPAR BLK
 845   };
 846 
 847 enum _faultRegisterBits1
 848   {
 849      FR_PORT_A    = 0400000000000llu, //  0 t PORT A
 850      FR_PORT_B    = 0200000000000llu, //  1 u PORT B
 851      FR_PORT_C    = 0100000000000llu, //  2 v PORT C
 852      FR_PORT_D    = 0040000000000llu, //  3 w PORT D
 853      FR_WNO_BO    = 0020000000000llu, //  4 x Cache Primary Directory WNO Buffer Overflow
 854      FR_WNO_PAR   = 0010000000000llu, //  5 y Write Notify (WNO) Parity Error on Port A, B, C or D.
 855      FR_LEVEL_0   = 0004000000000llu, //  6 z Level 0
 856      FR_LEVEL_1   = 0002000000000llu, //  7 A Level 1
 857      FR_LEVEL_2   = 0001000000000llu, //  8 B Level 2
 858      FR_LEVEL_3   = 0000400000000llu, //  0 C Level 3
 859      FR_CDDMM     = 0000200000000llu, // 10 D Cache Duplicate Directory Multiple Match
 860      FR_PAR_SDWAM = 0000100000000llu, // 11 E SDWAM parity error
 861      FR_PAR_PTWAM = 0000040000000llu  // 12 F PTWAM parity error
 862   };
 863 
 864 enum _systemControllerIllegalActionCodes
 865   {
 866     SCIAC_NONE    = 000,
 867     SCIAC_NEA     = 002,
 868     SCIAC_SOC     = 003,
 869     SCIAC_PAR5    = 005,
 870     SCIAC_PAR6    = 006,
 871     SCIAC_PAR7    = 007,
 872     SCIAC_NC      = 010,
 873     SCIAC_PNE     = 011,
 874     SCIAC_ILL_CMD = 012,
 875     SCIAC_NR      = 013,
 876     SCIAC_PAR14   = 014,
 877     SCIAC_PAR15   = 015,
 878     SCIAC_PAR16   = 016,
 879     SCIAC_PAR17   = 017
 880   };
 881 
 882 /////////////////////////////////////
 883 //
 884 // Interrupts
 885 //
 886 
 887 # define N_INTERRUPTS 32
 888 
 889 /////////////////////////////////////
 890 //
 891 // Memory map
 892 //
 893 
 894 # define IOM_MBX_LOW   01200
 895 # define IOM_MBX_LEN   02200
 896 # define DN355_MBX_LOW 03400
 897 # define DN355_MBX_LEN 03000
 898 
 899 /////////////////////////////////////
 900 //
 901 // Opcodes
 902 //
 903 
 904 // MM's opcode stuff ...
 905 
 906 // Opcodes with low bit (bit 27) == 0.  Enum value is value of upper 9 bits.
 907 typedef enum {
 908         opcode0_mme    = 0001U, // (1 decimal)
 909         opcode0_drl    = 0002U, // (2 decimal)
 910         opcode0_mme2   = 0004U, // (4 decimal)
 911         opcode0_mme3   = 0005U, // (5 decimal)
 912         opcode0_mme4   = 0007U, // (7 decimal)
 913         opcode0_nop    = 0011U, // (9 decimal)
 914         opcode0_puls1  = 0012U, // (10 decimal)
 915         opcode0_puls2  = 0013U, // (11 decimal)
 916         opcode0_cioc   = 0015U, // (13 decimal)
 917         opcode0_adlx0  = 0020U, // (16 decimal)
 918         opcode0_adlx1  = 0021U, // (17 decimal)
 919         opcode0_adlx2  = 0022U, // (18 decimal)
 920         opcode0_adlx3  = 0023U, // (19 decimal)
 921         opcode0_adlx4  = 0024U, // (20 decimal)
 922         opcode0_adlx5  = 0025U, // (21 decimal)
 923         opcode0_adlx6  = 0026U, // (22 decimal)
 924         opcode0_adlx7  = 0027U, // (23 decimal)
 925         opcode0_ldqc   = 0032U, // (26 decimal)
 926         opcode0_adl    = 0033U, // (27 decimal)
 927         opcode0_ldac   = 0034U, // (28 decimal)
 928         opcode0_adla   = 0035U, // (29 decimal)
 929         opcode0_adlq   = 0036U, // (30 decimal)
 930         opcode0_adlaq  = 0037U, // (31 decimal)
 931         opcode0_asx0   = 0040U, // (32 decimal)
 932         opcode0_asx1   = 0041U, // (33 decimal)
 933         opcode0_asx2   = 0042U, // (34 decimal)
 934         opcode0_asx3   = 0043U, // (35 decimal)
 935         opcode0_asx4   = 0044U, // (36 decimal)
 936         opcode0_asx5   = 0045U, // (37 decimal)
 937         opcode0_asx6   = 0046U, // (38 decimal)
 938         opcode0_asx7   = 0047U, // (39 decimal)
 939         opcode0_adwp0  = 0050U, // (40 decimal)
 940         opcode0_adwp1  = 0051U, // (41 decimal)
 941         opcode0_adwp2  = 0052U, // (42 decimal)
 942         opcode0_adwp3  = 0053U, // (43 decimal)
 943         opcode0_aos    = 0054U, // (44 decimal)
 944         opcode0_asa    = 0055U, // (45 decimal)
 945         opcode0_asq    = 0056U, // (46 decimal)
 946         opcode0_sscr   = 0057U, // (47 decimal)
 947         opcode0_adx0   = 0060U, // (48 decimal)
 948         opcode0_adx1   = 0061U, // (49 decimal)
 949         opcode0_adx2   = 0062U, // (50 decimal)
 950         opcode0_adx3   = 0063U, // (51 decimal)
 951         opcode0_adx4   = 0064U, // (52 decimal)
 952         opcode0_adx5   = 0065U, // (53 decimal)
 953         opcode0_adx6   = 0066U, // (54 decimal)
 954         opcode0_adx7   = 0067U, // (55 decimal)
 955         opcode0_awca   = 0071U, // (57 decimal)
 956         opcode0_awcq   = 0072U, // (58 decimal)
 957         opcode0_lreg   = 0073U, // (59 decimal)
 958         opcode0_ada    = 0075U, // (61 decimal)
 959         opcode0_adq    = 0076U, // (62 decimal)
 960         opcode0_adaq   = 0077U, // (63 decimal)
 961         opcode0_cmpx0  = 0100U, // (64 decimal)
 962         opcode0_cmpx1  = 0101U, // (65 decimal)
 963         opcode0_cmpx2  = 0102U, // (66 decimal)
 964         opcode0_cmpx3  = 0103U, // (67 decimal)
 965         opcode0_cmpx4  = 0104U, // (68 decimal)
 966         opcode0_cmpx5  = 0105U, // (69 decimal)
 967         opcode0_cmpx6  = 0106U, // (70 decimal)
 968         opcode0_cmpx7  = 0107U, // (71 decimal)
 969         opcode0_cwl    = 0111U, // (73 decimal)
 970         opcode0_cmpa   = 0115U, // (77 decimal)
 971         opcode0_cmpq   = 0116U, // (78 decimal)
 972         opcode0_cmpaq  = 0117U, // (79 decimal)
 973         opcode0_sblx0  = 0120U, // (80 decimal)
 974         opcode0_sblx1  = 0121U, // (81 decimal)
 975         opcode0_sblx2  = 0122U, // (82 decimal)
 976         opcode0_sblx3  = 0123U, // (83 decimal)
 977         opcode0_sblx4  = 0124U, // (84 decimal)
 978         opcode0_sblx5  = 0125U, // (85 decimal)
 979         opcode0_sblx6  = 0126U, // (86 decimal)
 980         opcode0_sblx7  = 0127U, // (87 decimal)
 981         opcode0_sbla   = 0135U, // (93 decimal)
 982         opcode0_sblq   = 0136U, // (94 decimal)
 983         opcode0_sblaq  = 0137U, // (95 decimal)
 984         opcode0_ssx0   = 0140U, // (96 decimal)
 985         opcode0_ssx1   = 0141U, // (97 decimal)
 986         opcode0_ssx2   = 0142U, // (98 decimal)
 987         opcode0_ssx3   = 0143U, // (99 decimal)
 988         opcode0_ssx4   = 0144U, // (100 decimal)
 989         opcode0_ssx5   = 0145U, // (101 decimal)
 990         opcode0_ssx6   = 0146U, // (102 decimal)
 991         opcode0_ssx7   = 0147U, // (103 decimal)
 992         opcode0_adwp4  = 0150U, // (104 decimal)
 993         opcode0_adwp5  = 0151U, // (105 decimal)
 994         opcode0_adwp6  = 0152U, // (106 decimal)
 995         opcode0_adwp7  = 0153U, // (107 decimal)
 996         opcode0_sdbr   = 0154U, // (108 decimal)
 997         opcode0_ssa    = 0155U, // (109 decimal)
 998         opcode0_ssq    = 0156U, // (110 decimal)
 999         opcode0_sbx0   = 0160U, // (112 decimal)
1000         opcode0_sbx1   = 0161U, // (113 decimal)
1001         opcode0_sbx2   = 0162U, // (114 decimal)
1002         opcode0_sbx3   = 0163U, // (115 decimal)
1003         opcode0_sbx4   = 0164U, // (116 decimal)
1004         opcode0_sbx5   = 0165U, // (117 decimal)
1005         opcode0_sbx6   = 0166U, // (118 decimal)
1006         opcode0_sbx7   = 0167U, // (119 decimal)
1007         opcode0_swca   = 0171U, // (121 decimal)
1008         opcode0_swcq   = 0172U, // (122 decimal)
1009         opcode0_lpri   = 0173U, // (123 decimal)
1010         opcode0_sba    = 0175U, // (125 decimal)
1011         opcode0_sbq    = 0176U, // (126 decimal)
1012         opcode0_sbaq   = 0177U, // (127 decimal)
1013         opcode0_cnax0  = 0200U, // (128 decimal)
1014         opcode0_cnax1  = 0201U, // (129 decimal)
1015         opcode0_cnax2  = 0202U, // (130 decimal)
1016         opcode0_cnax3  = 0203U, // (131 decimal)
1017         opcode0_cnax4  = 0204U, // (132 decimal)
1018         opcode0_cnax5  = 0205U, // (133 decimal)
1019         opcode0_cnax6  = 0206U, // (134 decimal)
1020         opcode0_cnax7  = 0207U, // (135 decimal)
1021         opcode0_cmk    = 0211U, // (137 decimal)
1022         opcode0_absa   = 0212U, // (138 decimal)
1023         opcode0_epaq   = 0213U, // (139 decimal)
1024         opcode0_sznc   = 0214U, // (140 decimal)
1025         opcode0_cnaa   = 0215U, // (141 decimal)
1026         opcode0_cnaq   = 0216U, // (142 decimal)
1027         opcode0_cnaaq  = 0217U, // (143 decimal)
1028         opcode0_ldx0   = 0220U, // (144 decimal)
1029         opcode0_ldx1   = 0221U, // (145 decimal)
1030         opcode0_ldx2   = 0222U, // (146 decimal)
1031         opcode0_ldx3   = 0223U, // (147 decimal)
1032         opcode0_ldx4   = 0224U, // (148 decimal)
1033         opcode0_ldx5   = 0225U, // (149 decimal)
1034         opcode0_ldx6   = 0226U, // (150 decimal)
1035         opcode0_ldx7   = 0227U, // (151 decimal)
1036         opcode0_lbar   = 0230U, // (152 decimal)
1037         opcode0_rsw    = 0231U, // (153 decimal)
1038         opcode0_ldbr   = 0232U, // (154 decimal)
1039         opcode0_rmcm   = 0233U, // (155 decimal)
1040         opcode0_szn    = 0234U, // (156 decimal)
1041         opcode0_lda    = 0235U, // (157 decimal)
1042         opcode0_ldq    = 0236U, // (158 decimal)
1043         opcode0_ldaq   = 0237U, // (159 decimal)
1044         opcode0_orsx0  = 0240U, // (160 decimal)
1045         opcode0_orsx1  = 0241U, // (161 decimal)
1046         opcode0_orsx2  = 0242U, // (162 decimal)
1047         opcode0_orsx3  = 0243U, // (163 decimal)
1048         opcode0_orsx4  = 0244U, // (164 decimal)
1049         opcode0_orsx5  = 0245U, // (165 decimal)
1050         opcode0_orsx6  = 0246U, // (166 decimal)
1051         opcode0_orsx7  = 0247U, // (167 decimal)
1052         opcode0_spri0  = 0250U, // (168 decimal)
1053         opcode0_spbp1  = 0251U, // (169 decimal)
1054         opcode0_spri2  = 0252U, // (170 decimal)
1055         opcode0_spbp3  = 0253U, // (171 decimal)
1056         opcode0_spri   = 0254U, // (172 decimal)
1057         opcode0_orsa   = 0255U, // (173 decimal)
1058         opcode0_orsq   = 0256U, // (174 decimal)
1059         opcode0_lsdp   = 0257U, // (175 decimal)
1060         opcode0_orx0   = 0260U, // (176 decimal)
1061         opcode0_orx1   = 0261U, // (177 decimal)
1062         opcode0_orx2   = 0262U, // (178 decimal)
1063         opcode0_orx3   = 0263U, // (179 decimal)
1064         opcode0_orx4   = 0264U, // (180 decimal)
1065         opcode0_orx5   = 0265U, // (181 decimal)
1066         opcode0_orx6   = 0266U, // (182 decimal)
1067         opcode0_orx7   = 0267U, // (183 decimal)
1068         opcode0_tsp0   = 0270U, // (184 decimal)
1069         opcode0_tsp1   = 0271U, // (185 decimal)
1070         opcode0_tsp2   = 0272U, // (186 decimal)
1071         opcode0_tsp3   = 0273U, // (187 decimal)
1072         opcode0_ora    = 0275U, // (189 decimal)
1073         opcode0_orq    = 0276U, // (190 decimal)
1074         opcode0_oraq   = 0277U, // (191 decimal)
1075         opcode0_canx0  = 0300U, // (192 decimal)
1076         opcode0_canx1  = 0301U, // (193 decimal)
1077         opcode0_canx2  = 0302U, // (194 decimal)
1078         opcode0_canx3  = 0303U, // (195 decimal)
1079         opcode0_canx4  = 0304U, // (196 decimal)
1080         opcode0_canx5  = 0305U, // (197 decimal)
1081         opcode0_canx6  = 0306U, // (198 decimal)
1082         opcode0_canx7  = 0307U, // (199 decimal)
1083         opcode0_eawp0  = 0310U, // (200 decimal)
1084         opcode0_easp0  = 0311U, // (201 decimal)
1085         opcode0_eawp2  = 0312U, // (202 decimal)
1086         opcode0_easp2  = 0313U, // (203 decimal)
1087         opcode0_cana   = 0315U, // (205 decimal)
1088         opcode0_canq   = 0316U, // (206 decimal)
1089         opcode0_canaq  = 0317U, // (207 decimal)
1090         opcode0_lcx0   = 0320U, // (208 decimal)
1091         opcode0_lcx1   = 0321U, // (209 decimal)
1092         opcode0_lcx2   = 0322U, // (210 decimal)
1093         opcode0_lcx3   = 0323U, // (211 decimal)
1094         opcode0_lcx4   = 0324U, // (212 decimal)
1095         opcode0_lcx5   = 0325U, // (213 decimal)
1096         opcode0_lcx6   = 0326U, // (214 decimal)
1097         opcode0_lcx7   = 0327U, // (215 decimal)
1098         opcode0_eawp4  = 0330U, // (216 decimal)
1099         opcode0_easp4  = 0331U, // (217 decimal)
1100         opcode0_eawp6  = 0332U, // (218 decimal)
1101         opcode0_easp6  = 0333U, // (219 decimal)
1102         opcode0_lca    = 0335U, // (221 decimal)
1103         opcode0_lcq    = 0336U, // (222 decimal)
1104         opcode0_lcaq   = 0337U, // (223 decimal)
1105         opcode0_ansx0  = 0340U, // (224 decimal)
1106         opcode0_ansx1  = 0341U, // (225 decimal)
1107         opcode0_ansx2  = 0342U, // (226 decimal)
1108         opcode0_ansx3  = 0343U, // (227 decimal)
1109         opcode0_ansx4  = 0344U, // (228 decimal)
1110         opcode0_ansx5  = 0345U, // (229 decimal)
1111         opcode0_ansx6  = 0346U, // (230 decimal)
1112         opcode0_ansx7  = 0347U, // (231 decimal)
1113         opcode0_epp0   = 0350U, // (232 decimal)
1114         opcode0_epbp1  = 0351U, // (233 decimal)
1115         opcode0_epp2   = 0352U, // (234 decimal)
1116         opcode0_epbp3  = 0353U, // (235 decimal)
1117         opcode0_stac   = 0354U, // (236 decimal)
1118         opcode0_ansa   = 0355U, // (237 decimal)
1119         opcode0_ansq   = 0356U, // (238 decimal)
1120         opcode0_stcd   = 0357U, // (239 decimal)
1121         opcode0_anx0   = 0360U, // (240 decimal)
1122         opcode0_anx1   = 0361U, // (241 decimal)
1123         opcode0_anx2   = 0362U, // (242 decimal)
1124         opcode0_anx3   = 0363U, // (243 decimal)
1125         opcode0_anx4   = 0364U, // (244 decimal)
1126         opcode0_anx5   = 0365U, // (245 decimal)
1127         opcode0_anx6   = 0366U, // (246 decimal)
1128         opcode0_anx7   = 0367U, // (247 decimal)
1129         opcode0_epp4   = 0370U, // (248 decimal)
1130         opcode0_epbp5  = 0371U, // (249 decimal)
1131         opcode0_epp6   = 0372U, // (250 decimal)
1132         opcode0_epbp7  = 0373U, // (251 decimal)
1133         opcode0_ana    = 0375U, // (253 decimal)
1134         opcode0_anq    = 0376U, // (254 decimal)
1135         opcode0_anaq   = 0377U, // (255 decimal)
1136         opcode0_mpf    = 0401U, // (257 decimal)
1137         opcode0_mpy    = 0402U, // (258 decimal)
1138         opcode0_cmg    = 0405U, // (261 decimal)
1139         opcode0_lde    = 0411U, // (265 decimal)
1140         opcode0_rscr   = 0413U, // (267 decimal)
1141         opcode0_ade    = 0415U, // (269 decimal)
1142         opcode0_ufm    = 0421U, // (273 decimal)
1143         opcode0_dufm   = 0423U, // (275 decimal)
1144         opcode0_fcmg   = 0425U, // (277 decimal)
1145         opcode0_dfcmg  = 0427U, // (279 decimal)
1146         opcode0_fszn   = 0430U, // (280 decimal)
1147         opcode0_fld    = 0431U, // (281 decimal)
1148         opcode0_dfld   = 0433U, // (283 decimal)
1149         opcode0_ufa    = 0435U, // (285 decimal)
1150         opcode0_dufa   = 0437U, // (287 decimal)
1151         opcode0_sxl0   = 0440U, // (288 decimal)
1152         opcode0_sxl1   = 0441U, // (289 decimal)
1153         opcode0_sxl2   = 0442U, // (290 decimal)
1154         opcode0_sxl3   = 0443U, // (291 decimal)
1155         opcode0_sxl4   = 0444U, // (292 decimal)
1156         opcode0_sxl5   = 0445U, // (293 decimal)
1157         opcode0_sxl6   = 0446U, // (294 decimal)
1158         opcode0_sxl7   = 0447U, // (295 decimal)
1159         opcode0_stz    = 0450U, // (296 decimal)
1160         opcode0_smic   = 0451U, // (297 decimal)
1161         opcode0_scpr   = 0452U, // (298 decimal)
1162         opcode0_stt    = 0454U, // (300 decimal)
1163         opcode0_fst    = 0455U, // (301 decimal)
1164         opcode0_ste    = 0456U, // (302 decimal)
1165         opcode0_dfst   = 0457U, // (303 decimal)
1166         opcode0_fmp    = 0461U, // (305 decimal)
1167         opcode0_dfmp   = 0463U, // (307 decimal)
1168         opcode0_fstr   = 0470U, // (312 decimal)
1169         opcode0_frd    = 0471U, // (313 decimal)
1170         opcode0_dfstr  = 0472U, // (314 decimal)
1171         opcode0_dfrd   = 0473U, // (315 decimal)
1172         opcode0_fad    = 0475U, // (317 decimal)
1173         opcode0_dfad   = 0477U, // (319 decimal)
1174         opcode0_rpl    = 0500U, // (320 decimal)
1175         opcode0_bcd    = 0505U, // (325 decimal)
1176         opcode0_div    = 0506U, // (326 decimal)
1177         opcode0_dvf    = 0507U, // (327 decimal)
1178         opcode0_fneg   = 0513U, // (331 decimal)
1179         opcode0_fcmp   = 0515U, // (333 decimal)
1180         opcode0_dfcmp  = 0517U, // (335 decimal)
1181         opcode0_rpt    = 0520U, // (336 decimal)
1182         opcode0_fdi    = 0525U, // (341 decimal)
1183         opcode0_dfdi   = 0527U, // (343 decimal)
1184         opcode0_neg    = 0531U, // (345 decimal)
1185         opcode0_cams   = 0532U, // (346 decimal)
1186         opcode0_negl   = 0533U, // (347 decimal)
1187         opcode0_ufs    = 0535U, // (349 decimal)
1188         opcode0_dufs   = 0537U, // (351 decimal)
1189         opcode0_sprp0  = 0540U, // (352 decimal)
1190         opcode0_sprp1  = 0541U, // (353 decimal)
1191         opcode0_sprp2  = 0542U, // (354 decimal)
1192         opcode0_sprp3  = 0543U, // (355 decimal)
1193         opcode0_sprp4  = 0544U, // (356 decimal)
1194         opcode0_sprp5  = 0545U, // (357 decimal)
1195         opcode0_sprp6  = 0546U, // (358 decimal)
1196         opcode0_sprp7  = 0547U, // (359 decimal)
1197         opcode0_sbar   = 0550U, // (360 decimal)
1198         opcode0_stba   = 0551U, // (361 decimal)
1199         opcode0_stbq   = 0552U, // (362 decimal)
1200         opcode0_smcm   = 0553U, // (363 decimal)
1201         opcode0_stc1   = 0554U, // (364 decimal)
1202         opcode0_ssdp   = 0557U, // (367 decimal)
1203         opcode0_rpd    = 0560U, // (368 decimal)
1204         opcode0_fdv    = 0565U, // (373 decimal)
1205         opcode0_dfdv   = 0567U, // (375 decimal)
1206         opcode0_fno    = 0573U, // (379 decimal)
1207         opcode0_fsb    = 0575U, // (381 decimal)
1208         opcode0_dfsb   = 0577U, // (383 decimal)
1209         opcode0_tze    = 0600U, // (384 decimal)
1210         opcode0_tnz    = 0601U, // (385 decimal)
1211         opcode0_tnc    = 0602U, // (386 decimal)
1212         opcode0_trc    = 0603U, // (387 decimal)
1213         opcode0_tmi    = 0604U, // (388 decimal)
1214         opcode0_tpl    = 0605U, // (389 decimal)
1215         opcode0_ttf    = 0607U, // (391 decimal)
1216         opcode0_rtcd   = 0610U, // (392 decimal)
1217         opcode0_rcu    = 0613U, // (395 decimal)
1218         opcode0_teo    = 0614U, // (396 decimal)
1219         opcode0_teu    = 0615U, // (397 decimal)
1220         opcode0_dis    = 0616U, // (398 decimal)
1221         opcode0_tov    = 0617U, // (399 decimal)
1222         opcode0_eax0   = 0620U, // (400 decimal)
1223         opcode0_eax1   = 0621U, // (401 decimal)
1224         opcode0_eax2   = 0622U, // (402 decimal)
1225         opcode0_eax3   = 0623U, // (403 decimal)
1226         opcode0_eax4   = 0624U, // (404 decimal)
1227         opcode0_eax5   = 0625U, // (405 decimal)
1228         opcode0_eax6   = 0626U, // (406 decimal)
1229         opcode0_eax7   = 0627U, // (407 decimal)
1230         opcode0_ret    = 0630U, // (408 decimal)
1231         opcode0_rccl   = 0633U, // (411 decimal)
1232         opcode0_ldi    = 0634U, // (412 decimal)
1233         opcode0_eaa    = 0635U, // (413 decimal)
1234         opcode0_eaq    = 0636U, // (414 decimal)
1235         opcode0_ldt    = 0637U, // (415 decimal)
1236         opcode0_ersx0  = 0640U, // (416 decimal)
1237         opcode0_ersx1  = 0641U, // (417 decimal)
1238         opcode0_ersx2  = 0642U, // (418 decimal)
1239         opcode0_ersx3  = 0643U, // (419 decimal)
1240         opcode0_ersx4  = 0644U, // (420 decimal)
1241         opcode0_ersx5  = 0645U, // (421 decimal)
1242         opcode0_ersx6  = 0646U, // (422 decimal)
1243         opcode0_ersx7  = 0647U, // (423 decimal)
1244         opcode0_spri4  = 0650U, // (424 decimal)
1245         opcode0_spbp5  = 0651U, // (425 decimal)
1246         opcode0_spri6  = 0652U, // (426 decimal)
1247         opcode0_spbp7  = 0653U, // (427 decimal)
1248         opcode0_stacq  = 0654U, // (428 decimal)
1249         opcode0_ersa   = 0655U, // (429 decimal)
1250         opcode0_ersq   = 0656U, // (430 decimal)
1251         opcode0_scu    = 0657U, // (431 decimal)
1252         opcode0_erx0   = 0660U, // (432 decimal)
1253         opcode0_erx1   = 0661U, // (433 decimal)
1254         opcode0_erx2   = 0662U, // (434 decimal)
1255         opcode0_erx3   = 0663U, // (435 decimal)
1256         opcode0_erx4   = 0664U, // (436 decimal)
1257         opcode0_erx5   = 0665U, // (437 decimal)
1258         opcode0_erx6   = 0666U, // (438 decimal)
1259         opcode0_erx7   = 0667U, // (439 decimal)
1260         opcode0_tsp4   = 0670U, // (440 decimal)
1261         opcode0_tsp5   = 0671U, // (441 decimal)
1262         opcode0_tsp6   = 0672U, // (442 decimal)
1263         opcode0_tsp7   = 0673U, // (443 decimal)
1264         opcode0_lcpr   = 0674U, // (444 decimal)
1265         opcode0_era    = 0675U, // (445 decimal)
1266         opcode0_erq    = 0676U, // (446 decimal)
1267         opcode0_eraq   = 0677U, // (447 decimal)
1268         opcode0_tsx0   = 0700U, // (448 decimal)
1269         opcode0_tsx1   = 0701U, // (449 decimal)
1270         opcode0_tsx2   = 0702U, // (450 decimal)
1271         opcode0_tsx3   = 0703U, // (451 decimal)
1272         opcode0_tsx4   = 0704U, // (452 decimal)
1273         opcode0_tsx5   = 0705U, // (453 decimal)
1274         opcode0_tsx6   = 0706U, // (454 decimal)
1275         opcode0_tsx7   = 0707U, // (455 decimal)
1276         opcode0_tra    = 0710U, // (456 decimal)
1277         opcode0_call6  = 0713U, // (459 decimal)
1278         opcode0_tss    = 0715U, // (461 decimal)
1279         opcode0_xec    = 0716U, // (462 decimal)
1280         opcode0_xed    = 0717U, // (463 decimal)
1281         opcode0_lxl0   = 0720U, // (464 decimal)
1282         opcode0_lxl1   = 0721U, // (465 decimal)
1283         opcode0_lxl2   = 0722U, // (466 decimal)
1284         opcode0_lxl3   = 0723U, // (467 decimal)
1285         opcode0_lxl4   = 0724U, // (468 decimal)
1286         opcode0_lxl5   = 0725U, // (469 decimal)
1287         opcode0_lxl6   = 0726U, // (470 decimal)
1288         opcode0_lxl7   = 0727U, // (471 decimal)
1289         opcode0_ars    = 0731U, // (473 decimal)
1290         opcode0_qrs    = 0732U, // (474 decimal)
1291         opcode0_lrs    = 0733U, // (475 decimal)
1292         opcode0_als    = 0735U, // (477 decimal)
1293         opcode0_qls    = 0736U, // (478 decimal)
1294         opcode0_lls    = 0737U, // (479 decimal)
1295         opcode0_stx0   = 0740U, // (480 decimal)
1296         opcode0_stx1   = 0741U, // (481 decimal)
1297         opcode0_stx2   = 0742U, // (482 decimal)
1298         opcode0_stx3   = 0743U, // (483 decimal)
1299         opcode0_stx4   = 0744U, // (484 decimal)
1300         opcode0_stx5   = 0745U, // (485 decimal)
1301         opcode0_stx6   = 0746U, // (486 decimal)
1302         opcode0_stx7   = 0747U, // (487 decimal)
1303         opcode0_stc2   = 0750U, // (488 decimal)
1304         opcode0_stca   = 0751U, // (489 decimal)
1305         opcode0_stcq   = 0752U, // (490 decimal)
1306         opcode0_sreg   = 0753U, // (491 decimal)
1307         opcode0_sti    = 0754U, // (492 decimal)
1308         opcode0_sta    = 0755U, // (493 decimal)
1309         opcode0_stq    = 0756U, // (494 decimal)
1310         opcode0_staq   = 0757U, // (495 decimal)
1311         opcode0_lprp0  = 0760U, // (496 decimal)
1312         opcode0_lprp1  = 0761U, // (497 decimal)
1313         opcode0_lprp2  = 0762U, // (498 decimal)
1314         opcode0_lprp3  = 0763U, // (499 decimal)
1315         opcode0_lprp4  = 0764U, // (500 decimal)
1316         opcode0_lprp5  = 0765U, // (501 decimal)
1317         opcode0_lprp6  = 0766U, // (502 decimal)
1318         opcode0_lprp7  = 0767U, // (503 decimal)
1319         opcode0_arl    = 0771U, // (505 decimal)
1320         opcode0_qrl    = 0772U, // (506 decimal)
1321         opcode0_lrl    = 0773U, // (507 decimal)
1322         opcode0_gtb    = 0774U, // (508 decimal)
1323         opcode0_alr    = 0775U, // (509 decimal)
1324         opcode0_qlr    = 0776U, // (510 decimal)
1325         opcode0_llr    = 0777U  // (511 decimal)
1326 } opcode0_t;
1327 
1328 // Opcodes with low bit (bit 27) == 1.  Enum value is value of upper 9 bits.
1329 typedef enum {
1330         opcode1_mve    = 0020U, // (16 decimal)
1331         opcode1_mvne   = 0024U, // (20 decimal)
1332         opcode1_csl    = 0060U, // (48 decimal)
1333         opcode1_csr    = 0061U, // (49 decimal)
1334         opcode1_sztl   = 0064U, // (52 decimal)
1335         opcode1_sztr   = 0065U, // (53 decimal)
1336         opcode1_cmpb   = 0066U, // (54 decimal)
1337         opcode1_mlr    = 0100U, // (64 decimal)
1338         opcode1_mrl    = 0101U, // (65 decimal)
1339         opcode1_cmpc   = 0106U, // (70 decimal)
1340         opcode1_scd    = 0120U, // (80 decimal)
1341         opcode1_scdr   = 0121U, // (81 decimal)
1342         opcode1_scm    = 0124U, // (84 decimal)
1343         opcode1_scmr   = 0125U, // (85 decimal)
1344         opcode1_sptr   = 0154U, // (108 decimal)
1345         opcode1_mvt    = 0160U, // (112 decimal)
1346         opcode1_tct    = 0164U, // (116 decimal)
1347         opcode1_tctr   = 0165U, // (117 decimal)
1348         opcode1_lptr   = 0173U, // (123 decimal)
1349         opcode1_ad2d   = 0202U, // (130 decimal)
1350         opcode1_sb2d   = 0203U, // (131 decimal)
1351         opcode1_mp2d   = 0206U, // (134 decimal)
1352         opcode1_dv2d   = 0207U, // (135 decimal)
1353         opcode1_ad3d   = 0222U, // (146 decimal)
1354         opcode1_sb3d   = 0223U, // (147 decimal)
1355         opcode1_mp3d   = 0226U, // (150 decimal)
1356         opcode1_dv3d   = 0227U, // (151 decimal)
1357         opcode1_lsdr   = 0232U, // (154 decimal)
1358         opcode1_spbp0  = 0250U, // (168 decimal)
1359         opcode1_spri1  = 0251U, // (169 decimal)
1360         opcode1_spbp2  = 0252U, // (170 decimal)
1361         opcode1_spri3  = 0253U, // (171 decimal)
1362         opcode1_ssdr   = 0254U, // (172 decimal)
1363         opcode1_lptp   = 0257U, // (175 decimal)
1364         opcode1_mvn    = 0300U, // (192 decimal)
1365         opcode1_btd    = 0301U, // (193 decimal)
1366         opcode1_cmpn   = 0303U, // (195 decimal)
1367         opcode1_dtb    = 0305U, // (197 decimal)
1368         opcode1_easp1  = 0310U, // (200 decimal)
1369         opcode1_eawp1  = 0311U, // (201 decimal)
1370         opcode1_easp3  = 0312U, // (202 decimal)
1371         opcode1_eawp3  = 0313U, // (203 decimal)
1372         opcode1_easp5  = 0330U, // (216 decimal)
1373         opcode1_eawp5  = 0331U, // (217 decimal)
1374         opcode1_easp7  = 0332U, // (218 decimal)
1375         opcode1_eawp7  = 0333U, // (219 decimal)
1376         opcode1_epbp0  = 0350U, // (232 decimal)
1377         opcode1_epp1   = 0351U, // (233 decimal)
1378         opcode1_epbp2  = 0352U, // (234 decimal)
1379         opcode1_epp3   = 0353U, // (235 decimal)
1380         opcode1_epbp4  = 0370U, // (248 decimal)
1381         opcode1_epp5   = 0371U, // (249 decimal)
1382         opcode1_epbp6  = 0372U, // (250 decimal)
1383         opcode1_epp7   = 0373U, // (251 decimal)
1384         opcode1_sareg  = 0443U, // (291 decimal)
1385         opcode1_spl    = 0447U, // (295 decimal)
1386         opcode1_lareg  = 0463U, // (307 decimal)
1387         opcode1_lpl    = 0467U, // (311 decimal)
1388         opcode1_a9bd   = 0500U, // (320 decimal)
1389         opcode1_a6bd   = 0501U, // (321 decimal)
1390         opcode1_a4bd   = 0502U, // (322 decimal)
1391         opcode1_abd    = 0503U, // (323 decimal)
1392         opcode1_awd    = 0507U, // (327 decimal)
1393         opcode1_s9bd   = 0520U, // (336 decimal)
1394         opcode1_s6bd   = 0521U, // (337 decimal)
1395         opcode1_s4bd   = 0522U, // (338 decimal)
1396         opcode1_sbd    = 0523U, // (339 decimal)
1397         opcode1_swd    = 0527U, // (343 decimal)
1398         opcode1_camp   = 0532U, // (346 decimal)
1399         opcode1_ara0   = 0540U, // (352 decimal)
1400         opcode1_ara1   = 0541U, // (353 decimal)
1401         opcode1_ara2   = 0542U, // (354 decimal)
1402         opcode1_ara3   = 0543U, // (355 decimal)
1403         opcode1_ara4   = 0544U, // (356 decimal)
1404         opcode1_ara5   = 0545U, // (357 decimal)
1405         opcode1_ara6   = 0546U, // (358 decimal)
1406         opcode1_ara7   = 0547U, // (359 decimal)
1407         opcode1_sptp   = 0557U, // (367 decimal)
1408         opcode1_aar0   = 0560U, // (368 decimal)
1409         opcode1_aar1   = 0561U, // (369 decimal)
1410         opcode1_aar2   = 0562U, // (370 decimal)
1411         opcode1_aar3   = 0563U, // (371 decimal)
1412         opcode1_aar4   = 0564U, // (372 decimal)
1413         opcode1_aar5   = 0565U, // (373 decimal)
1414         opcode1_aar6   = 0566U, // (374 decimal)
1415         opcode1_aar7   = 0567U, // (375 decimal)
1416         opcode1_trtn   = 0600U, // (384 decimal)
1417         opcode1_trtf   = 0601U, // (385 decimal)
1418         opcode1_tmoz   = 0604U, // (388 decimal)
1419         opcode1_tpnz   = 0605U, // (389 decimal)
1420         opcode1_ttn    = 0606U, // (390 decimal)
1421         opcode1_arn0   = 0640U, // (416 decimal)
1422         opcode1_arn1   = 0641U, // (417 decimal)
1423         opcode1_arn2   = 0642U, // (418 decimal)
1424         opcode1_arn3   = 0643U, // (419 decimal)
1425         opcode1_arn4   = 0644U, // (420 decimal)
1426         opcode1_arn5   = 0645U, // (421 decimal)
1427         opcode1_arn6   = 0646U, // (422 decimal)
1428         opcode1_arn7   = 0647U, // (423 decimal)
1429         opcode1_spbp4  = 0650U, // (424 decimal)
1430         opcode1_spri5  = 0651U, // (425 decimal)
1431         opcode1_spbp6  = 0652U, // (426 decimal)
1432         opcode1_spri7  = 0653U, // (427 decimal)
1433         opcode1_nar0   = 0660U, // (432 decimal)
1434         opcode1_nar1   = 0661U, // (433 decimal)
1435         opcode1_nar2   = 0662U, // (434 decimal)
1436         opcode1_nar3   = 0663U, // (435 decimal)
1437         opcode1_nar4   = 0664U, // (436 decimal)
1438         opcode1_nar5   = 0665U, // (437 decimal)
1439         opcode1_nar6   = 0666U, // (438 decimal)
1440         opcode1_nar7   = 0667U, // (439 decimal)
1441         opcode1_sar0   = 0740U, // (480 decimal)
1442         opcode1_sar1   = 0741U, // (481 decimal)
1443         opcode1_sar2   = 0742U, // (482 decimal)
1444         opcode1_sar3   = 0743U, // (483 decimal)
1445         opcode1_sar4   = 0744U, // (484 decimal)
1446         opcode1_sar5   = 0745U, // (485 decimal)
1447         opcode1_sar6   = 0746U, // (486 decimal)
1448         opcode1_sar7   = 0747U, // (487 decimal)
1449         opcode1_sra    = 0754U, // (492 decimal)
1450         opcode1_lar0   = 0760U, // (496 decimal)
1451         opcode1_lar1   = 0761U, // (497 decimal)
1452         opcode1_lar2   = 0762U, // (498 decimal)
1453         opcode1_lar3   = 0763U, // (499 decimal)
1454         opcode1_lar4   = 0764U, // (500 decimal)
1455         opcode1_lar5   = 0765U, // (501 decimal)
1456         opcode1_lar6   = 0766U, // (502 decimal)
1457         opcode1_lar7   = 0767U, // (503 decimal)
1458         opcode1_lra    = 0774U  // (508 decimal)
1459 } opcode1_t;
1460 
1461 /////////////////////////////////////
1462 //
1463 // History registers
1464 //
1465 
1466 enum { N_HIST_SETS       =  4 };
1467 enum { N_DPS8M_HIST_SIZE = 64 };
1468 enum { N_L68_HIST_SIZE   = 16 };
1469 enum { N_MAX_HIST_SIZE   = 64 };
1470 
1471 # define N_MODEL_HIST_SIZE (cpu.tweaks.l68_mode ? N_L68_HIST_SIZE : N_DPS8M_HIST_SIZE)
1472 
1473 // Bit in CU history register word 0
1474 
1475 // cu_hist_t flags
1476 enum
1477   {
1478     CU_HIST_PIA      = 0400000000000,  //  0   Prepare instruction address
1479     CU_HIST_POA      = 0200000000000,  //  1   Prepare operand address
1480     CU_HIST_RIW      = 0100000000000,  //  2   Request indirect word
1481     CU_HIST_SIW      = 0040000000000,  //  3   Restore indirect word
1482     CU_HIST_POT      = 0020000000000,  //  4   Prepare operand tally (indirect tally chain)
1483     CU_HIST_PON      = 0010000000000,  //  5   Prepare operand no tally (as for POT except no chain)
1484     CU_HIST_RAW      = 0004000000000,  //  6   Request read-alter-rewrite word
1485     CU_HIST_SAW      = 0002000000000,  //  7   Restore read-later-rewrite word
1486     CU_HIST_TRGO     = 0001000000000,  //  8   Transfer GO (conditions met)
1487     CU_HIST_XDE      = 0000400000000,  //  9   Execute XED even instruction
1488     CU_HIST_XDO      = 0000200000000,  // 10   Execute XED odd instruction
1489     CU_HIST_IC       = 0000100000000,  // 11   Execute odd instruction of the current pair
1490     CU_HIST_RPTS     = 0000040000000,  // 12   Execute a repeat instruction
1491     CU_HIST_PORTF    = 0000020000000,  // 13   Memory cycle to port on previous cycle
1492     CU_HIST_INTERNAL = 0000010000000,  // 14   Memory cycle to cache or direct on previous cycle
1493     CU_HIST_PAI      = 0000004000000,  // 15   Prepare interrupt address
1494     CU_HIST_PFA      = 0000002000000,  // 16   Prepare fault address
1495     CU_HIST_PRIV     = 0000001000000   // 17   In privileged mode
1496   };
1497 
1498 // cu_hist_t flags2
1499 enum
1500   {
1501     CU_HIST_XINT = 0100,  //  29   Execute instruction
1502     CU_HIST_IFT  = 0040,  //  30   Perform an instruction fetch
1503     CU_HIST_CRD  = 0020,  //  31   Cache read, this CU cycle
1504     CU_HIST_MRD  = 0010,  //  32   Memory read, this CU cycle
1505     CU_HIST_MSTO = 0004,  //  33   Memory store, this CU cycle
1506     CU_HIST_PIB  = 0002,  //  34   Memory port interface busy
1507    };
1508 
1509 enum
1510   {
1511     DU_FANLD1  = 0400000000000,  //   0  Alpha-num load desc l (complemented)
1512     DU_FANLD2  = 0200000000000,  //   1  Alpha-num load desc 2 (complemented)
1513     DU_FANSTR  = 0100000000000,  //   2  Alpha-num store (complemented)
1514     DU_FLDWRT1 = 0040000000000,  //   3  Load re-write reg l (complemented)
1515     DU_FLDWRT2 = 0020000000000,  //   4  Load re-write reg 2 (complemented)
1516     DU_FNLD1   = 0010000000000,  //   5  Numeric load desc l (complemented)
1517     DU_FNLD2   = 0004000000000,  //   6  Numeric load desc 2 (complemented)
1518     DU_NOSEQF  = 0002000000000,  //   7  End sequence flag
1519     DU_FDUD    = 0001000000000,  //   8  Decimal unit idle (complemented)
1520     DU_FGSTR   = 0000400000000,  //   9  General store flag (complemented)
1521     DU_NOSEQ   = 0000200000000,  //  10  End of sequence (complemented)
1522     DU_NINE    = 0000100000000,  //  11  9-bit character operation
1523     DU_SIX     = 0000040000000,  //  12  6-bit character operation
1524     DU_FOUR    = 0000020000000,  //  13  4-bit character operation
1525     DU_DUBIT   = 0000010000000,  //  14  Bit operation
1526     DU_UWORD   = 0000004000000,  //  15  Word operation
1527     DU_PTR1    = 0000002000000,  //  16  Select ptr l
1528     DU_PTR2    = 0000001000000,  //  17  Select ptr 2
1529     DU_PRT3    = 0000000400000,  //  18  Select ptr 3
1530     DU_FPOP    = 0000000200000,  //  19  Prepare operand pointer
1531     DU_GEAM    = 0000000100000,  //  20  Add timing gates (complemented)
1532     DU_LPD12   = 0000000040000,  //  21  Load pointer l or 2 (complemented)
1533     DU_GEMAE   = 0000000020000,  //  22  Multiply gates A E (complemented)
1534     DU_BTDS    = 0000000010000,  //  23  Binary to decimal gates (complemented)
1535     DU_SP15    = 0000000004000,  //  24  Align cycles (complemented)
1536     DU_FSWEQ   = 0000000002000,  //  25  Single word sequence flag (complemented)
1537     DU_FGCH    = 0000000001000,  //  26  Character cycle (complemented)
1538     DU_DFRST   = 0000000000400,  //  27  Processing descriptor for first time
1539     DU_EXH     = 0000000000200,  //  28  Exhaust
1540     DU_FGADO   = 0000000000100,  //  29  Add cycle (complemented)
1541     DU_INTRPTD = 0000000000040,  //  30  Interrupted
1542     DU_GLDP2   = 0000000000020,  //  31  Load DP2
1543     DU_GEMC    = 0000000000010,  //  32  Multiply gate C
1544     DU_GBDA    = 0000000000004,  //  33  Binary to decimal gate A
1545     DU_GSP5    = 0000000000002   //  34  Final align cycle
1546   };
1547 
1548 // apu_hist_t flags
1549 enum
1550   {
1551     APU_PIA_OVF = 04000000,  //  15   PIA Page overflow
1552     APU_PIA_OOB = 02000000,  //  16   PIA out of segment bounds
1553     APU_FDSPTW  = 01000000,  //  17   Fetch descriptor segment PTW
1554     APU_MDSPTW  = 00400000,  //  18   Descriptor segment PTW is modified
1555     APU_FSDW    = 00200000,  //  19   Fetch SDW
1556     APU_FPTW    = 00100000,  //  20   Fetch PTW
1557     APU_FPTW2   = 00040000,  //  21   Fetch pre-page PTW
1558     APU_MPTW    = 00020000,  //  22   PTW modified
1559     APU_FANP    = 00010000,  //  23   Final address nonpaged
1560     APU_FAP     = 00004000,  //  24   Final address paged
1561     APU_MTCHSDW = 00002000,  //  25   SDW match found
1562     APU_SDWMF   = 00001000,  //  26   SDW match found and used
1563     // BSY Data source for ESN
1564     APU_BSY_IC  = 00000000,  // 27-28  00 = from ppr.ic
1565     APU_BSY_TSE = 00000200,  // 27-28  01 = from prn.tsr
1566     APU_BSY_SWR = 00000400,  // 27-28  10 = from tpr.swr
1567     APU_BSY_CA  = 00000600,  // 27-28  11 = from tpr.ca
1568     APU_MTCHPTW = 00000100,  //  29   PTW match found (AM)
1569     //APU_PTWMF = 00000000,  // 30-31 PTW match found (AM) and used
1570     //APU_PTWAM = 00000000   // 32-35 PTW AM direct address (ZCA bits 4-7)
1571   };
1572 
1573 // apu_hist_t flags2
1574 enum
1575   {
1576     APU_SDWME    = 0400, //   27   SDW match error
1577     //APU_SDWLVL = 0000, // 28-29  SDW match level count (0 = Level A)
1578     APU_CACHE    = 0040, //   30   Cache used this cycle
1579     APU_PTW      = 0020, //   31   match error
1580     //APU_PTWLVL = 0000, // 32-33  PTW match level count (0 = level A)
1581     APU_FLTHLD   = 0002, //   34   A directed fault or access violation fault is waiting
1582     // bit 35 is marked 'w' but undocumented
1583   };
1584 
1585 enum { CU_HIST_REG = 0, DPS8M_DU_OU_HIST_REG = 1, DPS8M_APU_HIST_REG = 2, DPS8M_EAPU_HIST_REG = 3 };
1586 enum { /* CU_HIST_REG = 0,*/ L68_DU_HIST_REG = 1, L68_OU_HIST_REG    = 2, L68_APU_HIST_REG    = 3 };
1587 
1588 #endif // DPS8_HW_CONSTS_H

/* */