PSR 26 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PSR 154 src/dps8/doAppendCycleABSA.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PSR 281 src/dps8/doAppendCycleABSA.h DBGAPP ("doAppendCycleABSA (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PSR 24 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PSR 166 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PSR 184 src/dps8/doAppendCycleAPUDataRMW.h if (cpu.TPR.TSR == cpu.PPR.PSR) PSR 347 src/dps8/doAppendCycleAPUDataRMW.h DBGAPP ("doAppendCycleAPUDataRMW (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PSR 24 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PSR 163 src/dps8/doAppendCycleAPUDataRead.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PSR 300 src/dps8/doAppendCycleAPUDataRead.h DBGAPP ("doAppendCycleAPUDataRead (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PSR 24 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PSR 151 src/dps8/doAppendCycleAPUDataStore.h if (cpu.TPR.TSR == cpu.PPR.PSR) PSR 303 src/dps8/doAppendCycleAPUDataStore.h DBGAPP ("doAppendCycleAPUDataStore (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PSR 60 src/dps8/doAppendCycleIndirectWordFetch.h DBGAPP ("doAppendCycleIndirectWordFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PSR 261 src/dps8/doAppendCycleIndirectWordFetch.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PSR 473 src/dps8/doAppendCycleIndirectWordFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PSR 76 src/dps8/doAppendCycleInstructionFetch.h DBGAPP ("doAppendCycleInstructionFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PSR 644 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.PSR = cpu.TPR.TSR; PSR 669 src/dps8/doAppendCycleInstructionFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PSR 24 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PSR 168 src/dps8/doAppendCycleOperandRMW.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PSR 186 src/dps8/doAppendCycleOperandRMW.h if (cpu.TPR.TSR == cpu.PPR.PSR) PSR 354 src/dps8/doAppendCycleOperandRMW.h DBGAPP ("doAppendCycleOperandRMW (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PSR 66 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PSR 333 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PSR 389 src/dps8/doAppendCycleOperandRead.h cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, cpu.SDW->EB, PSR 407 src/dps8/doAppendCycleOperandRead.h if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS) PSR 746 src/dps8/doAppendCycleOperandRead.h cpu.PR[n].SNR = cpu.PPR.PSR; PSR 758 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PSR = cpu.TPR.TSR; PSR 805 src/dps8/doAppendCycleOperandRead.h cpu.PPR.PSR = cpu.TPR.TSR; PSR 818 src/dps8/doAppendCycleOperandRead.h DBGAPP ("doAppendCycleOperandRead (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PSR 24 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PSR 146 src/dps8/doAppendCycleOperandStore.h if (cpu.TPR.TSR == cpu.PPR.PSR) PSR 308 src/dps8/doAppendCycleOperandStore.h DBGAPP ("doAppendCycleOperandStore (Exit) PRR %o PSR %05o P %o IC %06o\r\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PSR 24 src/dps8/doAppendCycleRTCDOperandFetch.h DBGAPP ("doAppendCycleRTCDOperandFetch(Entry) PPR.PRR=%o PPR.PSR=%05o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PSR 192 src/dps8/doAppendCycleRTCDOperandFetch.h if (cpu.PPR.PSR != cpu.TPR.TSR) { PSR 366 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PSR = cpu.TPR.TSR; PSR 392 src/dps8/doAppendCycleRTCDOperandFetch.h cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PSR 1227 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.PPR.PSR); PSR 1467 src/dps8/dps8_append.c if (cpu.PPR.PSR != cpu.TPR.TSR) PSR 1497 src/dps8/dps8_append.c if (cpu.TPR.TSR == cpu.PPR.PSR) PSR 1617 src/dps8/dps8_append.c cpu.SDW->E, cpu.SDW->G, cpu.PPR.PSR, cpu.TPR.TSR, cpu.TPR.CA, PSR 1637 src/dps8/dps8_append.c if (cpu.PPR.PSR == cpu.TPR.TSR && ! TST_I_ABS) PSR 2087 src/dps8/dps8_append.c cpu.PR[n].SNR = cpu.PPR.PSR; PSR 2135 src/dps8/dps8_append.c cpu.PPR.PSR = cpu.TPR.TSR; PSR 2189 src/dps8/dps8_append.c cpu.PPR.PSR = cpu.TPR.TSR; PSR 2237 src/dps8/dps8_append.c cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PSR 987 src/dps8/dps8_console.c cpus[i].PPR.PSR, PSR 996 src/dps8/dps8_cpu.c cpu.PPR.PSR = 0; PSR 2452 src/dps8/dps8_cpu.c ((((t_addr) cpu.PPR.PSR) & 037777) << 18), PSR 3367 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 3589 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 3608 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 3782 src/dps8/dps8_cpu.c if (stall_points[i].segno && stall_points[i].segno == cpu.PPR.PSR && PSR 3838 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 4151 src/dps8/dps8_cpu.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 4682 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, real, PSR 4702 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); PSR 4709 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, addr, PSR 4744 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PSR 4791 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PSR 4814 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PSR 4832 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PSR 4882 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PSR 4921 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); PSR 4928 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PSR 4939 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PSR 4958 src/dps8/dps8_cpu.c addr, cpu.PPR.PSR, cpu.PPR.IC, ctx); PSR 4965 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PSR 4976 src/dps8/dps8_cpu.c cpu.PPR.PSR, cpu.PPR.IC); PSR 5018 src/dps8/dps8_cpu.c (unsigned long long int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PSR 5041 src/dps8/dps8_cpu.c (long long unsigned int)cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, PSR 96 src/dps8/dps8_cpu.h word15 PSR; // The segment number of the procedure being executed. PSR 1789 src/dps8/dps8_cpu.h word15 PSR; PSR 590 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 660 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 827 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 889 src/dps8/dps8_eis.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 388 src/dps8/dps8_faults.c sim_printf (" TRO PSR:IC %05o:%06o\r\n", cpu.PPR.PSR, cpu.PPR.IC); PSR 393 src/dps8/dps8_faults.c sim_printf (" ACV %012llo PSR:IC %05o:%06o\r\n", subFault.bits, cpu.PPR.PSR, cpu.PPR.IC); PSR 425 src/dps8/dps8_faults.c fault_psr = cpu . PPR.PSR; PSR 118 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 136 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) PSR 197 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 211 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PSR 267 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 282 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PSR 339 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 353 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PSR 409 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 423 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PSR 482 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 496 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PSR 552 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 566 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) { PSR 635 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 730 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 822 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 909 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 950 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 1033 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 1133 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 1157 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) PSR 1257 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 1282 src/dps8/dps8_iefp.c if (cpu.PPR.PSR != 061 && cpu.PPR.IC != 0307) PSR 1351 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 1423 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 1497 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 1579 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 1658 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 1738 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 1835 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 1966 src/dps8/dps8_iefp.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 322 src/dps8/dps8_ins.c cpu.PR[n].SNR = cpu.PPR.PSR; PSR 334 src/dps8/dps8_ins.c __func__, cpu.PPR.PSR, cpu.PPR.IC); PSR 372 src/dps8/dps8_ins.c putbits36_15 (& words[0], 3, cpu.PPR.PSR); PSR 629 src/dps8/dps8_ins.c cpu.cu_data.PSR = cpu.PPR.PSR; PSR 662 src/dps8/dps8_ins.c cpu.PPR.PSR = getbits36_15 (words[0], 3); PSR 1264 src/dps8/dps8_ins.c char * where = lookup_address (cpu.PPR.PSR, cpu.PPR.IC, & compname, PSR 1286 src/dps8/dps8_ins.c cpu.PPR.PSR, PSR 1292 src/dps8/dps8_ins.c cpu.PPR.PSR, cpu.PPR.IC, where); PSR 1343 src/dps8/dps8_ins.c cpu.PPR.PSR, PSR 1362 src/dps8/dps8_ins.c cpu.PPR.PSR, PSR 1415 src/dps8/dps8_ins.c trk (cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC, IWB_IRODD); PSR 1787 src/dps8/dps8_ins.c if (n_dbgevents && (dbgevt = (dbgevent_lookup (cpu.PPR.PSR, cpu.PPR.IC))) >= 0) { PSR 1965 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 2041 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 2133 src/dps8/dps8_ins.c cpu.TPR.TSR = cpu.PPR.PSR; PSR 2392 src/dps8/dps8_ins.c cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC); PSR 4094 src/dps8/dps8_ins.c putbits36_15 (& cpu.Ypair[0], 3, cpu.PPR.PSR); PSR 4104 src/dps8/dps8_ins.c putbits36_15 (& cpu.Ypair[0], 3, cpu.cu_data.PSR); PSR 6613 src/dps8/dps8_ins.c "call6 PRR %o PSR %o\r\n", cpu.PPR.PRR, cpu.PPR.PSR); PSR 7760 src/dps8/dps8_ins.c sim_printf (" ldt %d PSR:IC %05o:%06o\r\n", cpu.rTR, cpu.PPR.PSR, cpu.PPR.IC); PSR 7811 src/dps8/dps8_ins.c sim_printf (" RALR set to %o PSR:IC %05o:%06o\r\n", cpu.rRALR, cpu.PPR.PSR, cpu.PPR.IC); PSR 8920 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 034 && cpu.PPR.IC == 03535) { PSR 8971 src/dps8/dps8_ins.c if (cpu.PPR.PSR == 0430 && cpu.PPR.IC == 012) PSR 9011 src/dps8/dps8_ins.c (cpu.PPR.PSR !=0 || cpu.PPR.IC != 0)) { PSR 9013 src/dps8/dps8_ins.c sim_printf ("CPU%c DIS %o:%o gives up master\r\n", cpu.cpuIdx + 'A', cpu.PPR.PSR, cpu.PPR.IC); PSR 9030 src/dps8/dps8_ins.c PSR 10178 src/dps8/dps8_ins.c (cpu.Yblock8[0]>>18)&MASK15, (cpu.Yblock8[4]>>18)&MASK18, cpu.PPR.PSR, cpu.PPR.IC); PSR 4076 src/dps8/dps8_iom.c __func__, iomChar (iom_unit_idx), cpu.cycleCnt, cpu.PPR.PSR, cpu.PPR.IC); PSR 30 src/dps8/dps8_simh.h (! sim_deb_segno_on) || sim_deb_segno[cpu.PPR.PSR & (DEBUG_SEGNO_LIMIT - 1)]) && \ PSR 2771 src/dps8/dps8_sys.c word15 icSegno = cpu.PPR.PSR; PSR 4102 src/dps8/dps8_sys.c { "cpus[].PPR.PSR", SYM_STRUCT_OFFSET, SYM_UINT16_15, offsetof (struct ppr_s, PSR) }, PSR 177 src/dps8/hdbg.c if (filter && hdbgSegNum >= 0 && hdbgSegNum != cpu.PPR.PSR) \ PSR 201 src/dps8/hdbg.c hevp[p].trace.segno = cpu.PPR.PSR; PSR 378 src/dps8/panelScraper.c SETL (bank_a, 3+3, cpu.PPR.PSR, 15);