sim_debug         332 src/dps8/doAppendCycleAPUDataRMW.h   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
sim_debug         288 src/dps8/doAppendCycleAPUDataRead.h   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
sim_debug         293 src/dps8/doAppendCycleAPUDataStore.h   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
sim_debug         403 src/dps8/doAppendCycleIndirectWordFetch.h   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
sim_debug         580 src/dps8/doAppendCycleInstructionFetch.h   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
sim_debug         331 src/dps8/doAppendCycleOperandRMW.h   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
sim_debug         685 src/dps8/doAppendCycleOperandRead.h   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
sim_debug         291 src/dps8/doAppendCycleOperandStore.h   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
sim_debug         328 src/dps8/doAppendCycleRTCDOperandFetch.h   sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
sim_debug         271 src/dps8/dps8_absi.c     sim_debug (DBG_TRACE, & absi_dev,
sim_debug          80 src/dps8/dps8_addrmods.c           sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         106 src/dps8/dps8_addrmods.c             sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         198 src/dps8/dps8_addrmods.c     sim_debug (DBG_APPENDING, & cpu_dev,
sim_debug         242 src/dps8/dps8_addrmods.c     sim_debug (DBG_APPENDING, & cpu_dev,
sim_debug         262 src/dps8/dps8_addrmods.c     sim_debug (DBG_APPENDING, & cpu_dev,
sim_debug         286 src/dps8/dps8_addrmods.c     sim_debug (DBG_APPENDING, & cpu_dev,
sim_debug         318 src/dps8/dps8_addrmods.c     sim_debug (DBG_APPENDING, & cpu_dev, "do_ITS_ITP sets XSF to 1\n");
sim_debug         328 src/dps8/dps8_addrmods.c     sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         337 src/dps8/dps8_addrmods.c     sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         377 src/dps8/dps8_addrmods.c     sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         380 src/dps8/dps8_addrmods.c     sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         416 src/dps8/dps8_addrmods.c         sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         439 src/dps8/dps8_addrmods.c     sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         473 src/dps8/dps8_addrmods.c         sim_debug (DBG_ADDRMOD, & cpu_dev, "R_MOD: Cr=%06o\n", Cr);
sim_debug         477 src/dps8/dps8_addrmods.c             sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         507 src/dps8/dps8_addrmods.c         sim_debug (DBG_ADDRMOD, & cpu_dev, "R_MOD: TPR.CA=%06o\n",
sim_debug         516 src/dps8/dps8_addrmods.c         sim_debug (DBG_ADDRMOD, & cpu_dev, "RI_MOD: Td=%o\n", Td);
sim_debug         529 src/dps8/dps8_addrmods.c             sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         554 src/dps8/dps8_addrmods.c             sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         613 src/dps8/dps8_addrmods.c         sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         631 src/dps8/dps8_addrmods.c         sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         641 src/dps8/dps8_addrmods.c         sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         670 src/dps8/dps8_addrmods.c         sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         675 src/dps8/dps8_addrmods.c         sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         685 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         740 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         747 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         750 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         799 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         838 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         853 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         865 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         961 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         997 src/dps8/dps8_addrmods.c                     sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1024 src/dps8/dps8_addrmods.c                     sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1038 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1045 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1066 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1082 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1085 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1115 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1145 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1152 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1155 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1183 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1204 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1220 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1223 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1241 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1273 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1288 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1312 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1355 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1373 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1395 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1418 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1467 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1485 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1506 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug        1532 src/dps8/dps8_addrmods.c                 sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug          56 src/dps8/dps8_append.c # define DBGAPP(...) sim_debug (DBG_APPENDING, & cpu_dev, __VA_ARGS__)
sim_debug        1896 src/dps8/dps8_append.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "loading of cpu.TPR.TSR sets XSF to 1\n");
sim_debug        1309 src/dps8/dps8_console.c         sim_debug (DBG_DEBUG, & opc_dev, "%s: Status request\n", __func__);
sim_debug        1315 src/dps8/dps8_console.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Read BCD echoed\n", __func__);
sim_debug        1324 src/dps8/dps8_console.c         sim_debug (DBG_DEBUG, & opc_dev, "%s: Write BCD\n", __func__);
sim_debug        1333 src/dps8/dps8_console.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Read ASCII echoed\n", __func__);
sim_debug        1342 src/dps8/dps8_console.c         sim_debug (DBG_DEBUG, & opc_dev, "%s: Write ASCII\n", __func__);
sim_debug        1360 src/dps8/dps8_console.c         sim_debug (DBG_DEBUG, & opc_dev, "%s: Reset\n", __func__);
sim_debug        1372 src/dps8/dps8_console.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Read ASCII unechoed\n", __func__);
sim_debug        1381 src/dps8/dps8_console.c         sim_debug (DBG_DEBUG, & opc_dev, "%s: Alert\n", __func__);
sim_debug        1398 src/dps8/dps8_console.c         sim_debug (DBG_DEBUG, & opc_dev, "%s: Read ID\n", __func__);
sim_debug        1407 src/dps8/dps8_console.c         sim_debug (DBG_DEBUG, & opc_dev, "%s: Lock\n", __func__);
sim_debug        1414 src/dps8/dps8_console.c         sim_debug (DBG_DEBUG, & opc_dev, "%s: Unlock\n", __func__);
sim_debug        1421 src/dps8/dps8_console.c         sim_debug (DBG_DEBUG, & opc_dev, "%s: Unknown command 0%o\n", __func__, p->IDCW_DEV_CMD);
sim_debug         906 src/dps8/dps8_cpu.c     sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to %s\n",
sim_debug        1599 src/dps8/dps8_cpu.c     sim_debug (DBG_INFO, & cpu_dev, "CPU reset: Running\n");
sim_debug        2159 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, "set_temporary_absolute_mode bit 29 sets XSF to 0\n");
sim_debug        2373 src/dps8/dps8_cpu.c         sim_debug (DBG_CYCLE, & cpu_dev, "Cycle is %s\n",
sim_debug        2409 src/dps8/dps8_cpu.c                 sim_debug (DBG_INTR, & cpu_dev, "intr_pair_addr %u flag %d\n",
sim_debug        2593 src/dps8/dps8_cpu.c                       sim_debug (DBG_CYCLE, & cpu_dev,
sim_debug        2696 src/dps8/dps8_cpu.c sim_debug (DBG_TRACEEXT, & cpu_dev, "fetchCycle bit 29 sets XSF to 0\n");
sim_debug        2799 src/dps8/dps8_cpu.c                           sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        2807 src/dps8/dps8_cpu.c                           sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        3552 src/dps8/dps8_cpu.c         sim_debug (DBG_WARN, & cpu_dev,
sim_debug        3580 src/dps8/dps8_cpu.c     sim_debug (DBG_CORE, & cpu_dev,
sim_debug        3647 src/dps8/dps8_cpu.c     sim_debug (DBG_CORE, & cpu_dev,
sim_debug        3729 src/dps8/dps8_cpu.c     sim_debug (DBG_CORE, & cpu_dev,
sim_debug        3747 src/dps8/dps8_cpu.c         sim_debug (DBG_MSG, & cpu_dev,
sim_debug        3756 src/dps8/dps8_cpu.c         sim_debug (DBG_WARN, & cpu_dev,
sim_debug        3784 src/dps8/dps8_cpu.c     sim_debug (DBG_CORE, & cpu_dev,
sim_debug        3793 src/dps8/dps8_cpu.c         sim_debug (DBG_WARN, & cpu_dev,
sim_debug        3820 src/dps8/dps8_cpu.c     sim_debug (DBG_CORE, & cpu_dev,
sim_debug        3835 src/dps8/dps8_cpu.c     sim_debug (DBG_MSG, & cpu_dev,
sim_debug        3869 src/dps8/dps8_cpu.c   sim_debug (DBG_CORE, & cpu_dev, "core_write2 %08o %012llo (%s)\n", addr - 1,
sim_debug        3895 src/dps8/dps8_cpu.c   sim_debug (DBG_CORE, & cpu_dev, "core_write2 %08o %012"PRIo64" (%s)\n", addr, odd, ctx);
sim_debug        4032 src/dps8/dps8_cpu.c         sim_debug (DBG_DEBUG, & cpu_dev, "APU: Setting absolute mode.\n");
sim_debug        4041 src/dps8/dps8_cpu.c           sim_debug (DBG_DEBUG, & cpu_dev, "APU: Keeping append mode.\n");
sim_debug        4043 src/dps8/dps8_cpu.c           sim_debug (DBG_DEBUG, & cpu_dev, "APU: Setting append mode.\n");
sim_debug        4049 src/dps8/dps8_cpu.c         sim_debug (DBG_ERR, & cpu_dev,
sim_debug        1186 src/dps8/dps8_crdpun.c   sim_debug (DBG_TRACE, & pun_dev, "%s: PUN %c%02o_%02o\n",
sim_debug        1200 src/dps8/dps8_crdpun.c         sim_debug (DBG_DEBUG, & pun_dev, "%s: Punch Binary\n", __func__);
sim_debug        1206 src/dps8/dps8_crdpun.c         sim_debug (DBG_DEBUG, & pun_dev, "%s: Set Diagnostic Mode\n", __func__);
sim_debug        1211 src/dps8/dps8_crdpun.c         sim_debug (DBG_DEBUG, & pun_dev, "%s: Reset Status\n", __func__);
sim_debug        1223 src/dps8/dps8_crdpun.c     sim_debug (DBG_DEBUG, & pun_dev, "%s: stati %04o\n", __func__, p->stati);
sim_debug         466 src/dps8/dps8_crdrdr.c   sim_debug (DBG_NOTIFY, & rdr_dev, "Read binary\n");
sim_debug         914 src/dps8/dps8_crdrdr.c   sim_debug (DBG_TRACE, & rdr_dev, "%s: RDR %c%02o_%02o\n",
sim_debug         931 src/dps8/dps8_crdrdr.c         sim_debug (DBG_DEBUG, & rdr_dev, "%s: Request Status\n", __func__);
sim_debug         942 src/dps8/dps8_crdrdr.c         sim_debug (DBG_DEBUG, & rdr_dev, "%s: Read Binary\n", __func__);
sim_debug         964 src/dps8/dps8_crdrdr.c         sim_debug (DBG_DEBUG, & rdr_dev, "%s: Request Status\n", __func__);
sim_debug         986 src/dps8/dps8_crdrdr.c     sim_debug (DBG_DEBUG, & rdr_dev, "%s: stati %04o\n", __func__, p->stati);
sim_debug         420 src/dps8/dps8_decimal.c 
sim_debug         422 src/dps8/dps8_decimal.c 
sim_debug         465 src/dps8/dps8_decimal.c 
sim_debug         468 src/dps8/dps8_decimal.c 
sim_debug         482 src/dps8/dps8_decimal.c 
sim_debug         501 src/dps8/dps8_decimal.c 
sim_debug         530 src/dps8/dps8_decimal.c 
sim_debug         547 src/dps8/dps8_decimal.c 
sim_debug         569 src/dps8/dps8_decimal.c 
sim_debug         582 src/dps8/dps8_decimal.c 
sim_debug         600 src/dps8/dps8_decimal.c 
sim_debug         604 src/dps8/dps8_decimal.c 
sim_debug         620 src/dps8/dps8_decimal.c 
sim_debug         645 src/dps8/dps8_decimal.c 
sim_debug         669 src/dps8/dps8_decimal.c 
sim_debug         687 src/dps8/dps8_decimal.c 
sim_debug         695 src/dps8/dps8_decimal.c 
sim_debug          85 src/dps8/dps8_dia.c         sim_debug (DBG_ERR, & dia_dev, "DIA SET CONFIG: Invalid unit number %ld\n",
sim_debug         131 src/dps8/dps8_dia.c         sim_debug (DBG_ERR, & dia_dev,
sim_debug         151 src/dps8/dps8_dia.c         sim_debug (DBG_ERR, & dia_dev,
sim_debug         482 src/dps8/dps8_dia.c     sim_debug (DBG_TRACE, & dia_dev, "CS interrupt %u\n", cell);
sim_debug         497 src/dps8/dps8_dia.c         sim_debug (DBG_ERR, & dia_dev, "fnp illegal cell number %d\n", cell);
sim_debug         634 src/dps8/dps8_dia.c           sim_debug (DBG_TRACE, & dia_dev, "FNP reset??\n");
sim_debug         784 src/dps8/dps8_dia.c         sim_debug (DBG_TRACE, & dia_dev, "FNP data xfer??\n");
sim_debug         823 src/dps8/dps8_dia.c             sim_debug (DBG_NOTIFY, & dia_dev, "Request status\n");
sim_debug        1187 src/dps8/dps8_disk.c     sim_debug (DBG_NOTIFY, & dsk_dev, "Read %d\n", dev_unit_idx);
sim_debug         562 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteCache addr %06o\n", p->cachedAddr);
sim_debug         577 src/dps8/dps8_eis.c                   sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug         583 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
sim_debug         605 src/dps8/dps8_eis.c                   sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug         611 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Write8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
sim_debug         626 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadCache addr %06o\n", address);
sim_debug         650 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
sim_debug         656 src/dps8/dps8_eis.c               sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug         671 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "EIS %ld Read8 NO PR TRR %o TSR %05o\n", eisaddr_idx, cpu.TPR.TRR, cpu.TPR.TSR); }
sim_debug         676 src/dps8/dps8_eis.c               sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug         694 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteIdx addr %06o n %u\n", cpu.du.Dk_PTR_W[eisaddr_idx], n);
sim_debug         697 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "EISWriteIdx addr %06o n %u\n", p->address, n);
sim_debug         733 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadIdx addr %06o n %u\n", cpu.du.Dk_PTR_W[eisaddr_idx], n);
sim_debug         737 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "EISReadIdx %ld addr %06o n %u\n", eisaddr_idx, p->address, n);
sim_debug         763 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "EISRead addr %06o\n", cpu.du.Dk_PTR_W[eisaddr_idx]);
sim_debug         765 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "EISRead addr %06o\n", p->address);
sim_debug         776 src/dps8/dps8_eis.c 
sim_debug         778 src/dps8/dps8_eis.c 
sim_debug         798 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "%s addr %06o\n", __func__, addressN);
sim_debug         818 src/dps8/dps8_eis.c               sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug         822 src/dps8/dps8_eis.c               sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug         841 src/dps8/dps8_eis.c               sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug         860 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "%s addr %06o\n", __func__, addressN);
sim_debug         880 src/dps8/dps8_eis.c               sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug         884 src/dps8/dps8_eis.c               sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug         903 src/dps8/dps8_eis.c               sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug         965 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "EISGet469 : k: %u TAk %u coffset %u c %o \n", k, cpu.du.TAk[k - 1], residue, c);
sim_debug         967 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "EISGet469 : k: %u TAk %u coffset %u c %o \n", k, e -> TA [k - 1], residue, c);
sim_debug        1280 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "AR n %u k %u\n", n, k - 1);
sim_debug        1285 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "No ARb %u\n", k - 1);
sim_debug        1312 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "No ARa %u\n", k - 1);
sim_debug        1428 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "AR n %u k %u\n", n, k - 1);
sim_debug        1435 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "initial CN%u %u\n", k, CN);
sim_debug        1470 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "N%u %o\n", k, e->N[k-1]);
sim_debug        1514 src/dps8/dps8_eis.c             sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA4\n",
sim_debug        1538 src/dps8/dps8_eis.c           sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA6\n",
sim_debug        1552 src/dps8/dps8_eis.c           sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        1564 src/dps8/dps8_eis.c           sim_debug (DBG_TRACEEXT, & cpu_dev, "CN%d set to %d by CTA9\n",
sim_debug        1719 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(): N%u %0o\n", k, e->N[k-1]);
sim_debug        1817 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(): address:%06o cPos:%d bPos:%d N%u %u\n", cpu.du.Dk_PTR_W[k-1], a->cPos, a->bPos, k, e->N[k-1]);
sim_debug        1819 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "parseNumericOperandDescriptor(): address:%06o cPos:%d bPos:%d N%u %u\n", a->address, a->cPos, a->bPos, k, e->N[k-1]);
sim_debug        1857 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d AR%d\n", k, n);
sim_debug        1877 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d RL reg %u val %"PRIo64"\n", k, reg, (word36)e->N[k-1]);
sim_debug        1884 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "bitstring k %d opdesc %012"PRIo64"\n", k, opDesc);
sim_debug        1885 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "N%u %u\n", k, e->N[k-1]);
sim_debug        2108 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r);
sim_debug        2113 src/dps8/dps8_eis.c        sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn));
sim_debug        2116 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd augend 0%o\n", augend);
sim_debug        2122 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd force augend 0%o\n", augend);
sim_debug        2141 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "axbd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum);
sim_debug        2250 src/dps8/dps8_eis.c 
sim_debug        2281 src/dps8/dps8_eis.c 
sim_debug        2332 src/dps8/dps8_eis.c 
sim_debug        2370 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev,
sim_debug        2376 src/dps8/dps8_eis.c        sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "awd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn));
sim_debug        2382 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "awd augend 0%o\n", augend);
sim_debug        2387 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "awd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum);
sim_debug        2445 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r);
sim_debug        2450 src/dps8/dps8_eis.c        sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd ARn %d WORDNO %o CHAR %o BITNO %0o %d.\n", ARn, cpu.PAR[ARn].WORDNO, GET_AR_CHAR (ARn), GET_AR_BITNO (ARn), GET_AR_BITNO (ARn));
sim_debug        2456 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd minued 0%o\n", minued);
sim_debug        2461 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "swd minued 0%o subtractend 0%o difference 0%o\n", minued, subtractend, difference);
sim_debug        2482 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd r 0%o\n", r);
sim_debug        2484 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "s9bd ARn 0%o address 0%o reg 0%o r 0%o\n", ARn, address, reg, r);
sim_debug        2768 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d r 0%"PRIo64"\n", sz, rcnt);
sim_debug        2784 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd sz %d ARn 0%o address 0%o reg 0%o r 0%o\n", sz, ARn, address, reg, r);
sim_debug        2861 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT|DBG_CAC, & cpu_dev, "asxbd augend 0%o addend 0%o sum 0%o\n", augend, addend, sum);
sim_debug        3040 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpc tally %d c1 %03o c2 %03o\n", cpu.du.CHTALLY, c1, c2);
sim_debug        3917 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        3920 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        3984 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        4011 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        4112 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        4115 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        4179 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        4207 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        4436 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, TA1, TA2, e -> N1, e -> N2, e -> CN1, e -> CN2);
sim_debug        4438 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR TALLY %u TA1 %u TA2 %u N1 %u N2 %u CN1 %u CN2 %u\n", cpu.du.CHTALLY, e -> TA1, e -> TA2, e -> N1, e -> N2, e -> CN1, e -> CN2);
sim_debug        4473 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #3\n");
sim_debug        4513 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #4\n");
sim_debug        4553 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #1\n");
sim_debug        4583 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "MLR special case #2\n");
sim_debug        4848 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "MRL special case #1\n");
sim_debug        4879 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "MRL special case #2\n");
sim_debug        5042 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "src: %d: %o\n", n, c);
sim_debug        5166 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "inBuffer:");
sim_debug        5168 src/dps8/dps8_eis.c           sim_debug (DBG_TRACEEXT, & cpu_dev, " %02o", * q);
sim_debug        5169 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "\n");
sim_debug        5842 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "LTE IT[%d]<=%d\n", e -> mopIF - 1, next);
sim_debug        5893 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC IF %d, srcTally %d, dstTally %d\n", e->mopIF, e->srcTally, e->dstTally);
sim_debug        5896 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC n %d, srcTally %d, dstTally %d\n", n, e->srcTally, e->dstTally);
sim_debug        5908 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC c %d (0%o)\n", c, c);
sim_debug        5911 src/dps8/dps8_eis.c             sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC ES off\n");
sim_debug        5913 src/dps8/dps8_eis.c                 sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC is zero\n");
sim_debug        5920 src/dps8/dps8_eis.c                 sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC is not zero\n");
sim_debug        5934 src/dps8/dps8_eis.c             sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLC ES on\n");
sim_debug        6004 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "MFLS n %d c %o\n", n, c);
sim_debug        6010 src/dps8/dps8_eis.c                 sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is off, c is zero; edit insertion table entry 1 is moved to the receiving field in place of the character.\n");
sim_debug        6021 src/dps8/dps8_eis.c                     sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is off, c is non-zero, SN is off; edit insertion table entry 3 is moved to the receiving field; the character is also moved to the receiving field, and ES is set ON.\n");
sim_debug        6042 src/dps8/dps8_eis.c                     sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is off, c is non-zero, SN is OFF; edit insertion table entry 4 is moved to the receiving field; the character is also moved to the receiving field, and ES is set ON.\n");
sim_debug        6056 src/dps8/dps8_eis.c             sim_debug (DBG_TRACEEXT, & cpu_dev, "ES is ON, the character is moved to the receiving field.\n");
sim_debug        6098 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "MORS mopIF %d src %d dst %d\n", e->mopIF, e->srcTally, e->dstTally);
sim_debug        6140 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC mopIF %d\n", e->mopIF);
sim_debug        6144 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC n %d srcTally %d dstTally %d\n", n, e->srcTally, e->dstTally);
sim_debug        6152 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC write to output buffer %o\n", *e->in);
sim_debug        6161 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "MVC done\n");
sim_debug        6492 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "MOP %s(%o) %o\n", m -> mopName, mop, e->mopIF);
sim_debug        6496 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "getMop(e->m == NULL || e->m->f == NULL): mop:%d IF:%d\n", mop, e->mopIF);
sim_debug        6544 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "mopExecutor srcTally %d dstTally %d mopTally %d\n", e->srcTally, e->dstTally, e->mopTally);
sim_debug        6548 src/dps8/dps8_eis.c             sim_debug (DBG_TRACEEXT, & cpu_dev, "mopExecutor EISgetMop forced break\n");
sim_debug        6573 src/dps8/dps8_eis.c 
sim_debug        6579 src/dps8/dps8_eis.c             sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        6599 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "mop faults %o src %d dst %d mop %d\n", e->_faults, e->srcTally, e->dstTally, e->mopTally);
sim_debug        6616 src/dps8/dps8_eis.c 
sim_debug        6632 src/dps8/dps8_eis.c 
sim_debug        6653 src/dps8/dps8_eis.c     sim_debug(DBG_TRACEEXT, & cpu_dev, "mve\n");
sim_debug        6950 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        6954 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        7179 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        7657 src/dps8/dps8_eis.c     sim_debug (DBG_CAC, & cpu_dev,
sim_debug        7660 src/dps8/dps8_eis.c     sim_debug (DBG_CAC, & cpu_dev,
sim_debug        7663 src/dps8/dps8_eis.c     sim_debug (DBG_CAC, & cpu_dev,
sim_debug        7702 src/dps8/dps8_eis.c     sim_debug (DBG_CAC, & cpu_dev, "n1 %d sc1 %d\n", n1, sc1);
sim_debug        7733 src/dps8/dps8_eis.c     sim_debug (DBG_CAC, & cpu_dev, "n2 %d\n", n2);
sim_debug        7766 src/dps8/dps8_eis.c     sim_debug (DBG_CAC, & cpu_dev, "mvn res: '%s'\n", res);
sim_debug        7888 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "is neg %o\n", decNumberIsNegative(op1));
sim_debug        7889 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "is zero %o\n", decNumberIsZero(op1));
sim_debug        7890 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "R %o\n", R);
sim_debug        7891 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "Trunc %o\n", Trunc);
sim_debug        7892 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "TRUNC %o\n", TST_I_TRUNC);
sim_debug        7893 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "OMASK %o\n", TST_I_OMASK);
sim_debug        7894 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "tstOVFfault %o\n", tstOVFfault ());
sim_debug        7895 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "T %o\n", T);
sim_debug        7896 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "EOvr %o\n", EOvr);
sim_debug        7897 src/dps8/dps8_eis.c sim_debug (DBG_CAC, & cpu_dev, "Ovr %o\n", Ovr);
sim_debug        8030 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        8299 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        8303 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        8516 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        8686 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        8690 src/dps8/dps8_eis.c     sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        8890 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb N1 %d N2 %d\n", e -> N1, e -> N2);
sim_debug        8917 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(min(e->N1, e->N2)) i %d b1 %d b2 %d\n", i, b1, b2);
sim_debug        8937 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(e->N1 < e->N2) i %d b1fill %d b2 %d\n", i, b1, b2);
sim_debug        8957 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "cmpb(e->N1 > e->N2) i %d b1 %d b2fill %d\n", i, b1, b2);
sim_debug        9554 src/dps8/dps8_eis.c     sim_debug (DBG_CAC, & cpu_dev,
sim_debug        9720 src/dps8/dps8_eis.c 
sim_debug        9745 src/dps8/dps8_eis.c 
sim_debug        9756 src/dps8/dps8_eis.c 
sim_debug        9778 src/dps8/dps8_eis.c 
sim_debug        9799 src/dps8/dps8_eis.c 
sim_debug        9820 src/dps8/dps8_eis.c 
sim_debug        9840 src/dps8/dps8_eis.c 
sim_debug        9847 src/dps8/dps8_eis.c 
sim_debug        12376 src/dps8/dps8_eis.c 
sim_debug        12378 src/dps8/dps8_eis.c 
sim_debug        12422 src/dps8/dps8_eis.c 
sim_debug        12425 src/dps8/dps8_eis.c 
sim_debug        12441 src/dps8/dps8_eis.c 
sim_debug        12460 src/dps8/dps8_eis.c 
sim_debug        12550 src/dps8/dps8_eis.c 
sim_debug        12567 src/dps8/dps8_eis.c 
sim_debug        12589 src/dps8/dps8_eis.c 
sim_debug        12602 src/dps8/dps8_eis.c 
sim_debug        12616 src/dps8/dps8_eis.c 
sim_debug        12620 src/dps8/dps8_eis.c 
sim_debug        12636 src/dps8/dps8_eis.c 
sim_debug        12679 src/dps8/dps8_eis.c 
sim_debug        12716 src/dps8/dps8_eis.c 
sim_debug        12734 src/dps8/dps8_eis.c 
sim_debug        12742 src/dps8/dps8_eis.c 
sim_debug        12924 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: clz1 %d clz2 %d\n",clz1,clz2);
sim_debug        12930 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d S1 %d S2 %d N1 %d N2 %d clz1 %d clz2 %d E1 %d E2 %d SF2 %d NQ %d\n",e->S1,e->S2,e->N1,e->N2,clz1,clz2,op1->exponent,op2->exponent,e->SF2,NQ);
sim_debug        12951 src/dps8/dps8_eis.c         ) { sim_debug (DBG_TRACEEXT, & cpu_dev, "oops! dv2d anomalous results"); }      // divide by zero has already been checked before
sim_debug        13004 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: exp1 %d exp2 %d digits op1 %d op2 %d op1a %d op2a %d\n",op1->exponent,op2->exponent,op1->digits,op2->digits,_1a.digits,_2a.digits);
sim_debug        13015 src/dps8/dps8_eis.c             sim_debug (DBG_TRACEEXT, & cpu_dev, "dv2d: addzero n2 %d %s exp %d\n",n2,res,op3->exponent);
sim_debug        13352 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: clz1 %d clz2 %d\n",clz1,clz2);
sim_debug        13358 src/dps8/dps8_eis.c sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d S1 %d S2 %d N1 %d N2 %d clz1 %d clz2 %d E1 %d E2 %d SF3 %d NQ %d\n",e->S1,e->S2,e->N1,e->N2,clz1,clz2,op1->exponent,op2->exponent,e->SF3,NQ);
sim_debug        13379 src/dps8/dps8_eis.c         ) { sim_debug (DBG_TRACEEXT, & cpu_dev, "oops! dv3d anomalous results"); }      // divide by zero has already been checked before
sim_debug        13432 src/dps8/dps8_eis.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: exp1 %d exp2 %d digits op1 %d op2 %d op1a %d op2a %d\n",op1->exponent,op2->exponent,op1->digits,op2->digits,_1a.digits,_2a.digits);
sim_debug        13443 src/dps8/dps8_eis.c             sim_debug (DBG_TRACEEXT, & cpu_dev, "dv3d: addzero n3 %d %s exp %d\n",n3,res,op3->exponent);
sim_debug         395 src/dps8/dps8_faults.c     sim_debug (DBG_FAULT, & cpu_dev,
sim_debug         546 src/dps8/dps8_faults.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "MIF %o\n", TST_I_MIF);
sim_debug         548 src/dps8/dps8_faults.c 
sim_debug         674 src/dps8/dps8_faults.c         sim_debug (DBG_CYCLE, & cpu_dev, "Changing fault number to Trouble fault\n");
sim_debug         717 src/dps8/dps8_faults.c     sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to FAULT_cycle\n");
sim_debug         725 src/dps8/dps8_faults.c     sim_debug (DBG_FAULT, & cpu_dev,
sim_debug         804 src/dps8/dps8_faults.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "MIF %o\n", TST_I_MIF);
sim_debug         848 src/dps8/dps8_faults.c         sim_debug (DBG_CYCLE, & cpu_dev, "Setting cycle to FAULT_cycle\n");
sim_debug         897 src/dps8/dps8_faults.c     sim_debug (DBG_FAULT, & cpu_dev, "setG7fault CPU %d fault %d (%o) sub %"PRId64" %"PRIo64"\n",
sim_debug         909 src/dps8/dps8_faults.c     sim_debug (DBG_FAULT, & cpu_dev, "set_FFV_fault CPU f_fault_no %u\n",
sim_debug         432 src/dps8/dps8_fnp2.c     sim_debug (DBG_TRACE, & fnp_dev, "[%d]notifyCS %d %d\n", lineno, mbx, chan_num);
sim_debug         437 src/dps8/dps8_fnp2.c     sim_debug (DBG_TRACE, & fnp_dev, "[%d]rcd ack_echnego_init\n", lineno);
sim_debug         456 src/dps8/dps8_fnp2.c     sim_debug (DBG_TRACE, & fnp_dev, "[%d]rcd ack_echnego_stop\n", lineno);
sim_debug         475 src/dps8/dps8_fnp2.c     sim_debug (DBG_TRACE, & fnp_dev, "[%d]rcd line_disconnected\n", lineno);
sim_debug         494 src/dps8/dps8_fnp2.c     sim_debug (DBG_TRACE, & fnp_dev, "[%d]rcd input_in_mailbox\n", lineno);
sim_debug         601 src/dps8/dps8_fnp2.c     sim_debug (DBG_TRACE, & fnp_dev, "[%d]rcd accept_input\n", lineno);
sim_debug         644 src/dps8/dps8_fnp2.c     sim_debug (DBG_TRACE, & fnp_dev, "[%d]rcd line_break\n", lineno);
sim_debug         663 src/dps8/dps8_fnp2.c     sim_debug (DBG_TRACE, & fnp_dev, "[%d]rcd send_output\n", lineno);
sim_debug         682 src/dps8/dps8_fnp2.c     sim_debug (DBG_TRACE, & fnp_dev, "[%d]rcd acu_dial_failure\n", lineno);
sim_debug         702 src/dps8/dps8_fnp2.c     sim_debug (DBG_TRACE, & fnp_dev, "[%d]rcd accept_new_terminal\n", lineno);
sim_debug         767 src/dps8/dps8_fnp2.c     sim_debug (DBG_TRACE, & fnp_dev, "[%d]rcd wru_timeout\n", lineno);
sim_debug        1301 src/dps8/dps8_fnp2.c     sim_debug (DBG_TRACE, & fnp_dev, "set_3270_write_complete\n");
sim_debug        1348 src/dps8/dps8_fnp2.c       sim_debug (DBG_TRACE, & fnp_dev, "fnp2 send_stn_in_buffer\r\n");
sim_debug        1398 src/dps8/dps8_fnp2.c         sim_debug (DBG_TRACE, & fnp_dev, "handling in used %u %u\r\n", stnp->stn_in_used, n_to_send);
sim_debug        1468 src/dps8/dps8_fnp2.c     sim_debug (DBG_TRACE, & fnp_dev, "fnp2 3270 poll\n");
sim_debug        1503 src/dps8/dps8_fnp2.c         sim_debug (DBG_TRACE, & fnp_dev, "fnp2 specific poll\n");
sim_debug        1699 src/dps8/dps8_fnp2.c                             sim_debug (DBG_TRACE, & fnp_dev, "FNP input_in_mailbox\n");
sim_debug        1892 src/dps8/dps8_fnp2.c         sim_debug (DBG_ERR, & fnp_dev,
sim_debug        2125 src/dps8/dps8_fnp2.c         sim_debug (DBG_ERR, & fnp_dev,
sim_debug        2145 src/dps8/dps8_fnp2.c         sim_debug (DBG_ERR, & fnp_dev,
sim_debug        2234 src/dps8/dps8_fnp2.c         sim_debug (DBG_ERR, & fnp_dev, "fnpSetConfig: Invalid unit number %ld\n", (long) fnpUnitIdx);
sim_debug        2670 src/dps8/dps8_fnp2.c         sim_debug (DBG_TRACE, & fnp_dev, "process3270Input nread %ld\n", (long)nread);
sim_debug        2671 src/dps8/dps8_fnp2.c         for (int i = 0; i < nread; i ++) sim_debug (DBG_TRACE, & fnp_dev, "%c", isgraph (e2a[buf[i]]) ? e2a[buf[i]] : '.');
sim_debug        2672 src/dps8/dps8_fnp2.c         sim_debug (DBG_TRACE, & fnp_dev, "\r\n");
sim_debug        2673 src/dps8/dps8_fnp2.c         for (int i = 0; i < nread; i ++) sim_debug (DBG_TRACE, & fnp_dev, " %02x", buf[i]);
sim_debug        2674 src/dps8/dps8_fnp2.c         sim_debug (DBG_TRACE, & fnp_dev, "\r\n");
sim_debug        2725 src/dps8/dps8_fnp2.c sim_debug (DBG_TRACE, & fnp_dev, "process3270Input stashed %lu bytes in stn %u; stn_in_size now %u\n", (unsigned long)nread, stn_no, stn_p->stn_in_size);
sim_debug         167 src/dps8/dps8_fnp2_iomcmd.c     sim_debug (DBG_TRACE, & fnp_dev, "[%u] wcd op_code %u 0%o\n", decoded_p->slot_no, decoded_p->op_code, decoded_p->op_code);
sim_debug         177 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    disconnect_this_line\n", decoded_p->slot_no);
sim_debug         196 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    dont_accept_calls\n", decoded_p->slot_no);
sim_debug         203 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    accept_calls\n", decoded_p->slot_no);
sim_debug         216 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    set_framing_chars\n", decoded_p->slot_no);
sim_debug         227 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    dial out\n", decoded_p->slot_no);
sim_debug         235 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    line_control\n", decoded_p->slot_no);
sim_debug         255 src/dps8/dps8_fnp2_iomcmd.c                   sim_debug (DBG_TRACE, & fnp_dev, "ACCEPT_BID\n");
sim_debug         283 src/dps8/dps8_fnp2_iomcmd.c                   sim_debug (DBG_TRACE, & fnp_dev, "REPORT_WRITE_STATUS\n");
sim_debug         286 src/dps8/dps8_fnp2_iomcmd.c                   sim_debug (DBG_TRACE, & fnp_dev, "SET_3270_MODE\n");
sim_debug         290 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "SET_POLLING_ADDR\n");
sim_debug         298 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "    char1 %u\n", c1);
sim_debug         299 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "    char3 %u\n", c3);
sim_debug         310 src/dps8/dps8_fnp2_iomcmd.c                   sim_debug (DBG_TRACE, & fnp_dev, "START_POLL\n");
sim_debug         315 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "SET_SELECT_ADDR\n");
sim_debug         321 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "    char1 %u\n", c1);
sim_debug         322 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "    char3 %u\n", c3);
sim_debug         361 src/dps8/dps8_fnp2_iomcmd.c                   sim_debug (DBG_TRACE, & fnp_dev, "STOP_AUTO_POLL\n");
sim_debug         376 src/dps8/dps8_fnp2_iomcmd.c                   sim_debug (DBG_TRACE, & fnp_dev, "SET_HASP_MODE\n");
sim_debug         379 src/dps8/dps8_fnp2_iomcmd.c                   sim_debug (DBG_TRACE, & fnp_dev, "SET_NAK_LIMIT\n");
sim_debug         382 src/dps8/dps8_fnp2_iomcmd.c                   sim_debug (DBG_TRACE, & fnp_dev, "SET_HASP_TIMERS\n");
sim_debug         447 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev,
sim_debug         539 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev,
sim_debug         568 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev,
sim_debug         581 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev,
sim_debug         611 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    input_fc_chars\n", decoded_p->slot_no);
sim_debug         642 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    output_fc_chars\n", decoded_p->slot_no);
sim_debug         673 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    alter_parameters\n", decoded_p->slot_no);
sim_debug         684 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters fullduplex %u\n", decoded_p->slot_no, flag);
sim_debug         692 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters crecho %u\n", decoded_p->slot_no, flag);
sim_debug         701 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters lfecho %u\n", decoded_p->slot_no, flag);
sim_debug         708 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters dumpoutput\n", decoded_p->slot_no);
sim_debug         718 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters tabecho %u\n", decoded_p->slot_no, flag);
sim_debug         726 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters listen %u\n", decoded_p->slot_no, flag);
sim_debug         749 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters handlequit%u \n", decoded_p->slot_no, flag);
sim_debug         759 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters chngstring %u\n", decoded_p->slot_no, flag);
sim_debug         766 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters wru\n", decoded_p->slot_no);
sim_debug         773 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters echoplex %u\n", decoded_p->slot_no, flag);
sim_debug         781 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters dumpinput\n", decoded_p->slot_no);
sim_debug         795 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters replay %u\n", decoded_p->slot_no, flag);
sim_debug         803 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters polite %u\n", decoded_p->slot_no, flag);
sim_debug         813 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters block_xfer %u %u\n", decoded_p->slot_no, bufsiz1, bufsiz2);
sim_debug         829 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters set_buffer_size %u\n", decoded_p->slot_no, flag);
sim_debug         837 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters breakall %u\n", decoded_p->slot_no, flag);
sim_debug         845 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters prefixnl %u\n", decoded_p->slot_no, flag);
sim_debug         853 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters input_flow_control %u\n", decoded_p->slot_no, flag);
sim_debug         861 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters output_flow_control %u\n", decoded_p->slot_no, flag);
sim_debug         869 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters odd_parity %u\n", decoded_p->slot_no, flag);
sim_debug         877 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters eight_bit_in %u\n", decoded_p->slot_no, flag);
sim_debug         885 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters eight_bit_out %u\n", decoded_p->slot_no, flag);
sim_debug         903 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters unimplemented\n", decoded_p->slot_no);
sim_debug         911 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        alter_parameters illegal\n", decoded_p->slot_no);
sim_debug         922 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    set_delay_table\n", decoded_p->slot_no);
sim_debug        1018 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    report_meters\n", decoded_p->slot_no);
sim_debug        1050 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    unimplemented opcode\n", decoded_p->slot_no);
sim_debug        1061 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]fnp illegal opcode %d (%o)\n", decoded_p->slot_no, decoded_p->op_code, decoded_p->op_code);
sim_debug        1123 src/dps8/dps8_fnp2_iomcmd.c     sim_debug (DBG_TRACE, & fnp_dev, "[%u]rcd wtx_output\n", decoded_p->slot_no);
sim_debug        1189 src/dps8/dps8_fnp2_iomcmd.c     sim_debug (DBG_TRACE, & fnp_dev, "[%u]wtx op_code %u 0%o\n", decoded_p->slot_no, decoded_p->op_code, decoded_p->op_code);
sim_debug        1193 src/dps8/dps8_fnp2_iomcmd.c         sim_debug (DBG_TRACE, & fnp_dev, "[%u]     unimplemented opcode\n", decoded_p->slot_no);
sim_debug        1194 src/dps8/dps8_fnp2_iomcmd.c         sim_debug (DBG_ERR, & fnp_dev, "[%u]fnp wtx unimplemented opcode %d (%o)\n", decoded_p->slot_no, decoded_p->op_code, decoded_p->op_code);
sim_debug        1359 src/dps8/dps8_fnp2_iomcmd.c     sim_debug (DBG_TRACE, & fnp_dev, "io_cmd %u\n", io_cmd);
sim_debug        1389 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]rcd unimplemented\n", decoded_p->slot_no);
sim_debug        1390 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_ERR, & fnp_dev, "[%u]fnp unimplemented io_cmd %d\n", decoded_p->slot_no, io_cmd);
sim_debug        1397 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]rcd illegal opcode\n", decoded_p->slot_no);
sim_debug        1398 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_ERR, & fnp_dev, "[%u]fnp illegal io_cmd %d\n", decoded_p->slot_no, io_cmd);
sim_debug        1442 src/dps8/dps8_fnp2_iomcmd.c     sim_debug (DBG_TRACE, & fnp_dev, "[%u]fnp interrupt\n", decoded_p->slot_no);
sim_debug        1447 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    rtx\n", decoded_p->slot_no);
sim_debug        1452 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        input_accepted\n", decoded_p->slot_no);
sim_debug        1457 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        illegal rtx ack\n", decoded_p->slot_no);
sim_debug        1465 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]    wcd\n", decoded_p->slot_no);
sim_debug        1470 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        terminal accepted\n", decoded_p->slot_no);
sim_debug        1488 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        disconnect_this_line\n", decoded_p->slot_no);
sim_debug        1496 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        reject_request_temp\n", decoded_p->slot_no);
sim_debug        1539 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        unimplemented opcode\n", decoded_p->slot_no);
sim_debug        1540 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_ERR, & fnp_dev, "[%u]fnp reply unimplemented opcode %d (%o)\n", decoded_p->slot_no, op_code, op_code);
sim_debug        1548 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_TRACE, & fnp_dev, "[%u]        illegal opcode\n", decoded_p->slot_no);
sim_debug        1549 src/dps8/dps8_fnp2_iomcmd.c                     sim_debug (DBG_ERR, & fnp_dev, "[%u]fnp reply illegal opcode %d (%o)\n", decoded_p->slot_no, op_code, op_code);
sim_debug        1570 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "[%u]        illegal io_cmd\n", decoded_p->slot_no);
sim_debug        1571 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_ERR, & fnp_dev, "[%u]illegal/unimplemented io_cmd (%d) in fnp submbx\n", decoded_p->slot_no, io_cmd);
sim_debug        1591 src/dps8/dps8_fnp2_iomcmd.c         sim_debug (DBG_ERR, & fnp_dev, "odd -- Multics marked an unused mbx as unused? cell %d (mbx %d)\n", decoded_p->cell, mbx);
sim_debug        1592 src/dps8/dps8_fnp2_iomcmd.c         sim_debug (DBG_ERR, & fnp_dev, "  %d %d %d %d\n", decoded_p->fudp -> fnpMBXinUse [0], decoded_p->fudp -> fnpMBXinUse [1], decoded_p->fudp -> fnpMBXinUse [2], decoded_p->fudp -> fnpMBXinUse [3]);
sim_debug        1596 src/dps8/dps8_fnp2_iomcmd.c         sim_debug (DBG_TRACE, & fnp_dev, "Multics marked cell %d (mbx %d) as unused; was %o\n", decoded_p->cell, mbx, decoded_p->fudp -> fnpMBXinUse [mbx]);
sim_debug        1601 src/dps8/dps8_fnp2_iomcmd.c             sim_debug (DBG_TRACE, & fnp_dev, "clearing wait; was %d\n", linep->waitForMbxDone);
sim_debug        1604 src/dps8/dps8_fnp2_iomcmd.c           sim_debug (DBG_TRACE, & fnp_dev, "  %d %d %d %d\n", decoded_p->fudp->fnpMBXinUse [0], decoded_p->fudp->fnpMBXinUse [1], decoded_p->fudp->fnpMBXinUse [2], decoded_p->fudp->fnpMBXinUse [3]);
sim_debug        1654 src/dps8/dps8_fnp2_iomcmd.c     sim_debug (DBG_TRACE, & fnp_dev, "CS interrupt %u\n", decoded_p->cell);
sim_debug        1669 src/dps8/dps8_fnp2_iomcmd.c         sim_debug (DBG_ERR, & fnp_dev, "fnp illegal cell number %d\n", decoded_p->cell);
sim_debug        1692 src/dps8/dps8_fnp2_iomcmd.c               sim_debug (DBG_TRACE, & fnp_dev, "3270 controller found at unit %u line %u\r\n", devUnitIdx, lineno);
sim_debug        1749 src/dps8/dps8_fnp2_iomcmd.c     sim_debug (DBG_TRACE, & fnp_dev,
sim_debug        1858 src/dps8/dps8_fnp2_iomcmd.c         sim_debug (DBG_TRACE, & fnp_dev,
sim_debug          82 src/dps8/dps8_iefp.c                 sim_debug (DBG_FINAL, & cpu_dev,
sim_debug         103 src/dps8/dps8_iefp.c                 sim_debug (DBG_FINAL, & cpu_dev,
sim_debug         123 src/dps8/dps8_iefp.c                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug         140 src/dps8/dps8_iefp.c                     sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug         172 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\n", address, *result);
sim_debug         182 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\n", address, *result);
sim_debug         198 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
sim_debug         208 src/dps8/dps8_iefp.c           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRead (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
sim_debug         234 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\n", address, *result);
sim_debug         244 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\n", address, *result);
sim_debug         260 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
sim_debug         271 src/dps8/dps8_iefp.c           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "readOperandRead (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
sim_debug         298 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\n", address, *result);
sim_debug         308 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\n", address, *result);
sim_debug         324 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
sim_debug         334 src/dps8/dps8_iefp.c           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadOperandRMW (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
sim_debug         360 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\n", address, *result);
sim_debug         370 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\n", address, *result);
sim_debug         386 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
sim_debug         396 src/dps8/dps8_iefp.c           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadAPUDataRMW (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
sim_debug         424 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\n", address, *result);
sim_debug         434 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\n", address, *result);
sim_debug         450 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
sim_debug         460 src/dps8/dps8_iefp.c           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadInstructionFetch (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
sim_debug         486 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read:       bar address=%08o  readData=%012"PRIo64"\n", address, *result);
sim_debug         496 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read:       abs address=%08o  readData=%012"PRIo64"\n", address, *result);
sim_debug         512 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read:  bar iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
sim_debug         522 src/dps8/dps8_iefp.c           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "ReadIndirectWordFetch (Actual) Read:  iefpFinalAddress=%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress, * result);
sim_debug         555 src/dps8/dps8_iefp.c               sim_debug (DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
sim_debug         569 src/dps8/dps8_iefp.c             sim_debug (DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
sim_debug         589 src/dps8/dps8_iefp.c            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         601 src/dps8/dps8_iefp.c             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         606 src/dps8/dps8_iefp.c               sim_debug (DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         640 src/dps8/dps8_iefp.c               sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
sim_debug         654 src/dps8/dps8_iefp.c             sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
sim_debug         674 src/dps8/dps8_iefp.c            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         686 src/dps8/dps8_iefp.c             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         690 src/dps8/dps8_iefp.c             sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRead (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         722 src/dps8/dps8_iefp.c               sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
sim_debug         736 src/dps8/dps8_iefp.c             sim_debug (DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
sim_debug         756 src/dps8/dps8_iefp.c            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         768 src/dps8/dps8_iefp.c             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2OperandRMW (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         800 src/dps8/dps8_iefp.c               sim_debug (DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
sim_debug         814 src/dps8/dps8_iefp.c             sim_debug (DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
sim_debug         834 src/dps8/dps8_iefp.c            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         846 src/dps8/dps8_iefp.c             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2InstructionFetch (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         871 src/dps8/dps8_iefp.c        sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         883 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2 (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         912 src/dps8/dps8_iefp.c               sim_debug (DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read:       bar address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
sim_debug         926 src/dps8/dps8_iefp.c             sim_debug (DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read:       abs address=%08o" "  readData=%012"PRIo64"\n", address + i, result [i]);
sim_debug         946 src/dps8/dps8_iefp.c            sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read:  bar iefpFinalAddress=" "%08o  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         958 src/dps8/dps8_iefp.c             sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Read2IndirectWordFetch (Actual) Read:  iefpFinalAddress=%08o" "  readData=%012"PRIo64"\n", cpu.iefpFinalAddress + i, result [i]);
sim_debug         997 src/dps8/dps8_iefp.c                       sim_debug (DBG_FINAL, & cpu_dev,
sim_debug        1017 src/dps8/dps8_iefp.c                       sim_debug (DBG_FINAL, & cpu_dev,
sim_debug        1044 src/dps8/dps8_iefp.c                      sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug        1066 src/dps8/dps8_iefp.c                           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug        1121 src/dps8/dps8_iefp.c                       sim_debug (DBG_FINAL, & cpu_dev,
sim_debug        1141 src/dps8/dps8_iefp.c                       sim_debug (DBG_FINAL, & cpu_dev,
sim_debug        1168 src/dps8/dps8_iefp.c                      sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug        1191 src/dps8/dps8_iefp.c                           sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug        1227 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "Write(Actual) Write:      bar address=%08o writeData=%012"PRIo64"\n", address, data);
sim_debug        1240 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "Write(Actual) Write:      abs address=%08o writeData=%012"PRIo64"\n", address, data);
sim_debug        1256 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data);
sim_debug        1264 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data);
sim_debug        1292 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write:      bar address=%08o writeData=%012"PRIo64"\n", address, data);
sim_debug        1302 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write:      abs address=%08o writeData=%012"PRIo64"\n", address, data);
sim_debug        1318 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data);
sim_debug        1326 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteAPUDataStore(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data);
sim_debug        1355 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write:      bar address=%08o writeData=%012"PRIo64"\n", address, data);
sim_debug        1368 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write:      abs address=%08o writeData=%012"PRIo64"\n", address, data);
sim_debug        1384 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write: bar iefpFinalAddress=%08o writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data);
sim_debug        1392 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "WriteOperandStore(Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64"\n", cpu.iefpFinalAddress, data);
sim_debug        1429 src/dps8/dps8_iefp.c                 sim_debug (DBG_FINAL, & cpu_dev,
sim_debug        1440 src/dps8/dps8_iefp.c                 sim_debug (DBG_FINAL, & cpu_dev,
sim_debug        1462 src/dps8/dps8_iefp.c                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug        1476 src/dps8/dps8_iefp.c                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug        1512 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "Write2OperandStore (Actual) Write:      bar address=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n", address, data [0], data [1]);
sim_debug        1518 src/dps8/dps8_iefp.c         sim_debug (DBG_FINAL, & cpu_dev, "Write2OperandStore (Actual) Write:      abs address=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n", address, data [0], data [1]);
sim_debug        1535 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write2OperandStore (Actual) Write: bar iefpFinalAddress=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n", address, data [0], data [1]);
sim_debug        1544 src/dps8/dps8_iefp.c         sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev, "Write2OperandStore (Actual) Write: iefpFinalAddress=%08o " "writeData=%012"PRIo64" %012"PRIo64"\n", address, data [0], data [1]);
sim_debug        1573 src/dps8/dps8_iefp.c                 sim_debug (DBG_FINAL, & cpu_dev,
sim_debug        1588 src/dps8/dps8_iefp.c                 sim_debug (DBG_FINAL, & cpu_dev,
sim_debug        1610 src/dps8/dps8_iefp.c                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug        1624 src/dps8/dps8_iefp.c                 sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug        1661 src/dps8/dps8_iefp.c                       sim_debug (DBG_FINAL, & cpu_dev,
sim_debug        1681 src/dps8/dps8_iefp.c                       sim_debug (DBG_FINAL, & cpu_dev,
sim_debug        1708 src/dps8/dps8_iefp.c                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug        1728 src/dps8/dps8_iefp.c                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug        1790 src/dps8/dps8_iefp.c                       sim_debug (DBG_FINAL, & cpu_dev,
sim_debug        1810 src/dps8/dps8_iefp.c                       sim_debug (DBG_FINAL, & cpu_dev,
sim_debug        1837 src/dps8/dps8_iefp.c                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug        1857 src/dps8/dps8_iefp.c                       sim_debug (DBG_APPENDING | DBG_FINAL, & cpu_dev,
sim_debug          93 src/dps8/dps8_ins.c     sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         148 src/dps8/dps8_ins.c         sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         172 src/dps8/dps8_ins.c     sim_debug (DBG_ADDRMOD, &cpu_dev,
sim_debug         175 src/dps8/dps8_ins.c     sim_debug (DBG_ADDRMOD, &cpu_dev,
sim_debug         194 src/dps8/dps8_ins.c         sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         207 src/dps8/dps8_ins.c         sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         233 src/dps8/dps8_ins.c         sim_debug (DBG_ADDRMOD, & cpu_dev,
sim_debug         291 src/dps8/dps8_ins.c     sim_debug (DBG_TRACE, & cpu_dev, "%s %05o:%06o\n",
sim_debug         307 src/dps8/dps8_ins.c     sim_debug (DBG_FAULT, & cpu_dev, "CU: P %d IR %#o PSR %0#o IC %0#o TSR %0#o\n",
sim_debug         310 src/dps8/dps8_ins.c     sim_debug (DBG_FAULT, & cpu_dev, "CU: xsf %d rf %d rpt %d rd %d rl %d pot %d xde %d xdo %d itp %d rfi %d its %d fif %d hold %0#o\n",
sim_debug         315 src/dps8/dps8_ins.c     sim_debug (DBG_FAULT, & cpu_dev, "CU: iwb %012"PRIo64" irodd %012"PRIo64"\n",
sim_debug         584 src/dps8/dps8_ins.c sim_debug (DBG_TRACEEXT, & cpu_dev, "%s sets XSF to %o\n", __func__, cpu.cu.XSF);
sim_debug        1174 src/dps8/dps8_ins.c                     sim_debug (flag, &cpu_dev, "%06o|%06o %s\n",
sim_debug        1179 src/dps8/dps8_ins.c                     sim_debug (flag, &cpu_dev, "%06o %s\n", cpu.PPR.IC, where);
sim_debug        1186 src/dps8/dps8_ins.c                     sim_debug (flag, &cpu_dev, "%05o:%06o|%06o %s\n",
sim_debug        1192 src/dps8/dps8_ins.c                     sim_debug (flag, &cpu_dev, "%05o:%06o %s\n",
sim_debug        1202 src/dps8/dps8_ins.c                 sim_debug (flag, &cpu_dev,
sim_debug        1220 src/dps8/dps8_ins.c                 sim_debug (flag, &cpu_dev,
sim_debug        1240 src/dps8/dps8_ins.c                 sim_debug (flag, &cpu_dev,
sim_debug        1259 src/dps8/dps8_ins.c                 sim_debug (flag, &cpu_dev,
sim_debug        1763 src/dps8/dps8_ins.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD first %d rpt %d rd %d e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, cpu.cu.rpt, cpu.cu.rd, cpu.PPR.IC & 1, cpu.rX[0], !! (cpu.rX[0] & 01000), !! (cpu.rX[0] & 0400));
sim_debug        1764 src/dps8/dps8_ins.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD CA %06o\n", cpu.TPR.CA);
sim_debug        1790 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; offset is %06o\n", offset);
sim_debug        1794 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d was %06o\n", Xn, cpu.rX[Xn]);
sim_debug        1801 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "rpt/rd/rl repeat first; X%d now %06o\n", Xn, cpu.rX[Xn]);
sim_debug        1817 src/dps8/dps8_ins.c     sim_debug (DBG_APPENDING, &cpu_dev, "initialize EIS descriptors\n");
sim_debug        1875 src/dps8/dps8_ins.c       sim_debug (DBG_APPENDING, &cpu_dev, "doPtrReg: PR[%o] SNR=%05o RNR=%o WORDNO=%06o " "BITNO=%02o\n", n, cpu.PAR[n].SNR, cpu.PAR[n].RNR, cpu.PAR[n].WORDNO, GET_PR_BITNO (n));
sim_debug        1890 src/dps8/dps8_ins.c       sim_debug (DBG_APPENDING, &cpu_dev, "doPtrReg: n=%o offset=%05o TPR.CA=%06o " "TPR.TBR=%o TPR.TSR=%05o TPR.TRR=%o\n", n, offset, cpu.TPR.CA, cpu.TPR.TBR, cpu.TPR.TSR, cpu.TPR.TRR);
sim_debug        2035 src/dps8/dps8_ins.c       sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta first %d rf %d rpt %d rd %d " "e/o %d X0 %06o a %d b %d\n", cpu.cu.repeat_first, rf, cpu.cu.rpt, cpu.cu.rd, icOdd, cpu.rX[0], rptA, rptB);
sim_debug        2045 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]);
sim_debug        2061 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]);
sim_debug        2073 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "RPT/RPD delta; X%d now %06o\n", Xn, cpu.rX[Xn]);
sim_debug        2125 src/dps8/dps8_ins.c       sim_debug (DBG_TRACEEXT, & cpu_dev, "tally %d\n", x);
sim_debug        2127 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "tally runout\n");
sim_debug        2131 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "not tally runout\n");
sim_debug        2139 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "is zero terminate\n");
sim_debug        2144 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "is not zero terminate\n");
sim_debug        2149 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "is neg terminate\n");
sim_debug        2154 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "is not neg terminate\n");
sim_debug        2159 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "is carry terminate\n");
sim_debug        2164 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "is not carry terminate\n");
sim_debug        2169 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "is overflow terminate\n");
sim_debug        2182 src/dps8/dps8_ins.c         sim_debug (DBG_TRACEEXT, & cpu_dev, "not terminate\n");
sim_debug        2220 src/dps8/dps8_ins.c     sim_debug (DBG_REGDUMPAQI, &cpu_dev, "A=%012"PRIo64" Q=%012"PRIo64" IR:%s\n", cpu.rA, cpu.rQ, dump_flags (buf, cpu.cu.IR));
sim_debug        2222 src/dps8/dps8_ins.c     sim_debug (DBG_REGDUMPFLT, &cpu_dev, "E=%03o A=%012"PRIo64" Q=%012"PRIo64" %.10Lg\n", cpu.rE, cpu.rA, cpu.rQ, EAQToIEEElongdouble ());
sim_debug        2224 src/dps8/dps8_ins.c     sim_debug (DBG_REGDUMPFLT, &cpu_dev, "E=%03o A=%012"PRIo64" Q=%012"PRIo64" %.10g\n", cpu.rE, cpu.rA, cpu.rQ, EAQToIEEEdouble ());
sim_debug        2226 src/dps8/dps8_ins.c     sim_debug (DBG_REGDUMPIDX, &cpu_dev, "X[0]=%06o X[1]=%06o X[2]=%06o X[3]=%06o\n", cpu.rX[0], cpu.rX[1], cpu.rX[2], cpu.rX[3]);
sim_debug        2227 src/dps8/dps8_ins.c     sim_debug (DBG_REGDUMPIDX, &cpu_dev, "X[4]=%06o X[5]=%06o X[6]=%06o X[7]=%06o\n", cpu.rX[4], cpu.rX[5], cpu.rX[6], cpu.rX[7]);
sim_debug        2229 src/dps8/dps8_ins.c       sim_debug (DBG_REGDUMPPR, &cpu_dev, "PR%d/%s: SNR=%05o RNR=%o WORDNO=%06o BITNO:%02o ARCHAR:%o ARBITNO:%02o\n", n, PRalias[n], cpu.PR[n].SNR, cpu.PR[n].RNR, cpu.PR[n].WORDNO, GET_PR_BITNO (n), GET_AR_CHAR (n), GET_AR_BITNO (n));
sim_debug        2231 src/dps8/dps8_ins.c     sim_debug (DBG_REGDUMPPPR, &cpu_dev, "PRR:%o PSR:%05o P:%o IC:%06o\n", cpu.PPR.PRR, cpu.PPR.PSR, cpu.PPR.P, cpu.PPR.IC);
sim_debug        2232 src/dps8/dps8_ins.c     sim_debug (DBG_REGDUMPDSBR, &cpu_dev, "ADDR:%08o BND:%05o U:%o STACK:%04o\n", cpu.DSBR.ADDR, cpu.DSBR.BND, cpu.DSBR.U, cpu.DSBR.STACK);
sim_debug        2854 src/dps8/dps8_ins.c               sim_debug (DBG_APPENDING, & cpu_dev,
sim_debug        4910 src/dps8/dps8_ins.c               sim_debug (DBG_CAC, & cpu_dev, "\n");
sim_debug        4911 src/dps8/dps8_ins.c               sim_debug (DBG_CAC, & cpu_dev,
sim_debug        4914 src/dps8/dps8_ins.c               sim_debug (DBG_CAC, & cpu_dev,
sim_debug        4925 src/dps8/dps8_ins.c               sim_debug (DBG_CAC, & cpu_dev, ">>> quot 1 %"PRId64"\n", quotient);
sim_debug        4926 src/dps8/dps8_ins.c               sim_debug (DBG_CAC, & cpu_dev, ">>> rem 1 %"PRId64"\n", remainder);
sim_debug        4942 src/dps8/dps8_ins.c 
sim_debug        4944 src/dps8/dps8_ins.c 
sim_debug        4952 src/dps8/dps8_ins.c               sim_debug (DBG_CAC, & cpu_dev,
sim_debug        4954 src/dps8/dps8_ins.c               sim_debug (DBG_CAC, & cpu_dev,
sim_debug        4959 src/dps8/dps8_ins.c                   sim_debug (DBG_CAC, & cpu_dev,
sim_debug        4967 src/dps8/dps8_ins.c                   sim_debug (DBG_ERR, & cpu_dev,
sim_debug        4979 src/dps8/dps8_ins.c               sim_debug (DBG_CAC, & cpu_dev, "rA (rem)  %012"PRIo64"\n", cpu.rA);
sim_debug        4980 src/dps8/dps8_ins.c               sim_debug (DBG_CAC, & cpu_dev, "rQ (quot) %012"PRIo64"\n", cpu.rQ);
sim_debug        5641 src/dps8/dps8_ins.c             sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        6123 src/dps8/dps8_ins.c           sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        6797 src/dps8/dps8_ins.c                 sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        6805 src/dps8/dps8_ins.c                 sim_debug (DBG_TRACEEXT, & cpu_dev,
sim_debug        7229 src/dps8/dps8_ins.c           sim_debug (DBG_TRACEEXT, & cpu_dev, "ldt TR %d (%o)\n",
sim_debug        7279 src/dps8/dps8_ins.c             sim_debug (DBG_TRACEEXT, & cpu_dev, "RALR set to %o\n", cpu.rRALR);
sim_debug        8370 src/dps8/dps8_ins.c                 sim_debug (DBG_MSG, & cpu_dev, "BCE DIS causes CPU halt\n");
sim_debug        8390 src/dps8/dps8_ins.c 
sim_debug        8400 src/dps8/dps8_ins.c                 sim_debug (DBG_MSG, & cpu_dev, "sys_trouble$die DIS causes CPU halt\n");
sim_debug        8405 src/dps8/dps8_ins.c           sim_debug (DBG_TRACEEXT, & cpu_dev, "entered DIS_cycle\n");
sim_debug        8432 src/dps8/dps8_ins.c               sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS sees an interrupt\n");
sim_debug        8449 src/dps8/dps8_ins.c               sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS sees a TRO\n");
sim_debug        8455 src/dps8/dps8_ins.c               sim_debug (DBG_TRACEEXT, & cpu_dev, "DIS refetches\n");
sim_debug        9401 src/dps8/dps8_ins.c     sim_debug (DBG_APPENDING, & cpu_dev, "absa CA:%08o\n", cpu.TPR.CA);
sim_debug        9456 src/dps8/dps8_ins.c         sim_debug (DBG_FAULT, & cpu_dev, "RCU interrupt return\n");
sim_debug        9534 src/dps8/dps8_ins.c         sim_debug (DBG_FAULT, & cpu_dev, "RCU FIF REFETCH return\n");
sim_debug        9542 src/dps8/dps8_ins.c         sim_debug (DBG_FAULT, & cpu_dev, "RCU rfi refetch return\n");
sim_debug        9562 src/dps8/dps8_ins.c         sim_debug (DBG_FAULT, & cpu_dev, "RCU MME2 restart return\n");
sim_debug        9578 src/dps8/dps8_ins.c         sim_debug (DBG_FAULT, & cpu_dev, "RCU rfi/FIF REFETCH return\n");
sim_debug        9589 src/dps8/dps8_ins.c         sim_debug (DBG_FAULT, & cpu_dev, "RCU MME2 restart return\n");
sim_debug        9620 src/dps8/dps8_ins.c         sim_debug (DBG_FAULT, & cpu_dev, "RCU sync fault return\n");
sim_debug        9634 src/dps8/dps8_ins.c         sim_debug (DBG_FAULT, & cpu_dev, "RCU MMEx sync fault return\n");
sim_debug        9644 src/dps8/dps8_ins.c         sim_debug (DBG_FAULT, & cpu_dev, "RCU LUF RESTART return\n");
sim_debug        9661 src/dps8/dps8_ins.c         sim_debug (DBG_FAULT, & cpu_dev, "RCU ACV RESTART return\n");
sim_debug        1764 src/dps8/dps8_iom.c     sim_debug (DBG_DEBUG, & iom_dev, "%s: Status: 0%012"PRIo64" 0%012"PRIo64"\n",
sim_debug        1768 src/dps8/dps8_iom.c         sim_debug (DBG_WARN, &iom_dev,
sim_debug        1811 src/dps8/dps8_iom.c             sim_debug (DBG_WARN, & iom_dev,
sim_debug        2354 src/dps8/dps8_iom.c     sim_debug (DBG_DEBUG, & iom_dev,
sim_debug        2402 src/dps8/dps8_iom.c         sim_debug (DBG_DEBUG, & iom_dev,
sim_debug        2420 src/dps8/dps8_iom.c         sim_debug (DBG_DEBUG, & iom_dev,
sim_debug        2492 src/dps8/dps8_iom.c     sim_debug (DBG_DEBUG, & iom_dev, "%s: addr %08o\n", __func__, addr);
sim_debug        2535 src/dps8/dps8_iom.c       sim_debug (DBG_DEBUG, & iom_dev,
sim_debug        2541 src/dps8/dps8_iom.c         sim_debug (DBG_DEBUG, & iom_dev,
sim_debug        2546 src/dps8/dps8_iom.c         sim_debug (DBG_DEBUG, & iom_dev,
sim_debug        2581 src/dps8/dps8_iom.c     sim_debug (DBG_DEBUG, & iom_dev,
sim_debug        2629 src/dps8/dps8_iom.c     sim_debug (DBG_DEBUG, & iom_dev,
sim_debug        3040 src/dps8/dps8_iom.c   sim_debug (DBG_DEBUG, & iom_dev, "%s: Payload channel %c%02o\n", __func__, iomChar (iomUnitIdx), chan);
sim_debug        3287 src/dps8/dps8_iom.c   sim_debug (DBG_DEBUG, & iom_dev, "%s: Connect channel\n", __func__);
sim_debug        3341 src/dps8/dps8_iom.c       sim_debug (DBG_DEBUG, & iom_dev, "%s: PCW %012llo %012llo chan %02o\n", __func__, q->PCW0, q->PCW1, q->PCW_CHAN);
sim_debug        3470 src/dps8/dps8_iom.c     sim_debug (DBG_DEBUG, & iom_dev,
sim_debug        3482 src/dps8/dps8_iom.c     sim_debug (DBG_DEBUG, & iom_dev,
sim_debug        3536 src/dps8/dps8_iom.c         sim_debug (DBG_DEBUG, & iom_dev,
sim_debug        1214 src/dps8/dps8_math.c sim_debug (DBG_TRACEEXT, & cpu_dev, "fmp A %012"PRIo64" Q %012"PRIo64" E %03o\n", cpu.rA, cpu.rQ, cpu.rE);
sim_debug        2308 src/dps8/dps8_math.c   sim_debug (DBG_TRACEEXT, & cpu_dev, "dufm e1 %d %03o m1 %012"PRIo64" %012"PRIo64"\n", e1, e1, (word36) (m1 >> 36) & MASK36, (word36) m1 & MASK36);
sim_debug        2323 src/dps8/dps8_math.c   sim_debug (DBG_TRACEEXT, & cpu_dev, "dufm e2 %d %03o m2 %012"PRIo64" %012"PRIo64"\n", e2, e2, (word36) (m2 >> 36) & MASK36, (word36) m2 & MASK36);
sim_debug         388 src/dps8/dps8_mgp.c       sim_debug(DBG_DEBUG, &mgp_dev,
sim_debug         393 src/dps8/dps8_mgp.c   sim_debug(DBG_DEBUG, &mgp_dev,
sim_debug         448 src/dps8/dps8_mgp.c   sim_debug(DBG_TRACE, &mgp_dev,
sim_debug         476 src/dps8/dps8_mgp.c       sim_debug(DBG_DEBUG, &mgp_dev, "%s: mgp_dev_$read\n", __func__);
sim_debug         543 src/dps8/dps8_mgp.c       sim_debug(DBG_DEBUG, &mgp_dev, "%s: mgp_dev_$write\n", __func__);
sim_debug         735 src/dps8/dps8_mt.c         sim_debug (DBG_ERR, & tape_dev,
sim_debug         991 src/dps8/dps8_mt.c     sim_debug (DBG_DEBUG, & tape_dev, "%s: Read %s record\n", __func__,
sim_debug        1002 src/dps8/dps8_mt.c     sim_debug (DBG_DEBUG, & tape_dev, "%s: sim_tape_rdrecf returned %d, with tbc %d\n",
sim_debug        1007 src/dps8/dps8_mt.c          sim_debug (DBG_NOTIFY, & tape_dev,
sim_debug        1021 src/dps8/dps8_mt.c         sim_debug (DBG_NOTIFY, & tape_dev,
sim_debug        1040 src/dps8/dps8_mt.c         sim_debug (DBG_ERR, & tape_dev,
sim_debug        1043 src/dps8/dps8_mt.c         sim_debug (DBG_ERR, & tape_dev,
sim_debug        1063 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev,
sim_debug        1069 src/dps8/dps8_mt.c     sim_debug (DBG_DEBUG, & tape_dev,
sim_debug        1107 src/dps8/dps8_mt.c         sim_debug (DBG_WARN, & tape_dev,
sim_debug        1242 src/dps8/dps8_mt.c     sim_debug (DBG_DEBUG, & tape_dev, "%s: Write %s record\n", __func__,
sim_debug        1250 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev,
sim_debug        1256 src/dps8/dps8_mt.c     sim_debug (DBG_DEBUG, & tape_dev,
sim_debug        1314 src/dps8/dps8_mt.c             sim_debug (DBG_WARN, & tape_dev,
sim_debug        1334 src/dps8/dps8_mt.c     sim_debug (DBG_DEBUG, & tape_dev, "%s: sim_tape_wrrecf returned %d, with tbc %d\n",
sim_debug        1346 src/dps8/dps8_mt.c             sim_debug (DBG_NOTIFY, & tape_dev,
sim_debug        1379 src/dps8/dps8_mt.c     sim_debug (DBG_INFO, & tape_dev,
sim_debug        1405 src/dps8/dps8_mt.c     sim_debug (DBG_DEBUG, & tape_dev,
sim_debug        1437 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev,
sim_debug        1494 src/dps8/dps8_mt.c   sim_debug (DBG_DEBUG, & tape_dev, "%s: Tape %c%02o_%02o\n", __func__, iomChar (iomUnitIdx), chan, dev_code);
sim_debug        1522 src/dps8/dps8_mt.c     sim_debug (DBG_DEBUG, & tape_dev, "%s: IDCW_DEV_CMD %oo %d.\n", __func__, p->IDCW_DEV_CMD, p->IDCW_DEV_CMD);
sim_debug        1531 src/dps8/dps8_mt.c             sim_debug (DBG_DEBUG, & tape_dev, "%s: controller suspend\n", __func__);
sim_debug        1537 src/dps8/dps8_mt.c           sim_debug (DBG_DEBUG, & tape_dev, "%s: Request status: %04o control %0o chan_cmd %02o\n", __func__,
sim_debug        1599 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Read controller main memory\n", __func__);
sim_debug        1609 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Read 9 record\n", __func__);
sim_debug        1625 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Read binary record\n", __func__);
sim_debug        1659 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: initiate read data transfer\n", __func__);
sim_debug        1676 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Write 9 record\n", __func__);
sim_debug        1691 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Write binary record\n", __func__);
sim_debug        1704 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Write Control Registers\n", __func__);
sim_debug        1714 src/dps8/dps8_mt.c             sim_debug (DBG_DEBUG, & tape_dev, "%s: Release controller\n", __func__);
sim_debug        1716 src/dps8/dps8_mt.c             sim_debug (DBG_DEBUG, & tape_dev, "%s: Release status: %04o control %0o chan_cmd %02o\n",
sim_debug        1750 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Write controller main memory\n", __func__);
sim_debug        1767 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s Reset status\n", __func__);
sim_debug        1785 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Set 6250 cpi\n", __func__);
sim_debug        1793 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Set 800 bpi\n", __func__);
sim_debug        1806 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Set 800 bpi\n", __func__);
sim_debug        1819 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Set 556 bpi\n", __func__);
sim_debug        1836 src/dps8/dps8_mt.c           sim_debug (DBG_DEBUG, & tape_dev, "%s: Tally of zero interpreted as 64\n", __func__);
sim_debug        1839 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Forward skip record %d\n", __func__, tally);
sim_debug        1892 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s:: Forward Skip File\n", __func__);
sim_debug        1915 src/dps8/dps8_mt.c         sim_debug (DBG_NOTIFY, & tape_dev, "%s: Forward space %d files\n", __func__, tally);
sim_debug        1941 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Backspace Record\n", __func__);
sim_debug        1949 src/dps8/dps8_mt.c           sim_debug (DBG_DEBUG, & tape_dev, "%s: Tally of zero interpreted as 64\n", __func__);
sim_debug        1953 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Backspace record tally %d\n", __func__, tally);
sim_debug        1981 src/dps8/dps8_mt.c         sim_debug (DBG_NOTIFY, & tape_dev, "%s: Backspace %d records\n", __func__, skipped);
sim_debug        2004 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Backspace File\n", __func__);
sim_debug        2015 src/dps8/dps8_mt.c 
sim_debug        2019 src/dps8/dps8_mt.c 
sim_debug        2048 src/dps8/dps8_mt.c         sim_debug (DBG_NOTIFY, & tape_dev, "%s: Backspace %d records\n", __func__, tally);
sim_debug        2076 src/dps8/dps8_mt.c           sim_debug (DBG_DEBUG, & tape_dev, "%s: Request device status: %o\n", __func__, p->stati);
sim_debug        2101 src/dps8/dps8_mt.c           sim_debug (DBG_DEBUG, & tape_dev, "%s: Reset device status: %o\n", __func__, p->stati);
sim_debug        2116 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Write tape mark\n", __func__);
sim_debug        2127 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: returned %d\n", __func__, ret);
sim_debug        2132 src/dps8/dps8_mt.c             sim_debug (DBG_NOTIFY, & tape_dev, "%s: EOM: %s\n", __func__, simh_tape_msg (ret));
sim_debug        2156 src/dps8/dps8_mt.c         sim_debug (DBG_INFO, & tape_dev, "%s: Wrote tape mark; status %04o\n", __func__, p->stati);
sim_debug        2169 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: survey_devices\n", __func__);
sim_debug        2182 src/dps8/dps8_mt.c         sim_debug (DBG_WARN, & tape_dev, "%s: Set file permit\n", __func__);
sim_debug        2199 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Set 200 bpi\n", __func__);
sim_debug        2211 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Set 1600 CPI\n", __func__);
sim_debug        2220 src/dps8/dps8_mt.c         sim_debug (DBG_DEBUG, & tape_dev, "%s: Rewind\n", __func__);
sim_debug        2248 src/dps8/dps8_mt.c           sim_debug (DBG_DEBUG, & tape_dev, "%s: Rewind/unload\n", __func__);
sim_debug        2279 src/dps8/dps8_mt.c     sim_debug (DBG_DEBUG, & tape_dev, "%s: stati %04o\n", __func__, p->stati);
sim_debug         555 src/dps8/dps8_prt.c 
sim_debug         561 src/dps8/dps8_prt.c 
sim_debug        1062 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev,
sim_debug        1137 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Request Status\n", __func__);
sim_debug        1142 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Nonedited BCD, Slew One Line\n", __func__);
sim_debug        1152 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Edited BCD, Slew Zero Lines\n", __func__);
sim_debug        1162 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Reset Status\n", __func__);
sim_debug        1175 src/dps8/dps8_prt.c     sim_debug (DBG_DEBUG, & prt_dev, "%s: stati %04o\n", __func__, p->stati);
sim_debug        1219 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Request Status\n", __func__);
sim_debug        1224 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Nonedited ASCII, Slew One Line\n", __func__);
sim_debug        1234 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Load Image Buffer\n", __func__);
sim_debug        1240 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Edited ASCII, Slew Zero Lines\n", __func__);
sim_debug        1250 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Reset Status\n", __func__);
sim_debug        1263 src/dps8/dps8_prt.c     sim_debug (DBG_DEBUG, & prt_dev, "%s: stati %04o\n", __func__, p->stati);
sim_debug        1312 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Request Status\n", __func__);
sim_debug        1317 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Load Image Buffer\n", __func__);
sim_debug        1323 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Nonedited ASCII, Slew One Line\n", __func__);
sim_debug        1333 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Edited ASCII, Slew Zero Lines\n", __func__);
sim_debug        1343 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Reset Status\n", __func__);
sim_debug        1356 src/dps8/dps8_prt.c     sim_debug (DBG_DEBUG, & prt_dev, "%s: stati %04o\n", __func__, p->stati);
sim_debug        1406 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Request Status\n", __func__);
sim_debug        1411 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Load Image Buffer\n", __func__);
sim_debug        1417 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Load Image Buffer\n", __func__);
sim_debug        1447 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Load VFC Image\n", __func__);
sim_debug        1453 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Nonedited BCD, Slew Zero Lines\n", __func__);
sim_debug        1463 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Nonedited BCD, Slew One Line\n", __func__);
sim_debug        1473 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Nonedited BCD, Slew Two Lines\n", __func__);
sim_debug        1483 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Nonedited BCD, Slew Top Of Page\n", __func__);
sim_debug        1493 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Nonedited ASCII, Slew Zero Lines\n", __func__);
sim_debug        1503 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Nonedited ASCII, Slew One Line\n", __func__);
sim_debug        1513 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Nonedited ASCII, Slew Two Lines\n", __func__);
sim_debug        1523 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Nonedited ASCII, Slew Top Of Page\n", __func__);
sim_debug        1533 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Edited BCD, Slew Zero Lines\n", __func__);
sim_debug        1543 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Edited BCD, Slew One Line\n", __func__);
sim_debug        1553 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Edited BCD, Slew Two Lines\n", __func__);
sim_debug        1563 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Edited BCD, Slew Top Of Page\n", __func__);
sim_debug        1573 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Edited ASCII, Slew Zero Lines\n", __func__);
sim_debug        1583 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Edited ASCII, Slew One Line\n", __func__);
sim_debug        1593 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Edited ASCII, Slew Two Lines\n", __func__);
sim_debug        1603 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Print Edited ASCII, Slew Top Of Page\n", __func__);
sim_debug        1613 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Reset Status\n", __func__);
sim_debug        1619 src/dps8/dps8_prt.c           sim_debug (DBG_DEBUG, & prt_dev, "%s: Slew One Line\n", __func__);
sim_debug        1635 src/dps8/dps8_prt.c           sim_debug (DBG_DEBUG, & prt_dev, "%s: Slew Two Lines\n", __func__);
sim_debug        1651 src/dps8/dps8_prt.c           sim_debug (DBG_DEBUG, & prt_dev, "%s: Slew To Top Of Page\n", __func__);
sim_debug        1667 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Reserve Device\n", __func__);
sim_debug        1673 src/dps8/dps8_prt.c         sim_debug (DBG_DEBUG, & prt_dev, "%s: Release Device\n", __func__);
sim_debug        1686 src/dps8/dps8_prt.c     sim_debug (DBG_DEBUG, & prt_dev, "%s: stati %04o\n", __func__, p->stati);
sim_debug        1964 src/dps8/dps8_prt.c         sim_debug (DBG_ERR, & prt_dev,
sim_debug         633 src/dps8/dps8_scu.c         sim_debug (DBG_ERR, & scu_dev,
sim_debug         698 src/dps8/dps8_scu.c         sim_debug (DBG_ERR, & scu_dev,
sim_debug         850 src/dps8/dps8_scu.c         sim_debug (DBG_ERR, & scu_dev,
sim_debug        1047 src/dps8/dps8_scu.c     sim_debug (DBG_DEBUG, & scu_dev,
sim_debug        1051 src/dps8/dps8_scu.c     sim_debug (DBG_DEBUG, & scu_dev,
sim_debug        1056 src/dps8/dps8_scu.c 
sim_debug        1060 src/dps8/dps8_scu.c 
sim_debug        1062 src/dps8/dps8_scu.c 
sim_debug        1064 src/dps8/dps8_scu.c 
sim_debug        1068 src/dps8/dps8_scu.c 
sim_debug        1070 src/dps8/dps8_scu.c 
sim_debug        1236 src/dps8/dps8_scu.c             sim_debug (DBG_TRACE, & scu_dev, "finagle clock\n");
sim_debug        1338 src/dps8/dps8_scu.c     sim_debug (DBG_DEBUG, & scu_dev, "deliver_interrupts %o\n", scu_unit_idx);
sim_debug        1359 src/dps8/dps8_scu.c         sim_debug (DBG_DEBUG, & scu_dev, "trying to deliver %d\n", inum);
sim_debug        1360 src/dps8/dps8_scu.c         sim_debug (DBG_INTR, & scu_dev,
sim_debug        1405 src/dps8/dps8_scu.c                 sim_debug (DBG_DEBUG, & scu_dev,
sim_debug        1414 src/dps8/dps8_scu.c sim_debug (DBG_DEBUG, & scu_dev, "interrupt set for CPU %d SCU %d\n", cpu_unit_udx, scu_unit_idx);
sim_debug        1415 src/dps8/dps8_scu.c                 sim_debug (DBG_INTR, & scu_dev,
sim_debug        1426 src/dps8/dps8_scu.c         sim_debug (DBG_DEBUG, & scu_dev, "trying to deliver %d\n", inum);
sim_debug        1427 src/dps8/dps8_scu.c         sim_debug (DBG_INTR, & scu_dev,
sim_debug        1472 src/dps8/dps8_scu.c                 sim_debug (DBG_DEBUG, & scu_dev,
sim_debug        1481 src/dps8/dps8_scu.c sim_debug (DBG_DEBUG, & scu_dev, "interrupt set for CPU %d SCU %d\n", cpu_unit_udx, scu_unit_idx);
sim_debug        1482 src/dps8/dps8_scu.c                 sim_debug (DBG_INTR, & scu_dev,
sim_debug        1507 src/dps8/dps8_scu.c         sim_debug (DBG_TRACE, & scu_dev,
sim_debug        1519 src/dps8/dps8_scu.c         sim_debug (DBG_TRACE, & scu_dev,
sim_debug        1531 src/dps8/dps8_scu.c 
sim_debug        1543 src/dps8/dps8_scu.c 
sim_debug        1589 src/dps8/dps8_scu.c     sim_debug (DBG_DEBUG, & scu_dev, "sscr SCU unit %o\n", scu_unit_idx);
sim_debug        1638 src/dps8/dps8_scu.c             sim_debug (DBG_DEBUG, & scu_dev,
sim_debug        1651 src/dps8/dps8_scu.c                     sim_debug (DBG_DEBUG, & scu_dev,
sim_debug        1658 src/dps8/dps8_scu.c                     sim_debug (DBG_DEBUG, & scu_dev,
sim_debug        1671 src/dps8/dps8_scu.c                 sim_debug (DBG_INTR, & scu_dev,
sim_debug        1718 src/dps8/dps8_scu.c             sim_debug (DBG_DEBUG, & scu_dev, "Set mask register port %d to "
sim_debug        1742 src/dps8/dps8_scu.c                 sim_debug (DBG_WARN, & scu_dev,
sim_debug        1754 src/dps8/dps8_scu.c                 sim_debug (DBG_WARN, & scu_dev,
sim_debug        1767 src/dps8/dps8_scu.c 
sim_debug        1775 src/dps8/dps8_scu.c             sim_debug (DBG_TRACE, & scu_dev,
sim_debug        1782 src/dps8/dps8_scu.c             sim_debug (DBG_INTR, & scu_dev,
sim_debug        1808 src/dps8/dps8_scu.c             sim_debug (DBG_TRACE, & scu_dev,
sim_debug        1811 src/dps8/dps8_scu.c             sim_debug (DBG_INTR, & scu_dev,
sim_debug        1940 src/dps8/dps8_scu.c             sim_debug (DBG_DEBUG, & scu_dev, "rscr 1 %d\n", scu_unit_idx);
sim_debug        2024 src/dps8/dps8_scu.c             sim_debug (DBG_DEBUG, & scu_dev,
sim_debug        2065 src/dps8/dps8_scu.c             sim_debug (DBG_TRACE, & scu_dev,
sim_debug        2180 src/dps8/dps8_scu.c     sim_debug (DBG_DEBUG, & scu_dev,
sim_debug        2194 src/dps8/dps8_scu.c         sim_debug (DBG_ERR, & scu_dev,
sim_debug        2196 src/dps8/dps8_scu.c         sim_debug (DBG_ERR, & scu_dev,
sim_debug        2260 src/dps8/dps8_scu.c             sim_debug (DBG_INFO, & scu_dev,
sim_debug        2339 src/dps8/dps8_scu.c         sim_debug (DBG_ERR, & scu_dev,
sim_debug        2367 src/dps8/dps8_scu.c         sim_debug (DBG_WARN, & scu_dev,
sim_debug        2412 src/dps8/dps8_scu.c                 sim_debug (DBG_TRACE, & scu_dev, "scu_get_highest_intr inum %d pima %u mask 0%011o port %u cells 0%011o\n", inum, pima, mask, port, scu [scu_unit_idx].cells [inum]);
sim_debug        2505 src/dps8/dps8_scu.c         sim_debug (DBG_ERR, & scu_dev,
sim_debug        2520 src/dps8/dps8_scu.c     sim_debug (DBG_TRACE, & scu_dev, "rmcm selected scu port %u\n",
sim_debug        2529 src/dps8/dps8_scu.c         sim_debug (DBG_TRACE, & scu_dev, "rmcm got mask %011o from pima A\n",
sim_debug        2535 src/dps8/dps8_scu.c         sim_debug (DBG_TRACE, & scu_dev, "rmcm got mask %011o from pima B\n",
sim_debug        2557 src/dps8/dps8_scu.c     sim_debug (DBG_TRACE, & scu_dev,
sim_debug        2566 src/dps8/dps8_scu.c     sim_debug (DBG_TRACE, & scu_dev,
sim_debug        2602 src/dps8/dps8_scu.c     sim_debug (DBG_TRACE, & scu_dev, "SMCM SCU port num %d\n", scu_port_num);
sim_debug        2620 src/dps8/dps8_scu.c         sim_debug (DBG_TRACE, & scu_dev, "SMCM intr mask 0 set to %011o\n",
sim_debug        2626 src/dps8/dps8_scu.c         sim_debug (DBG_TRACE, & scu_dev, "SMCM intr mask 1 set to %011o\n",
sim_debug         831 src/dps8/dps8_socket_dev.c         sim_debug (DBG_DEBUG, & skc_dev,
sim_debug         837 src/dps8/dps8_socket_dev.c     sim_debug (DBG_DEBUG, & skc_dev,
sim_debug         853 src/dps8/dps8_socket_dev.c     sim_debug (DBG_DEBUG, & skc_dev, "IDCW_DEV_CODE %d\n", p->IDCW_DEV_CODE);
sim_debug         862 src/dps8/dps8_socket_dev.c             sim_debug (DBG_DEBUG, & skc_dev,
sim_debug         864 src/dps8/dps8_socket_dev.c             sim_debug (DBG_DEBUG, & skc_dev,
sim_debug         866 src/dps8/dps8_socket_dev.c             sim_debug (DBG_DEBUG, & skc_dev,
sim_debug         873 src/dps8/dps8_socket_dev.c             sim_debug (DBG_DEBUG, & skc_dev,
sim_debug         897 src/dps8/dps8_socket_dev.c             sim_debug (DBG_DEBUG, & skc_dev,
sim_debug         930 src/dps8/dps8_socket_dev.c             sim_debug (DBG_DEBUG, & skc_dev,
sim_debug         956 src/dps8/dps8_socket_dev.c             sim_debug (DBG_DEBUG, & skc_dev,
sim_debug         982 src/dps8/dps8_socket_dev.c             sim_debug (DBG_DEBUG, & skc_dev,
sim_debug        1012 src/dps8/dps8_socket_dev.c             sim_debug (DBG_DEBUG, & skc_dev,
sim_debug        1037 src/dps8/dps8_socket_dev.c             sim_debug (DBG_DEBUG, & skc_dev,
sim_debug        1066 src/dps8/dps8_socket_dev.c             sim_debug (DBG_DEBUG, & skc_dev,
sim_debug        1094 src/dps8/dps8_socket_dev.c             sim_debug (DBG_DEBUG, & skc_dev,
sim_debug        1111 src/dps8/dps8_socket_dev.c     sim_debug (DBG_DEBUG, & skc_dev, "stati %04o\n", p->stati);
sim_debug        2615 src/dps8/dps8_sys.c                           sim_debug (dflag, & cpu_dev, "%s", line);
sim_debug        2736 src/dps8/dps8_sys.c                           sim_debug (dflag, & cpu_dev, "%s", line);
sim_debug        2755 src/dps8/dps8_sys.c                               sim_debug (dflag, & cpu_dev, "%s", line);
sim_debug         232 src/dps8/dps8_urp.c         sim_debug (DBG_DEBUG, & urp_dev, "%s: Request Status\n", __func__);
sim_debug         238 src/dps8/dps8_urp.c         sim_debug (DBG_DEBUG, & urp_dev, "%s: Initiate Read Data Xfer\n", __func__);
sim_debug         248 src/dps8/dps8_urp.c         sim_debug (DBG_DEBUG, & urp_dev, "%s: Set Diagnostic Mode\n", __func__);
sim_debug         255 src/dps8/dps8_urp.c         sim_debug (DBG_DEBUG, & urp_dev, "%s: Reset Status\n", __func__);
sim_debug         269 src/dps8/dps8_urp.c     sim_debug (DBG_DEBUG, & urp_dev, "%s: stati %04o\n", __func__, p->stati);
sim_debug         178 src/dps8/dps8_utils.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "Add36b op1 %012"PRIo64" op2 %012"PRIo64" carryin %o flagsToSet %06o flags %06o\n", op1, op2, carryin, flagsToSet, * flags);
sim_debug         249 src/dps8/dps8_utils.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "Add36b res %012"PRIo64" flags %06o ovf %o\n", res, * flags, * ovf);
sim_debug         615 src/dps8/dps8_utils.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1 %012"PRIo64"%012"PRIo64" op2 %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n",
sim_debug         618 src/dps8/dps8_utils.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1 %012"PRIo64"%012"PRIo64" op2 %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n",
sim_debug         659 src/dps8/dps8_utils.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1e %012"PRIo64"%012"PRIo64" op2e %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n",
sim_debug         662 src/dps8/dps8_utils.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b op1e %012"PRIo64"%012"PRIo64" op2e %012"PRIo64"%012"PRIo64" carryin %o flagsToSet %06o flags %06o\n",
sim_debug         673 src/dps8/dps8_utils.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) (rshift_128 (res, 36).l & MASK36), (word36) (res.l & MASK36), * flags, * ovf);
sim_debug         675 src/dps8/dps8_utils.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) ((res >> 36) & MASK36), (word36) (res & MASK36), * flags, * ovf);
sim_debug         753 src/dps8/dps8_utils.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) (rshift_128 (res, 36).l & MASK36), (word36) (res.l & MASK36), * flags, * ovf);
sim_debug         755 src/dps8/dps8_utils.c     sim_debug (DBG_TRACEEXT, & cpu_dev, "Sub72b res %012"PRIo64"%012"PRIo64" flags %06o ovf %o\n", (word36) ((res >> 36) & MASK36), (word36) (res & MASK36), * flags, * ovf);
sim_debug        1091 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1 %016"PRIx64"%016"PRIx64"\n", op1.h, op1.l);
sim_debug        1092 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2 %016"PRIx64"%016"PRIx64"\n", op2.h, op2.l);
sim_debug        1095 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\n", op1s.h, op1s.l);
sim_debug        1096 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2s %016"PRIx64"%016"PRIx64"\n", op2s.h, op2s.l);
sim_debug        1098 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1 %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op1>>64), (uint64_t) op1);
sim_debug        1099 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2 %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op2>>64), (uint64_t) op2);
sim_debug        1102 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op1s %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op1s>>64), (uint64_t) op1s);
sim_debug        1103 src/dps8/dps8_utils.c sim_debug (DBG_TRACEEXT, & cpu_dev, "op2s %016"PRIx64"%016"PRIx64"\n", (uint64_t) (op2s>>64), (uint64_t) op2s);
sim_debug        8338 src/simh/scp.c     sim_debug (SIM_DBG_EVENT, sim_dflt_dev, "Queue Empty New Interval = %d\n", sim_interval);
sim_debug        8352 src/simh/scp.c     sim_debug (SIM_DBG_EVENT, sim_dflt_dev, "Processing Event for %s\n", sim_uname (uptr));
sim_debug        8364 src/simh/scp.c     sim_debug (SIM_DBG_EVENT, sim_dflt_dev, "Processing Queue Complete New Interval = %d\n", sim_interval);
sim_debug        8367 src/simh/scp.c     sim_debug (SIM_DBG_EVENT, sim_dflt_dev, "Processing Queue Complete New Interval = %d(%s)\n", sim_interval, sim_uname(sim_clock_queue));
sim_debug        8406 src/simh/scp.c sim_debug (SIM_DBG_ACTIVATE, sim_dflt_dev, "Activating %s delay=%d\n", sim_uname (uptr), event_time);
sim_debug        8485 src/simh/scp.c sim_debug (SIM_DBG_EVENT, sim_dflt_dev, "Canceling Event for %s\n", sim_uname(uptr));
sim_debug        9494 src/simh/scp.c                     sim_debug (exp->dbit, exp->dptr, "Checking String[0:%d]: %s\n", exp->buf_ins, estr);
sim_debug        9495 src/simh/scp.c                     sim_debug (exp->dbit, exp->dptr, "Against Match Data: %s\n", mstr);
sim_debug        9506 src/simh/scp.c                 sim_debug (exp->dbit, exp->dptr, "Checking String[%d:%d]: %s\n", exp->buf_size-(ep->size-exp->buf_ins), ep->size-exp->buf_ins, estr);
sim_debug        9507 src/simh/scp.c                 sim_debug (exp->dbit, exp->dptr, "Against Match Data: %s\n", mstr);
sim_debug        9520 src/simh/scp.c                 sim_debug (exp->dbit, exp->dptr, "Checking String[%d:%d]: %s\n", exp->buf_ins-ep->size, ep->size, estr);
sim_debug        9521 src/simh/scp.c                 sim_debug (exp->dbit, exp->dptr, "Against Match Data: %s\n", mstr);
sim_debug        9533 src/simh/scp.c         sim_debug (exp->dbit, exp->dptr, "Buffer wrapping\n");
sim_debug        9536 src/simh/scp.c     sim_debug (exp->dbit, exp->dptr, "Matched expect pattern!\n");
sim_debug        9539 src/simh/scp.c         sim_debug (exp->dbit, exp->dptr, "Waiting for %d more match%s before stopping\n",
sim_debug        9546 src/simh/scp.c             sim_debug (exp->dbit, exp->dptr, "Initiating actions: %s\n", ep->act);
sim_debug        9549 src/simh/scp.c             sim_debug (exp->dbit, exp->dptr, "No actions specified, stopping...\n");
sim_debug        9651 src/simh/scp.c         sim_debug (snd->dbit, snd->dptr, "Too soon to inject next byte\n");
sim_debug        9659 src/simh/scp.c         sim_debug (snd->dbit, snd->dptr, "Byte value: 0x%02X%s injected\n", *stat & 0xFF, dstr);
sim_debug        10063 src/simh/scp.c     sim_debug (reason, dptr, "%s %s %slen: %08X\n", sim_uname(uptr), txt, position, (unsigned int)len);
sim_debug        10110 src/simh/scp.c                 sim_debug (reason, dptr, "%04X thru %04X same as above\n", i-(16*same), i-1);
sim_debug        10153 src/simh/scp.c             sim_debug (reason, dptr, "%04X%-48s %s%s%s\n", i, outbuf, strbuf, ebcdicbuf, rad50buf);
sim_debug        10156 src/simh/scp.c             sim_debug (reason, dptr, "%04X thru %04X same as above\n", i-(16*same), (unsigned int)(len-1));
sim_debug         739 src/simh/sim_console.c                     sim_debug (DBG_XMT, &sim_remote_console, "Prompt Written: %s\n", sim_is_running ? "SIM> " : "sim> ");
sim_debug         818 src/simh/sim_console.c                     sim_debug (DBG_RCV, &sim_remote_console, "Got Command (%lu bytes still in buffer): %s\n", (unsigned long)tmxr_input_pending_ln (lp), sim_rem_buf[i]);
sim_debug        2045 src/simh/sim_console.c sim_debug (DBG_TRC, &sim_con_telnet, "sim_os_poll_kbd()\n");
sim_debug         243 src/simh/sim_disk.c sim_debug (ctx->dbit, ctx->dptr, "_sim_disk_rdsect(unit=%lu, lba=0x%X, sects=%lu)\n", (unsigned long)(uptr-ctx->dptr->units), lba, (unsigned long)sects);
sim_debug         267 src/simh/sim_disk.c sim_debug (ctx->dbit, ctx->dptr, "sim_disk_rdsect(unit=%lu, lba=0x%X, sects=%lu)\n", (unsigned long)(uptr-ctx->dptr->units), lba, (unsigned long)sects);
sim_debug         343 src/simh/sim_disk.c sim_debug (ctx->dbit, ctx->dptr, "_sim_disk_wrsect(unit=%lu, lba=0x%X, sects=%lu)\n", (unsigned long)(uptr-ctx->dptr->units), lba, (unsigned long)sects);
sim_debug         366 src/simh/sim_disk.c sim_debug (ctx->dbit, ctx->dptr, "sim_disk_wrsect(unit=%lu, lba=0x%X, sects=%lu)\n", (unsigned long)(uptr-ctx->dptr->units), lba, (unsigned long)sects);
sim_debug         808 src/simh/sim_disk.c sim_debug (ctx->dbit, ctx->dptr, "sim_disk_attach(unit=%lu,filename='%s')\n", (unsigned long)(uptr-ctx->dptr->units), uptr->filename);
sim_debug        1099 src/simh/sim_disk.c sim_debug (ctx->dbit, ctx->dptr, "sim_disk_reset(unit=%lu)\n", (unsigned long)(uptr-ctx->dptr->units));
sim_debug         574 src/simh/sim_tape.c sim_debug (MTSE_DBG_STR, ctx->dptr, "rd_lnt: st: %d, lnt: %d, pos: %" T_ADDR_FMT "u\n", r, *bc, uptr->pos);
sim_debug         759 src/simh/sim_tape.c sim_debug (MTSE_DBG_STR, ctx->dptr, "rd_lnt: st: %d, lnt: %d, pos: %" T_ADDR_FMT "u\n", r, *bc, uptr->pos);
sim_debug         794 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_rdrecf(unit=%d, buf=%p, max=%d)\n", (int)(uptr-ctx->dptr->units), buf, max);
sim_debug         857 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_rdrecr(unit=%d, buf=%p, max=%d)\n", (int)(uptr-ctx->dptr->units), buf, max);
sim_debug         907 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_wrrecf(unit=%d, buf=%p, bc=%d)\n", (int)(uptr-ctx->dptr->units), buf, bc);
sim_debug         976 src/simh/sim_tape.c sim_debug (MTSE_DBG_STR, ctx->dptr, "wr_lnt: lnt: %d, pos: %" T_ADDR_FMT "u\n", dat, uptr->pos);
sim_debug         989 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_wrtmk(unit=%d)\n", (int)(uptr-ctx->dptr->units));
sim_debug        1013 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_wreom(unit=%d)\n", (int)(uptr-ctx->dptr->units));
sim_debug        1041 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_wreomrw(unit=%d)\n", (int)(uptr-ctx->dptr->units));
sim_debug        1172 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_wrgap(unit=%d, gaplen=%u)\n", (int)(uptr-ctx->dptr->units), gaplen);
sim_debug        1339 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_sprecf(unit=%d)\n", (int)(uptr-ctx->dptr->units));
sim_debug        1380 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_sprecsf(unit=%d, count=%d)\n", (int)(uptr-ctx->dptr->units), count);
sim_debug        1425 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_sprecr(unit=%d)\n", (int)(uptr-ctx->dptr->units));
sim_debug        1472 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_sprecsr(unit=%d, count=%d)\n", (int)(uptr-ctx->dptr->units), count);
sim_debug        1521 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_spfilebyrecf(unit=%d, count=%d, check_leot=%d)\n", (int)(uptr-ctx->dptr->units), count, check_leot);
sim_debug        1589 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_spfilef(unit=%d, count=%d)\n", (int)(uptr-ctx->dptr->units), count);
sim_debug        1632 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_spfilebyrecr(unit=%d, count=%d)\n", (int)(uptr-ctx->dptr->units), count);
sim_debug        1683 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_spfiler(unit=%d, count=%d)\n", (int)(uptr-ctx->dptr->units), count);
sim_debug        1704 src/simh/sim_tape.c     sim_debug (ctx->dbit, ctx->dptr, "sim_tape_rewind(unit=%d)\n", (int)(uptr-ctx->dptr->units));
sim_debug        1727 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_position(unit=%d, flags=0x%X, recs=%d, files=%d)\n", (int)(uptr-ctx->dptr->units), flags, recs, files);
sim_debug        1791 src/simh/sim_tape.c sim_debug (ctx->dbit, ctx->dptr, "sim_tape_reset(unit=%d)\n", (int)(uptr-ctx->dptr->units));
sim_debug        1906 src/simh/sim_tape.c sim_debug (MTSE_DBG_STR, dptr, "tpc_map: tape_size: %" T_ADDR_FMT "u\n", tape_size);
sim_debug        1918 src/simh/sim_tape.c         sim_debug (MTSE_DBG_STR, dptr, "tpc_map: %d byte count at pos: %" T_ADDR_FMT "u\n", bc, tpos);
sim_debug        1925 src/simh/sim_tape.c         sim_debug (MTSE_DBG_STR, dptr, "tpc_map: tape mark at pos: %" T_ADDR_FMT "u\n", tpos);
sim_debug        1934 src/simh/sim_tape.c sim_debug (MTSE_DBG_STR, dptr, "tpc_map: objc: %u, different record sizes: %u\n", objc, sizec);
sim_debug        1938 src/simh/sim_tape.c             sim_debug (MTSE_DBG_STR, dptr, "tpc_map: summary - %u tape marks\n", countmap[i]);
sim_debug        1940 src/simh/sim_tape.c             sim_debug (MTSE_DBG_STR, dptr, "tpc_map: summary - %u %d byte record%s\n", countmap[i], (int)i, (countmap[i] > 1) ? "s" : "");
sim_debug        1950 src/simh/sim_tape.c         sim_debug (MTSE_DBG_STR, dptr, "tpc_map: ERROR unexpected EOT byte count: %d\n", last_bc);
sim_debug        1952 src/simh/sim_tape.c         sim_debug (MTSE_DBG_STR, dptr, "tpc_map: ERROR next record position %" T_ADDR_FMT "u beyond EOT: %" T_ADDR_FMT "u\n", tpos, tape_size);
sim_debug        1954 src/simh/sim_tape.c         sim_debug (MTSE_DBG_STR, dptr, "tpc_map: ERROR tape cnly contains tape marks\n");
sim_debug        1961 src/simh/sim_tape.c     sim_debug (MTSE_DBG_STR, dptr, "tpc_map: WARNING unexpected EOT byte count: %d, double tape mark before %" T_ADDR_FMT "u provides logical EOT\n", last_bc, leot);
sim_debug        1967 src/simh/sim_tape.c sim_debug (MTSE_DBG_STR, dptr, "tpc_map: OK objc: %d\n", objc);
sim_debug         392 src/simh/sim_timer.c sim_debug (DBG_CAL, &sim_timer_dev, "_sim_rtcn_init_unit(unit=%s, time=%d, tmr=%d)\n", sim_uname(uptr), time, tmr);
sim_debug         456 src/simh/sim_timer.c sim_debug (DBG_TRC, &sim_timer_dev, "sim_timer_init()\n");
sim_debug         783 src/simh/sim_timer.c         sim_debug (DBG_CAL, &sim_timer_dev, "_rtcn_configure_calibrated_clock() - Starting Internal Calibrated Timer at %dHz\n", sim_int_clk_tps);
sim_debug         795 src/simh/sim_timer.c     sim_debug (DBG_CAL, &sim_timer_dev, "_rtcn_configure_calibrated_clock() - Stopping Internal Calibrated Timer, New Timer = %d (%dHz)\n", tmr, rtc_hz[tmr]);
sim_debug         807 src/simh/sim_timer.c     sim_debug (DBG_CAL, &sim_timer_dev, "_rtcn_configure_calibrated_clock() - Changing Calibrated Timer from %d (%dHz) to %d (%dHz)\n", sim_calb_tmr, rtc_hz[sim_calb_tmr], tmr, rtc_hz[tmr]);
sim_debug         815 src/simh/sim_timer.c sim_debug (DBG_TRC, &sim_timer_dev, "sim_timer_clock_reset()\n");
sim_debug         826 src/simh/sim_timer.c sim_debug (DBG_TRC, &sim_timer_dev, "sim_start_timer_services()\n");
sim_debug         834 src/simh/sim_timer.c sim_debug (DBG_TRC, &sim_timer_dev, "sim_stop_timer_services()\n");
sim_debug         905 src/simh/sim_timer.c sim_debug (DBG_TIM, &sim_timer_dev, "sim_timer_activate_after() - queue addition %s at %d (%d usecs)\n",
sim_debug         960 src/simh/sim_timer.c             sim_debug (SIM_DBG_EVENT, &sim_timer_dev, "Canceled Clock Coscheduled Event for %s\n", sim_uname(uptr));
sim_debug        1333 src/simh/sim_tmxr.c     sim_debug (TMXR_DBG_MDM, dptr, " - Line %d - %p\n", (int)(lp-lp->mp->ldsc), lp->txb);
sim_debug         277 src/simh/sim_tmxr.h # define tmxr_debug_msg(dbits, lp, msg) do {if (sim_deb && (lp)->mp && (lp)->mp->dptr && ((dbits) & (lp)->mp->dptr->dctrl)) sim_debug (dbits, (lp)->mp->dptr, "%s", msg); } while (0)
sim_debug         278 src/simh/sim_tmxr.h # define tmxr_debug_return(lp, val) do {if (sim_deb && (val) && (lp)->mp && (lp)->mp->dptr && (TMXR_DBG_RET & (lp)->mp->dptr->dctrl)) { if ((lp)->rxbps) sim_debug (TMXR_DBG_RET, (lp)->mp->dptr, "Ln%d: 0x%x - Next after: %.0f\n", (int)((lp)-(lp)->mp->ldsc), val, (lp)->rxnexttime); else sim_debug (TMXR_DBG_RET, (lp)->mp->dptr, "Ln%d: 0x%x\n", (int)((lp)-(lp)->mp->ldsc), val); } } while (0)
sim_debug         279 src/simh/sim_tmxr.h # define tmxr_debug_trace(mp, msg) do {if (sim_deb && (mp)->dptr && (TMXR_DBG_TRC & (mp)->dptr->dctrl)) sim_debug (TMXR_DBG_TRC, mp->dptr, "%s\n", (msg)); } while (0)
sim_debug         280 src/simh/sim_tmxr.h # define tmxr_debug_trace_line(lp, msg) do {if (sim_deb && (lp)->mp && (lp)->mp->dptr && (TMXR_DBG_TRC & (lp)->mp->dptr->dctrl)) sim_debug (TMXR_DBG_TRC, (lp)->mp->dptr, "Ln%d:%s\n", (int)((lp)-(lp)->mp->ldsc), (msg)); } while (0)
sim_debug         281 src/simh/sim_tmxr.h # define tmxr_debug_connect(mp, msg) do {if (sim_deb && (mp)->dptr && (TMXR_DBG_CON & (mp)->dptr->dctrl)) sim_debug (TMXR_DBG_CON, mp->dptr, "%s\n", (msg)); } while (0)
sim_debug         282 src/simh/sim_tmxr.h # define tmxr_debug_connect_line(lp, msg) do {if (sim_deb && (lp)->mp && (lp)->mp->dptr && (TMXR_DBG_CON & (lp)->mp->dptr->dctrl)) sim_debug (TMXR_DBG_CON, (lp)->mp->dptr, "Ln%d:%s\n", (int)((lp)-(lp)->mp->ldsc), (msg)); } while (0)